PI6C3Q991A-5I [ETC]
Clock IC | 500ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz. Industrial Temp. Operation ; 时钟IC | 500PS精度。 3.3V 。平衡的。 3.75 〜85 MHz的。工业级温度范围。手术\n
| 型号： | PI6C3Q991A-5I |
| 厂家： | 
ETC |
| 描述： | Clock IC | 500ps Accuracy. 3.3V. Balanced. 3.75 to 85 MHz. Industrial Temp. Operation
|
| 文件： | 总10页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver
SuperClock
Features
Description
• PI6C3Q99X family provides following products:
PI6C3Q991A:32-pinPLCCversion
PI6C3Q993A:28-pinQSOPversion
• Inputs are 5V Tolerant
ThePI6C3Q99Xfamily,ahigh-fanout3.3VPLL-basedclockdriver,
isintendedforhigh-performancecomputinganddata-communica-
tion applications. A key feature of the programmable skew is the
abilityofoutputstoleadorlagtheREFinputsignal.ThePI6C3Q991A
has 8 programmable skew outputs in 4 banks of 2, while the
PI6C3Q993A has 6 programmable skew outputs and 2 zero skew
outputs. Skew is controlled by 3-level input signals that may be
hard-wiredtoappropriateHIGH-MID-LOWlevels.
• 4 pairs of programmable skew outputs
• Low skew: 200ps same pair; 250ps all outputs
• Selectable positive or negative edge synchronization:
Excellent for DSP applications
• Synchronous output enable
When the GND/sOE pin is held LOW, all the outputs are synchro-
nously enabled. However, if GND/sOE is held HIGH, all outputs
except 3Q0 and 3Q1 are synchronously disabled. Furthermore,
• Input frequency: 3.75 MHz to 110 MHz
• Output frequency: 15 MHz to 110 MHz
• 2x, 4x, 1/2, and 1/4 outputs
whentheV
/PEisheldHIGH,alloutputsaresynchronizedwith
CCQ
• 3 skew grades:
the positive edge of the REF clock input. When V
/PE is held
CCQ
PI6C3Q99x:tSKEW0<750ps
LOW, all outputs are synchronized with the negative edge of REF.
Both devices have LVTTL outputs with 12mA balanced drive
outputs.
PI6C3Q99x-5:tSKEW0<500ps
PI6C3Q99x-2:tSKEW0<250ps
• 3-level inputs for skew and PLL range control
• PLL bypass for DC testing
• Externalfeedback,internalloopfilter
• 12mA balanced drive outputs
• LowJitter:<200pspeak-to-peak
• Industrial temperature range
• Pin-to-pincompatiblewithIDTQS5V991AandQS5V993A
• Availablein32-pinPLCCand28-pinQSOP
PinConfigurations
PI6C3Q991A
PI6C3Q993A
1
REF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
TEST
2F1
2
V
CCQ
FS
3
4
3
2
1 32 31 30
29
4
3F0
3F1
/PE
2F0
3F1
4F0
4F1
/PE
5
6
7
8
9
2F0
GND/sOE
1F1
5
GND/sOE
1F1
28
27
26
25
24
23
22
21
6
V
CCQ
V
28-Pin
Q
7
1F0
V
CCN
1F0
CCQ
V
32-Pin
8
4Q1
4Q0
GND
3Q1
3Q0
V
CCN
V
CCN
4Q1
4Q0
GND
GND
J
CCN
9
1Q0
1Q1
GND
GND
2Q0
2Q1
10
11
12
13
1Q0
1Q1
GND
GND
10
11
12
13
14
V
14 15 16 17 18 19 20
CCN
FB
PS8628A
02/06/03
1
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Logic Block Diagrams
PI6C3Q993A
PI6C3Q991A
GND/sOE
GND/sOE
Skew
1Q0
Skew
1Q0
1Q1
Select
Select
1Q1
3
3
3
3
1F1:0
2F1:0
3F1:0
1F1:0
2F1:0
3F1:0
4F1:0
V
/PE
V
/PE
CCQ
CCQ
Skew
Skew
2Q0
2Q1
2Q0
2Q1
Select
Select
3
3
3
3
REF
FB
REF
FB
PLL
PLL
Skew
Select
Skew
Select
3Q0
3Q1
3Q0
3Q1
3
3
3
3
3
3
FS
FS
Skew
Select
4Q0
4Q1
4Q0
4Q1
3
3
Table 1. Pin Descriptions
Pin Name
Type
Functional Description
REF
IN
Reference Clock input
Feedback Input
FB
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew
selections (see table 3) remain in effect. Set LOW for normal operation.
TEST(1)
GND/sOE(1)
VCCQ/ PE
IN
IN
IN
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state -
3Q0 or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level
and GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] =
LL. Set GND/sOE LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock.
nF [1:0]
FS
IN
IN
3-level inputs for selecting 1of 9 skew taps or frequency range.
Selects appropriate oscillator circuit based on anticipated frequency range. See table 2
4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993A 4Q1:0 are fixed zero skew
outputs.
nQ [1:0]
OUT
VCCN
VCCQ
GND
PWR Power supply for output buffers
PWR Power supply for phase locked loop and other internal circuitry
PWR Ground
Note:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for
individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
PS8628A
02/06/03
2
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
ExternalFeedback
Byprovidingexternalfeedback, thePI6C3Q99xfamilygivesusers
flexibilitywithregardtoskewadjustment.TheFBsignaliscompared
with the input REF signal at the phase detector in order to drive the
ProgrammableSkew
Output skew with respect to the REF input is adjustable to compen-
sate for PCB trace delays, backplane propagation delays or to
accommodaterequirementsforspecialtimingrelationshipsbetween
clocked components. Skew is selectable as a multiple of a time unit
V
. PhasedifferencescausetheV ofthePLLtoadjustupwards
CO
CO
or downwards accordingly. An internal loop filter moderates the
t which is of the order of a nanosecond (see Table 2). There are 9
U
response of the V to the phase detector. The loop filter transfer
skew configurations available for each output pair. These configu-
rations are choosen by the nF1:0 control pins. In order to minimize
the number of control pins, 3-level inputs (HIGH-MID-LOW) are
used,theyareintendedforbutnotrestrictedtohard-wiring.Undriven
3-level inputs default to the MID level. Where programmable skew
isnotarequirement,thecontrolpinscanbeleftopenforthezeroskew
default setting. The Skew Selection Table (Table 3) shows how to
select specific skew taps by using the nF1:0 control pins.
CO
function has been chosen to provide minimal jitter (or frequency
variation) while still providing accurate responses to input fre-
quency changes.
Table2. PLLProgrammableSkewRangeandResolutionTable
FS = LOW
FS = MID
FS = HIGH
Comments
Timing unit calculation (t )
1/(44xFNOM
)
1/(26xFNOM
)
1/(16xFNOM)
U
(2,3)
VCO frequency range (FNOM
)
15 to 35 MHz
25 to 60 MHz
40 to 110 MHz
±9.09ns
±49°
±14%
±9.23ns
±83°
±23%
±9.38ns
±135°
±37%
Skew adjustment range(4)
Max. adjustment
ns Phase degrees % of cycle time
Example 1, FNOM = 15 MHz
Example 2, FNOM = 25 MHz
Example 3, FNOM = 30 MHz
Example 4, FNOM = 40 MHz
Example 5, FNOM = 50 MHz
Example 6, FNOM = 80 MHz
tU = 1.52ns
tU = 0.91ns
tU = 0.76ns
tU = 1.54ns
tU = 1.28ns
tU = 0.96ns
tU = 0.77ns
tU = 1.56ns
tU = 1.25ns
tU = 0.78ns
Notes:
2. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
Selecting the appropriate FS value based on input frequency range allows the PLL to operate in its ‘sweet spot’ where jitter is
lowest.
3. The level to be set on FS is determined by the nominal operating frequency of the V and Time Unit Generator. The V
CO
CO
frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The
frequency appearing at the REF and FB inputs will be the same as the V when the output connected to FB is undivided.
CO
The frequency of the REF and FB inputs will be 1/2 or 1/4 the V frequency when the part is configured for a frequency
CO
multiplication by using a divided output as the FB input.
4. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then
adjustment range will be greater. For example if a 4t skewed output is used for feedback, all other outputs will be skewed
U
–4t in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range applies to output pairs
U
3 and 4 where ±6t skew adjustment is possible and at the lowest F
value.
U
NOM
PS8628A
02/06/03
3
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Table 3. Skew Selection Table for Output Pairs
nF1:0
LL(6)
LM
Skew (Pair #1, #2)
Skew (Pair #3)
Divide by 2
–6tU
Skew (Pair #4)(5)
Divide by 2*
–6tU
–4tU
–3tU
LH
–2tU
–4tU
–4tU
ML
–1tU
–2tU
–2tU
MM
MH
HL
Zero skew
+1tU
Zero skew
+2tU
Zero skew
+2tU
+2tU
+4tU
+4tU
HM
HH
+3tU
+6tU
+6tU
Inverted(7)
+4tU
Divide by 4*
Notes:
5. Programmable skew on pair #4 is not applicable for the PI6C3Q993A.
6. LL disables outputs if TEST = MID and GND/sOE = HIGH.
7. When pair #4 is set to HH (inverted), GND/sOE disables pair #4 HIGH when V
/PE = HIGH, GND/sOE disables pair #4 LOW
CCQ
whenV
/PE=LOW.
CCQ
* The rising edge of 3Qx and 4Qx are not aligned only when both 3F1 : 0 = HH (divide by 4) and 4F1 : 0 = LL (divide by 2) are
selected. This is not applicable for PI6C3Q993A.
Table 4. Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings
Supply Voltage to Ground ...................................... –0.5Vto7.0V
Input Voltage .......................................................... –0.5Vto7.0V
may cause permanent damage to the device. These ratings
arestress specifications only and functional operation of the
MaximumPowerDissipationatT =85°C,PLCC ....... 0.80watts
A
device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Expo-
suretoabsolutemaximumratingconditionsforextendedperiods
may affect product reliability.
QSOP ....... 0.66watts
TSTGStorageTemperature.................................. –65°Cto150°C
Table 5. Recommended Operating Range
PI6C3Q991A/PI6C3Q993A
PI6C3Q99A-5/PI6C3Q993A-5
PI6C3Q991A/PI6C3Q993A
PI6C3Q991A-2/PI6C3Q993A-2
PI6C3Q991A-5/PI6C3Q993A-5
(Commercial)
(Industrial)
Symbol
VCC
Description
Power Supply Voltage
Min.
3.0
Max.
3.6
Min.
3.0
0
Max.
3.6
Units
V
TA
Ambient Operating Temperature
–40
85
70
°C
PS8628A
02/06/03
4
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Table 6. DC Characteristics Over Operating Range
Symbol
Parameter
Test Condition
Min.
Max.
Units
Guaranteed Logic HIGH
(REF, FB inputs only)
VIH
Input HIGH Voltage
2.0
5.5
Guaranteed Logic LOW
(REF, FB inputs only)
VIL
Input LOW Voltage
–0.5
0.8
V
VIHH
VIMM
VILL
Input HIGH Voltage(8)
Input MID Voltage(8)
Input LOW Voltage(8)
3-Level Inputs Only
3-Level Inputs Only
3-Level Inputs Only
VCC –0.6
VCC/2 –0.3
VCC/2 +0.3
0.6
VIN = VCC or GND,
VCC = Max.
IIN
Input Leakage Current (REF, FB inputs only)
5
VIN = VCC
HIGH Level
200
50
I3
3-Level Input DC Current (TEST, FS, nF1:0)
Input Pull-Up Current (VCCQ/PE)
VIN = VCC/2 MID Level
µA
V
VIN = GND
LOW Level
200
IPU
VCC = Max., VIN = GND
100
100
IPD
VOH
VOL
Input Pull-Down Current (GND/sOE)
Output HIGH Voltage
VCC = Max., VIN = VCC
VCC = Min., IOH = –12mA
VCC = Min., IOL = 12mA
2.2
Output LOW Voltage
0.55
Table7.PowerSupplyCharacteristics
Symbol
Parameter
Test Condition
Typ. Max. Units
VCC = Max., TEST = Mid., REF = LOW,
GND/sOE = LOW, All outputs unloaded
ICCQ Quiescent Power Supply Current
8.0
1.0
55
15
30
mA
∆ICC Power Supply Current per Input HIGH(9)
VCC = Max., VIN = 3.0V
µA
N
µA/
MHz
ICCD Dynamic Power Supply Current per Output(9) VCC = Max., CL = 0pF
90
125
IC
IC
Total Power Supply Current(9)
Total Power Supply Current(9)
Total Power Supply Current(9)
VCC = 3.3V, FREF = 20 MHz, CL = 160pF(10)
VCC = 3.3V, FREF = 33 MHz, CL = 160pF(10)
VCC = 3.3V, FREF = 66 MHz, CL = 160pF(10)
29
42
76
mA
IC
Notes:
8. These inputs are normally wired to V , GND, or unconnected. Internal termination resistors bias unconnected inputs to V /2.
CC
CC
LOCK
If these inputs are switched, the function and timing of the outputs may glitched, and the PLL may require an additional t
time before all datasheet limits are achieved.
9. Guaranteed by characterization but not production tested.
10. For 8 outputs each loaded with 20pF.
PS8628A
02/06/03
5
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Table8. Capacitance (T = 25°C, f = 1 MHz, V = 0V)
A
IN
QSOP
PLCC
Units
Typ.
Max.
Typ.
Max.
CIN
4
6
5
7
pF
VCC
150Ω
Output
150Ω
20pF
tORISE
tOFALL
≤1ns
≤1ns
3.0V
2.0V
Vth=1.5V
0.8V
2.0V
0.8V
tPWL
tPWH
0V
LVTTL Input Test Waveform
LVTTL Output Waveform
Figure 1. AC Test Loads and Waveforms
PS8628A
02/06/03
6
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Table9.SwitchingCharacteristicsOverOperatingRange
PI6C3Q991A-2
PI6C3Q993A-2
PI6C3Q991A-5
PI6C3Q993A-5
PI6C3Q991A
PI6C3Q993A
Description
Units
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
FNOM
tRPWH
tRPWL
tU
VCO frequency range
see Table 2
see Table 2
see Table 2
3.0
REF pulse width HIGH(21)
3.0
3.0
3.0
3.0
ns
REF pulse width LOW(21)
3.0
Programmable skew time unit
see Table 3
see Table 3
see Table 3
0.1 0.25
0.3 0.75
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
Zero output matched-pair skew (xQ0, xQ1)(11,12,13)
Zero output skew (all outputs) CL = 0pF(11,14)
Output skew (rise-rise, fall-fall, same class outputs)(11,15)
Output skew (rise-fall, nominal-inverted, divided-divided(11,15)
Output skew (rise-rise, fall-fall, different class outputs)(11,15)
Output skew (rise-fall, nominal-divided, divided inverted(11,15)
Device-to-device skew(11,12,16)
0.05 0.20
0.1 0.25
0.25 0.50
0.30 1.2
0.1 0.25
0.25
0.6
0.5
0.5
0.5
0.5
0.7
1.2
0.7
1.0
1.25
0.5
1.2
2.5
3.0
1.5
1.5
0.5
40
0.6
1.0
0.7
1.2
1.0
1.5
1.2
1.7
1.65
0.7
1.2
3.0
3.5
2.5
2.5
0.5
40
0.25 0.50
0.50 0.90
0.75
ns
tPD
REF input to FB propagation delay(11,18)
Output duty cycle varation from 50%(11)
Output HIGH time deviation from 50%(11,19)
Output LOW time deviation from 50%(11,20)
Output rise time(11)
Output fall time(11)
PLL lock time(11,17)
–0.25
–1.2
0
0
0.25 –0.5
0
0
–0.7
–1.2
0
0
tODCV
tPWH
1.2
2.0
1.5
1.5
1.5
0.5
25
–1.2
tPWL
tORISE
tOFALL
tLOCK
0.15
0.15
1.0
1.0
0.15 1.0
0.15 1.0
0.15 1.5
0.15 1.5
ms
ps
RMS
Cycle-to-cycle output
jitter(11)
tJR
Peak-to-peak
200
200
200
Notes:
11. All timing tolerances apply for F
production testing.
≥ 25MHz. Guaranteed by design and characterization, not subject to 100%
NOM
12. Skew is the time between the earliest and the latest output transition among all outputs for which the same t delay
U
has been selected when all are loaded with the specified load.
13.
14.
t
is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t .
SKEWPR U
t
is the skew between outputs when they are selected for 0t .
SKEW0
U
15. There are 3 classes of outputs: Nominal (multiple of t delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
U
andDivided(3Qxand4QxonlyinDivide-by-2orDivide-by-4mode).
16.
17.
t
is output-to-output skew between any two devices operating under the same conditions (V , ambient temperature,
DEV CC
airflow,etc.)
t
is time that is required before synchronization is achieved. This specification is valid only after V is stable & within
LOCK
CC
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until t is
PD
withinspecifiedlimits.
18.
t
PD
is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
19. Measured at 2.0V.
20. Measured at 0.8V.
21. RefertoTable10formoredetail.
PS8628A
02/06/03
7
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
Table10.InputTimingRequirements(22)
Symbol
Description
Min.
Max.
Units
ns/V
ns
tR, tF
tPWC
DH
Maximum input rise and fall times, 0.8V to 2.0V
Input clock pulse, HIGH or LOW
Input duty cycle
10
3
10
90
%
Notes:
22. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by D is less than t
limit,
PWC
H
t
limit applies.
PWC
t
t
REF
RPWL
t
RPWH
REF
t
PD
t
t
ODCV
ODCV
FB
Q
t
JR
t
SKEWPR
t
SKEWPR
t
SKEW0, 1
t
SKEW0, 1
Other Q
t
t
SKEW2
SKEW2
Inverted Q
t
t
SKEW3,4
t
t
SKEW3,4
SKEW3,4
SKEW2,4
REF Divided by 2
t
SKEW1,3,4
REF Divided by 4
Figure2. ACTimingDiagram
Notes:
/PE: The AC timing diagram above applies to V
V
CCQ
/PE=V . For V
/PE=GND, the negative edge of FB aligns with the
CCQ
CCQ
CC
negative edge of REF, divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2
and the divide-by-4 signals align.
Skew:
The time between the earliest and the latest output transition among all outputs for which the same t delay has been
U
selected when all are loaded with 20pF and terminated with 75ohms to V /2.
CC
t
t
t
: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0t .
SKEWPR
U
:
The skew between outputs when they are selected for 0t U.
SKEW0
:
The output-to-output skew between any two devices operating under the same conditions (V , ambient temperature,
DEV
CC
airflow,etc.)
t
t
:
:
The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t
specifications.
and t
SKEW2 SKEW4
ODCV
The time that is required before synchronization is achieved. This specification is valid only after V is stable and within
LOCK
CC
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until
t
is within specified limits.
PD
t
t
t
ismeasuredat2.0V.
is measured at 0.8V.
PWH
PWL
& t
ORISE
OFALL
aremeasuredbetween0.8Vand2.0V.
PS8628A
02/06/03
8
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
32-PinPLCCPackageDiagram
28-PinQSOPPackageDiagram
28
.008
0.20
MIN.
.008
.013
0.20
0.33
0.150
0.157
3.81
3.99
Guage Plane
0˚-6˚
.010
.016
0.254
.035
0.41
0.89
1
Detail A
.041
1.04
REF
.386 9.804
.394 10.009
.015 x 45˚
.033
REF
0.84
1.35 .053
1.75 .069
Detail A
SEATING
PLANE
0.178
0.254
.007
.010
0.41 .016
1.27 .050
0.101
0.254
.004
.010
.228
.244
5.79
6.19
.008
.012
.025
BSC
0.635
0.203
0.305
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
PS8628A
02/06/03
9
PI6C3Q991A, PI6C3Q993A
3.3V Programmable Skew PLL Clock Driver SuperClock
OrderingInformation
Ordering Code
Package Code
Package Type
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
32-Pin PLCC
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
28-Pin QSOP
Operating Range
PI6C3Q991AJ
J32
J32
PI6C3Q991A-2J
PI6C3Q991A-5J
PI6C3Q991A-IJ
PI6C3Q991A-5IJ
PI6C3Q993AQ
Commercial
J32
J32
Industrial
Commercial
Industrial
J32
Q28
Q28
Q28
Q28
Q28
PI6C3Q993A-2Q
PI6C3Q993A-5Q
PI6C3Q993A-IQ
PI6C3Q993A-5IQ
PericomSemiconductorCorporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8628A
02/06/03
10
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明