PI6C110EV [ETC]
CPU System Clock Generator ; CPU的系统时钟发生器\n
| 型号： | PI6C110EV |
| 厂家： | 
ETC |
| 描述： | CPU System Clock Generator
|
| 文件： | 总15页 (文件大小：611K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Features
Description
3of2.5V66/100/133MHz CPU(CPU[0-2])
2of2.5V33MHzAPIC(APIC[0-1])
9of3.3V100/133MHz SDRAM(SDRAM[0-7],DCLK)
8of3.3V33MHzPCI(PCI[0-7])
PericomPI6C110EintegratesadualPLLclockgenerator,SDRAM
buffer and I C interface. The clock generator section comprised
of an oscillator, 2 low jitter phased locked loop, skew control, and
power down logic. The SDRAM buffers are high speed and low
skew to handle data transfers in excess of 133 MHz.
2
2of3.3V66MHz(3V66[0-1])
When Spread Spectrum mode is enabled, all clock outputs are
modulated except for REF and 48 MHz[0-1] outputs. These clocks
are down spread linearly (triangular modulation) by +0%, 0.6%.
2of3.3V48MHz(48MHz[0-1])
1of3.3V14.3MHz(REF)
To minimize power consumption and EMI radiation some unused
Selectable CPU and SDRAM clocks (on power up only)
2
outputs can be turned off. Two wire I C interface is used to enable/
Power down function using PWR_DWN#
disable Spread Spectrum mode, and to turned off PCI clocks, CPU
clocks, and 48 MHz clocks.
2
Spread Spectrum Enable/Disable by I C
2
For low power sleep mode, the entire device can be placed to power
down mode. Driving the PWR_DWN# to low state disables the
entire chip. In this state the crystal oscillator, and both PLLs are
turned off. Furthermore, all outputs are deactivated to low state, all
inputs are inactive except for PWR_DWN#.
I C interface to turn off unused clocks
56pinSSOPpackage(V)
Block Diagram
Pin Configuration
V
All trademarks are of their respective companies.
PS8410
08/11/99
1
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Pin Description Table
Pin
Type Qty. P/S
Symbol
REF/SEL2
XTAL_IN
Description
Normally 14.318 MHz reference output. During power up this pin is
sampled as SEL2, clock bit 2. Internally pulled down w/100K Ohm.
1
I/O
1
3.3
3
4
I
1
1
2
3.3
3.3
3.3
14.318 MHz crystal input
O
O
XTAL_OUT 14.318 MHz crystal output
3V66 [0-1] 66 MHz
7, 8
11, 12, 13, 15,
16, 18, 19, 20
O
8
3.3
PCI [0-7]
PCI outputs
25, 26
28, 29
30
O
I
1
2
1
1
1
3.3 48 MHz [0-1] 48 MHz output
3.3
3.3
3.3
SEL [0-1]
SDATA
LVTTL level frequency select inputs, internal pullup
2
I/O
I
I C compatible SDATA, internal pullup
2
31
SCLOCK
I C compatible SCLOCK, internal pullup
32
I
3.3 PWRDWN# LVTTL level Power Down control input, active low
34, 36, 37, 39,
40, 42, 43, 45, 46
DCLK,
SDRAM and DCLK outputs. 100/133 MHz depending on SEL [0-2].
O
9
3.3
2
SDRAM [0-7] SDRAM [0-7] can be turned off through I C, but not DCLK.
49, 50, 52
54, 55
O
O
3
2
2.5
2.5
CPU [0-2] Host Bus Clock output. 66/100/133 MHz depending on SEL [0-2]
APIC [0-1] 33 MHz APIC clock, synchronous to PCI clock
2, 9, 10, 21, 27,
33, 38, 44
PWR
GND
8
8
3.3
V
3.3V Power Supply
3.3V Ground
DD3.3
5, 6, 14, 17, 24,
35, 41, 47
N/A
V
SS3.3
51, 53
48, 56
22
PWR
GND
PWR
GND
2
2
1
1
2.5
N/A
3.3
V
2.5V Power Supply
2.5V Ground
DD2.5
V
SS2.5
V
3.3V Core Power Supply
3.3V Core Ground
DDA
23
N/A
V
SSA
Frequency Select Function Table
SEL2 SEL1 SEL0
Function
X
X
0
0
0
1
1
1
1
0
1
0
1
0
1
Tri-State
Test
CPU = 66 MHz, SDRAM = 100 MHz
CPU = 100 MHz, SDRAM = 100 MHz
CPU = 133 MHz, SDRAM = 133 MHz
CPU = 133 MHz, SDRAM = 100 MHz
0
1
1
PS8410
08/11/99
2
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
DC Specifications
DC parameters must be sustainable under steady state (DC) conditions.
Absolute Maximum DC Power Supply
Symbol Parameter
Min.
-0.5
-0.5
-0.5
-65
Max.
4.6
Units
V
Notes
V
DDA
V
DD2.5
V
DD3.3
S
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
3.3V I/O Supply Voltage
Storage Temperature
3.6
V
4.6
V
T
150
°C
Absolute Maximum DC I/O
Symbol
Parameter
Min.
-0.5
Max.
Units
V
Notes
V
IH3
V
IL3
3.3V Input High Voltage
3.3V Input Low Voltage
4.6
1
-0.5
V
ESD prot. Input ESD protection
2000
V
2
Notes:
1. Maximum VIH is not to exceed maximum VDD
.
2. Human body model.
DC Operating Specification
Symbol
Parameter
Condition
Min.
Max.
Units Notes
V
V
V
3.3V Core Supply Voltage 3.3V ±5%
3.135
3.135
2.375
3.465
3.465
2.625
V
V
V
2
2
2
DDA
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.3V ±5%
2.5V ±5%
DD3.3
DD2.5
V
V
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current
V
2.0
-5
V +0.3
DD
V
V
4
IH3
IL3
DDA
V -0.3
0.8
+5
4
SS
I
0 <V <V
DD3.3
µA
1,4
IL
IN
C
C
C
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
pF
pF
pF
nH
°C
in
13.5
0
22.5
6
3
xtal
out
PIN
A
L
T
7
Ambient Temperature
No Airflow
70
Notes:
1. Input Leakage Current does not include inputs with Pull-Up or Pull-down resistors.
2. No power sequencing is implied or allowed to be required in the system.
3. As seen by the crystal. Device is intended to be used with a 17-20pF AT crystal.
4. All inputs referenced to 3.3V power supply.
PS8410
08/11/99
3
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Clock Output Buffer DC Characteristics
Buffer Name
CPU, APIC
48MHz, REF
SDRAM
VCC Range (V)
Impedance (Ohm)
13.5-45
Buffer Type
Type 1
2.375 - 2.625
20-60
Type 3
3.135-3.465
10-24
Type 4
PCI, 3V66
12-55
Type 5
Type 1: CPU, APIC Clocks
Symbol
IOHMIN
IOHMAX
IOLMIN
IOLMAX
Parameter
Condition
Min.
Typ.
Max. Units
VOUT = 1.0V
VOUT = 2.375V
VOUT = 1.2V
VOUT = 0.3V
27
Pull-Up Current
27
mA
30
Pull-Down Current
30
Type 3: 48 MHz, REF Clocks
Symbol
Parameter
Condition
Min.
Typ.
Max. Units
I
V
= 1.0V
= 3.135V
= 1.95V
= 0.4V
29
OHMIN
OUT
Pull-Up Current
I
V
OUT
23
mA
OHMAX
I
V
OUT
29
OLMIN
Pull-Down Current
I
V
27
OLMAX
OUT
Type 4: SDRAM Clocks
Symbol
Parameter
Condition
= 2.0V
OUT
Min.
Typ.
Max.
46
53
Units
I
V
54
OHMIN
Pull-Up Current
I
V
= 3.135V
= 1.0V
OUT
OHMAX
OUT
mA
I
V
54
OLMIN
Pull-Down Current
I
V
OUT
= 0.4V
OLMAX
Type 5: PCI, 3V66 Clocks
Symbol
Parameter
Condition
= 1.0V
OUT
Min.
Typ.
Max.
33
38
Units
I
V
33
OHMIN
Pull-Up Current
I
V
= 3.135V
OHMAX
OUT
mA
I
V
= 1.95V
= 0.4V
30
OLMIN
OUT
Pull-Down Current
I
V
OUT
OLMAX
PS8410
08/11/99
4
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
AC Timing Specifications
66 MHz
100 MHz
133 MHz
Symbol
Parameter
Units Notes
Min. Max. Min. Max. Min. Max.
15.0 15.5 10.0 10.5 7.5 8.0
T Period
T HIGH
T LOW
Host/CPU CLK period
Host/CPU CLK high time
Host/CPU CLK low time
ns
ns
2, 7
3
5.2
5.0
1.0
1.0
0.4
0.4
N/A
N/A
4.0
3.0
2.8
1.0
1.0
0.4
0.4
N/A 1.87 N/A
N/A 1.67 N/A
ns
4
Edge Rate Rising Edge Rate (Type 1 Buffer 2.5V)
Edge Rate Falling Edge Rate (Type 1 Buffer 2.5V)
4.0
4.0
1.6
1.6
1.0
1.0
0.4
0.4
4.0
4.0
1.6
1.6
V/ns
V/ns
ns
4.0
T Rise
Host/CPU CLK rise time
Host/CPU CLK fall time
1.6
1, 6
1, 6
2, 7
3
T Fall
1.6
ns
T Period
T HIGH
T LOW
APIC 33 MHz CLK period
APIC 33 MHz CLK high time
APIC 33 MHz CLK low time
30.0 N/A 30.0 N/A 30.0 N/A
12.0 N/A 12.0 N/A 12.0 N/A
12.0 N/A 12.0 N/A 12.0 N/A
ns
ns
ns
4
Edge Rate Rising Edge Rate (Type 1 Buffer 2.5V)
Edge Rate Falling Edge Rate (Type 1 Buffer 2.5V)
1.0
1.0
0.4
0.4
4.0
4.0
1.6
1.6
1.0
1.0
0.4
0.4
4.0
4.0
1.6
1.6
1.0
1.0
0.4
0.4
4.0
4.0
1.6
1.6
V/ns
V/ns
ns
T Rise
APIC 33 MHz CLK rise time
APIC 33 MHz CLK fall time
3V66 CLK period
1, 6
1, 6
2, 7
3
T Fall
ns
T Period
T HIGH
T LOW
15.0 16.0 15.0 16.0 15.0 16.0
5.25 N/A 5.25 N/A 5.25 N/A
ns
3V66 CLK high time
ns
3V66 CLK low time
5.5
1.0
1.0
0.5
0.5
N/A
4.0
4.0
2.0
2.0
5.5
1.0
1.0
0.5
0.5
N/A
4.0
4.0
2.0
2.0
5.5 N/A
ns
4
Edge Rate Rising Edge Rate (Type 5 Buffer 3.3V)
Edge Rate Falling Edge Rate (Type 5 Buffer 3.3V)
1.0
1.0
0.5
0.5
4.0
4.0
2.0
2.0
V/ns
V/ns
ns
T Rise
3V66 CLK rise time
1, 6
1, 6
2, 7
3
T Fall
3V66 CLK fall time
ns
T Period
T HIGH
T LOW
PCI & APIC CLK period
PCI & APIC CLK high time
PCI & APIC CLK low time
30.0 N/A 30.0 N/A 30.0 N/A
12.0 N/A 12.0 N/A 12.0 N/A
12.0 N/A 12.0 N/A 12.0 N/A
ns
ns
ns
4
Edge Rate Rising Edge Rate (Type 5 Buffer 3.3V)
Edge Rate Falling Edge Rate (Type 5 Buffer 3.3V)
1.0
1.0
4.0
4.0
2.0
2.0
1.0
1.0
0.5
0.5
4.0
4.0
2.0
2.0
1.0
1.0
0.5
0.5
4.0
4.0
2.0
2.0
8.0
V/ns
V/ns
ns
T Rise
PCI & APIC CLK rise time
PCI & APIC CLK fall time
SDRAM CLK period
0.5
1, 6
1, 6
2, 7
3
T Fall
0.5
ns
T Period
T HIGH
T LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1.0
N/A 10.5 10.5 7.5
ns
SDRAM CLK high time
SDRAM CLK low time
N/A
N/A
N/A
N/A
N/A
N/A
10.0
10.0
3
3.0
2.8
1.5
1.5
0.4
0.4
1.0
1.0
N/A 1.87 N/A
N/A 1.67 N/A
ns
ns
4
Edge Rate Rising Edge Rate (Type 4 Buffer 3.3V)
Edge Rate Falling Edge Rate (Type 4 Buffer 3.3V)
4.0
4.0
1.6
1.6
1.0
1.0
0.4
0.4
4.0
4.0
1.6
1.6
V/ns
V/ns
ns
T Rise
T Fall
SDRAM CLK rise time
SDRAM CLK fall time
1, 6
1, 6
ns
TpZL, tpZH Output Enable Delay (All Outputs)
TpLZ, tpZH Output Disable Delay (All Outputs)
10.0 1.0 10.0
10.0 1.0 10.0
ns
1.0
ns
Tstable
All clock stabilization from power-up
3
3
ms
5
(see notes on next page)
PS8410
08/11/99
5
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
AC Timing Notes:
1. Output drivers must have monotonic rise/fall times through the specified V /V levels.
OL OH
2. Period, jitter, offset and skew measured on rising edge @1.25V for 2.5V clocks and @ 1.5V for 3.3V clocks.
3. T
4. T
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
is measured at 0.4V for all outputs.
HIGH
LOW
5. The time specified is measured from when the power supply achieves its nominal operating level
(typical condition V = 3.3V) until the frequency output is stable and operating within specification.
DD3.3V
6. T
and T
are measured as a transition through the threshold region
RISE
FALL
V
OL
= 0.4V and V = 2.0V (1mA) JEDEC Specification.
OH
7. The average period over any 1µs period of time must be greater than the minimum specified period.
Group Skew And Jitter Limits
Pin-pin
Output
Group
Skew
MAX.
Cycle-Cycle
Jitter
Skew, jitter
measure point
Duty Cycle
45/55
Nom V
2.5V
3.3V
2.5V
3.3V
3.3V
3.3V
3.3V
DD
CPU
175ps
250ps
250ps
N/A
250ps
250ps
500ps
500ps
500ps
500ps
1000ps
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
SDRAM
APIC
48 MHz
3V66
PCI
45/55
45/55
45/55
175ps
500ps
N/A
45/55
45/55
REF
45/55
Output
Buffer
Test Point
Test Load
Output Waveform
Tperiod
Duty Cycle
THIGH
2.0
2.5V Clocking
1.25
0.4
Interface
TLOW
TRISE
TFALL
Tperiod
Duty Cycle
THIGH
2.4
1.5
0.4
3.3V Clocking
Interface
TLOW
TRISE
TFALL
Figure 1.
PS8410
08/11/99
6
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
2.5 Volt Measure Points
VDD2.5
Measurement Points For Component Output
Voh = 2.0V
Vih = 1.7V
1.25V
Vil = 0.7V
Vol =0.4V
Vss
Measurement Points For System Level Inputs
3.3 Volt Measure Points
VDD2.5
Measurement Points For Component Output
Voh = 2.4V
Vih = 2.0V
1.5V
Vil = 0.8V
Vol =0.4V
Vss
Measurement Points for System Level Inputs
Figure 2. Component Versus System Measure Points
Group to Group Skew Tolerance
CPU66
CPU66
CPU100
Offset
5.0ns
CPU100
Tolerance
500ps
N/A
CPU133
Offset
0.0ns
CPU133
Tolerance
500ps
500ps
500ps
500ps
500ps
500ps
1.0ns
Group
Offset
2.5ns
Tolerance
500ps
N/A
CPU to SDRAM100
CPU to SDRAM133
CPU to 3V66
N/A
N/A
5.0ns
5.0ns
500ps
500ps
N/A
5.0ns
500ps
500ps
N/A
0.0ns
SDRAM100 to 3V66
SDRAM133 to 3V66
3V66 to PCI
0.0ns
0.0ns
0.0ns
N/A
N/A
0.0ns
1.5~3.5ns
0.0ns
500ps
1.0ns
1.5~3.5ns
0.0ns
500ps
1.0ns
1.5~3.5ns
0.0ns
PCI to APIC
48 MHz & DOT
Async
N/A
Async
N/A
Async
N/A
Note:
Only offset specifications listed above are guaranteed/tested. The specification is treated as ANY output within first
specified bank to ANY output of the second specified bank. Pin-pin skew is implied within offset specification, jitter
is not. Previous offset specifications such as CPU to PCI offset are no longer required.
PS8410
08/11/99
7
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Group Offset Measurement Clarification
PS8410
08/11/99
8
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Clock Enable Configuration
REF,
48 MHZ
PWR_DWN#
CPU
SDRAM APIC
3V66
PCI
Osc
VCOs
0
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
LOW
ON
OFF
ON
OFF
ON
1
Notes:
1. LOW means outputs held static LOW.
2. ON means active.
3. PWR_DWN# pulled LOW, impacts all outputs including REF and 48 MHz outputs.
Truth Table
SEL2 SEL1 SEL0
CPU
SDRAM
Hi-Z
3V66
Hi-Z
PCI
48 MHz
REF
APIC
Hi-Z
Notes
1
X
0
0
1
1
1
1
0
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
X
TCLK/2
66 MHz
100 MHz
133 MHz
133 MHz
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
TCLK/3
66 MHz
66 MHz
66 MHz
66 MHz
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
TCLK
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
3, 4
0
14.318 MHz
14.318 MHz
14.318 MHz
14.318 MHz
0
1
2, 5, 6
1
Notes:
1. Required for board level bed of nails testing.
2. Normal mode of operation.
3. TCLK is a test clock over driven on the XTAL_IN input during test mode.
4. Required for DC output impedance verification.
5. Range of reference frequency allowed is min = 14.316 MHz, nominal = 14.31818 MHz, max = 14.32 MHz.
6. Frequency accuracy of 48 MHz is ±167PPM to match 48 MHz default.
System Clock Design Considerations
PI6C110E supports 4 operational modes. It varies the FSB (Front Side Bus) and SDRAM clock frequencies. FSB selection is 66
MHz, 100 MHz or 133 MHz. SDRAM frequency is either 100 MHz or 133 MHz. The supported modes are:
SEL[2:0] Mode
CPU SDRAM 3V66
APIC/PCI
0 1 0
0 1 1
1 1 0
1 1 1
Mode 0
Mode 1
Mode 2
Mode 3
66
100
133
133
100
100
133
100
66
66
66
66
33
33
33
33
default
The clock select pins, SEL[2:0] have the appropriate 100K (±20K) internal pull up and pull down to allow the system defaults to 100 MHz
CPUclockand100MHzSDRAMclockwithoutexternalstrappingresistor. SEL2inpulleddown, SEL1andSEL0ispulleduptoindicate
0 1 1.
The APIC clock is a 33 MHz, the same frequency and phase as the PCI clocks, except it is powered by 2.5V supply. APIC and PCI clocks
are always in phase with the other clocks. In Mode 0, CPU and 3V66 are inverted. In Mode 1 and Mode 3, CPU and SDRAM clocks
are inverted.
System Debug and Timing Margin Analysis
To support system debug and to measure/test margin analysis, the internal PI6C110E oscillator circuits allows the input crystal frequency
to be driven with parallel resonant crystal with frequency range of 10 MHz to 20 MHz in laboratory environment. The alternative is to
put the device in TEST mode, SEL2 = dont care, SEL1 = 1 and SEL0 = 0. Then drive a clock signal to XTAL_IN (pin 3) from
a signal generator and float XTAL_OUT (pin 4).
PS8410
08/11/99
9
PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Power Management
Maximum Current
Max. 2.5 supply consumption,
Max. discreet cap loads,
Max. 3.3 supply consumption,
Max. discreet cap loads,
Condition
VDD2.5 = 2.625V
VDD3.3 = 3.465V,
All static inputs = VDD3.3 or VSS
All static inputs = VDD3.3 or VSS
Power Down Mode
(PWRDWN#) = 0)
100µA
200µA
CPU = 66 MHz, SDRAM = 100 MHz
SEL [0-2] = 010
70mA
100mA
TBD
280mA
280mA
TBD
CPU = 100 MHz, SDRAM = 100 MHz
SEL [2-0] = 011
CPU = 133 MHz, SDRAM = 133 MHz
SEL [2-0] = 110
CPU = 133 MHz, SDRAM = 100 MHz
SEL [2-0] = 111
TBD
TBD
Power Management
Latency
No. of rising edges of PCI Clocks
3ms
Signal
Signal State
PWRDWN#
1 (normal operation)
0 (power down)
See Timing Diagram Below
Notes:
1. Clock on/off latency is defined in the number of rising edges of free running PCI clock
between the clock disable goes low/high to the first valid clock comes out of the device.
2. Power up latency is when PWRDWN# goes inactive (high) to when the first valid clocks
are driven from the device.
The power down selection is used to put the part into a very low
power state without turning off the power to the part. PWRDWN#
is an asynchronous active low input. This signal is synchronized
internal to the device prior to powering down the clock synthesizer.
PWRDWN# is an asynchronous function for powering up the
system. Internal clocks are not running after the device is put in
power down. When PWRDWN# is active low all clocks are driven
toalowvalueandheldpriortoturningofftheVCOsandthecrystal.
The power -up latency needs to be less than 3ms. The REF and
48 MHz clocks are expected to be stopped in the LOW state as soon
as possible. Due to the state of the internal logic, stopping and
holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
PS8410
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
PWRDWN# Timing Diagram
Notes:
1. Once the PWRDWN# signal is sampled LOW for two consecutive rising edges of CPU clock, clocks of interest should be held LOW on the
next high to low transition.
2. PWRDWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside the part.
3. The shaded sections on the SDRAM, REF, and 48 MHz clocks indicate dont care states.
4. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66/133 MHz.
Minimum and Maximum Lumped Capacitive Loads
Min.
Load
Max.
Load
Clock
Units
Notes
CPU
PCI
10
10
20
10
10
10
10
20
30
30
30
20
20
20
1 device load, possible 2 loads
Must meet PCI 2.1 requirements
PC100/PC133 specs
1 device load, possible 2 loads
1 device load,
SDRAM
3V66
pF
48MHz
REF
1 device load,
APIC
1 device load,
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
2
I C Considerations
1. Address Assignment: Any clock driver in this specification can use the single, 7 bit address shown below. All devices can use
the address if only one master clock driver is used in a design.
The following address was confirmed by Philips on 09/04/96.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W#
0
Note:
2
The R/W# bit is used by the I C controller as a data direction bit. A zero indicates a transmission (WRITE) to the clock device.
A one indicates a request for data (READ) from the clock driver. Since the definition of the clock buffer only allows the controller
to WRITE data; the R/W# bit of the address will always be seen as a zero.
2. Slave/Receiver: The clock driver is assumed to require only slave/receiver functionality.
3. Data Transfer Rate: 100 kbits/s (standard mode) is the base functionality.
4. Logic Levels: Assume all devices are based on a 3.3 Volt supply.
5. Data Byte Format: Byte format is 8-bits.
6. Data Protocol:
2
To simplify the clock I C interface, the clock driver serial protocol was specified to use only block writes from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. Indexed bytes are not allowed.
2
The clock driver must meet this protocol which is more rigorous than previously stated I C protocol. Treat the description from
the viewpoint of controller. The controller writes to the clock driver and if possible would read from the clock driver.
The block write begins with a slave address and a write condition. After the command code the host (controller) issues a byte
count which describes how many more bytes will follow in the message. If the host had 20 bytes to send, the first byte would
be the number 20 (14h), followed by the 20 bytes of data. The byte count may not be 0. A block write command is allowed
to transfer a maximum of 32 data bytes.”
Note: The acknowledgment bit is returned by the slave/receiver (the clock driver).
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software
programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of
additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is
required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. For example:
Byte count byte
Notes
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte.
Data for functional and frequency select register (currently byte 0 in spec)
Reads first two bytes of data (byte 0, then byte 1)
Reads first three bytes of data (byte 0, 1, 2 in order)
Reads first four bytes of data (byte 0, 1, 2, 3 in order)
Reads first five bytes of data (byte 0, 1, 2, 3, 4 in order)
Reads first six bytes of data (byte 0, 1, 2, 3, 4, 5 in order)
Reads first seven bytes of data (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller
interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the
bytes that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes
than the clock driver can handle.
7. Clock Stretching: The clock device must not hold/stretch the SCLK or SDATA lines low for more than 10 mS. Clock stretching is
discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/
time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without
the use of clock/data stretching.
8. General Call: It is assumed that the clock driver will not have to respond to the general call.
9. Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15
2
of the I C specification.
A) Pull-Up Resistors: There is a 100k internal resistor pull-ups on the SDATA and SCLK inputs. Assume that the board designer
2
will use a single external pull-up resistor for each line and that these values are in the 5-6K Ohm range. Assume one I C device
2
2
per DIMM (serial presence detect), one I C controller, one clock driver plus one/two more I C devices on the platform for capacitive
loading purposes.
2
B) Input Glitch Filters: Only fast mode I C devices require input glitch filters to suppress bus noise. The clock driver is specified
as a standard mode device and is not required to support this feature.
10. PWRDWN#: If a clock driver is placed in Power down mode, the SDATA and SCLK inputs are Tri-Stated and the device must retain
all programming information.
2
2
For specific I C information consult the Philips I C Peripherals Data Handbook ICI2 (1996)
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
PI6C110E Conditions
At power up all SDRAM outputs are enabled and active. The SDATA and SCLK inputs have internal pull-up resistors with values
above 100K Ohms as well for complete platform flexibility.
PI6C110E Serial Configuration Map
A) The serial bits will be read by the clock driver in the following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
B) All unused register bits (reserved and N/A) are designed as don't care. The controller will force all of these bits to a 0 level.
C) All reserved bits should be programmed to a logic level 0.
Note:
1. Default is for ALL clocks to be enabled and all reserved bits should be programmed to a logic level 0.
Spread spectrum modulation should power up disabled (Byte 0 bit 3 = 0).
Byte 0 : Control Register (1 = Enable, 0 = Disable)
Byte 1: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Pin Description
Bit
Pin#
36 SDRAM7
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
37 SDRAM6
39 SDRAM5
40 SDRAM4
42 SDRAM3
43 SDRAM2
45 SDRAM1
46 SDRAM0
(Active/Inactive)
(Active/Inactive)
Spread Spectrum
(1 = On / 0 = Off)
Bit 3
Bit 2
Bit 1
Bit 0
26 USB1
25 USB0
49 CPU2
Byte 3 and Byte 4:
Reserved Register (1 = Enable, 0 = Disable)
Byte 2: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
20 PCI7
Name
Pin Description
Bit
Pin#
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
Reserved Drive to '0'
19 PCI6
18 PCI5
16 PCI4
15 PCI3
13 PCI2
12 PCI1
(Active/Inactive)
(Active/Inactive)
Reserved Drive to '0'
Note: Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not
expected to be configured during the normal modes of operation.
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PI6C110E
Clock Solution for 133 MHz
Celeron/Pentium II/III Processors
Ordering Information
P/N
Description
PI6C110EV
56-pin SSOP Package
56 Pin SSOP Package Data
56
.291
.299
7.39
7.59
.396
.416
10.06
10.56
Gauge Plane
0.25
.02
.04
.010
0.51
1.01
1
.015 0.381
x 45˚
18.29
18.54
.720
.730
.008
0.20
.025 0.635
Nom.
.110 2.79
Max
.008
.0135
0.20
0.34
.025 BSC
0.635
0.20
0.40
.008
.016
0-8˚
X.XX
X.XX
DENOTES DIMENSIONS
IN MILLIMETERS
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
PS8410
08/11/99
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