PEEL16V8P-25 [ETC]
PEEL™6V8 -15/-25 CMOS Programmable Electrically Erasable Logic; PEEL ™ 6V8 -15 / -25 CMOS可编程电可擦除逻辑
| 型号： | PEEL16V8P-25 |
| 厂家： | 
ETC |
| 描述： | PEEL™6V8 -15/-25 CMOS Programmable Electrically Erasable Logic |
| 文件： | 总10页 (文件大小：207K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Commercial
PEEL 16V8 -15/-25
CMOS Programmable Electrically Erasable Logic
Features
■ Compatible with Popular 16V8 Devices
16V8 socket and function compatible
Programs with standard 16V8 JEDEC file
20-pin DIP and PLCC packages
■ I
CC
45mA typical I
CC
■ Development/Programmer Support
Third party software and programmers
ICT PLACE Development Software and
PDS-3 programmer
■ CMOS Electrically Erasable Technology
Superior factory testing
Automatic programmer translation and
JEDEC file translation software available
for the most popular PAL devices
Reprogrammable in plastic package
Reduces retrofit and development costs
■ Application Versatility
Replaces random logic
Super-sets standard 20-pin PLDs (PALs)
General Description
The PEEL16V8 is a Programmable Electrically
Erasable Logic (PEEL) device providing an attrac-
tive alternative to ordinary PLDs. The PEEL16V8
offers the performance, flexibility, ease-of-design
and production practicality needed by logic design-
ers today. The PEEL16V8 is available in 20-pin DIP
and PLCC packages (see Figure 1) with speeds
ranging from 15ns to 25ns and power consumption
less than 45mA. EE-reprogrammability provides the
convenience of instant reprogramming for develop-
ment and a reusable production inventory minimiz-
ing the impact of programming changes or errors.
EE-reprogrammability also improves factory test-
ability, thus ensuring the highest quality possible.
The PEEL16V8 architecture allows it to replace
standard 20-pin PAL devices. (See Figure 2). ICT’s
PEEL16V8 can be programmed with any existing
16V8 JEDEC file. Some programmers also allow
the PEEL16V8 to be programmed directly from PAL
16L8, 16R4, 16R6 and 16R8 JEDEC files. Addi-
tional development and programming support for
the PEEL16V8 is provided by popular third-party
programmers and development software. ICT also
offers free PLACE development software and a low-
cost development system (PDS-3).
Pin Configuration (Figure 1)
Block Diagram (Figure 2)
I/ CLK
VCC
I/ O
I
CLK
I/ O
I
I/ CLK
I/ O
I
PEEL
I
I/ O
I/ O
"AND"
I
ARRAY
I/ O
I
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
I/ O
MACRO
CELL
I/ O
I
I
64 TERMS
X
32 INPUTS
I/ O
GND
I/ OE
DIP
I/ OE
PLCC
3 - 7
PEEL 16V8
Functional Description
16 additional lines carry the true and complement
of 8 macrocell feedback signals or inputs from I/O
pins or the clock/OE pins
The PEEL16V8 implements logic functions as sum-
of-products expressions in a programmable-
AND/fixed-OR logic array. User-defined functions
are created by programming the connections of in-
put signals into the array. User-configurable output
structures in the form of macrocells further increase
logic flexibility.
64 product terms:
56 product terms (arranged in 8 groups of 7) form
sum-of-product functions for macrocell combina-
torial or registered logic
8 product terms (arranged 1 per macrocell) add an
additional product term for macrocell sum-of-prod-
ucts functions or I/O pin output enable control
Architecture Overview
The PEEL16V8 features ten dedicated input pins
and eight I/O pins, which allow a total of up to 16
inputs and 8 outputs for creating logic functions. At
the core of the device is a programmable electri-
cally-erasable AND array which drives a fixed OR
array. With this structure the PEEL16V8 can imple-
ment up to 8 sum-of-products logic expressions.
At each input-line/product-term intersection there is
an EEPROM memory cell which determines
whether or not there is a logical connection at that
intersection. Each product term is essentially a 32-
input AND gate. A product term which is connected to
both the true and complement of an input signal will
always be FALSE and thus will not affect the OR func-
tion that it drives. When all the connections on a product
term are opened, that term will always be TRUE.
Associated with each of the eight OR functions is a
macrocell which can be independently programmed
to one of up to four different basic configurations.
The programmable macrocells allow each I/O to
create sequential or combinatorial logic functions of
active-high or active-low polarity, while providing two
possible feedback paths into the array.
When programming the PEEL16V8, the device pro-
grammer first performs a bulk erase to remove the
previous pattern. The erase cycle opens every logical
connection in the array. The device is configured to
perform the user-defined function by programming
selected connections in the AND array. (Note that
PEEL device programmers automatically program all
of the connections on unused product terms so that
they will have no effect on the output function.)
Three different device modes, Simple, Complex and
Registered, support various user configurations. In
Simple mode, a macrocell can be configured for
combinatorial function with the output buffer perma-
nently enabled, or the output buffer can be disabled
and the I/O pin used as a dedicated input. In Com-
plex mode, a macrocell is configured for combina-
torial function with the output buffer enable control-
led by a product term. In Registered mode, a macro-
cell can be configured for registered operation with
the register clock and output buffer enable control-
led directly from pins, or can be configured for com-
binatorial function with the output buffer enable con-
trolled by a product term. In most cases, the device
mode is set automatically by the development soft-
ware based on the features specified in the design.
Table 1. PEEL16V8/PAL Device Compatibility
PAL Architecture
PEEL16V8
Compatibility
Device Mode
10H8
10L8
10P8
12H6
12L6
12P6
14H4
14L4
14P4
16H2
16HD8
16L2
16LD8
16P2
16H8
16L8
16P8
16R4
16R6
Simple
Simple
The three device modes support designs created
explicitly for the PEEL16V8, as well as designs cre-
ated originally for popular PAL devices such as the
16R4, 16R8 and 16L8. Table 1 shows the device
mode used to emulate the various PALs. Design
conversion into the 16V8 is accommodated by
JEDEC-to-JEDEC translators available from ICT, as
well as several programmers which can read the
original PAL JEDEC file and automatically program
the 16V8 to perform the same function.
Simple
Simple
Simple
Simple
Simple
Simple
Simple
Simple
AND/OR Logic Array
Simple
Simple
The programmable AND array of the PEEL16V8 is
formed by input lines intersecting product terms.
The input lines and product terms are used as fol-
lows:
Simple
Simple
Complex
Complex
Complex
Registered
Registered
32 input lines:
16 input lines carry the true and complement of
the signals applied to the 8 dedicated input pins
3 - 8
PEEL 16V8
Simple Mode
16R8
16RP4
16RP6
14RP8
Registered
Registered
Registered
Registered
In Simple mode, all eight product terms feed the OR
array which can generate a purely combinatorial
function for the output pin. The programmable out-
put polarity selector allows active-high or active-low
logic, eliminating the need for external inverters.
For output functions, the buffer can be permanently
enabled. Feedback into the array is available on all
macrocell I/O pins, except for pins 15 and 16. Figure
Programmable Macrocell
The macrocell provides complete control over the
architecture of each output. The ability to configure
each output independently permits users to tailor
the configuration of the PEEL16V8 to the precise
requirements of their designs.
1
2
Sim p le Mod e
Ac tive Low Outp ut
Sim p le Mod e
Ac tive Hig h Outp ut
Macrocell Architecture
VCC
VCC
Each macrocell consists of an OR function, a D-type
flip-flop, an output polarity selector, and a program-
mable feedback path. Four EEPROM architecture
bits MS0, MS1, OP and RC control the configuration
of each macrocell. Bits MS0 and MS1 are global,
and select between Simple, Complex and Regis-
tered mode for the whole device. Bits OP and RC
are local for each macrocell; bit OP controls the
output polarity and bit RC selects between regis-
tered and combinatorial operation and also speci-
fies the feedback path. Table 2 shows the architec-
ture bit settings for each possible configuration.
3
Sim p le Mod e
I/ O Pin Inp ut
Equivalent circuits for the possible macrocell con-
figurations are illustrated in Figures 3, 4 and 5.
When creating a PEEL device design, the desired
macrocell configuration generally is specified explic-
itly in the design file. When the design is assembled
or compiled, the macrocell configuration bits are
defined in the last lines of the JEDEC programming
file.
Figure 3. Macrocell Configurations for the Simple
Mode of the PEEL16V8
Table 2. PEEL16V8 Device Mode/Macrocell Architecture Configuration Bits
Config.
#
Mode
Architecture Bits
Function
Polarity
Feedback
I/O Pin
MS0
1
MS1
0
OP
0
RC
0
1
2
3
1
2
1
2
3
4
Simple
Combinatorial
Combinatorial
None
Active Low
Active High
None
Simple
1
0
1
0
I/O Pin
Simple
1
0
X
0
1
I/O Pin
Complex
Complex
Registered
Registered
Registered
Registered
1
1
1
Combinatorial
Combinatorial
Registered
Active Low
Active High
Active Low
Active High
Active Low
Active High
I/O Pin
1
1
1
1
I/O Pin
0
1
0
0
Registered
Registered
I/O Pin
0
1
1
0
Registered
0
1
0
1
Combinatorial
Combinatorial
0
1
1
1
I/O Pin
3 - 9
PEEL 16V8
2
1
Re g iste re d Mod e
Re g iste re d Mod e
6 shows the logic array of the PEEL16V8 configured
in Simple mode.
Ac tive Hig h Re g iste re d Outp ut
Ac tive Low Re g iste re d Outp ut
OE PIN
OE PIN
Simple mode also provides the option of configuring
an I/O pin as a dedicated input. In this case, the
output buffer is permanently disabled and the I/O
pin feedback is used to bring the input signal from
the pin into the logic array. This option is available
for all I/O pins except pins 15 and 16.
D
Q
Q
D
Q
Q
CLK PIN
CLK PIN
3
4
Re g iste re d Mod e
Ac tive Low Com b ina toria l Outp ut
Re g iste re d Mod e
Ac tive Hig h Com b ina toria l Outp ut
Complex Mode
PRODUCT TERM
PRODUCT TERM
In Complex mode, seven product terms feed the OR
array which can generate a purely combinatorial
2
1
Com p le x Mod e
Ac tive L ow Outp ut
Com p le x Mod e
Ac tive Hig h Outp ut
PRODUCT T ERM
PRODUCT T ERM
Figure 5. Macrocell Configurations for the Regis-
tered Mode of the PEEL16V8
The programmable output polarity selector provides
active-high or active-low logic. The output buffer en-
able is controlled by the eighth product term, allow-
ing the macrocell to be configured for input, output
or bidirectional functions. Feedback into the array
for input or bidirectional functions is available on all
I/O pins.
Figure 4. Macrocell Configurations for the Com-
plex Mode of the PEEL16V8
function for the output pin. The programmable out-
put polarity selector provides active-high or active-
low logic, eliminating the need for external inverters.
The output buffer is controlled by the eighth product
term, allowing the macrocell to be configured for
input, output or bidirectional functions. Feedback
into the array for input or bidirectional functions is
available on all pins except 12 and 19. Figure 7
shows the logic array of the PEEL16V8 configured
in Complex mode.
Design Security
The PEEL16V8 provides a special EEPROM secu-
rity bit that prevents unauthorized reading or copy-
ing of designs programmed into the device. The
security bit is set by the PLD programmer, either at
the conclusion of the programming cycle or as a
separate step after the device has been pro-
grammed. Once the security bit has been set, it is
impossible to verify (read) or program the PEEL
until the entire device has first been erased with the
bulk-erase function.
Registered Mode
In Registered mode, eight product terms are pro-
vided to the OR array for registered functions. The
programmable output polarity selector provides ac-
tive-high or active-low logic, eliminating the need for
external inverters. (Note, however, that PEEL16V8
registers power-up reset and so before the first
clock arrives, the output at the pin will be low if the
user has selected active-high logic and high if the
user has selected active-low logic.) For registered
functions, the output buffer enable is controlled di-
rectly from the /OE control pin. Feedback into the
array comes from the macrocell register. In Regis-
tered mode, input pins 1 and 11 are permanently
allocated as CLK and /OE, respectively. Figure 8
shows the logic array of the PEEL16V8 configured
in Registered mode.
Signature Word
The signature word feature allows a 64-bit code to
be programmed into the PEEL16V8. The code can-
not be read back after the security bit has been set.
The signature word can be used to identify the
pattern programmed into the device or to record the
design revision, etc.
Registered mode also provides the option of config-
uring a macrocell for combinatorial operation, with
seven product terms feeding the OR function.
3 - 10
PEEL 16V8
1
2
I
I
I/ O
19
MACRO
CELL
I/ O
18
MACRO
CELL
3
I
I
I
17 I/ O
MACRO
CELL
4
16 I/ O
MACRO
CELL
5
I/ O
15
MACRO
CELL
6
I
I
I
I
14 I/ O
13 I/ O
12 I/ O
MACRO
CELL
7
8
9
MACRO
CELL
MACRO
CELL
11
I
Figure 6. PEEL16V8 Logic Array - Simple Mode
3 - 11
PEEL 16V8
1
2
I
I
I/ O
19
MACRO
CELL
I/ O
18
MACRO
CELL
3
I
I
I
17 I/ O
MACRO
CELL
4
16 I/ O
MACRO
CELL
5
I/ O
15
MACRO
CELL
6
I
I
I
I
14 I/ O
13 I/ O
12 I/ O
MACRO
CELL
7
8
9
MACRO
CELL
MACRO
CELL
11
I
Figure 7. PEEL16V8 Logic Array - Complex Mode
3 - 12
PEEL 16V8
1
2
CLK
I/ O
19
MACRO
CELL
I
I/ O
18
MACRO
CELL
3
I
I
I
17 I/ O
MACRO
CELL
4
16 I/ O
MACRO
CELL
5
I/ O
15
MACRO
CELL
6
I
I
I
I
14 I/ O
13 I/ O
12 I/ O
MACRO
CELL
7
8
9
MACRO
CELL
MACRO
CELL
11
OE
Figure 8. PEEL16V8 Logic Array - Registered Mode
3 - 13
PEEL 16V8
This device has been designed and tested for the
specified operating ranges. Proper operation outside
of these levels is not guaranteed. Exposure to abso-
lute maximum ratings may cause permanent damage.
Absolute Maximum Ratings
Rating
-0.5 to + 7.0
-0.5 to VCC + 0.6
±25
Unit
V
Symbol Parameter
Conditions
VCC
VI, VO
IO
Supply Voltage
Relative to Ground
Relative to Ground1
Voltage Applied to Any Pin2
V
Output Current
Per pin (IOL, IOH
)
mA
°C
°C
TST
TLT
Storage Temperature
Lead Temperature
-65 to +150
+300
Soldering 10 seconds
Operating Ranges
Min
4.75
0
Max
5.25
+70
20
Unit
V
Symbol Parameter
Conditions
Commercial
Commercial
See Note 3
See Note 3
See Note 3
VCC
TA
Supply Voltage
Ambient Temperature
Clock Rise Time
Clock Fall Time
VCC Rise Time
°C
ns
TR
TF
20
ns
TRVCC
250
ms
D.C. Electrical Characteristics Over the operating range
Min
Max
Unit
V
Symbol Parameter
Conditions
VOH
VOL
VIH
VIL
IIL
Output HIGH Voltage
VCC=Min, IOH=-4.0mA
VCC=Min, IOL=16mA
2.4
Output LOW Voltage
0.5
VCC + 0.3
0.8
V
Input HIGH Voltage
2.0
V
Input LOW Voltage
-0.3
V
Input Leakage Current LOW
Input Leakage Current HIGH
Output Leakage Current
Output Short Circuit Current
VCC = Max, VIN = GND
0 (Typ)
0 (Typ)
-10
µA
µA
µA
mA
IIH
40
VCC = Max, VIN = VCC
IOZ
ISC
I/O = High-Z, GND ≤ VO ≤ VCC
VCC = 5V, VO = 0.5V9, TA = 25°C
±10
-30
-150
45
VIN = 0V or 3V
f = 25MHz
-15
-25
10
7
ICC
VCC Current
mA
All outputs disabled4
37
7
CIN
Input Capacitance
Output Capacitance
6
pF
pF
TA = 25°C, VCC = 5.0V
@ f = 1MHz
COUT
12
3 - 14
PEEL 16V8
8, 11
A.C. Electrical Characteristics
Over the Operating Range
-15
-25
Unit
Symbol Parameter
Min
3
Max
15
Min
Max
tPD
Input5 to non-registered output
Input5 to output enable6
Input5 to output disable6
Clock to output
3
3
3
2
25
20
20
12
ns
ns
ns
ns
tOE
tOD
tCO1
3
15
3
15
2
10
Clock to comb. output delay via
internal registered feedback
tCO2
25
8
35
10
ns
tCF
tSC
tHC
Clock to Feedback
ns
ns
Input5 or feedback setup to clock
Input5 hold after clock
12
0
15
0
ns
tCL, tCH Clock low time, clock high time8
8
12
27
40
37
41.6
25
ns
tCP
Min clock period Ext (tSC + tCO1
)
22
ns
12
fMAX1
fMAX2
fMAX3
tAW
Internal Feedback (1/tSC+tCF
)
50
MHz
MHz
MHz
ns
12
External Feedback (1/tCP
)
45.5
62.5
15
12
No Feedback (1/tCL+tCH
)
Asynchronous Reset pulse width
Input5 to Asynchronous Reset
Asynch. Reset recovery time
tAP
15
15
25
25
ns
tAR
ns
Power-on reset time for
registers in clear state
tRESET
5
5
µs
Switching Waveforms
Inputs, I/O,
Registered Feedback,
Synchronous Preset
Clock
Asynchronous
Reset
Registered
Outputs
Combinatorial
Outputs
Notes
1. Minimum DC input is -0.5V, however inputs may
undershoot to -2.0V for periods less than 20ns.
2. VI and VO are not specified for program/verify
operation.
8. Test conditions assume: signal transition times of 3ns
or less from the 10% and 90% points, timing reference
levels of 1.5V (unless otherwise specified).
9. Test one output at a time for a duration of less than 1
sec.
10. ICC for a typical application: This parameter is tested
with the device programmed as an 8-bit Counter.
11. PEEL Device test loads are specified in Section 6 of
the Data Book.
12. Parameters are not 100% tested. Specifications are
based on initial characterization and are tested after
any design or process modification which may affect
operational frequency.
3. Test points for Clock and VCC in tR, tF are referenced at
10% and 90% levels.
4. I/O pins are 0V and 3V.
5. “Input” refers to an Input pin signal.
6.
tOE is measured from input transition to VREF ± 0.1V,
tOD is measured from input transition to VOH - 0.1V or
VOL + 0.1V; VREF = VL see test loads in Section 6 of the
Data Book.
7. Capacitances are tested on a sample basis.
3 - 15
PEEL 16V8
Ordering Information
PART NUMBER
PEEL16V8P-15
PEEL16V8J-15
PEEL16V8P-25
PEEL16V8J-25
SPEED
15ns
TEMPERATURE
PACKAGE
P20
C
C
C
C
15ns
J20
25ns
P20
25ns
J20
Part Number
Device
Suffix
PEEL16V8P-25
Speed
-15
-25
=
=
15ns tpd
25ns tpd
Package
P = Plastic 300mil DIP
J = Plastic (J) Leaded Chip Carrier (PLCC)
3 - 16
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