OR4E4-3BC432 概述
FPGA
FPGA产品将打
OR4E4-3BC432 数据手册
通过下载OR4E4-3BC432数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载Product Brief
January 15, 2002
®
ORCA Series 4
Field-Programmable Gate Arrays
■ Traditional I/O selections:
— LVTTL and LVCMOS (3.3 V, 2.5 V, and 1.8 V)
I/Os.
Introduction
Built on the Series 4 reconfigurable embedded sys-
tem-on-chip (SoC) architecture, Lattice introduces its
new family of generic field-programmable gate arrays
(FPGA). The high-performance and highly versatile
architecture brings a new dimension to bringing net-
work system designs to market in less time than ever
before. This new device family offers many new fea-
tures and architectural enhancements not available
in any earlier FPGA generations. Bringing together
highly flexible SRAM-based programmable logic,
powerful system features, a rich hierarchy of routing
and interconnect resources, and meeting multiple
interface standards, the Series 4 FPGA accommo-
dates the most complex and high-performance intel-
lectual property (IP) network designs.
— Per pin-selectable I/O clamping diodes provide
3.3 V PCI compliance.
— Individually programmable drive capability:
24 mA sink/12 mA source, 12 mA sink/6 mA
source, or 6 mA sink/3 mA source.
— Two slew rates supported (fast and slew-lim-
ited).
— Fast-capture input latch and input flip-flop
(FF)/latch for reduced input setup time and zero
hold time.
— Fast open-drain drive capability.
— Capability to register 3-state enable signal.
— Off-chip clock drive capability.
— Two-input function generator in output path.
■ New programmable high-speed I/O:
— Single-ended: GTL, GTL+, PECL, SSTL3/2
(class I and II), HSTL (Class I, III, and IV), ZBT,
and DDR.
— Double-ended: LDVS, bused-LVDS, and
LVPECL. Programmable (on/off) internal parallel
termination (100 Ω) also supported for these
I/Os.
Programmable Features
■ High-performance platform design:
— 0.16 µm 7-level metal technology.
— Internal performance of >250 MHz.
— I/O performance of >420 MHz.
— Meets multiple I/O interface standards.
— 1.5 V operation (30% less power than 1.8 V
operation) translates to greater performance.
Table 1. ORCA Series 4—Available FPGA Logic
EBR
Blocks
EBR Bits
(K)
Usable*
Gates (K)
Device
Rows
Columns
PFUs
User I/O
LUTs
OR4E2
OR4E4
OR4E6
26
36
46
24
36
44
624
1296
2024
400
576
720
4,992
10,368
16,192
8
74
260—515
380—800
515—1095
12
16
111
147
* The usable gate counts range from a logic-only gate count to a gate count assuming 20% of the PFUs/SLICs being used as RAMs. The
logic-only gate count includes each PFU/SLIC (counted as 108 gates/PFU), including 12 gates per LUT/FF pair (eight per PFU) and
12 gates per SLIC/FF pair (one per PFU). Each of the four PIO groups are counted as 16 gates (three FFs, fast-capture latch, output
logic, CLK, and I/O buffers). PFUs used as RAM are counted at four gates per bit, with each PFU capable of implementing a 32 x 4 RAM
(or 512 gates) per PFU. Embedded block RAM (EBR) is counted as four gates per bit, plus each block has an additional 25 K gates.
7 K gates are used for each PLL and 50K gates for the embedded system bus and microprocessor interface logic. Both the EBR and
PLLs are conservatively utilized in the gate count calculations.
Note: Devices are not pinout compatible with ORCA Series 2/3.
ORCA Series 4
Field-Programmable Gate Arrays
Product Brief
January 15, 2002
■ Improved built-in clock management with program-
mable phase-locked loops (PPLLs) provide optimum
clock modification and conditioning for phase, fre-
quency, and duty cycle from 20 MHz up to 420 MHz.
Multiplication of the input frequency up to 64x, and
division of the input frequency down to 1/64x, is pos-
sible.
Programmable Features (continued)
■ New capability to (de)multiplex I/O signals:
— New double data rate on both input and output at
rates up to 350 MHz (700 MHz effective rate).
— New 2x and 4x downlink and uplink capability per
I/O (i.e., 50 MHz internal to 200 MHz I/O).
■ New 200 MHz embedded quad-port RAM blocks,
two read ports, two write ports, and two sets of byte
lane enables. Each embedded RAM block can be
configured as:
— 1-512 x 18 (quad-port, two read/two write) with
optional built in arbitration.
— 1-256 x 36 (dual-port, one read/one write).
— 1-1K x 9 (dual-port, one read/one write).
— 2-512 x 9 (dual-port, one read/one write for each).
— 2 RAMS with arbitrary number of words whose
sum is 512 or less by 18 (dual-port, one read/one
write).
— Supports joining of RAM blocks.
— Two 16 x 8-bit content addressable memory
(CAM) support.
— FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.
— Constant multiply (8 x 16 or 16 x 8).
— Dual-variable multiply (8 x 8).
■ Enhanced twin-quad programmable function unit
(PFU):
— Eight 16-bit look-up tables (LUTs) per PFU.
— Nine user registers per PFU, one following each
LUT and organized to allow two nibbles to act
independently, plus one extra for arithmetic opera-
tions.
— New register control in each PFU has two inde-
pendent programmable clocks, clock enables,
local set/reset, and data selects.
— New LUT structure allows flexible combinations of
LUT4, LUT5, new LUT6, 4 to 1 MUX, new
8 to 1 MUX, and ripple mode arithmetic functions
in the same PFU.
— 32 x 4 RAM per PFU, configurable as single- or
dual-port. Create large, fast RAM/ROM blocks
(128 x 8 in only eight PFUs) using the SLIC
decoders as bank drivers.
— Soft-wired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU
through fast internal routing, which reduces rout-
ing congestion and improves speed.
— Flexible fast access to PFU inputs from routing.
— Fast-carry logic and routing to all four adjacent
PFUs for nibble-, byte-wide, or longer arithmetic
functions, with the option to register the PFU
carry-out.
■ Embedded 32-bit internal system bus plus 4-bit par-
ity interconnects FPGA logic, microprocessor inter-
face (MPI), embedded RAM blocks, and embedded
standard cell blocks with 100 MHz bus performance.
Included are built-in system registers that act as the
control and status center for the device.
■ Built-in testability:
— Full boundary scan (IEEE ® 1149.1 and Draft
1149.2 joint test access group (JTAG)).
— Programming and readback through boundary
scan port compliant to IEEE Draft 1532:D1.7.
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
■ Abundant high-speed buffered and nonbuffered rout-
ing resources provide 2x average speed improve-
ments over previous architectures.
■ Hierarchical routing optimized for both local and glo-
bal routing with dedicated routing resources. This
results in faster routing times with predictable and
efficient performance.
■ New cycle stealing capability allows a typical 15% to
40% internal speed improvement after final place
and route. This feature also enables compliance with
many setup/hold and clock-to-out I/O specifications,
and may provide reduced ground bounce for output
buses by allowing flexible delays of switching output
buffers.
■ SLIC provides eight 3-statable buffers, up to 10-bit
decoder, and PAL™-like and-or-invert (AOI) in each
programmable logic cell.
2
Lattice Semiconductor
ORCA Series 4
Field-Programmable Gate Arrays
Product Brief
January 15, 2002
■ New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
System Features
■ PCI local bus compliant.
®
■ New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
■ Improved PowerPC /PowerQUICC MPC860 and
PowerPC II MPC8260 high-speed synchronous
microprocessor interface can be used for configura-
tion, readback, device control, and device status, as
well as for a general-purpose interface to the FPGA
logic, RAMs, and embedded standard cell blocks.
Glueless interface to synchronous PowerPC proces-
sors with user-configurable address space is pro-
vided.
■ Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed specifications for UTOPIA level 4, POS-
PHY Level 3 (2.5 Gbits/s), and POS-PHY 4
(10 Gbits/s) interface standards for packet-over-
SONET as defined by the Saturn Group.
■ New embedded AMBA™ specification 2.0 AHB sys-
tem bus (ARM ™ processor) facilitates communica-
tion among the microprocessor interface,
configuration logic, embedded block RAM, FPGA
logic, and embedded standard cell blocks.
■ ORCA Foundry development system software s
upported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
■ New network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
■ Variable size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
■ Internal, 3-state, bidirectional buses with simple con-
trol provided by the SLIC.
■ New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 ps for OR4E4).
■ New local clock routing structures allow creation of
localized clock trees.
■ Two new edge clock routing structures allow up to six
high-speed clocks on each edge of the device for
improved setup/hold and clock-to-out performance.
Lattice Semiconductor
3
ORCA Series 4
Field-Programmable Gate Arrays
Product Brief
January 15, 2002
System Features (continued)
EMBEDDED
BLOCK RAM
HIGH-SPEED I/Os
EMBEDDED
MICROPROCESSOR
INTERFACE (MPI)
REPLACED BY
EMBEDDED IP
CORE FOR FPSCs
SYSTEM BUS
CLOCK PINS
(ALL 4 SIDES)
PFU
SLIC
PLC
PIO
FPGA/SYSTEM
BUS INTERFACE
PLLs
(ALL 4
CORNERS)
5-7536(F).a
Figure 1. Series 4 FPGA Block Diagram
4
Lattice Semiconductor
ORCA Series 4
Field-Programmable Gate Arrays
Product Brief
January 15, 2002
Ordering Information
OR4Exx –1 BM 680
TEMPERATURE RANGE
NUMBER OF PINS
DEVICE TYPE
SPEED GRADE
PACKAGE TYPE
5-6435 (F).l
OR4Exx, –1 Speed Grade, 680-pin Plastic Ball Grid Array Multilayer (PBGAM)
Table 2. Device Type Options
Device
Voltage
1.5 V internal
3.3 V/2.5 V/1.8 V/1.5 V I/O
OR4Exx
Table 3.Temperature Options
Symbol Description Ambient Temperature
(Blank) Industrial –40 ˚C to +85 ˚C
Note: Device junction temperature of –40 ˚C to +125 ˚C are recommended.
Table 4. Package Options
Symbol
Description
BA
BC
BM
Plastic Ball Grid Array (PBGA)
Enhanced Ball Grid Array (EBGA)
Plastic Ball Grid Array, Multilayer (PBGAM)
Table 5. ORCA OR4EXX Series Package Matrix (Speed Grade)
256-Pin
352-Pin
416-Pin
432-Pin
680-Pin
Devices
FSBGA(BA) PBGA(BA) PBGAM(BA) EBGA(BC) PBGAM(BM)
OR4E2
OR4E4
OR4E6
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
—
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
–1, –2, –3
—
—
Lattice Semiconductor
5
IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
PowerPC is a registered trademark of International Business Machines, Inc.
AMBA and ARM are trademarks of Advanced RISC Machines Limited.
www.latticesemi.com
Copyright © 2002 Lattice Semiconductor
All Rights Reserved
Printed in U.S.A.
January 15, 2002
PB02-027NCIP (Replaces PB01-046NCIP)
OR4E4-3BC432 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
OR4E4-3BM680 | ETC | FPGA | 获取价格 | |
OR4E6 | AGERE | Field-Programmable Gate Arrays | 获取价格 | |
OR4E6-1BA352 | ETC | FPGA | 获取价格 | |
OR4E6-1BC432 | ETC | FPGA | 获取价格 | |
OR4E6-1BM680 | ETC | FPGA | 获取价格 | |
OR4E6-2BA352 | ETC | FPGA | 获取价格 | |
OR4E6-2BC432 | LATTICE | Field Programmable Gate Array, 2024 CLBs, 515000 Gates, CMOS, PBGA432, PLASTIC, BGA-432 | 获取价格 | |
OR4E6-2BM680 | ETC | FPGA | 获取价格 | |
OR4E6-3BA352 | LATTICE | Field Programmable Gate Array, 2024 CLBs, 515000 Gates, CMOS, PBGA256, PLASTIC, BGA-256 | 获取价格 | |
OR4E6-3BC432 | ETC | FPGA | 获取价格 |
OR4E4-3BC432 相关文章
- 2024-09-20
- 6
- 2024-09-20
- 9
- 2024-09-20
- 8
- 2024-09-20
- 6