NS32081-10 [ETC]
;
| 型号： | NS32081-10 |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总18页 (文件大小：232K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 1988
NS32081-10/NS32081-15 Floating-Point Units
General Description
The NS32081 Floating-Point Unit functions as a slave proc-
Features
Y
Eight on-chip data registers
Y
essor in National Semiconductor’s Series 32000 micro-
32-bit and 64-bit operations
É
Y
processor family. It provides a high-speed floating-point in-
struction set for any Series 32000 family CPU, while remain-
ing architecturally consistent with the full two-address archi-
tecture and powerful addressing modes of the Series 32000
micro-processor family.
Supports proposed IEEE standard for binary floating-
point arithmetic, Task P754
Y
Directly compatible with NS32016, NS32008 and
NS32032 CPUs
High-speed XMOSTM technology
Single 5V supply
Y
Y
Y
24-pin dual in-line package
Block Diagram
TL/EE/5234–1
TRI-STATEÉ and Series 32000É are registered trademarks of National Semiconductor Corp.
XMOSTM is a trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/EE/5234
RRD-B30M105/Printed in U. S. A.
Table of Contents
1.0 PRODUCT INTRODUCTION
3.0 FUNCTIONAL DESCRIPTION (Continued)
3.4 Bus Operation
1.1 Operand Formats
3.4.1 Bus Cycles
1.1.1 Normalized Numbers
1.1.2 Zero
3.4.2 Operand Transfer Sequences
1.1.3 Reserved Operands
1.1.4 Integers
3.5 Instruction Protocols
3.5.1 General Protocol Sequence
3.5.2 Floating-Point Protocols
1.1.5 Memory Representations
2.0 ARCHITECTURAL DESCRIPTION
4.0 DEVICE SPECIFICATIONS
2.1 Programming Model
4.1 Pin Descriptions
2.1.1 Floating-Point Registers
4.1.1 Supplies
2.1.2 Floating-Point Status Register (FSR)
2.1.2.1 FSR Mode Control Fields
2.1.2.2 FSR Status Fields
4.1.2 Input Signals
4.1.3 Input/Output Signals
4.2 Absolute Maximum Ratings
4.3 Electrical Characteristics
4.4 Switching Characteristics
2.1.2.3 FSR Software Field (SWF)
2.2 Instruction Set
2.2.1 General Instruction Format
2.2.2 Addressing Modes
4.4.1 Definitions
4.4.2 Timing Tables
2.2.3 Floating-Point Instruction Set
4.4.2.1 Output Signals: Internal Propagation De-
lays
2.3 Traps
4.4.2.2 Input Signals Requirements
4.4.2.3 Clocking Requirements
4.4.3 Timing Diagrams
3.0 FUNCTIONAL DESCRIPTION
3.1 Power and Grounding
3.2 Clocking
3.3 Resetting
2
List of Illustrations
Floating-Point Operand Formats ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-1
Register SetÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-1
The Floating-Point Status Register ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-2
General Instruction Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-3
Index Byte Format ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-4
Displacement EncodingsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-5
Floating-Point Instruction FormatsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-6
Recommended Supply Connections ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-1
Power-On Reset Requirements ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-2
General Reset Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-3
System Connection Diagram ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-4
Slave Processor Read CycleÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-5
Slave Processor Write CycleÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-6
FPU Protocol Status Word FormatÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-7
Dual-In-Line PackageÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-1
Timing Specification Standard (Signal Valid After Clock Edge)ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-2
Timing Specification Standard (Signal Valid Before Clock Edge) ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-3
Clock Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-4
Power-On-Reset ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-5
Non-Power-On-ResetÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-6
Read Cycle From FPU ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-7
Write Cycle To FPU ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-8
SPC Pulse from FPU ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-9
RST Release Timing ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ4-10
List of Tables
Sample F Fields ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-1
Sample E Fields ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-2
Normalized Number RangesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ1-3
Series 32000 Family Addressing ModesÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ2-1
General Instruction Protocol ÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-1
Floating-Point Instruction ProtocolsÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀÀ3-2
3
1.0 Product Introduction
TABLE 1-2. Sample E Fields
The NS32081 Floating-Point Unit (FPU) provides high
speed floating-point operations for the Series 32000 family,
and is fabricated using National high-speed XMOS technol-
ogy. It operates as a slave processor for transparent expan-
sion of the Series 32000 CPU’s basic instruction set. The
FPU can also be used with other microprocessors as a pe-
ripheral device by using additional TTL interface logic. The
NS32081 is compatible with the IEEE Floating-Point For-
mats by means of its hardware and software features.
E Field
F Field
100 . . . 0
100 . . . 0
100 . . . 0
Represented Value
b
1
c
e
0.75
011 . . . 110
011 . . . 111
100 . . . 000
1.5
2
0
1
c
e
e
1.5
2
2
1.50
3.00
c
1.5
Two values of the E field are not exponents. 11 . . . 11 sig-
nals a reserved operand (Section 2.1.3). 00 . . . 00 repre-
sents the number zero if the F field is also all zeroes, other-
wise it signals a reserved operand.
1.1 OPERAND FORMATS
The S bit indicates the sign of the operand. It is 0 for posi-
tive and 1 for negative. Floating-point numbers are in sign-
magnitude form, that is, only the S bit is complemented in
order to change the sign of the represented number.
The NS32081 FPU operates on two floating-point data
typesÐsingle precision (32 bits) and double precision (64
bits). Floating-point instruction mnemonics use the suffix F
(Floating) to select the single precision data type, and the
suffix L (Long Floating) to select the double precision data
type.
1.1.1 Normalized Numbers
Normalized numbers are numbers which can be expressed
as floating-point operands, as described above, where the E
field is neither all zeroes nor all ones.
A floating-point number is divided into three fields, as shown
in Figure 1-1.
The value of a Normalized number can be derived by the
formula:
The F field is the fractional portion of the represented num-
ber. In Normalized numbers (Section 1.1.1), the binary point
is assumed to be immediately to the left of the most signifi-
cant bit of the F field, with an implied 1 bit to the left of the
binary point. Thus, the F field represents values in the range
S
1)
(E-Bias)
c
2
b
c
a
(1 F)
(
The range of Normalized numbers is given in Table 1-3.
1.1.2 Zero
s
s
1.0
x
2.0.
There are two representations for zeroÐpositive and nega-
tive. Positive zero has all-zero F and E fields, and the S bit is
zero. Negative zero also has all-zero F and E fields, but its S
bit is one.
TABLE 1-1. Sample F Fields
F Field
000 . . . 0
010 . . . 0
100 . . . 0
110 . . . 0
Binary Value
1.000 . . . 0
1.010 . . . 0
1.100 . . . 0
1.110 . . . 0
Decimal Value
1.000 . . . 0
1.250 . . . 0
1.500 . . . 0
1.750 . . . 0
1.1.3 Reserved Operands
The proposed IEEE Standard for Binary Floating-Point Arith-
metic (Task P754) provides for certain exceptional forms of
floating-point operands. The NS32081 FPU treats these
forms as reserved operands. The reserved operands are:
u
Implied Bit
Positive and negative infinity
#
#
#
The E field contains an unsigned number that gives the bi-
nary exponent of the represented number. The value in the
E field is biased; that is, a constant bias value must be sub-
tracted from the E field value in order to obtain the true
Not-a-Number (NaN) values
Denormalized numbers
Both Infinity and NaN values have all ones in their E fields.
Denormalized numbers have all zeroes in their E fields and
non-zero values in their F fields.
exponent. The bias value is 011 . . . 11 , which is either 127
2
(single precision) or 1023 (double precision). Thus, the true
exponent can be either positive or negative, as shown in
Table 1-2.
The NS32081 FPU causes an Invalid Operation trap (Sec-
tion 2.1.2.2) if it receives a reserved operand, unless the
operation is simply a move (without conversion). The FPU
does not generate reserved operands as results.
Single Precision
31 30
23 22
0
S
1
E
8
F
23
Double Precision
63 62
52 51
0
S
1
E
F
11
52
FIGURE 1-1. Floating-Point Operand Formats
4
1.0 Product Introduction (Continued)
TABLE 1-3. Normalized Number Ranges
Single Precision
b
Double Precision
b
52
127
23
1023
c
b
3.40282346 10
c
b
(2 2
Most Positive
Least Positive
Least Negative
Most Negative
2
(2
2
)
2
)
38
308
e
c
e
c
1.7976931348623157 10
2b
1022
2b
126
b
b
308
38
e
c
1.17549436 10
e
c
2.2250738585072014 10
b
b
1022
126
b
b
(2
)
(2
)
b
b
308
38
eb
c
1.17549436 10
eb
c
2.2250738585072014 10
b
b
52
127
23
1023
2
b
c
b
3.40282346 10
b
c
b
2
2
(2
2
)
(2
)
38
308
eb
c
eb
c
1.7976931348623157 10
Note: The values given are extended one full digit beyond their represented accuracy to help in generating rounding and conversion algorithms.
1.1.4 Integers
2.1.1 Floating-Point Registers
In addition to performing floating-point arithmetic, the
NS32081 FPU performs conversions between integer and
floating-point data types. Integers are accepted or generat-
ed by the FPU as two’s complement values of byte (8 bits),
word (16 bits) or double word (32 bits) length.
There are eight registers (F0–F7) on the NS32081 FPU for
providing high-speed access to floating-point operands.
Each is 32 bits long. A floating-point register is referenced
whenever a floating-point instruction uses the Register ad-
dressing mode (Section 2.2.2) for a floating-point operand.
All other Register mode usages (i.e., integer operands) refer
to the General Purpose Registers (R0–R7) of the CPU, and
the FPU transfers the operand as if it were in memory.
When the Register addressing mode is specified for a dou-
ble precision (64-bit) operand, a pair of registers holds the
operand. The programmer must specify the even register of
the pair. The even register contains the least significant half
of the operand and the next consecutive register contains
the most significant half.
1.1.5 Memory Representations
The NS32081 FPU does not directly access memory. How-
ever, it is cooperatively involved in the execution of a set of
two-address instructions with its Series 32000 Family CPU.
The CPU determines the representation of operands in
memory.
In the Series 32000 family of CPUs, operands are stored in
memory with the least significant byte at the lowest byte
address. The only exception to this rule is the Immediate
addressing mode, where the operand is held (within the in-
struction format) with the most significant byte at the lowest
address.
2.1.2 Floating-Point Status Register (FSR)
The Floating-Point Status Register (FSR) selects operating
modes and records any exceptional conditions encountered
during execution of a floating-point operation. Figure 2-2
shows the format of the FSR.
2.0 Architectural Description
2.1 PROGRAMMING MODEL
The Series 32000 architecture includes nine registers that
are implemented on the NS32081 Floating-Point Unit (FPU).
TL/EE/5234–5
FIGURE 2-2. The Floating-Point Status Register
2.1.2.1 FSR Mode Control Fields
The FSR mode control fields select FPU operation modes.
The meanings of the FSR mode control bits are given be-
low.
Rounding Mode (RM): Bits 7 and 8. This field selects the
rounding method. Floating-point results are rounded when-
ever they cannot be exactly represented. The rounding
modes are:
00 Round to nearest value. The value which is nearest to
the exact result is returned. If the result is exactly half-
way between the two nearest values the even value
e
(LSB 0) is returned.
01 Round toward zero. The nearest value which is closer to
zero or equal to the exact result is returned.
TL/EE/5234–4
FIGURE 2-1. Register Set
5
2.0 Architectural Description (Continued)
10 Round toward positive infinity. The nearest value which
is greater than or equal to the exact result is returned.
100 Illegal Instruction. Two undefined floating-point instruc-
tion forms are detected by the FPU as being illegal. The
binary formats causing this trap are:
11 Round toward negative infinity. The nearest value which
is less than or equal to the exact result is returned.
xxxxxxxxxx0011xx10111110
xxxxxxxxxx1001xx10111110
Underflow Trap Enable (UEN): Bit 3. If this bit is set, the
FPU requests a trap whenever a result is too small in abso-
lute value to be represented as a normalized number. If it is
not set, any underflow condition returns a result of exactly
zero.
101 Invalid Operation. One of the floating-point operands of
a floating-point instruction is a Reserved operand, or an
attempt has been made to divide zero by zero using the
DIVf instruction.
Inexact Result Trap Enable (IEN): Bit 5. If this bit is set,
the FPU requests a trap whenever the result of an operation
cannot be represented exactly in the operand format of the
destination. If it is not set, the result is rounded according to
the selected rounding mode.
110 Inexact Result. The result (either floating-point or inte-
ger) of a floating-point instruction cannot be represent-
ed exactly in the format of the destination operand, and
a rounding step must alter it to fit. This condition is al-
ways reported in the TT field and IF bit unless any other
exceptional condition has occurred in the same instruc-
tion. In this case, the TT field always contains the code
for the other exception and the IF bit is not altered. A
trap is caused by this condition only if the IEN bit is set;
otherwise the result is rounded and delivered, and no
trap occurs.
2.1.2.2 FSR Status Fields
The FSR Status Fields record exceptional conditions en-
countered during floating-point data processing. The mean-
ings of the FSR status bits are given below:
Trap Type (TT): bits 0-2. This 3-bit field records any excep-
tional condition detected by a floating-point instruction. The
TT field is loaded with zero whenever any floating-point in-
struction except LFSR or SFSR completes without encoun-
tering an exceptional condition. It is also set to zero by a
hardware reset or by writing zero into it with the Load FSR
(LFSR) instruction. Underflow and Inexact Result are always
reported in the TT field, regardless of the settings of the
UEN and IEN bits.
111 (Reserved for future use.)
Underflow Flag (UF): Bit 4. This bit is set by the FPU when-
ever a result is too small in absolute value to be represented
as a normalized number. Its function is not affected by the
state of the UEN bit. The UF bit is cleared only by writing a
zero into it with the Load FSR instruction or by a hardware
reset.
Inexact Result Flag (IF): Bit 6. This bit is set by the FPU
whenever the result of an operation must be rounded to fit
within the destination format. The IF bit is set only if no other
error has occurred. It is cleared only by writing a zero into it
with the Load FSR instruction or by a hardware reset.
000 No exceptional condition occurred.
001 Underflow. A non-zero floating-point result is too small
in magnitude to be represented as a normalized float-
ing-point number in the format of the destination oper-
and. This condition is always reported in the TT field
and UF bit, but causes a trap only if the UEN bit is set. If
the UEN bit is not set, a result of Positive Zero is pro-
duced, and no trap occurs.
2.1.2.3 FSR Software Field (SWF)
Bits 9-15 of the FSR hold and display any information writ-
ten to them (using the LFSR and SFSR instructions), but are
not otherwise used by FPU hardware. They are reserved for
use with NSC floating-point extension software.
010 Overflow. A result (either floating-point or integer) of a
floating-point instruction is too great in magnitude to be
held in the format of the destination operand. Note that
rounding, as well as calculations, can cause this condi-
tion.
2.2 INSTRUCTION SET
2.2.1 General Instruction Format
011 Divide by zero. An attempt has been made to divide a
non-zero floating-point number by zero. Dividing zero by
zero is considered an Invalid Operation instead (below).
Figure 2-3 shows the general format of an Series 32000
instruction. The Basic Instruction is one to three bytes long
TL/EE/5234–6
FIGURE 2-3. General Instruction Format
6
2.0 Architectural Description (Continued)
and contains the opcode and up to two 5-bit General Ad-
dressing Mode (Gen) fields. Following the Basic Instruction
field is a set of optional extensions, which may appear de-
pending on the instruction and the addressing modes se-
lected.
Memory Space: Identical to Register Relative above, ex-
cept that the register used is one of the dedicated CPU
registers PC, SP, SB or FP. These registers point to data
areas generally needed by high-level languages.
Memory Relative: A pointer variable is found within the
memory space pointed to by the CPU SP, SB or FP register.
A displacement is added to that pointer to generate the Ef-
fective Address of the operand.
The only form of extension issued to the NS32081 FPU is
an Immediate operand. Other extensions are used only by
the CPU to reference memory operands needed by the
FPU.
Immediate: The operand is encoded within the instruction.
This addressing mode is not allowed if the operand is to be
written. Floating-point operands as well as integer operands
may be specified using Immediate mode.
Index Bytes appear when either or both Gen fields specify
Scaled Index. In this case, the Gen field specifies only the
Scale Factor (1, 2, 4 or 8), and the Index Byte specifies
which General Purpose Register to use as the index, and
which addressing mode calculation to perform before index-
ing. See Figure 2-4.
Absolute: The address of the operand is specified by a
Displacement field in the instruction.
External: A pointer value is read from a specified entry of
the current Link Table. To this pointer value is added a dis-
placement, yielding the Effective Address of the operand.
Following Index Bytes come any displacements (addressing
constants) or immediate values associated with the select-
ed addressing modes. Each Disp/lmm field may contain
one or two displacements, or one immediate value. The size
of a Displacement field is encoded within the top bits of that
field, as shown in Figure 2-5, with the remaining bits inter-
preted as a signed (two’s complement) value. The size of an
immediate value is determined from the Opcode field. Both
Displacement and Immediate fields are stored most signifi-
cant byte first.
Top of Stack: The currently-selected CPU Stack Pointer
(SP0 or SP1) specifies the location of the operand. The op-
erand is pushed or popped, depending on whether it is writ-
ten or read.
Scaled Index: Although encoded as an addressing mode,
Scaled Indexing is an option on any addressing mode ex-
cept Immediate or another Scaled Index. It has the effect of
calculating an Effective Address, then multiplying any Gen-
eral Purpose Register by 1, 2, 4 or 8 and adding it into the
total, yielding the final Effective Address of the operand.
Some non-FPU instructions require additional, ‘‘implied’’ im-
mediates and/or displacements, apart from those associat-
ed with addressing modes. Any such extensions appear at
the end of the instruction, in the order that they appear with-
in the list of operands in the instruction definition.
The following table, Table 2-1, is a brief summary of the
addressing modes. For a complete description of their ac-
tions, see the Series 32000 Instruction Set Reference Man-
ual.
2.2.2 Addressing Modes
The Series 32000 Family CPUs generally access an oper-
and by calculating its Effective Address based on informa-
tion available when the operand is to be accessed. The
method to be used in performing this calculation is specified
by the programmer as an ‘‘addressing mode.’’
Addressing modes in the Series 32000 family are designed
to optimally support high-level language accesses to vari-
ables. In nearly all cases, a variable access requires only
one addressing mode within the instruction which acts upon
that variable. Extraneous data movement is therefore mini-
mized.
Series 32000 Addressing Modes fall into nine basic types:
Register: In floating-point instructions, these addressing
modes refer to a Floating-Point Register (F0–F7) if the op-
erand is of a floating-point type. Otherwise, a CPU General
Purpose Register (R0–R7) is referenced. See Section 2.1.1.
Register Relative: A CPU General Purpose Register con-
tains an address to which is added a displacement value
from the instruction, yielding the Effective Address of the
operand in memory.
TL/EE/5234–10
FIGURE 2-5. Displacement Encodings
TL/EE/5234–7
FIGURE 2-4. Index Byte Format
7
2.0 Architectural Description (Continued)
TABLE 2-1. Series 32000 Family Addressing Modes
Encoding
Mode
Assembler Syntax
Effective Address
REGISTER
00000
00001
00010
00011
00100
00101
00110
00111
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
R0 or F0
R1 or F1
R2 or F2
R3 or F3
R4 or F4
R5 or F5
R6 or F6
R7 or F7
None: Operand is in the specified register.
REGISTER RELATIVE
a
01000
01001
01010
01011
01100
01101
01110
01111
Register 0 relative
Register 1 relative
Register 2 relative
Register 3 relative
Register 4 relative
Register 5 relative
Register 6 relative
Register 7 relative
disp(R0)
disp(R1)
disp(R2)
disp(R3)
disp(R4)
disp(R5)
disp(R6)
disp(R7)
Disp
Register.
MEMORY SPACE
a
SP0 or SP1, as selected in PSR.
11000
11001
11010
11011
Frame memory
Stack memory
Static memory
Program memory
disp(FP)
disp(SP)
disp(SB)
Disp
Register; ‘‘SP’’ is either
a
*
disp
MEMORY RELATIVE
a
Disp2 Pointer; Pointer found at
a
address Disp1 Register. ‘‘SP’’ is
either SP0 or SP1, as selected in PSR.
10000
10001
10010
Frame memory relative
disp2(disp1(FP))
disp2(disp1(SP))
disp2(disp1(SB))
Stack memory relative
Static memory relative
IMMEDIATE
10100
Immediate
value
None: Operand is issued from
CPU instruction queue.
ABSOLUTE
10101
@
Absolute
External
disp
Disp.
EXTERNAL
10110
a
EXT (disp1) disp2
a
Disp2 Pointer; Pointer is found
at Link Table Entry number Disp1.
TOP OF STACK
10111
Top of Stack
TOS
Top of current stack, using either
User or Interrupt Stack Pointer,
as selected in PSR. Automatic
Push/Pop included.
SCALED INDEX
a
[
]
]
]
]
11100
11101
11110
11111
Index, bytes
mode Rn:B
Mode
Mode
Mode
Mode
Rn.
c
a
a
a
[
Index, words
mode Rn:W
2
Rn.
Rn.
Rn.
c
[
Index, double words
Index, quad words
mode Rn:D
4
c
[
mode Rn:Q
8
‘‘Mode’’ and ‘‘n’’ are contained
within the Index Byte.
10011
(Reserved for Future Use)
8
2.0 Architectural Description (Continued)
2.2.3 Floating-Point Instruction Set
Movement and Conversion
The NS32081 FPU instructions occupy formats 9 and 11 of
the Series 32000 Family instruction set (Figure 2-6 ). A list
of all Series 32000 family instruction formats is found in the
applicable CPU data sheet.
The following instructions move the gen1 operand to the
gen2 operand, leaving the gen1 operand intact.
Format Op
Instruction
Description
Move without
conversion
11
0001 MOVf gen1, gen2
Certain notations in the following instruction description ta-
bles serve to relate the assembly language form of each
instruction to its binary format in Figure 2-6.
9
010 MOVLF
011 MOVFL
gen1, gen2
gen1, gen2
Move, converting
from double
Format 9
precision to
single precision.
9
9
Move, converting
from single
precision to
double
TL/EE/5234–11
Format 11
precision.
000 MOVif
gen1, gen2
Move, converting
from any integer
type to any
floating-point
type.
TL/EE/5234–12
FIGURE 2-6. Floating-Point Instruction Formats
9
9
100 ROUNDfi gen1, gen2
101 TRUNCfi gen1, gen2
Move, converting
from floating-
point to the
The Format column indicates which of the two formats in
Figure 2-6 represents each instruction.
nearest integer.
Move, converting
from floating-
point to the
The Op column indicates the binary pattern for the field
called ‘‘op’’ in the applicable format.
The Instruction column gives the form of each instruction as
it appears in assembly language. The form consists of an
instruction mnemonic in upper case, with one or more suffix-
es (i or f) indicating data types, followed by a list of oper-
ands (gen1, gen2).
nearest integer
closer to zero.
9
111 FLOORfi gen1, gen2
Move, converting
from floating-
point to the
largest integer
less than or
equal to its
An i suffix on an instruction mnemonic indicates a choice of
integer data types. This choice affects the binary pattern in
the i field of the corresponding instruction format (Figure 2-6 )
as follows:
value.
Suffix i
Data Type
Byte
i Field
00
B
W
D
Note: The MOVLF instruction f bit must be 1 and the i field must be 10.
Word
01
The MOVFL instruction f bit must be 0 and the i field must be 11.
Double Word
11
Arithmetic Operations
An f suffix on an instruction mnemonic indicates a choice of
floating-point data types. This choice affects the setting of
the f bit of the corresponding instruction format (Figure 2-6 )
as follows:
The following instructions perform floating-point arithmetic
operations on the gen1 and gen2 operands, leaving the re-
sult in the gen2 operand.
Format
11
Op
Instruction
Description
Suffix f
Data Type
Single Precision
f Bit
1
0000 ADDf gen1, gen2 Add gen1 to gen2.
F
L
11
0100 SUBf gen1, gen2 Subtract gen1
Double Precision (Long)
0
from gen2.
An operand designation (gen1, gen2) indicates a choice of
addressing mode expressions. This choice affects the bina-
ry pattern in the corresponding gen1 or gen2 field of the
instruction format (Figure 2-6 ). Refer to Table 2-1 for the
options available and their patterns.
11
11
11
11
1100 MULf gen1, gen2 Multiply gen2 by
gen1.
1000 DIVf gen1, gen2 Divide gen2 by
gen1.
0101 NEGf gen1, gen2 Move negative of
gen1 to gen2.
Further details of the exact operations performed by each
instruction are found in the Series 32000 Instruction Set
Reference Manual.
1101 ABSf gen1, gen2 Move absolute
value of gen1 to
gen2.
9
2.0 Architectural Description (Continued)
Comparison
3.2 CLOCKING
The Compare instruction compares two floating-point val-
ues, sending the result to the CPU PSR Z and N bits for use
as condition codes. See Figure 3-7. The Z bit is set if the
gen1 and gen2 operands are equal; it is cleared otherwise.
The N bit is set if the gen1 operand is greater than the gen2
operand; it is cleared otherwise. The CPU PSR L bit is un-
conditionally cleared. Positive and negative zero are consid-
ered equal.
The NS32081 FPU requires a single-phase TTL clock input
on its CLK pin (pin 14). When the FPU is connected to a
Series 32000 CPU, the CLK signal is provided from the
CTTL pin of the NS32201 Timing Control Unit.
3.3 RESETTING
The RST pin serves as a reset for on-chip logic. The FPU
may be reset at any time by pulling the RST pin low for at
least 64 clock cycles. Upon detecting a reset, the FPU ter-
minates instruction processing, resets its internal logic, and
clears the FSR to all zeroes.
Format
Op
Instruction
Description
11
0010 CMPf gen1, gen2 Compare gen1
to gen2.
On application of power, RST must be held low for at least
50 ms after V is stable. This ensures that all on-chip volt-
CC
ages are completely stable before operation. SeeFigures 3-2
and 3-3.
Floating-Point Status Register Access
The following instructions load and store the FSR as a 32-
bit integer.
Format
Op
001
110
Instruction
Description
Load FSR
Store FSR
9
9
LFSR
SFSR
gen1
gen2
2.3 TRAPS
Upon detecting an exceptional condition in executing a
floating-point instruction, the NS32081 FPU requests a trap
by setting the Q bit of the status word transferred during the
slave protocol (Section 3.5). The CPU responds by perform-
ing a trap using a default vector value of 3. See the Series
32000 Instruction Set Reference Manual and the applicable
CPU data sheet for trap service details.
TL/EE/5234–14
FIGURE 3-2. Power-On Reset Requirements
A trapped floating-point instruction returns no result, and
does not affect the CPU Processor Status Register (PSR).
The FPU displays the reason for the trap in the Trap Type
(TT) field of the FSR (Section 2.1.2.2).
3.0 Functional Description
3.1 POWER AND GROUNDING
TL/EE/5234–15
FIGURE 3-3. General Reset Timing
The NS32081 requires a single 5V power supply, applied on
pin 24 (V ). See DC Electrical Characteristics table.
CC
3.4 BUS OPERATION
Instructions and operands are passed to the NS32081 FPU
with slave processor bus cycles. Each bus cycle transfers
either one byte (8 bits) or one word (16 bits) to or from the
FPU. During all bus cycles, the SPC line is driven by the
CPU as an active low data strobe, and the FPU monitors
Grounding connections are made on two pins. Logic Ground
(GNDL, pin 12) is the common pin for on-chip logic, and
Buffer Ground (GNDB, pin 13) is the common pin for the
output drivers. For optimal noise immunity, it is recommend-
ed that GNDL be attached through a single conductor di-
rectly to GNDB, and that all other grounding connections be
made only to GNDB, as shown below (Figure 3-1).
TL/EE/5234–13
TL/EE/5234–2
FIGURE 3-1. Recommended Supply Connections
FIGURE 3-4. System Connection Diagram
10
3.0 Functional Description (Continued)
pins ST0 and ST1 to keep track of the sequence (protocol)
established for the instruction being executed. This is nec-
essary in a virtual memory environment, allowing the FPU to
retry an aborted instruction.
3.5 INSTRUCTION PROTOCOLS
3.5.1 General Protocol Sequence
Slave Processor instructions have a three-byte Basic In-
struction field, consisting of an ID byte followed by an Oper-
ation Word. See Section 2.2.3 for FPU instruction encod-
ings. The ID Byte has three functions:
3.4.1 Bus Cycles
A bus cycle is initiated by the CPU, which asserts the proper
status on ST0 and ST1 and pulses SPC low. ST0 and ST1
are sampled by the FPU on the leading (falling) edge of the
SPC pulse. If the transfer is from the FPU (a slave processor
read cycle), the FPU asserts data on the data bus for the
duration of the SPC pulse. If the transfer is to the FPU (a
slave processor write cycle), the FPU latches data from the
data bus on the trailing (rising) edge of the SPC pulse. Fig-
ures 3-5 and 3-6 illustrate these sequences.
1) It identifies the instruction to the CPU as being a Slave
Processor instruction.
2) It specifies which Slave Processor will execute it.
3) It determines the format of the following Operation Word
of the instruction.
Upon receiving a Slave Processor instruction, the CPU initi-
ates the sequence outlined in Table 3-2. While applying
Status Code 11 (Broadcast ID. Table 3-1), the CPU trans-
fers the ID Byte on the least significant half of the Data Bus
(D0–D7). All Slave Processors input this byte and decode it.
The Slave Processor selected by the ID Byte is activated,
and from this point the CPU is communicating only with it. If
any other slave protocol was in progress (e.g., an aborted
Slave instruction), this transfer cancels it.
The direction of the transfer and the role of the bidirectional
SPC line are determined by the instruction protocol being
performed. SPC is always driven by the CPU during slave
processor bus cycles. Protocol sequences for each instruc-
tion are given in Section 3.5.
3.4.2 Operand Transfer Sequences
An operand is transferred in one or more bus cycles. A 1-
byte operand is transferred on the least significant byte of
the data bus (D0–D7). A 2-byte operand is transferred on
the entire bus. A 4-byte or 8-byte operand is transferred in
consecutive bus cycles, least significant word first.
The CPU next sends the Operation Word while applying
Status Code 01 (Transfer Slave Operand, Table 3-1). Upon
receiving it, the FPU decodes it, and at this point both the
CPU and the FPU are aware of the number of operands to
be transferred and their sizes. The Operation Word is
swapped on the Data Bus; that is, bits 0–7 appear on pins
D8–D15, and bits 8–15 appear on pins D0–D7.
TL/EE/5234–16
Note 1: FPU samples CPU status here.
FIGURE 3-5. Slave Processor Read Cycle
TL/EE/5234–17
Note 1: FPU samples CPU status here.
Note 2: FPU samples data bus here.
FIGURE 3-6. Slave Processor Write Cycle
11
3.0 Functional Description (Continued)
Using the Addressing Mode fields within the Operation
Word, the CPU starts fetching operands and issuing them to
the FPU. To do so, it references any Addressing Mode ex-
tensions appended to the FPU instruction. Since the CPU is
solely responsible for memory accesses, these extensions
are not sent to the Slave Processor. The Status Code ap-
plied is 01 (Transfer Slave Processor Operand, Table 3-1).
TABLE 3-1. General Instruction Protocol
Step
Status
11
Action
1
2
3
4
5
6
7
CPU sends ID Byte.
01
CPU sends Operation Word.
CPU sends required operands.
FPU starts execution.
01
XX
XX
10
FPU pulses SPC low.
After the CPU has issued the last operand, the FPU starts
the actual execution of the instruction. Upon completion, it
will signal the CPU by pulsing SPC low. To allow for this, the
CPU releases the SPC signal, causing it to float. SPC must
be held high by an external pull-up resistor.
CPU reads Status Word.
CPU reads result (if any).
01
3.5.2 Floating-Point Protocols
Table 3-2 gives the protocols followed for each floating-
point instruction. The instructions are referenced by their
mnemonics. For the bit encodings of each instruction, see
Section 2.2.3.
Upon receiving the pulse on SPC, the CPU uses SPC to
read a Status Word from the FPU, applying Status Code 10.
This word has the format shown in Figure 3-7. If the Q bit
(‘‘Quit’’, Bit 0) is set, this indicates that an error has been
detected by the FPU. The CPU will not continue the proto-
col, but will immediately trap through the Slave vector in the
Interrupt Table. If the instruction being performed is CMPf
(Section 2.2.3) and the Q bit is not set, the CPU loads Proc-
essor Status Register (PSR) bits N, Z and L from the corre-
sponding bits in the Status Word. The NS32081 FPU always
sets the L bit to zero.
The Operand Class columns give the Access Classes for
each general operand, defining how the addressing modes
are interpreted by the CPU (see Series 32000 Instruction
Set Reference Manual).
The Operand Issued columns show the sizes of the oper-
ands issued to the Floating-Point Unit by the CPU. ‘‘D’’ indi-
cates a 32-bit Double Word. ‘‘i’’ indicates that the instruction
e
e
Double Word). ‘‘f’’ indicates that the instruction
specifies an integer size for the operand (B
e
Byte, W
Word, D
specifies a floating-point size for the operand (F
e
32-bit
e
Standard Floating, L
64-bit Long Floating).
The Returned Value Type and Destination column gives the
size of any returned value and where the CPU places it. The
PSR Bits Affected column indicates which PSR bits, if any,
are updated from the Slave Processor Status Word (Figure
3-7 ).
TL/EE/5234–18
FIGURE 3-7. FPU Protocol Status Word Format
The last step in the protocol is for the CPU to read a result,
if any, and transfer it to the destination. The Read cycles
from the FPU are performed by the CPU while applying
Status Code 01 (Section 4.1.2).
Any operand indicated as being of type ‘‘f’’ will not cause a
transfer if the Register addressing mode is specified, be-
cause the Floating-Point Registers are physically on the
Floating-Point Unit and are therefore available without CPU
assistance.
TABLE 3-2. Floating Point Instruction Protocols
Operand 1
Class
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.f
read.F
read.L
read.i
read.D
N/A
Operand 2
Class
rmw.f
Operand 1
Operand 2
Returned Value
Type and Dest.
f to Op. 2
f to Op. 2
f to Op. 2
f to Op. 2
f to Op. 2
f to Op. 2
f to Op. 2
N/A
PSR Bits
Affected
none
none
none
none
none
none
none
N,Z,L
none
none
none
none
none
none
none
none
Mnemonic
Issued
Issued
f
ADDf
f
SUBf
rmw.f
f
f
MULf
rmw.f
f
f
DIVf
rmw.f
f
f
MOVf
write.f
write.f
write.f
read.f
write.i
write.i
write.i
write.L
write.F
write.f
N/A
f
N/A
N/A
N/A
f
ABSf
f
NEGf
f
CMPf
f
FLOORfi
TRUNCfi
ROUNDfi
MOVFL
MOVLF
MOVif
LFSR
f
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
i to Op. 2
i to Op. 2
i to Op. 2
L to Op. 2
F to Op. 2
f to Op. 2
N/A
f
f
F
L
i
D
SFSR
e
write.D
N/A
D to Op. 2
D
Double Word
e
i
Integer size (B, W, D) specified in mnemonic.
Floating-Point type (F, L) specified in mnemonic.
e
f
e
N/A
Not Applicable to this instruction.
12
4.1.1 Supplies
4.0 Device Specifications
4.1 PIN DESCRIPTIONS
a
Power (V ): 5V positive supply. Section 3.1.
CC
Logic Ground (GNDL): Ground reference for on-chip logic.
Section 3.1.
The following are brief descriptions of all NS32081 FPU
pins. The descriptions reference the relevant portions of the
Functional Description, Section 3.
Buffer Ground (GNDB): Ground reference for on-chip driv-
ers connected to output pins. Section 3.1.
Dual-In-Line Package
4.1.2 Input Signals
Clock (CLK): TTL-level clock signal.
Reset (RST): Active low. Initiates a Reset, Section 3.3.
Status (ST0, ST1): Input from CPU. ST0 is the least signifi-
cant bit. Section 3.4 encodings are:
00Ð(Reserved)
01ÐTransferring Operation Word or Operand
10ÐReading Status Word
11ÐBroadcasting Slave ID
4.1.3 Input/Output Signals
Slave Processor Control (SPC): Active low. Driven by the
CPU as the data strobe for bus transfers to and from the
NS32081 FPU, Section 3.4. Driven by the FPU to signal
completion of an operation, Section 3.5.1. Must be held high
with an external pull-up resistor while floating.
Data Bus (D0–D15): 16-bit bus for data transfer. D0 is the
least significant bit. Section 3.4.
TL/EE/5234–3
Top View
FIGURE 4-1. Connection Diagram
Order Number NS32081D-10 or NS32081D-15
See NS Package Number D24C
Order Number NS32081N-10 or NS32081N-15
See NS Package Number N24A
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
4.2 ABSOLUTE MAXIMUM RATINGS
a
0 C to 70 C
Temperature Under Bias
Storage Temperature
All Input or Output Voltages
with Respect to GND
Power Dissipation
§
65 C to 150 C
§
b
a
§
§
Note: Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous operation
at these limits is not intended; operation should be limited to
those conditions specified under Electrical Characteristics.
b
a
0.5V to 7.0V
1.5W
e
e
e
5V 5%, GND 0V
g
4.3 ELECTRICAL CHARACTERISTICS T
0 C to 70 C, V
§
§
A
CC
Symbol
Parameter
Conditions
Min
2.0
Typ
Max
Units
V
a
V
V
V
V
HIGH Level Input Voltage
LOW Level Input Voltage
V
0.5
IH
CC
b
0.5
0.8
V
IL
e b
HIGH Level Output Voltage
LOW Level Output Voltage
Input Load Current
I
I
400 mA
2.4
V
OH
OL
OH
e
4 mA
0.45
10.0
V
OL
s
s
V
b
I
I
0
V
IN
10.0
20.0
mA
I
CC
s
s
2.4V
Leakage Current
0.45
V
IN
L
b
Output and I/O Pins in
TRI-STATE/Input Mode
20.0
300
mA
e
e
25 C
I
Active Supply Current
I
0, T
A
200
mA
§
CC
OUT
13
4.0 Device Specifications (Continued)
4.4 SWITCHING CHARACTERISTICS
4.4.1 Definitions
All the Timing Specifications given in this section refer to 0.8V
and 2.0V on all the input and output signals as illustrated in
Figures 4.2 and 4.3, unless specifically stated otherwise.
ABBREVIATIONS
L.E. Ð Leading Edge
T.E. Ð Trailing Edge
R.E. Ð Rising Edge
F.E. Ð Falling Edge
TL/EE/5234–27
TL/EE/5234–26
FIGURE 4-2. Timing Specification Standard
(Signal Valid After Clock Edge)
FIGURE 4-3. Timing Specification Standard
(Signal Valid Before Clock Edge)
14
4.0 Device Specifications (Continued)
4.4.2 Timing Tables
4.4.2.1 Output Signal Propagation Delays
Maximum times assume capacitive loading of 100 pF.
NS32081-10
Min Max
NS32081-15
Reference/
Conditions
Units
Name
Figure
Description
Min
Max
t
4-7
4-7
4-9
Data Valid
D –D Floating
After SPC L.E.
After SPC T.E.
45
50
30
35
ns
ns
Dv
t
t
2
Df
0
15
SPC Pulse Width
from FPU
At 0.8V
SPCFw
b
a
b
a
40
CLKp
t
50
t
50
t
40
t
ns
CLKp
CLKp
CLKp
(Both Edges)
t
t
t
4-9
4-9
4-9
SPC Output Active
SPC Output Inactive
After CLK R.E.
After CLK R.E.
After CLK F.E.
55
55
38
38
ns
ns
SPCFl
SPCFh
SPCFnf
SPC Output
Nonforcing
45
35
ns
4.4.2.2 Input Signal Requirements
Reference/
Conditions
Name
Figure
Description
Min
50
Max
Min
50
Max
Units
t
t
t
t
4-5
Power Stable to
RST R.E.
After V
CC
PWR
RSTw
Ss
ms
Reaches 4.5V
4-6
4-7
4-7
RST Pulse Width
At 0.8V
64
64
t
CLKp
(Both Edges)
Status (ST0–ST1)
Setup
Before SPC L.E.
50
33
ns
Status (ST0–ST1)
Hold
After SPC L.E.
Sh
40
35
ns
t
t
t
4-8
4-8
4-7
D0–D15 Setup Time
D0–D15 Hold Time
Before SPC T.E.
After SPC T.E.
40
50
30
35
ns
ns
Ds
Dh
SPC Pulse Width
from CPU
At 0.8V
SPCw
70
50
ns
(Both Edges)
t
t
t
t
4-7
4-7
SPC Input Active
SPC Input Inactive
RST Setup
Before CLK R.E.
After CLK R.E.
Before CLK F.E.
After CLK R.E.
40
0
35
0
ns
ns
ns
ns
SPCs
SPCh
RSTs
RSTh
4-10
4-10
10
0
10
0
RST R.E. Delay
4.4.2.3 Clocking Requirements
Reference/
Conditions
Name
Figure
Description
Min
42
Max
1000
1000
2000
Min
27
Max
1000
1000
Units
ns
t
t
t
4-4
Clock High Time
At 2.0V
CLKh
(Both Edges)
4-4
4-4
Clock Low Time
Clock Period
At 0.8V
CLKl
42
27
ns
(Both Edges)
CLK R.E. to Next
CLK R.E.
CLKp
100
66
ns
15
4.0 Device Specifications (Continued)
4.4.3 Timing Diagrams
TL/EE/5234–19
TL/EE/5234–20
FIGURE 4-4. Clock Timing
FIGURE 4-5. Power-On Reset
TL/EE/5234–21
FIGURE 4-6. Non-Power-On Reset
TL/EE/5234–22
FIGURE 4-7. Read Cycle from FPU
Note: SPC pulse must be (nominally) 1 clock wide when writing into FPU.
TL/EE/5234–23
FIGURE 4-8. Write Cycle to FPU
Note: SPC pulse may also be 2 clocks wide, but its edges must meet the t
and t
requirements with respect to CLK.
SPCh
SPCs
16
4.0 Device Specifications (Continued)
TL/EE/5234–24
FIGURE 4-9. SPC Pulse from FPU
TL/EE/5234–25
FIGURE 4-10. RST Release Timing
Note: The rising edge of RST must occur while CLK is high, as shown.
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (D)
Order Number NS32081D-10 or NS32081D-15
NS Package Number D24C
17
Ý
Lit. 114287
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number NS32081N-10 or NS32081N-15
NS Package Number N24A
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