NCT3101S TR [ETC]
IC BUS TERM REGULATOR 8ESOP;
| 型号： | NCT3101S TR |
| 厂家： | 
ETC |
| 描述： | IC BUS TERM REGULATOR 8ESOP |
| 文件： | 总20页 (文件大小：659K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Nuvoton
Bus Termination Regulator
NCT3101S
DATE: MARCH, 2013
Revision: A4
NCT3101S
-Table of Content-
1. GENERAL DESCRIPTION ...................................................................................1
2. FEATURES...........................................................................................................1
3. BLOCK DIAGRAM ...............................................................................................2
4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT........................2
5. PIN DESCRIPTION...............................................................................................3
6. FUNCTIONAL DESCRIPTION .............................................................................3
7. ELECTRICAL CHARACTERISTICS.....................................................................7
8. TYPICAL OPERATING CHARACTERISTICS AND WAVEFORMS.....................9
9. PACKAGE DIMENSION.....................................................................................15
10. ORDERING INFORMATION............................................................................16
11. TOP MARKING SPECIFICATION ...................................................................16
12. REVISION HISTORY.......................................................................................17
Publication Date: Mar., 2013
-I-
Revision A4
NCT3101S
1. GENERAL DESCRIPTION
The NCT3101S is a sink/source Double Data Rate (DDR) termination regulator specifically
designed for low input voltage, low cost systems where space is a key consideration. The
NCT3101S maintains a fast transient response and only requires a minimum output capacitance
of 10uF. The NCT3101S supports all power requirements for DDR, DDR2, DDR3, DDR3L,
DDR3U, LPDDR3 and DDR4 VTT bus termination.
2. FEATURES
General
VCNTL Voltage: Supports 3.3V Rail and 5V Rail
VIN Voltage Range: 1.0V to 5.5V
Sink/Source Current: 2A
Requires Minimum Output Capacitance of 10uF MLCC for Memory Termination Application
Integrated Power MOSFET
VREF Input Allows for Flexible Input Tracking Either Directly or Through Resistor Divider
Low External Component Count
Low Output Voltage Offset
Current Limit Protection
Over Temperature Protection
Meets DDR, DDR2 JEDEC Specifications; Supports DDR3, DDR3L, DDR3U, LPDDR3 and
DDR4 VTT Regulation
-40°C to 85°C Ambient Operating Temperature Range
Package
SOP-8 150mil with Exposed Pad Package
Lead Free (ROHS Compliant) and Halogen Free
Applications
Desktop PCs, Notebooks, and Workstations
Graphics Card Memory Termination
Set Top Boxes, Digital TVs and Printers
Active Termination Buses
DDR, DDR2, DDR3, DDR3L, DDR3U, LPDDR3 and DDR4 Memory Systems
Publication Date: Mar., 2013
-1-
Revision A4
NCT3101S
3. BLOCK DIAGRAM
VCNTL
VIN
Current Limit
Protection
Control
Logic
VOUT
GND
VREF
Thermal
Shutdown
4. PIN CONFIGURATION AND TYPICAL APPLICATION CIRCUIT
NC
8
VIN
1
2
3
4
NC
7
6
5
GND
VREF
VCNTL
NC
VOUT
NCT3101S
(Top View)
VDDQ=2.5V/1.8V/1.5V/1.2V
VCNTL=3.3V/5V
CCNTL
CIN
R1
VIN VCNTL
VREF
VTT = VDDQ x R2 / (R1+R2)
COUT
Enable
VOUT
R2
CSS
GND
R1 = R2 = 1k ~ 5kΩ, CSS = 0.1uF ~ 1uF
CCNTL = 0.1uF, CIN = 10uF, COUT= 10uF
Publication Date: Mar., 2013
Revision A4
-2-
NCT3101S
5. PIN DESCRIPTION
SYMBOL
PIN
I/O
FUNCTION
Main power input pin which supplies current to output pin. For
lower power dissipation consideration, using VDDQ (Supply
voltage for DRAM) as power source is recommended.
VIN
1
I
Internal reference voltage source. Generally, VREF tracks
VDDQ/2 for DDR application.
Using voltage dividing resistors and capacitor as low pass
filter for noise immunity and output voltage soft start is
recommended.
VREF
3
I
If using an N-MOSFET as shutdown function, please make
sure the sinking current capability can pull down VREF under
0.2V.
Voltage output pin which is regulated to track VREF voltage.
Connect to VTT power rail of DDR-SDRAM DIMM.
VOUT
4
6
O
I
Power for internal control logic circuitry. A ceramic decoupling
capacitor with 0.1uF is required. The voltage on this pin must
be at least 2V greater than output voltage and no less than
minimum VCNTL supply voltage.
VCNTL
Ground.
GND
NC
2
Connect to negative terminal of the output capacitor(s).
No connection.
5, 7, 8
6. FUNCTIONAL DESCRIPTION
VTT Sink/Source Regulator
The NCT3101S is a sink/source tracking termination regulator specifically designed for low input
voltage, low cost and low external component count systems where space is a key application
parameter. The NCT3101S integrates a high performance, low dropout linear regulator that is
capable of both sinking and sourcing current. The load dropout regulator employs a fast
feedback loop so that small ceramic capacitors can be used to support the fast load transient
response. The NCT3101S also incorporates two distinct power rails that separates the analog
circuitry from the power output stage. This allows a split rail approach to be utilized to decrease
internal power dissipation.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data
transmission across the memory bus. This termination scheme is essential to prevent data error
from signal reflections while transmitting at high frequencies encountered with DDR-SDRAM.
The DDR-SDRAM memory termination structure determines the main characteristics of the VT
rail, which is to be able to sink and source current while maintaining acceptable VTT tolerance.
Fig. 6-1 shows typical characteristics for a single memory cell.
When Q1 is on and Q2 is off:
Current flows from VDDQ via the termination resistor to VTT
VTT sinks current
Publication Date: Mar., 2013
-3-
Revision A4
NCT3101S
When Q1 is off and Q2 is on:
Current flows from VTT via the termination resistor to GND
VTT sources current
VDDQ
Q1
VTT
RT
RS
Chipset
Memory
Q2
VREF
GND
Fig. 6-1 DDR Physical Signal System Bi-Directional SSTL Signaling
Power Sequence Requirement
The input sequence of power rails should be taken care. VCNTL can be energized after VIN and
VREF, but VREF cannot be energized before VIN. It is recommended that VIN and VREF
connect to the same power rail.
Reference Voltage, VREF
The output voltage, VOUT, is regulated to VREF. When VREF is configured for standard DDR
termination applications, VREF can be set by an external equivalent ratio voltage divider
connected to the memory supply bus (VDDQ). The NCT3101S supports VREF voltage from
0.5V to VIN-2.2V, making it versatile and ideal for many types of low power LDO applications.
An external bypass capacitor is also connected to VREF. The capacitor and the resistor divider
form a low pass filter to reduce the inherent reference noise from VIN. The capacitor is a 0.1uF
or greater ceramic capacitor and connected to VREF as close as possible. It is not allowed any
additional loading on the reference input pin.
Shutdown Function
When the external reference voltage at VREF pin is under shutdown threshold, the internal
regulator will be turned off.
Over Current Protection
The NCT3101S provides a current limit circuitry, which monitors the output current and controls
MOSFET’s gate voltage to limit the output current.
Over Temperature Protection
The NCT3101S monitors its junction temperature. If the device junction temperature exceeds its
threshold value, typically 165°C, the VOUT is shut off. The shutdown is a non-latch protection.
Publication Date: Mar., 2013
-4-
Revision A4
NCT3101S
Thermal Design
Since the NCT3101S is a linear regulator, the VOUT current flows in both source and sink
directions, thereby dissipating power from the device. When the device is sourcing current, the
voltage difference between VIN and VOUT times IOUT current becomes the power dissipation as
shown in below equation.
PDISS_SOURCE = (VIN-VOUT) x IOUT_SOURCE
In this case, if VIN is connected to an alternative power supply lower than the VDDQ voltage,
overall power loss can be reduced. For the sink phase, VOUT voltage is applied across the
internal LDO regulator and the power dissipation, PDISS_SINK can be calculated by below
equation.
PDISS_SINK = VOUT x IOUT_SINK
Because the device does not sink and source current at the same time and the IOUT current may
vary rapidly with time, the actual power dissipation should be the time average of the above
dissipations over the thermal relaxation duration of the system. Another source of power
consumption is the current used for the internal current control circuitry form VCNTL supply and
the VIN supply. This can be estimate as 10mW or less during normal operating conditions. The
power must be effectively dissipated from the package.
Maximum power dissipation allowed by the package is calculated by below equation.
PPKG = [ TJ(MAX) – TA(MAX)] / θJA
, where
TJ(MAX) is +125°C
TA(MAX) is the maximum ambient temperature in the system
θJA is the thermal resistance form junction to ambient
θJA highly depends on IC package, PCB layout, the aireflow. Thermal resistance θJA can be
improved by adding copper under the exposed pad of ESOP-8 while the IC package is fixed.
The copper under the exposed pad of ESOP-8 is an effective heatsink and is useful for
improving thermal conductivity. Figure 6-3 shows the relationship between thermal resistance
θJA vs. copper area on a standard JEDEC 51-7 (4 layers, 2S2P) thermal test board at TA =
25°C, PCB copper thickness = 2oz. The 70mm2 copper plane reduces θJA from 75°C/W to
45°C/W and increases maximum power disspation from 1.33W to 2.22W.
70mm2 copper area
30mm2 copper area
Minimum copper area
Fig. 6-2 Power Dissipation vs. Ambient Temperature
Fig. 6-3 Thermal Resistance θJA vs. Copper Area of
ESOP Packages
Publication Date: Mar., 2013
Revision A4
-5-
NCT3101S
Input Capacitor
Depend on the trace impedance between the VIN bulk power supply to the device, a transient
increase of source current is supplied mostly by the charge from the VIN input capacitor. If the
NCT3101S is located near the bulk capacitor(s) for upstream voltage regulator, the input
capacitor may not be required. Use a 10uF (or greater) capacitor to supply this transient charge.
Provide more input capacitance as more output capacitance is used at VOUT.
Input capacitor for VCNTL is recommended. Place the input capacitor for VCNTL as close to
VCNTL pin as possible prevents outside noise from entering NCT3101S’ control circuitry. The
recommended capacitance of VCNTL input capacitor is 0.1uF or above.
Output Capacitor
For stable operation, the total capacitance of the VOUT terminal must be greater than 10uF.
Total output capacitors value including MLCC and AL electrolytic capacitors should be larger
than 10uF.
Layout consideration
Consider the following points before starting the NCT3101S layout design. Fig. 6-4 shows the
suggestion of minimum land pattern. Fig. 6-5 shows the recommended PCB layout. Using “dog
bone” copper patterns on the top layer can increase efficiency of heat dissipating.
The input bypass capacitor for VIN should be placed as close as possible to the pin with
short and wide connections.
The output capacitor for VOUT should be placed close to the pin with short and wide
connection in order to avoid ESR and/or ESL trace inductance.
In order to effectively remove heat from the package, properly prepare the thermal land.
Apply solder directly to the package’s thermal pad. The wide traces of component and the
side copper connected to the thermal land pad help to dissipate heat. The thermal land
connected to the ground plane could also be used to help dissipation.
75
VCNTL
Ground
For heat
dissipating
CCNTL
90
219
90
Ground
CIN
Unit: mil
(Not to scale)
COUT
(Optional)
VIN
VOUT
24
50
Fig. 6-5 Recommended PCB Layout
Fig. 6-4 Recommended Land Pattern
Publication Date: Mar., 2013
Revision A4
-6-
NCT3101S
7. ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(Note1)
ITEM
Input Voltage
SYMBOL
RATING
-0.3 to 7
-0.3 to 7
-0.3 to 7
±2
UNITS
V
VIN
Control Logic Input Voltage
Reference Voltage
VCNTL
VREF
V
V
Human Body Mode
Machine Mode
Latch-Up
kV
V
Electrostatic discharge protection (Note2)
±200
±100
mA
°C
°C
Junction Temperature Range
Storage Temperature Range
-40 to 150
-65 to 150
Refer to IPC/JEDEC J-STD-020 Specification
260°C for 30sec max
Soldering Temperature
Note1. Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other
conditions beyond those indicated under recommended operating conditions is not implied. Exposure
to absolute maximum rated conditions for extended periods may affect device reliability.
Note2. Devices are ESD sensitive. Handling precaution recommended.
Thermal Information
ITEM
Power Dissipation, PD @ TA=25°C
RATING
1.33
75
UNITS
W
(Note3)
Junction to Ambient, θJA
Junction to Case, θJC
°C/W
°C/W
Package Thermal Resistance
20
Note3. At elevated temperatures, devices must be de-rated based on thermal resistance. The device in the
ESOP-8 package must be de-rated at θJA=75˚C/W junction to ambient with minimum PCB footprint.
Recommended Operating Conditions
ITEM
SYMBOL
VIN
MIN
1.0
3.0
0.5
0
MAX
UNITS
5.5
V
V
A
Input Voltage
VCNTL
VREF
Sourcing
Sinking
CCNTL
CIN
5.5
VCNTL-2.2
2
2
Output Current
0
Capacitance of VCNTL Decoupling Capacitor
Capacitance of VIN Decoupling Capacitor
Capacitance of VREF Soft Start Capacitor
Capacitance of VOUT Regulation Capacitor, MLCC
Operating Temperature Range
0.1
10
1
uF
uF
uF
uF
°C
°C
22
1
CSS
0.1
4.7
-40
-40
COUT
22
85
125
TOPT
Junction Temperature Range (Note3)
TJ
Publication Date: Mar., 2013
Revision A4
-7-
NCT3101S
DC Characteristics
Typicals and limits appearing in normal type apply for Tj = 25°C. Limits appearing in Boldface type apply over the
entire junction temperature range for operation, -40°C to 85°C (Note4). VCNTL= 3.3V/5V, VIN=2.5V/1.8V/1.5V,
VREF=1.25V/0.9V/0.75V, COUT=10uF, all voltage outputs unloaded (unless otherwise noted).
PARAMETER
SYM.
TEST CONDITION
MIN
TYP
MAX
UNITS
Input
VCNTL Operating Current
VIN Operating Current
ICNTL
IVIN
IOUT=0A, VCNTL=5V
IOUT=0A, VCNTL=5V
0.7
1.5
50
mA
uA
VCNTL Quiescent Current in Shutdown
Mode
VIN Quiescent Current in Shutdown
Mode
ISD_CNTL
ISD_VIN
VREF < 0.15V, VCNTL=5V
VREF < 0.15V
30
50
1
uA
uA
-1
IIH
IIL
VREF=3.3V
VREF=0V
-1
-1
1
1
VREF Leakage Current
uA
Output (DDR1 / DDR2 / DDR3)
Output Offset Voltage (VREF-VOUT)
VOS
IOUT=0A
-10
-20
-20
10
20
mV
mV
IOUT=0 → +2A (Note5), TA=25°C
IOUT=0 → -2A (Note5) , TA=25°C
VCNTL=3.3V, IOUT=2A
VCNTL=3.3V, IOUT=1.5A
VCNTL=3.3V, IOUT=1A
VCNTL=5V, IOUT=2A
VCNTL=5V, IOUT=1.5A
VCNTL=5V, IOUT=1A
Load Regulation (VREF-VOUT)
∆VL
20
390
260
160
350
240
150
600
400
280
600
400
280
mV
mV
mV
mV
mV
mV
Dropout Voltage(Note6)
VDROP
Protection
TA=25°C
±2.2
±1.7
±2
±3
±3
±4.2
±4.8
±4.2
±4.5
175
Current Limit Trip Threshold
IOCP
A
A
TA=-40°C ~ 85°C
TA=25°C
Current Limit
ILIM
TA=-40°C ~ 85°C
3.3V < VCNTL < 5V (Note7)
3.3V < VCNTL < 5V(Note7)
±1.5
150
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VREF Shutdown Mode
TSD
165
30
°C
°C
∆TSD
VIH
VIL
Enable
Disable
0.4
Shutdown Threshold
V
0.15
Note4. Limits are 100% production tested at 25˚C. Limits over operating temperature range are guaranteed through
correlation using Statistical Quality Control (SQC) methods. The limits are used to calculate average
outgoing quality level.
Note5. VOUT load regulation is tested by using a 10ms period and 50% duty cycle current pulse.
Note6. Measured when the output drops 2% below its nominal value. VOUT range is from 0.5V to VCNTL-2.2V.
Note7. The maximum allowable power dissipation is a function of the maximum junction temperature, TJ (MAX), the
junction to ambient thermal resistance, θJA, and the ambient temperature, TA exceeding the maximum
allowable power dissipation will cause excessive die temperature and the regulator will go into thermal
shutdown. Ensured by design, no production tested.
Publication Date: Mar., 2013
-8-
Revision A4
NCT3101S
8. TYPICAL OPERATING CHARACTERISTICS AND WAVEFORMS
Operating Characteristics
VOS vs. Temperature, VCNTL=5V
VOS vs. Temperature, VCNTL=3.3V
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
IOUT = 0mA
IOUT = 0mA
DDR1
DDR1
DDR2
DDR3
DDR2
DDR3
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100 120
Temperature (°C)
Temperature (°C)
VCNTL Current vs. Temperature
VCNTL Current vs. Temperature
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
VCNTL=3.3V
IOUT = 0mA
VCNTL=5V
IOUT = 0mA
DDR1
DDR2
DDR3
DDR1
DDR2
DDR3
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Publication Date: Mar., 2013
Revision A4
-9-
NCT3101S
Sourcing Current Limit vs. Temperature
Sinking Current Limit vs. Temperature
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
VCNTL=5V
VCNTL=5V
VCNTL=3.3V
VCNTL=3.3V
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Enable Threshold vs. Temperature @
VCNTL=5V
Enable Threshold vs. Temperature @
VCNTL=3.3V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
VIH
VIH
VIL
VIL
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
Dropout Voltage vs. IOUT @ VCNTL=3.3V
Dropout Voltage vs. IOUT @ VCNTL=5V
600
500
400
300
200
100
0
500
450
400
350
300
250
200
150
100
50
IOUT=2A
IOUT=2A
IOUT=1.5A
IOUT=1A
IOUT=1.5A
IOUT=1A
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1
0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
OUTPUT Voltage (V)
OUTPUT Voltage (V)
Publication Date: Mar., 2013
Revision A4
-10-
NCT3101S
Operating Waveforms
VCNTL=5V, VIN=VREF, CIN=COUT=10uF (MLCC), CSS=0.1uF
Load Transient Response (VIN=2.5V)
Load Transient Response (VIN=1.8V)
IOUT=10mA to 2A to 10mA
IOUT=10mA to 2A to 10mA
Load Transient Response (VIN=1.5V)
Load Transient Response (VIN=2.5V)
IOUT=-10mA to -2A to -10mA
IOUT=10mA to 2A to 10mA
Load Transient Response (VIN=1.8V)
Load Transient Response (VIN=1.5V)
IOUT=-10mA to -2A to -10mA
IOUT=-10mA to -2A to -10mA
Publication Date: Mar., 2013
Revision A4
-11-
NCT3101S
Power On Test (VIN=2.5V)
Power On Test (VIN=1.8V)
VCNTL Turn On
VCNTL Turn On
RLOAD=5Ω
RLOAD=5Ω
Power On Test (VIN=1.5V)
Power On Test (VIN=2.5V)
VIN Turn On
VCNTL Turn On
RLOAD=5Ω
RLOAD=5Ω
Power On Test (VIN=1.8V)
Power On Test (VIN=1.5V)
VIN Turn On
VIN Turn On
RLOAD=5Ω
RLOAD=5Ω
Publication Date: Mar., 2013
Revision A4
-12-
NCT3101S
Power On Test (VIN=2.5V)
Power On Test (VIN=1.8V)
VREF Turn On
VREF Turn On
RLOAD=5Ω
RLOAD=5Ω
Power On Test (VIN=1.5V)
Current Limit Test (VIN=2.5V)
VOUT Short to GND
Thermal
Shutdown
VREF Turn On
RLOAD=5Ω
Current Limit Test (VIN=1.8V)
Current Limit Test (VIN=1.5V)
VOUT Short to GND
VOUT Short to GND
Thermal
Shutdown
Thermal
Shutdown
Publication Date: Mar., 2013
Revision A4
-13-
NCT3101S
Current Limit Test (VIN=2.5V)
Current Limit Test (VIN=1.8V)
VOUT Short to VIN
VOUT Short to VIN
Thermal
Shutdown
Thermal
Shutdown
Current Limit Test (VIN=1.5V)
VOUT Short to VIN
Thermal
Shutdown
Publication Date: Mar., 2013
Revision A4
-14-
NCT3101S
9. PACKAGE DIMENSION
TAPING SPECIFICATION
8 Pin ESOP Package
Publication Date: Mar., 2013
Revision A4
-15-
NCT3101S
10. ORDERING INFORMATION
Supplied as
8PIN ESOP (Green Package) T Shape: 2,500 units/T&R
Part Number
NCT3101S
Package Type
Operating Temperature
Commercial, -40°C to +85°C
11. TOP MARKING SPECIFICATION
３１０１Ｓ
９５２ＡＸ
1st Line: Nuvoton logo
2
nd Line: 3101S (Part number)
3rd line: Tracking code
952: packages assembled in Year 2009, week 52
A: assembly house ID
X: the IC version (A means A; B means B & C means C…etc.)
Publication Date: Mar., 2013
Revision A4
-16-
NCT3101S
12. REVISION HISTORY
VERSION
A1
DATE
PAGE
All
DESCRIPTION
Aug., 2010
Jan., 2011
New Release
Correct typo
A2
8
1.Modified Recommended Land Pattern
2.Modified Package Dimension
3.Modified Ordering Information
4.Modified Importance Notice
A3
A4
Nov., 2011
Mar., 2013
6, 15, 16 & 18
1.Add supporting DDR3L, DDR3U, LPDDR3
and DDR4
2.Add OCP trip threshold and current spec
3.Add soldering information
1,7 & 8
4.Add junction temperature absolute
maximum rating
Publication Date: Mar., 2013
-17-
Revision A4
NCT3101S
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insecure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types
of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims
to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages
and liabilities thus incurred by Nuvoton.
Publication Date: Mar., 2013
-18-
Revision A4
相关型号：
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