MTV212A24 [ETC]
8051 Embedded Monitor Controller MTP Type; 8051嵌入式控制器监控MTP类型
| 型号： | MTV212A24 |
| 厂家： | 
ETC |
| 描述： | 8051 Embedded Monitor Controller MTP Type |
| 文件： | 总27页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MTV212M64
(Rev. 1.2)
MYSON
TECHNOLOGY
8051 Embedded Monitor Controller
MTP Type
FEATURES
·
·
·
·
·
8051 core, 12MHz operating frequency.
1024-byte RAM, 64K-byte program Flash-ROM.·
Maximum 14 channels of 9V open-drain PWM DAC.
Maximum 32 bi-directional I/O pins.
SYNC processor for composite separation/insertion, H/V polarity/frequency check, polarity adjustment
and programmable clamp pulse output.
·
·
·
·
·
·
·
·
Built-in self-test pattern generator with three free-running timings.
Built-in low power reset circuit.
Compliant with VESA DDC1/2B/2Bi/2B+ standard.
Dual slave IIC addresses.
Single master IIC interface for internal device communication.
4-channel 6-bit ADC.
Watchdog timer with programmable interval.
Compliant with Low Speed USB Spec.1.1 including 2 Endpoints: one is Control endpoint (8-byte IN & 8-
byte OUT FIFOs), the other one is Interrupt endpoint (8-byte IN FIFO).
Built-in 3.3V regulator for USB Interface.
·
·
40-pin DIP, 42-pin SDIP or 44-pin PLCC package.
GENERAL DESCRIPTIONS
The MTV212M micro-controller is an 8051 CPU core embedded device specially tailored to Monitor
applications. It includes an 8051 CPU core, 1024-byte SRAM, SYNC processor, 14 built-in PWM DACs,
VESA DDC interface, 4-channel A/D converter, Low Speed USB Interface and a 64K-byte internal program
Flash-ROM.
BLOCK DIAGRAM
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without
notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
Revision 1.2
- 1 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
DEVICE SUMMARY
The MTV212M is the MTP (Multi-Time Programming) type device for all of MTV212A mask ROM derivatives,
the memory size and package differences please see the table below:
Part Number
MTV212A16
MTV212A24
MTV212A32
MTV212A32U
MTV212A48U
MTV212A64U
USB
No
No
ROM
16K
24K
32K
32K
48K
64K
RAM
256
512
512
768
768
1024
Package
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
PDIP40, SDIP42, PLCC44
No
Yes
Yes
Yes
The use of Auxiliary RAM (AUXRAM) is limited for targeted mask ROM, the allowable XBANK (35h) bank
selection is defined as the table below:
Part Number
MTV212A16
MTV212A24
RAM
256
512
Xbnk2
Xbnk1
Xbnk0
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MTV212A32
512
768
MTV212A32U
MTV212A48U
MTV212A64U
768
1024
Remark:
The major pin connection differences between USB (MTV212M64U) and non-USB (MTV212M64) types are
pin# 4, #5 and #6 for SDIP42 and PLCC44. The pin name of USB device is V33CAP(#4), VM(#5) and
VP(#6), while NC (No Connection) for non-USB device.
Revision 1.2
- 2 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
PIN CONNECTION
DA2/P5.2
DA1/P5.1
DA0/P5.0
RST
1
2
3
4
5
6
7
8
9
40 VSYNC
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP
DM
1
2
3
4
5
6
7
8
9
40 VSYNC
39 HSYNC
39 HSYNC
38 DA3/P5.3
37 DA4/P5.4
36 DA5/P5.5
35 DA8/HALFH
34 DA9/HALFV
33 HBLANK/P4.1
32 VBLANK/P4.0
31 DA7/HCLAMP
30 DA6/P5.6
29 P2.7/DA13
28 P2.6/DA12
27 P2.5/DA11
26 P2.4/DA10
25 HSCL/P3.0/Rxd
24 HSDA/P3.1/Txd
23 P2.0/AD0
22 P2.1/AD1
21 P1.7
38 DA3/P5.3
37 DA4/P5.4
36 DA5/P5.5
35 DA8/HALFH
34 DA9/HALFV
VDD
VSS
DP
X2
RST
X1
VDD
33 HBLANK/P4.1
MTV212M
40 Pin
PDIP #1
MTV212M
40 Pin
PDIP #2
ISDA/P3.4/T0
VSS
32 VBLANK/P4.0
ISCL/P3.5/T1 10
STOUT/P4.2 11
P2.2/AD2 12
P1.0 13
X2 10
X1 11
31 DA7/HCLAMP
30 DA6/P5.6
29 P2.4/DA10
28 HSCL/P3.0/Rxd
27 HSDA/P3.1/Txd
26 P2.0/AD0
25 P2.1/AD1
24 P1.7
Non-USB
ISDA/P3.4/T0 12
ISCL/P3.5/T1 13
STOUT/P4.2 14
P2.2/AD2 15
P1.0 16
USB
P1.1 14
P3.2/INT0 15
P1.2 16
P1.3 17
P1.1 17
P1.4 18
P3.2/INT0 18
P1.2 19
23 P1.6
P1.5 19
22 P1.5
P1.6 20
P1.3 20
21 P1.4
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
1
2
3
4
5
6
7
8
9
42 VSYNC
41 HSYNC
40 DA3/P5.3
39 DA4/P5.4
38 DA5/P5.5
37 DA8/HALFH
36 DA9/HALFV
35 HBLANK/P4.1
34 VBLANK/P4.0
33 DA7/HCLAMP
32 DA6/P5.6
31 P2.6/DA12
30 P2.5/DA11
29 P2.4/DA10
28 HSCL/P3.0/Rxd
27 HSDA/P3.1/Txd
26 P2.0/AD0
25 P2.1/AD1
24 P1.7
RST
7
8
9
39 DA8/HALFH
38 DA9/HALFV
37 HBLANK/P4.1
36 VBLANK/P4.0
35 DA7/HCLAMP
34 DA6/P5.6
VDD
RST
P2.3/AD3
MTV212M
44 Pin
PLCC
VDD
VSS 10
X2 11
MTV212M
42 Pin
VSS
X2 10
X1 11
X1 12
SDIP
ISDA/P3.4/T0 13
ISCL/P3.5/T1 14
STOUT/P4.2 15
P2.2/AD2 16
P1.0 17
33 P2.7/DA13
32 P2.6/DA12
31 P2.5/DA11
30 P2.4/DA10
29 HSCL/P3.0/Rxd
USB
or
Non-USB
USB
or
Non-USB
ISDA/P3.4/T0 12
ISCL/P3.5/T1 13
STOUT/P4.2 14
P2.2/AD2 15
P1.0 16
P1.1 17
P3.2/INT0 18
P1.2 19
P1.3 20
23 P1.6
P1.4 21
22 P1.5
Revision 1.2
- 3 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
PIN DESCRIPTION
Pin#
40 40 42 44
Name
DA2/P5.2
DA1/P5.1
DA0/P5.0
V33CAP/NC
DM/NC
DP/NC
RST
VDD
P2.3/AD3
VSS
Type
Description
I/O
I/O
I/O
I/O
I/O
I/O
I
-
I/O
-
1
2
3
-
-
-
4
5
-
6
7
8
9
1
2
3
4
5
6
7
8
-
1
2
3
4
5
6
7
8
-
1
2
3
4
5
6
7
8
9
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
PWM DAC output / General purpose I/O (open drain).
3.3V Regulator Capacitor connection or NC.
USB DM or NC.
USB DP or NC.
Active high reset.
Positive Power Supply.
General purpose I/O / ADC Input.
9
9
10 Ground.
X2
X1
O
I
10 10 11 Oscillator output.
11 11 12 Oscillator input.
12 12 13 Master IIC data / General purpose I/O / T0.
ISDA/P3.4/T0
ISCL/P3.5/T1
STOUT/P4.2
P2.2/AD2
P1.0
P1.1
P3.2/INT0
P1.2
P1.3
P1.4
P1.5
P1.6
I/O
I/O
O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
10 13 13 14 Master IIC clock / General purpose I/O / T1.
11 14 14 15 Self-test video output / General purpose Output.
12 15 15 16 General purpose I/O / ADC Input.
13 16 16 17 General purpose I/O.
14 17 17 18 General purpose I/O.
15 18 18 19 General purpose Input / INT0.
16 19 19 20 General purpose I/O.
17 20 20 21 General purpose I/O.
18 21 21 22 General purpose I/O.
19 22 22 23 General purpose I/O.
20 23 23 24 General purpose I/O.
P1.7
21 24 24 25 General purpose I/O.
P2.1/AD1
P2.0/AD0
HSDA/P3.1/Txd
HSCL/P3.0/Rxd
P2.4/DA10
P2.5/DA11
P2.6/DA12
P2.7/DA13
DA6/P5.6
DA7/HCLAMP
VBLANK/P4.0
HBLANK/P4.1
DA9/HALFV
DA8/HALFH
DA5/P5.5
DA4/P5.4
DA3/P5.3
HSYNC
22 25 25 26 General purpose I/O / ADC Input.
23 26 26 27 General purpose I/O / ADC Input.
24 27 27 28 Slave IIC data / General purpose I/O / Txd.
25 28 28 29 Slave IIC clock / General purpose I/O / Rxd.
26 29 29 30 General purpose I/O / PWM DAC output (open drain).
27
28
29
-
-
-
30 31 General purpose I/O / PWM DAC output (open drain).
31 32 General purpose I/O / PWM DAC output (open drain).
-
33 General purpose I/O / PWM DAC output (open drain).
30 30 32 34 PWM DAC output / General purpose I/O (open drain).
31 31 33 35 PWM DAC output / Hsync clamp pulse output (open drain).
32 32 34 36 Vertical blank / General purpose Output.
O
O
O
O
I/O
O
O
I
I
33 33 35 37 Horizontal blank / General purpose Output.
34 34 36 38 PWM DAC output / Vsync half freq. output (open drain).
35 35 37 39 PWM DAC output / Hsync half freq. output (open drain).
36 36 38 40 PWM DAC output / General purpose I/O (open drain).
37 37 39 41 PWM DAC output / General purpose I/O (open drain).
38 38 40 42 PWM DAC output / General purpose I/O (open drain).
39 39 41 43 Horizontal SYNC or Composite SYNC Input.
40 40 42 44 Vertical SYNC input.
VSYNC
Revision 1.2
- 4 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
FUNCTIONAL DESCRIPTIONS
1. 8051 CPU Core
MTV212M includes all 8051 functions with the following exceptions:
1.1 PSEN, ALE, RD and WR pins are disabled. The external RAM access is restricted to XFRs within the
MTV212M.
1.2 Port0, port3.3, port3.6 and port3.7 are not general-purpose I/O ports. They are dedicated to monitor
special application.
1.3 INT1 input pin is not provided, it is connected to special interrupt sources.
1.4 Port2 are shared with special function pins.
In addition, there are 2 timers, 5 interrupt sources and serial interface compatible with the standard 8051.
Note: All registers listed in this document reside in external RAM area (XFR). For internal RAM memory map
please refer to 8051 spec.
2. Memory Allocation
2.1 Internal Special Function Registers (SFR)
The SFR is a group of registers that are the same as standard 8051.
2.2 Internal RAM
There are total 256 bytes internal RAM in MTV212M, same as standard 8052.
2.3 External Special Function Registers (XFR)
The XFR is a group of registers allocated in the 8051 external RAM area 00h - 7Fh. Most of the registers are
used for monitor control or PWM DAC. Program can initialize Ri value and use "MOVX" instruction to access
these registers.
2.4 Auxiliary RAM (AUXRAM)
There are total 768 bytes auxiliary RAM allocated in the 8051 external RAM area 80h - FFh. The AUXRAM is
divided into six banks, selected by XBANK register. Program can initialize Ri value and use "MOVX"
instruction to access the AUXRAM.
FFh
Internal RAM
SFR
Accessible by
indirect
Accessible by
direct addressing
addressing only
(Using
MOV A,@Ri
instruction)
80h
7Fh
Internal RAM
Accessible by
direct and indirect
addressing
00h
Revision 1.2
- 5 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
FFh
AUXRAM
AUXRAM
AUXRAM
AUXRAM
AUXRAM
AUXRAM
Accessible by
indirect external
RAM addressing
Accessible by
indirect external
RAM addressing
Accessible by
indirect external
RAM addressing
Accessible by
indirect external
RAM addressing
Accessible by
indirect external
RAM addressing
Accessible by
indirect external
RAM addressing
(XBANK=0)(Using (XBANK=1)(Using (XBANK=2)(Using (XBANK=3)(Using (XBANK=4)(Using (XBANK=5)(Using
MOVX A,@Ri
instruction)
MOVX A,@Ri
instruction)
MOVX A,@Ri
instruction)
MOVX A,@Ri
instruction)
MOVX A,@Ri
instruction)
MOVX A,@Ri
instruction)
80h
7Fh
XFR
Accessible by
indirect external
RAM addressing
(Using
MOVX A,@Ri
instruction
00h
3. Chip Configuration
The Chip Configuration registers define the chip pins function, as well as the functional blocks' connection,
configuration and frequency.
Reg name
PADMOD
PADMOD
PADMOD
OPTION
OPTION
XBANK
addr
bit7
bit6
bit5
bit4
bit3
AD3E
P53E
bit2
AD2E
P52E
P42E
Msel
bit1
bit0
30h (w) DA13E DA12E DA11E DA10E
AD1E
P51E
P41E
MIICF1 MIICF0
SlvAbs1 SlvAbs0
AD0E
P50E
P40E
31h (w)
32h (w)
33h (w)
34h (w)
35h (r/w)
P56E
IIICE
P55E
P54E
HIICE
PWMF DIV253
HLFVE HLFHE HCLPE
FclkE IICpass ENSCL
Xbnk2
Xbnk1
Xbnk0
PADMOD (w) : Pad mode control registers. (All are "0" in Chip Reset)
DA13E = 1
= 0
DA12E = 1
= 0
DA11E = 1
= 0
DA10E = 1
= 0
AD3E = 1
= 0
AD2E = 1
= 0
AD1E = 1
= 0
AD0E = 1
= 0
® pin “P2.7/DA13” is DA13.
® pin “P2.7/DA13” is P2.7.
® pin “P2.6/DA12” is DA12.
® pin “P2.6/DA12” is P2.6.
® pin “P2.5/DA11” is DA11.
® pin “P2.5/DA11” is P2.5.
® pin “P2.4/DA10” is DA10.
® pin “P2.4/DA10” is P2.4.
® pin “P2.3/AD3” is AD3.
® pin “P2.3/AD3” is P2.3.
® pin “P2.2/AD2” is AD2.
® pin “P2.2/AD2” is P2.2.
® pin “P2.1/AD1” is AD1.
® pin “P2.1/AD1” is P2.1.
® pin “P2.0/AD0” is AD0.
® pin “P2.0/AD0” is P2.0.
® pin “DA6/P5.6” is P5.6.
® pin “DA6/P5.6” is DA6.
® pin “DA5/P5.5” is P5.5.
® pin “DA5/P5.5” is DA5.
P56E = 1
= 0
P55E = 1
= 0
Revision 1.2
- 6 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
P54E = 1
= 0
P53E = 1
= 0
P52E = 1
= 0
P51E = 1
= 0
P50E = 1
= 0
HIICE = 1
= 0
IIICE = 1
= 0
® pin “DA4/P5.4” is P5.4.
® pin “DA4/P5.4” is DA4.
® pin “DA3/P5.3” is P5.3.
® pin “DA3/P5.3” is DA3.
® pin “DA2/P5.2” is P5.2.
® pin “DA2/P5.2” is DA2.
® pin “DA1/P5.1” is P5.1.
® pin “DA1/P5.1” is DA1.
® pin “DA0/P5.0” is P5.0.
® pin “DA0/P5.0” is DA0.
® pin “HSCL/P3.0/Rxd” is HSCL;
® pin “HSCL/P3.0/Rxd” is P3.0/Rxd;
® pin “ISDA/P3.4/T0” is ISDA;
® pin “ISDA/P3.4/T0” is P3.4/T0;
pin “HSDA/P3.1/Txd” is HSDA.
pin “HSDA/P3.1/Txd” is P3.1/Txd.
pin “ISCL/P3.5/T1” is ISCL.
pin “ISCL/P3.5/T1” is P3.5/T1.
HLFVE = 1
= 0
® pin “DA9/HALFV” is VSYNC half frequency output.
® pin “DA9/HALFV” is DA9.
HLFHE = 1
= 0
® pin “DA8/HALFH” is HSYNC half frequency output.
® pin “DA8/HALFH” is DA8.
HCLPE = 1
= 0
® pin “DA7/HCLAMP” is HSYNC clamp pulse output.
® pin “DA7/HCLAMP” is DA7.
P42E = 1
= 0
® pin “STOUT/P4.2” is P4.2.
® pin “STOUT/P4.2” is STOUT.
P41E = 1
= 0
P40E = 1
= 0
® pin “HBLANK/P4.1” is P4.1.
® pin “HBLANK/P4.1” is HBLANK.
® pin “VBLANK/P4.0” is P4.0.
® pin “VBLANK/P4.0” is VBLANK.
OPTION (w) : Chip option configuration (All are "0" in Chip Reset).
PWMF = 1
= 0
® select 94KHz PWM frequency.
® select 47KHz PWM frequency.
DIV253 = 1
= 0
FclkE = 1
IICpass = 1
= 0
® PWM pulse width is 253 step resolution.
® PWM pulse width is 256 step resolution.
® Double CPU clock freq.
® HSCL/HSDA pin bypass to ISCL/ISDA pin in DDC2 mode.
® Separate Master and Slave IIC block.
® Enable slave IIC block to hold HSCL pin low while MTV212M can't catch-up the
external master's speed.
ENSCL = 1
Msel
= 1
= 0
® Master IIC block connect to HSCL/HSDA pins.
® Master IIC block connect to ISCL/ISDA pins.
MIICF1,MIICF0 = 1,1 ® select 400KHz Master IIC frequency.
= 1,0 ® select 200KHz Master IIC frequency.
= 0,1 ® select 50KHz Master IIC frequency.
= 0,0 ® select 100KHz Master IIC frequency.
SlvAbs1,SlvAbs0 : Slave IIC block A's slave address length.
= 1,0 ® 5-bits slave address.
= 0,1 ® 6-bits slave address.
= 0,0 ® 7-bits slave address.
XBANK (r/w) : Auxiliary RAM bank switch.
Xbnk[2:0]
= 0
= 1
= 2
= 3
® Select AUXRAM bank 0.
® Select AUXRAM bank 1.
® Select AUXRAM bank 2.
® Select AUXRAM bank 3.
Revision 1.2
- 7 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
= 4
= 5
® Select AUXRAM bank 4.
® Select AUXRAM bank 5.
4. Extra I/O
The extra I/O is a group of I/O pins located in XFR area. Port4 is output mode only. Port5 can be used as
both output and input, because Port5's pin is open drain type, user must write Port5's corresponding bit to
"1" in input mode.
Reg name
PORT4
PORT5
addr
38h (w)
39h (r/w)
bit7
bit6
bit5
bit4
bit3
bit2
P42
P52
bit1
P41
P51
bit0
P40
P50
P56
P55
P54
P53
PORT4 (w) :
Port 4 data output value.
PORT5 (r/w) : Port 5 data input/output value.
5. PWM DAC
Each PWM DAC converter's output pulse width is controlled by an 8-bit register in XFR. The frequency of
PWM clk is 47KHz or 94KHz, selected by PWMF. And the total duty cycle step of these DAC outputs is 253
or 256, selected by DIV253. If DIV253=1, writing FDH/FEH/FFH to DAC register generates stable high
output. If DIV253=0, the output will pulse low at least once even if the DAC register's content is FFH. Writing
00H to DAC register generates stable low output.
Reg name
DA0
addr
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DA13
DA0-13 (r/w) : The output pulse width control for DA0-13.
* All of PWM DAC converters are centered with value 80h after power on.
6. H/V SYNC Processing
The H/V SYNC processing block performs the functions of composite signal separation/insertion, SYNC
inputs presence check, frequency counting, polarity detection and control, as well as the protection of
VBLANK output while VSYNC speed up in high DDC communication clock rate. The present and frequency
function block treat any pulse shorter than one OSC period as noise.
Revision 1.2
- 8 -
2000/07/04
MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
Present
Digital Filter
Vpre
Check
Vfreq
Vpol
Polarity Check &
Freq. Count
Vbpl
VSYNC
XOR
CVSYNC
XOR
VBLANK
Vself
CVpre
Present
Check
Polarity Check &
Sync Seperator
Hpol
Digital Filter
Hpre
Present Check &
Freq. Count
Hfreq
Hbpl
Composite
Pulse Insert
XOR
Hself
HSYNC
XOR
HBLANK
H/V SYNC Processor Block Diagram
6.1 Composite SYNC separation/insertion
The MTV212M continuously monitors the input HSYNC, if the vertical SYNC pulse can be extracted from the
input, a CVpre flag is set and user can select the extracted "CVSYNC" for the source of polarity check,
frequency count, and VBLANK output. The CVSYNC will have 8us delay compared to the original signal.
The MTV212M can also insert pulse to HBLANK output during composite VSYNC’s active time. The insert
pulse’s width is 1/8 HSYNC period and the insertion frequency can adapt to original HSYNC.
6.2 H/V Frequency Counter
MTV212M can discriminate HSYNC/VSYNC frequency and saves the information in XFRs. The 14 bits
Hcounter counts the time of 64xHSYNC period, then load the result into the HCNTH/HCNTL latch. The
output value will be [(128000000/H-Freq) - 1], updated once per VSYNC/CVSYNC period when
VSYNC/CVSYNC is present or continuously updated when VSYNC/CVSYNC is non-present. The 12 bits
Vcounter counts the time between two VSYNC pulses, then load the result into the VCNTH/VCNTL latch.
The output value will be (62500/V-Freq), updated every VSYNC/CVSYNC period. An extra overflow bit
indicates the condition of H/V counter overflow. The VFchg/HFchg interrupt is set when VCNT/HCNT value
changes or overflow. Table 4.2.1 and table 4.2.2 shows the HCNT/VCNT value under the operations of
12MHz.
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6.2.1 H-Freq Table
H-Freq(KHZ)
Output Value (14 bits)
12MHz OSC (hex / dec)
0FDEh / 4062
0D54h / 3412
0B8Bh / 2955
0AA8h / 2728
094Fh / 2383
0854h / 2132
0746h / 1862
06AAh / 1706
063Fh / 1599
05D1h / 1489
0554h / 1364
04B3h / 1203
1
31.5
37.5
43.3
46.9
53.7
60.0
68.7
75.0
80.0
85.9
93.8
106.3
2
3
4
5
6
7
8
9
10
11
12
6.2.2 V-Freq Table
Output value (12bits)
12MHz OSC (hex / dec)
45Ch / 1116
V-Freq(Hz)
1
2
3
4
5
6
56
60
70
72
75
85
411h / 1041
37Ch / 892
364h / 868
341h / 833
2DFh / 735
6.3 H/V Present Check
The Hpresent function checks the input HSYNC pulse, Hpre flag is set when HSYNC is over 10KHz or
cleared when HSYNC is under 10Hz. The Vpresent function checks the input VSYNC pulse, the Vpre flag is
set when VSYNC is over 40Hz or cleared when VSYNC is under 10Hz. The HPRchg interrupt is set when
the Hpre value changes. The VPRchg interrupt is set when the Vpre/CVpre value change. However, the
CVpre flag interrupt may be disabled when S/W disable the composite function.
6.4 H/V Polarity Detect
The polarity functions detect the input HSYNC/VSYNC high and low pulse duty cycle. If the high pulse
duration is longer than that of low pulse, the negative polarity is asserted; otherwise, positive polarity is
asserted. The HPLchg interrupt is set when the Hpol value changes. The VPLchg interrupt is set when the
Vpol value changes.
6.5 Output HBLANK/VBLANK Control and Polarity Adjust
The HBLANK is the mux output of HSYNC, composite Hpulse and self-test horizontal pattern. The VBLANK
is the mux output of VSYNC, CVSYNC and self-test vertical pattern. The mux selection and output polarity
are S/W controllable. The VBLANK output is cut off when VSYNC frequency is over 200Hz. The
HBLANK/VBLANK shares the output pin with P4.1/ P4.0.
6.6 Self Test Pattern Generator
This generator can generate 4 display patterns for testing purpose, which are positive cross-hatch, negative
cross-hatch, full white, and full black (showed as following figure). The HBLANK output frequency of the
pattern can be chosen to 63.5KHz, 47.6KHz and 31.75KHz. The VBLANK output frequency of the pattern is
60Hz. It is originally designed to support monitor manufacturer to do burn-in test, or offer end-user a
reference to check the monitor. The generator's output STOUT shares the output pin with P4.2.
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Display Region
Positive cross-hatch
Negative cross-hatch
Full white
Full black
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MTV212M Self-Test pattern timing
63.5KHz, 60Hz 47.6KHz, 60Hz
Absolute time H dots Absolute time H dots
31.7KHz, 60Hz
Absolute time
31.5us
24.05us
0.45us
3us
H dots
640
488.6
9
Hor. Total time (A)
Hor. Active time (D)
Hor. F. P. (E)
15.75us
12.05us
0.2us
1280
979.3
16.25
122
21.0us
16.07us
0.28us
2us
1024
783.2
12
SYNC pulse width (B)
Hor. B. P. (C)
1.5us
90
61
2us
162.54
2.67us
110
4us
81.27
Absolute time
16.663ms
15.655ms
0.063ms
V lines
1024
962
3.87
3.87
54.2
Absolute time
16.663ms
15.655ms
0.063ms
V lines
768
721.5
2.9
2.9
40.5
Absolute time
16.663ms
15.655ms
0.063ms
V lines
480
451
1.82
1.82
25.4
Vert. Total time (O)
Vert. Active time (R)
Vert. F. P. (S)
SYNC pulse width (P)
Vert. B. P. (Q)
0.063ms
0.882ms
0.063ms
0.882ms
0.063ms
0.882ms
* 8 x 8 blocks of cross hatch pattern in display region.
6.7 HSYNC Clamp Pulse Output
The HCLAMP output is active by setting “HCLPE” control bit. The HCLAMP’s leading edge position, pulse
width and polarity is S/W controllable.
6.8 VSYNC Interrupt
The MTV212M check the VSYNC input pulse and generate an interrupt at its leading edge. The VSYNC flag
is set each time when MTV212M detects a VSYNC pulse. The flag is cleared by S/W writing a "0".
6.9 H/V SYNC Processor Register
Reg name
HVSTUS
HCNTH
HCNTL
VCNTH
VCNTL
HVCTR0
HVCTR2
HVCTR3
INTFLG
INTEN
addr
bit7
CVpre
Hovf
HF7
Vovf
VF7
bit6
bit5
Hpol
HF13
HF5
bit4
Vpol
HF12
HF4
bit3
Hpre
HF11
HF3
VF11
VF3
bit2
Vpre
HF10
HF2
VF10
VF2
bit1
Hoff
HF9
HF1
VF9
VF1
HBpl
Rt0
bit0
Voff
HF8
HF0
VF8
VF0
VBpl
STE
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
40h (w)
42h (w)
43h (w)
HF6
VF6
C0
VF5
NoHins
Selft
VF4
C1
STF1
STF0
Rt1
CLPEG CLPPO CLPW2 CLPW1 CLPW0
48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg
49h (w) EHPR EVPR EHPL EVPL EHF
VFchg
EVF
Vsync
EVsync
HVSTUS (r) : The status of polarity, present and static level for HSYNC and VSYNC.
CVpre = 1
= 0
® The extracted CVSYNC is present.
® The extracted CVSYNC is not present.
® HSYNC input is positive polarity.
® HSYNC input is negative polarity.
® VSYNC (CVSYNC) is positive polarity.
® VSYNC (CVSYNC) is negative polarity.
® HSYNC input is present.
® HSYNC input is not present.
® VSYNC input is present.
® VSYNC input is not present.
® HSYNC input's off level is high.
H
= 1
= 0
= 1
= 0
= 1
= 0
= 1
= 0
= 1
pol
V
pol
H
pre
V
pre
H
off*
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= 0
= 1
= 0
® HSYNC input's off level is low.
® VSYNC input's off level is high.
® VSYNC input's off level is low.
V
off*
*H and V are valid when H
or V
off off pre=0
pre=0.
HCNTH (r) :
Hovf
HF13 - HF8 : 6 high bits of H-Freq counter.
H-Freq counter's high bits.
= 1 ® H-Freq counter is overflow, this bit is clear by H/W when condition removed.
HCNTL (r) :
H-Freq counter's low byte.
VCNTH (r) :
V-Freq counter's high bits.
Vovf
VF11 - 8 :
= 1
® V-Freq counter is overflow, this bit is clear by H/W when condition removed.
4 high bits of V-Freq counter.
VCNTL (r) :
V-Freq counter's low byte.
HVCTR0 (w) : H/V SYNC processor control register 0.
C1, C0 = 1,1 ® Select CVSYNC as the polarity, freq and VBLANK source.
= 1,0 ® Select VSYNC as the polarity, freq and VBLANK source.
= 0,0 ® Disable composite function.
= 0,1 ® H/W auto switch to CVSYNC when CVpre=1 and VSpre=0.
NoHins = 1
= 0
® HBLANK has no insert pulse in composite mode.
® HBLANK has insert pulse in composite mode.
® negative polarity HBLANK output.
® positive polarity HBLANK output.
® negative polarity VBLANK output.
HB
= 1
= 0
= 1
= 0
pl
VB
pl
® positive polarity VBLANK output.
HVCTR2 (w) : Self-test pattern generator control.
S
elft
= 1
® enable generator.
= 0
® disable generator.
STF1,STF0
= 1,1 ® 63.5KHz(horizontal) output selected.
= 1,0 ® 47.6KHz(horizontal) output selected.
= 0,0 ® 31.75KHz(horizontal) output selected.
Rt1, Rt0= 0,0 ® positive cross-hatch pattern output.
= 0,1 ® negative cross-hatch pattern output.
= 1,0 ® full white pattern output.
= 1,1 ® full black pattern output.
STE
= 1
= 0
® enable STOUT output.
® disable STOUT output.
HVCTR3 (w) : HSYNC clamp pulse control register.
CLPEG = 1
= 0
CLPPO = 1
= 0
® Clamp pulse follows HSYNC leading edge.
® Clamp pulse follows HSYNC trailing edge.
® Positive polarity clamp pulse output.
® Negative polarity clamp pulse output.
CLPW2 : CLPW0 : Pulse width of clamp pulse is
[(CLPW2:CLPW0) + 1] x 0.167 ms for 12MHz X’tal selection.
INTFLG (w) : Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 core's INT1 source will be driven by a zero level. Software MUST
clear this register while serve the interrupt routine.
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HPRchg= 1
= 0
VPRchg= 1
= 0
HPLchg= 1
= 0
VPLchg= 1
= 0
HFchg = 1
= 0
VFchg = 1
= 0
Vsync = 1
= 0
® No action.
® Clear HSYNC presence change flag.
® No action.
® Clear VSYNC presence change flag.
® No action.
® Clear HSYNC polarity change flag.
® No action.
® Clear VSYNC polarity change flag.
® No action.
® Clear HSYNC frequency change flag.
® No action.
® Clear VSYNC frequency change flag.
® No action.
® Clear VSYNC interrupt flag.
INTFLG (r) :
Interrupt flag.
HPRchg= 1
VPRchg= 1
HPLchg= 1
VPLchg= 1
HFchg = 1
VFchg = 1
Vsync = 1
® Indicates a HSYNC presence change.
® Indicates a VSYNC presence change.
® Indicates a HSYNC polarity change.
® Indicates a VSYNC polarity change.
® Indicates a HSYNC frequency change or counter overflow.
® Indicates a VSYNC frequency change or counter overflow.
® Indicates a VSYNC interrupt.
INTEN (w) :
Interrupt enable.
EHPR = 1
EVPR = 1
EHPL = 1
EVPL = 1
® Enable HSYNC presence change interrupt.
® Enable VSYNC presence change interrupt.
® Enable HSYNC polarity change interrupt.
® Enable VSYNC polarity change interrupt.
EHF
EVF
EVsync = 1
= 1
= 1
® Enable HSYNC frequency change / counter overflow interrupt.
® Enable VSYNC frequency change / counter overflow interrupt.
® Enable VSYNC interrupt.
7. DDC & IIC Interface
7.1 DDC1 Mode
The MTV212M enters DDC1 mode after Reset. In this mode, VSYNC is used as data clock. The HSCL pin
should remain at high. The data output to the HSDA pin is taken from a shift register in MTV212M. The shift
register fetch data byte from the DDC1 data buffer (DBUF) then send it in 9 bits packet formats which
includes a null bit (=1) as packet separator. The DBUF set the DbufI interrupt flag when the shift register
read out the data byte from DBUF. Software needs to write EDID data to DBUF as soon as the DbufI is set.
The DbufI interrupt is automatically cleared when Software writes a new data byte to DBUF. The DbufI
interrupt can be mask or enable by EDbufI control bit.
7.2 DDC2B Mode
The MTV212M switches to DDC2B mode when it detects a high to low transition on the HSCL pin. Once
MTV212M enters DDC2B mode, S/W can set IICpass control bit to allow HOST access EEPROM directly.
Under such condition, the HSDA and HSCL are directly bypassed to ISDA and ISCL pins. The other way to
perform DDC2 function is to clear IICpass and config the Slave A IIC block to act as EEPROM behavior. The
Slave A block's slave address can be chosen by S/W as 5-bits, 6-bits or 7-bits. For example, if S/W choose
5-bits slave address as 10100b, the slave IIC block A will respond to slave address 10100xxb and save the 2
LSB "xx" in XFR. This feature enables MTV212M to meet PC99 requirement.
The MTV212M will return to DDC1 mode if HSCL is kept high for 128 VSYNC clock period. However, it will
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lock in DDC2B mode if a valid IIC address (1010xxxb) has been detected on HSCL/HSDA bus. The DDC2
flag reflects the current DDC status, S/W may clear it by writing a "0" to it.
7.3 Slave Mode IIC function Block
The slave mode IIC block is connected to HSDA and HSCL pins. This block can receive/transmit data using
IIC protocol. There are 2 slave addresses MTV212M can respond to. S/W may write the
SLVAADR/SLVBADR register to determine the slave addresses. The SlaveA address can be configured to
5-bits, 6-bits or 7-bits by S/W setting the SlvAbs1 and SlvAbs0 control bits.
In receive mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. If the matched address is slave A, MTV212M will save the matched address's 2 LSB bits to
SlvAlsb1 and SlvAlsb0 register. The data from HSDA is shifted into shift register then written to
RCABUF/RCBBUF register when a data byte is received. The first byte loaded is word address (slave
address is dropped). This block also generates a RCAI/RCBI (receive buffer full interrupt) every time when
the RCABUF/RCBBUF is loaded. If S/W can't read out the RCABUF/RCBBUF in time, the next byte in shift
register will not be written to RCABUF/RCBBUF and the slave block return NACK to the master. This feature
guarantees the data integrity of communication. The WadrA/WadrB flag can tell S/W that if the data in
RCABUF/RCBBUF is a word address.
In transmit mode, the block first detects IIC slave address match condition then issues a SlvAMI/SlvBMI
interrupt. In the mean time, the SlvAlsb1/SlvAlsb0 is also updated if the matched address is slave A, and the
data pre-stored in the TXABUF/TXBBUF is loaded into shift register, result in TXABUF/TXBBUF empty and
generates a TXAI/TXBI (transmit buffer empty interrupt). S/W should write the TXABUF/TXBBUF a new byte
for next transfer before shift register empty. Fail to do this will cause data corrupt. The TXAI/TXBI occurs
every time when shift register reads out the data from TXABUF/TXBBUF.
The SlvAMI/SlvBMI is cleared by writing "0" to corresponding bit in INTFLG register. The RCAI/RCBI is
cleared by reading RCABUF/RCBBUF. The TXAI/TXBI is cleared by writing TXABUF/TXBBUF. If the control
bit ENSCL is set, the block will hold HSCL low until the RCAI/RCBI/TXAI/TXBI is cleared.
*Please see the attachments about "Slave IIC Block Timing".
7.4 Master Mode IIC Function Block
The master mode IIC block can be connected to the ISDA /ISCL pins or the HSDA/HSCL pins, select by
Msel control bit. Its speed can be selected to 50KHz-400KHz by S/W setting the MIICF1/MIICF0 control bit.
The software program can access the external IIC device through this interface. Since the EDID/VDIF data
and the display information share the common EEPROM, precaution must be taken to avoid bus conflicting
while Msel=0. In DDC1 mode or IICpass=0, the ISCL/ISDA is controlled by MTV212M only. In DDC2 mode
and IICpass flag is set, the host may access the EEPROM directly. Software can test the HSCL condition by
reading the Hbusy flag, which is set in case of HSCL=0, and keeps high for 100uS after the HSCL's rising
edge. S/W can launch the master IIC transmit/receive by clearing the P bit. Once P=0, MTV212M will hold
HSCL low to isolate the host's access to EEPROM. A summary of master IIC access is illustrated as follows.
7.4.1. To write IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M transmit this byte, a MbufI interrupt will be triggered.
4. Program can write MBUF to transfer next byte or set P bit to stop.
* Please see the attachments about "Master IIC Transmit Timing".
7.4.2. To read IIC Device
1. Write MBUF the Slave Address.
2. Set S bit to Start.
3. After the MTV212M transmit this byte, a MbufI interrupt will be triggered.
4. Set or reset the MAckO flag according to the IIC protocol.
5. Read out MBUF the useless byte to continue the data transfer.
6. After the MTV212M receives a new byte, the MbufI interrupt is triggered again.
7. Read MBUF also trigger the next receive operation, but set P bit before read can terminate the operation.
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* Please see the attachments about "Master IIC Receive Timing".
Reg name
IICCTR
addr
00h (r/w) DDC2
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w) ENSlvA
08h (r)
bit7
bit6
bit5
bit4
bit3
SLVS
RCAI
bit2
MAckO
bit1
P
bit0
S
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
WadrB WadrA SlvRWB SAckIn
MAckIn Hifreq
TXBI RCBI
SlvAlsb1 SlvAlsb0
Hbusy
SlvBMI
SlvBMI
TXAI
SlvAMI
SlvAMI
DbufI
MbufI
MbufI
ETXBI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
DBUF
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
08h (w)
09h (w) ENSlvB
0Ah (w)
DDC1 transmit data buffer
IICCTR (r/w) : IIC interface control register.
DDC2 = 1
= 0
® MTV212M is in DDC2 mode, write "0" can clear it.
® MTV212M is in DDC1 mode.
MAckO = 1
= 0
® In master receive mode, NACK is returned by MTV212M.
® In master receive mode, ACK is returned by MTV212M.
S, P
= • , 0 ® Start condition when Master IIC is not during transfer.
= X, • ® Stop condition when Master IIC is not during transfer.
= 1, X ® Will resume transfer after a read/write MBUF operation.
= X, 0 ® Force HSCL low and occupy the master IIC bus.
* A write/read MBUF operation can be recognized only after 10us of the MbufI flag's rising edge.
IICSTUS (r) : IIC interface status register.
WadrB = 1
WadrA = 1
SlvRWB = 1
= 0
® The data in RCBBUF is word address.
® The data in RCABUF is word address.
® Current transfer is slave transmit
® Current transfer is slave receive
SAckIn = 1
® The external IIC host respond NACK.
SLVS = 1
® The slave block has detected a START, cleared when STOP detected.
SlvAlsb1,SlvAlsb0 : The 2 LSB which host send to Slave A block.
MAckIn = 1
= 0
® Master IIC bus error, no ACK received from the slave IIC device.
® ACK received from the slave IIC device.
Hifreq = 1
Hbusy = 1
® MTV212M has detected a higher than 200Hz clock on the VSYNC pin.
® Host drives the HSCL pin to low.
INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
SlvBMI = 1
= 0
SlvAMI = 1
= 0
MbufI = 1
= 0
® No action.
® Clear SlvBMI flag.
® No action.
® Clear SlvAMI flag.
® No action.
® Clear Master IIC bus interrupt flag (MbufI).
INTFLG (r) :
Interrupt flag.
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TXBI = 1
RCBI = 1
SlvBMI = 1
TXAI = 1
RCAI = 1
SlvAMI = 1
DbufI = 1
MbufI = 1
® Indicates the TXBBUF need a new data byte, clear by writing TXBBUF.
® Indicates the RCBBUF has received a new data byte, clear by reading RCBBUF.
® Indicates the slave IIC address B match condition.
® Indicates the TXABUF need a new data byte, clear by writing TXABUF.
® Indicates the RCABUF has received a new data byte, clear by reading RCABUF.
® Indicates the slave IIC address A match condition.
® Indicates the DDC1 data buffer need a new data byte, clear by writing DBUF.
® Indicates a byte is sent/received to/from the master IIC bus.
INTEN (w) :
Interrupt enable.
ETXBI = 1
ERCBI = 1
ESlvBMI = 1
ETXAI = 1
ERCAI = 1
ESlvAMI = 1
EDbufI = 1
EMbufI = 1
® Enable TXBBUF interrupt.
® Enable RCBBUF interrupt.
® Enable slave address B match interrupt.
® Enable TXABUF interrupt.
® Enable RCABUF interrupt.
® Enable slave address A match interrupt.
® Enable DDC1 data buffer interrupt.
® Enable Master IIC bus interrupt.
Mbuf (w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV212M's transmission to the IIC bus.
Mbuf (r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV212M's receiving from the IIC bus.
RCABUF (r) : Slave IIC block A receive data buffer.
TXABUF (w) : Slave IIC block A transmit data buffer.
SLVAADR (w) :Slave IIC block A's enable and address.
ENslvA = 1
= 0
® Enable slave IIC block A.
® Disable slave IIC block A.
bit6-0 :
Slave IIC address A to which the slave block should respond.
RCBBUF (r) : Slave IIC block B receive data buffer.
TXBBUF (w) : Slave IIC block B transmit data buffer.
SLVBADR (w) :Slave IIC block B's enable and address.
ENslvB = 1
= 0
® Enable slave IIC block B.
® Disable slave IIC block B.
bit6-0 :
Slave IIC address B to which the slave block should respond.
8. Low Power Reset (LVR) & Watchdog Timer
When the voltage level of power supply is below 4.0V for a specific time, the LVR will generate a chip reset
signal. After the power supply is above 4.0V, LVR maintain in reset state for 144 Xtal cycle to guarantee the
chip exit reset condition with a stable X'tal oscillation.
The WatchDog Timer automatically generates a device reset when it is overflow. The interval of overflow is
0.25 sec x N, where N is a number from 1 to 8, and can be programmed via register WDT(2:0). The timer
function is disabled after power on reset, user can activate this function by setting WEN, and clear the timer
by set WCLR.
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9. A/D converter
The MTV212M is equipped with four 6-bit A/D converters, S/W can select the current convert channel by
setting the SADC1/SADC0 bit. The refresh rate for the ADC is OSC freq./12288. The ADC compare the input
pin voltage with internal VDD*N/64 voltage (where N = 0 - 63). The ADC output value is N when pin voltage
is greater than VDD*N/64 and smaller than VDD*(N+1)/64.
Reg name
ADC
addr
10h (w) ENADC
10h (r)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SADC3 SADC2 SADC1 SADC0
ADC convert Result
ADC
WDT
18h (w)
WEN
WCLR
WDT2
WDT1
WDT0
WDT (w) :
WEN
Watchdog Timer control register.
= 1
= 1
® Enable WatchDog Timer.
® Clear WatchDog Timer.
WCLR
WDT2: WDT0 = 0
® overflow interval = 8 x 0.25 sec.
® overflow interval = 1 x 0.25 sec.
® overflow interval = 2 x 0.25 sec.
® overflow interval = 3 x 0.25 sec.
® overflow interval = 4 x 0.25 sec.
® overflow interval = 5 x 0.25 sec.
® overflow interval = 6 x 0.25 sec.
® overflow interval = 7 x 0.25 sec.
= 1
= 2
= 3
= 4
= 5
= 6
= 7
ADC (w) :
ADC control.
ENADC
SADC0
SADC1
SADC2
SADC3
= 1
= 1
= 1
= 1
= 1
® Enable ADC.
® Select ADC0 pin input.
® Select ADC1 pin input.
® Select ADC2 pin input.
® Select ADC3 pin input.
ADC (r) :
ADC convert result.
10. USB Engine
The USB engine includes the Serial Interface Engine (SIE), the low-speed USB I/O transceiver and the 3.3
Volt Regulator. The SIE block performs most of the USB interface function with only minimum support from
S/W. Two endpoints are supported. Endpoint 0 is used to receive and transmit control (including SETUP)
packets while Endpoint 1 is only used to transmit data packets.
The USB SIE handles the following USB bus activity independently:
1. Bitstuffing/unstuffing
2. CRC generation/checking
3. ACK/NAK
4. TOKEN type identification
5. Address checking
S/W handles the following tasks:
1. Coordinate enumeration by responding to SETUP packets
2. Fill and empty the FIFOs
3. Suspend/Resume coordination
4. Verify and select DATA toggle values
10.1 USB Device Address
The USBADR register stores the device address. This register is reset to all 0 after chip reset or USB bus
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TECHNOLOGY
(Rev. 1.2)
reset. S/W must write this register a valid value after the USB enumeration process.
10.2 Endpoint 0 receive
After receiving a packet and placing the data into the Endpoint 0 receive FIFO (RC0FIFO), MTV212M
updates the Endpoint 0 status register (EP0STUS) to record the receive status and then generates an
Endpoint 0 receive interrupt (RC0I). S/W can read the EP0STUS register for the recent transfer information,
which includes the data byte count (RC0cnt), data direction (EP0dir), SETUP token flag (EP0set) and data
valid flag (RC0err). The received data is always stored into RC0FIFO and the RC0cnt is always updated for
DATA packets following SETUP tokens. The data following an OUT token is written into the RC0FIFO, and
the RC0cnt is updated unless Endpoint 0 STALL (EP0stall) or Endpoint 0 receive NAK (RC0nak) is set. The
RC0I interrupt will happen in case where the RC0cnt/RC0FIFO is updated.
10.3 Endpoint 0 transmit
After detecting a valid Endpoint 0 IN token, MTV212M automatically transmit the data pre-stored in the
Endpoint 0 transmit FIFO (TX0FIFO) to the USB bus if the Endpoint 0 transmit ready flag (TX0rdy) is set and
the EP0stall is cleared. The number of byte to be transmitted is base on the Endpoint 0 transmit byte count
register (TX0cnt). The DATA0/1 token to be transmitted is base on the Endpoint 0 transmit toggle control bit
(TX0tgl). After the TX0FIFO is updated, TX0rdy should be set to 1. This enables the MTV212M to respond to
an Endpoint 0 IN packet. TX0rdy is cleared and an Endpoint 0 transmit interrupt (TX0I) is generated once the
USB host acknowledges the data transmission. The interrupt service routine can check TX0rdy to confirm
that the data transfer was successful.
10.4 Endpoint 1 transmit
Endpoint 1 is capable of transmit only. This endpoint is enable when the Endpoint1 configured control bit
(EP1Cfgd) is set. After detecting a valid Endpoint 1 IN token, MTV212M automatically transmit the data pre-
stored in the Endpoint 1 transmit FIFO (TX1FIFO) to the USB bus if the Endpoint 1 transmit ready flag
(TX1rdy) is set and the EP1stall is cleared. The number of byte to be transmitted is base on the Endpoint 1
transmit byte count register (TX1cnt). The DATA0/1 token to be transmitted is base on the Endpoint 1
transmit toggle control bit (TX1tgl). After the TX1FIFO is updated, TX1rdy should be set to 1. This enables
the MTV212M to respond to an Endpoint 1 IN packet. TX1rdy is cleared and an Endpoint 1 transmit interrupt
(TX1I) is generated once the USB host acknowledges the data transmission. The interrupt service routine
can check TX0rdy to confirm that the data transfer was successful.
10.5 USB Control and Status
Other USB control bits include the USB enable (ENUSB), SUSPEND (Susp), RESUME (RsmO), Control
Read (CtrRD), and corresponding interrupt enable bits. The CtrRD should be set when program detects the
current transfer is an Endpoint0 Control Read Transfer. Once this bit is set, the MTV212M will stall an
Endpoint0 OUT packet with DATA toggle 0 or byte count other than 0. Other USB status flag includes the
USB reset interrupt (USBrstI), RESUME interrupt (RsmI), and USB bus active flag (USBactv). The USBactv
flag is set once the MTV212M detect the USB bus activity. S/W should read and clear it every 3 ms to
identify the suspend condition. Writing a "1" to the USBactv flag will not change its value.
10.6 Suspend and Resume
Once the Suspend condition is asserted, S/W can set the Susp bit to stop the USBSIE's clock. In the mean
time, the 3.3V Regulator is operating in low power mode. S/W can further save the device power by force the
8051 CPU core into the Power Down or Idle mode by setting the PCON register in SFR area. In the Idel
mode, the X'tal keeps oscillating and CPU can be waken-up by the trigger of any enabled interrupt. In the
Power Down mode, the X'tal is stop, but CPU can be waken-up by the trigger of enabled INT1's source. In
short, S/W can keep the RsmI alive before enter the suspend mode.
Reg name
USBADR
INTFLG
addr
60h (r/w) ENUSB
61h (r/w) USBrstI
bit7
bit6
bit5
bit4
bit3
USBadr
RsmI
bit2
bit1
bit0
RC0I
TX1I
TX0I
INTEN
EP0STUS
62h (w)
63h (r)
EUrstI
ERC0I
ETX1I
ETX0I
ERsmI
RC0tgl RC0err EP0dir EP0set
RC0cnt
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(Rev. 1.2)
USBCTR
TX0CTR
TX0CTR
TX1CTR
TX1CTR
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
64h (r/w)
Susp
RsmO EP1cfgd RC0nak CtrRD
USBactv
TX0cnt
65h (w) TX0rdy TX0tgl EP0stall
65h (r)
66h (w) TX1rdy TX1tgl EP1stall
66h (r)
68h (r)
TX0rdy TX0tgl EP0stall
TX1cnt
TX1rdy TX1tgl EP1stall
Endpoint 0 receive FIFO 1st byte
69h (r)
Endpoint 0 receive FIFO 2nd byte
Endpoint 0 receive FIFO 3rd byte
Endpoint 0 receive FIFO 4th byte
Endpoint 0 receive FIFO 5th byte
Endpoint 0 receive FIFO 6th byte
Endpoint 0 receive FIFO 7th byte
Endpoint 0 receive FIFO 8th byte
Endpoint 0 transmit FIFO 1st byte
Endpoint 0 transmit FIFO 2nd byte
Endpoint 0 transmit FIFO 3rd byte
Endpoint 0 transmit FIFO 4th byte
Endpoint 0 transmit FIFO 5th byte
Endpoint 0 transmit FIFO 6th byte
Endpoint 0 transmit FIFO 7th byte
Endpoint 0 transmit FIFO 8th byte
Endpoint 1 transmit FIFO 1st byte
Endpoint 1 transmit FIFO 2nd byte
Endpoint 1 transmit FIFO 3rd byte
Endpoint 1 transmit FIFO 4th byte
Endpoint 1 transmit FIFO 5th byte
Endpoint 1 transmit FIFO 6th byte
Endpoint 1 transmit FIFO 7th byte
Endpoint 1 transmit FIFO 8th byte
6Ah (r)
6Bh (r)
6Ch (r)
6Dh (r)
6Eh (r)
6Fh (r)
70h (w)
71h (w)
72h (w)
73h (w)
74h (w)
75h (w)
76h (w)
77h (w)
78h (w)
79h (w)
7Ah (w)
7Bh (w)
7Ch (w)
7Dh (w)
7Eh (w)
7Fh (w)
USBADR (r/w) :USB device address and enable.
ENUSB = 1
USBadr :
® Enable USB function, clear while chip reset.
USB device address, clear while chip reset or USB bus reset.
INTFLG (w) : Interrupt flag. A interrupt event will set its individual flag, and, if the corresponding interrupt
enable bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serve the interrupt routine.
USBrstI= 1
= 0
RC0I = 1
= 0
TX1I = 1
= 0
TX0I = 1
= 0
® No action.
® Clear USBrstI flag.
® No action.
® Clear RC0I flag.
® No action.
® Clear TX1I flag.
® No action.
® Clear TX0I flag.
® No action.
® Clear RsmI flag.
RsmI = 1
= 0
INTFLG (r) :
Interrupt flag.
USBrstI= 1
RC0I = 1
TX1I = 1
® Indicates the USB bus reset condition.
® Endpoint 0 has completed a receive transfer and save the data in RC0FIFO.
® Endpoint 1 has completed a transmit transfer and empty TX1FIFO.
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TECHNOLOGY
(Rev. 1.2)
TX0I = 1
RsmI = 1
® Endpoint 0 has completed a transmit transfer and empty TX0FIFO.
® Indicates the USB bus RESUME condition in suspend mode.
INTEN (w) :
Interrupt enable.
EUrstI = 1
ERC0I = 1
ETX1I = 1
ETX0I = 1
ERsmI = 1
® Enable USBrstI interrupt.
® Enable RC0I interrupt.
® Enable TX1I interrupt.
® Enable TX0I interrupt.
® Enable RsmI interrupt.
EP0STUS (r) : Endpoint 0 status.
RC0tgl = 1
= 0
® Receive a DATA1 packet.
® Receive a DATA0 packet.
RC0err = 1
= 0
® Receive DATA packet error.
® Receive DATA packet good.
EP0dir = 1
= 0
EP0set = 1
= 0
® Last transfer is transmit direction (IN).
® Last transfer is receive direction (OUT, SETUP).
® Last transfer is a SETUP.
® Last transfer is not a SETUP.
Last transfer's receive byte count.
RC0cnt :
USBCTR (r/w) : USB control register.
Susp = 1
RsmO = 1
EP1cfgd = 1
RC0nak = 1
CtrRD = 1
USBactv = 1
® S/W force USB interface into suspend mode.
® S/W force USB interface into send RESUME signal in suspend mode.
® Endpoint 1 is configed.
® Endpoint 0 will respond NAK to OUT token.
® MTV212M will stall a invalid OUT token during Control Read transfer.
® MTV212M detects USB bus activity, clear by S/W writing "0".
TX0CTR (r/w) : Endpoint 0 transmit control register.
TX0rdy = 1
= 0
® Enable the Endpoint 0 to respond to IN token.
® Endpoint 0 will respond NAK to IN token.
This bit can be set or cleared by S/W, clear by H/W while Host acknowledge the transfer.
TX0tgl = 1
® Endpoint 0 will transmit DATA1 packet.
® Endpoint 0 will transmit DATA0 packet.
® Endpoint 0 will stall OUT/IN packet.
Endpoint 0 transmit byte count, write only.
= 0
EP0stall = 1
TX0cnt :
TX1CTR (r/w) : Endpoint 1 transmit control register.
TX1rdy = 1
= 0
® Enable the Endpoint 1 to respond to IN token.
® Endpoint 1 will respond NAK to IN token.
This bit can be set or cleared by S/W, clear by H/W while Host acknowledge the transfer.
TX1tgl = 1
® Endpoint 1 will transmit DATA1 packet.
® Endpoint 1 will transmit DATA0 packet.
® Endpoint 1 will stall IN packet.
= 0
EP1stall = 1
TX1cnt :
Endpoint 1 transmit byte count, write only.
RC0FIFO (r) : Endpoint 0 receive FIFO registers.
TX0FIFO (w) : Endpoint 0 transmit FIFO registers.
TX1FIFO (w) : Endpoint 1 transmit FIFO registers.
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TECHNOLOGY
(Rev. 1.2)
Memory Map of XFR
Reg name
IICCTR
IICSTUS
IICSTUS
INTFLG
INTFLG
INTEN
MBUF
RCABUF
TXABUF
SLVAADR
RCBBUF
TXBBUF
SLVBADR
DBUF
addr
00h (r/w) DDC2
01h (r)
02h (r)
03h (r)
03h (w)
04h (w)
05h (r/w)
06h (r)
06h (w)
07h (w) ENSlvA
08h (r)
bit7
bit6
bit5
bit4
bit3
SLVS
RCAI
bit2
MAckO
bit1
P
bit0
S
WadrB WadrA SlvRWB SAckIn
MAckIn Hifreq
TXBI RCBI
SlvAlsb1 SlvAlsb0
Hbusy
SlvBMI
SlvBMI
TXAI
SlvAMI
SlvAMI
DbufI
MbufI
MbufI
ETXBI ERCBI ESlvBMI ETXAI ERCAI ESlvAMI EDbufI EMbufI
Master IIC receive/transmit data buffer
Slave A IIC receive buffer
Slave A IIC transmit buffer
Slave A IIC address
Slave B IIC receive buffer
Slave B IIC transmit buffer
Slave B IIC address
08h (w)
09h (w) ENSlvB
0Ah (w)
DDC1 transmit data buffer
ADC
ADC
WDT
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
10h (w) ENADC
10h (r)
SADC3 SADC2 SADC1 SADC0
ADC convert Result
WDT2
18h (w)
20h (r/w)
21h (r/w)
22h (r/w)
23h (r/w)
24h (r/w)
25h (r/w)
26h (r/w)
27h (r/w)
28h (r/w)
29h (r/w)
2Ah (r/w)
2Bh (r/w)
2Ch (r/w)
2Dh (r/w)
WEN
WCLR
WDT1
WDT0
Pulse width of PWM DAC 0
Pulse width of PWM DAC 1
Pulse width of PWM DAC 2
Pulse width of PWM DAC 3
Pulse width of PWM DAC 4
Pulse width of PWM DAC 5
Pulse width of PWM DAC 6
Pulse width of PWM DAC 7
Pulse width of PWM DAC 8
Pulse width of PWM DAC 9
Pulse width of PWM DAC 10
Pulse width of PWM DAC 11
Pulse width of PWM DAC 12
Pulse width of PWM DAC 13
DA13
PADMOD
PADMOD
PADMOD
OPTION
OPTION
XBANK
PORT4
PORT5
HVSTUS
HCNTH
HCNTL
VCNTH
VCNTL
HVCTR0
HVCTR2
HVCTR3
INTFLG
INTEN
30h (w) DA13E DA12E DA11E DA10E
AD3E
P53E
AD2E
P52E
P42E
Msel
AD1E
P51E
P41E
MIICF1 MIICF0
SlvAbs1 SlvAbs0
Xbnk1
P41
P51
Hoff
HF9
HF1
VF9
VF1
HBpl
Rt0
AD0E
P50E
P40E
31h (w)
32h (w)
33h (w)
34h (w)
35h (r/w)
38h (w)
39h (r/w)
40h (r)
41h (r)
42h (r)
43h (r)
44h (r)
P56E
IIICE
PWMF DIV253
P55E
P54E
HIICE
HLFVE HLFHE HCLPE
FclkE IICpass ENSCL
Xbnk2
P42
P52
Vpre
HF10
HF2
VF10
VF2
Xbnk0
P40
P50
P56
CVpre
P55
Hpol
HF13
HF5
P54
Vpol
HF12
HF4
P53
Hpre
HF11
HF3
VF11
VF3
Voff
Hovf
HF8
HF0
VF8
VF0
VBpl
STE
HF7
Vovf
VF7
C1
HF6
VF6
C0
VF5
NoHins
Selft
VF4
40h (w)
42h (w)
43h (w)
STF1
STF0
Rt1
CLPEG CLPPO CLPW2 CLPW1 CLPW0
48h (r/w) HPRchg VPRchg HPLchg VPLchg HFchg
49h (w) EHPR EVPR EHPL EVPL EHF
VFchg
EVF
Vsync
EVsync
Revision 1.2
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MYSON
TECHNOLOGY
(Rev. 1.2)
USBADR
INTFLG
60h (r/w) ENUSB
61h (r/w) USBrstI
USBadr
RsmI
RC0I
TX1I
TX0I
INTEN
62h (w)
63h (r)
64h (r/w)
EUrstI
ERC0I
ETX1I
ETX0I
ERsmI
EP0STUS
USBCTR
TX0CTR
TX0CTR
TX1CTR
TX1CTR
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
RC0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX0FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
TX1FIFO
RC0tgl RC0err EP0dir EP0set
Susp RsmO EP1cfgd RC0nak CtrRD
RC0cnt
USBactv
TX0cnt
65h (w) TX0rdy TX0tgl EP0stall
65h (r) TX0rdy TX0tgl EP0stall
66h (w) TX1rdy TX1tgl EP1stall
66h (r)
68h (r)
TX1cnt
TX1rdy TX1tgl EP1stall
Endpoint 0 receive FIFO 1st byte
69h (r)
Endpoint 0 receive FIFO 2nd byte
Endpoint 0 receive FIFO 3rd byte
Endpoint 0 receive FIFO 4th byte
Endpoint 0 receive FIFO 5th byte
Endpoint 0 receive FIFO 6th byte
Endpoint 0 receive FIFO 7th byte
Endpoint 0 receive FIFO 8th byte
Endpoint 0 transmit FIFO 1st byte
Endpoint 0 transmit FIFO 2nd byte
Endpoint 0 transmit FIFO 3rd byte
Endpoint 0 transmit FIFO 4th byte
Endpoint 0 transmit FIFO 5th byte
Endpoint 0 transmit FIFO 6th byte
Endpoint 0 transmit FIFO 7th byte
Endpoint 0 transmit FIFO 8th byte
Endpoint 1 transmit FIFO 1st byte
Endpoint 1 transmit FIFO 2nd byte
Endpoint 1 transmit FIFO 3rd byte
Endpoint 1 transmit FIFO 4th byte
Endpoint 1 transmit FIFO 5th byte
Endpoint 1 transmit FIFO 6th byte
Endpoint 1 transmit FIFO 7th byte
Endpoint 1 transmit FIFO 8th byte
6Ah (r)
6Bh (r)
6Ch (r)
6Dh (r)
6Eh (r)
6Fh (r)
70h (w)
71h (w)
72h (w)
73h (w)
74h (w)
75h (w)
76h (w)
77h (w)
78h (w)
79h (w)
7Ah (w)
7Bh (w)
7Ch (w)
7Dh (w)
7Eh (w)
7Fh (w)
Test Mode Condition
In normal application, users should avoid the MTV212M entering its test/program mode, outlined as follow:
Test Mode A: RESET=1 & DA9=1 & DA8=0 & STO=0
Test Mode B: RESET's falling edge & DA9=1 & DA8=0 & STO=1
Program Mode: RESET=1 & DA9=0 & DA8=1
Revision 1.2
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TECHNOLOGY
(Rev. 1.2)
ELECTRICAL PARAMETERS
1. Absolute Maximum Ratings
o
at: Ta= 0 to 70 C, VSS=0V
Name
Symbol
VDD
Vin
Vout
Topg
Range
-0.3 to +6.0
-0.3 to VDD+0.3
-0.3 to VDD+0.3
0 to +70
Unit
V
V
Maximum Supply Voltage
Maximum Input Voltage
Maximum Output Voltage
Maximum Operating Temperature
V
o
C
Maximum Storage Temperature
Tstg
-25 to +125
o
C
2. Allowable Operating Conditions
o
at: Ta= 0 to 70 C, VSS=0V
Name
Supply Voltage
Input "H" Voltage
Input "L" Voltage
Operating Freq.
Symbol
VDD
Vih1
Vil1
Fopg
Min.
4.5
0.4 x VDD
Max.
Unit
V
V
V
MHz
5.5
VDD +0.3
0.2 x VDD
15
-0.3
-
3. DC Characteristics
o
at: Ta=0 to 70 C, VDD=5.0V, VSS=0V
Name
Symbol
Voh1 Ioh=0uA
Voh2 Ioh=-50uA
Voh3 Ioh=-2mA
Condition
Min.
Typ.
Max.
Unit
V
V
Output "H" Voltage, open drain pin
Output "H" Voltage, 8051 I/O port pin
Output "H" Voltage, pin HBLANK,
VBLANK, STOUT
4
4
4
V
Output "L" Voltage
Vol
Idd
Iol=6mA
Active
Idle
0.45
24
4.0
80
V
mA
mA
uA
18
1.3
50
Power Supply Current
Power-Down
RST Pull-Down Resistor
Pin Capacitance
Rrst VDD=5V
Cio
50
150
15
Kohm
pF
4. AC Characteristics
o
at: Ta=0 to 70 C, VDD=5.0V, VSS=0V
Name
Crystal Frequency
PWM DAC Frequency
HS input pulse Width
Symbol
fXtal
fDA
tHIPW fXtal=12MHz
tVIPW fXtal=12MHz
tHHBJ
tVVBD fXtal=12MHz
tVCPW FXtal=12MHz
tDCSU
Condition
fXtal=12MHz
Min.
Typ.
12
Max.
Unit
MHz
KHz
uS
uS
nS
uS
uS
ns
46.875
0.3
94.86
8
VS input pulse Width
3
HSYNC to Hblank output jitter
H+V to Vblank output delay
VS pulse width in H+V signal
SDA to SCL setup time
5
10
20
200
Revision 1.2
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MYSON
TECHNOLOGY
(Rev. 1.2)
SDA to SCL hold time
SCL high time
SCL low time
START condition setup time
START condition hold time
STOP condition setup time
STOP condition hold time
tDCH
tSCLH
tSCLL
tSU:STA
tHD:STA
tSU:STO
tHD:STO
100
500
500
500
500
500
500
ns
ns
ns
ns
ns
ns
ns
t
SCKH
t
t
HD:STO
SCKL
t
SU:STA
t
t
t
t
HD:STA
DCSU
DCH
SU:STO
2
Data interface timing (I C)
Revision 1.2
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MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
PACKAGE DIMENSION
1. 40-pin PDIP 600 mil
52.197mm +/-0.127
1.981mm
+/-0.254
1.270mm +/-0.254 0.457mm +/-0.127
2.540mm
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
1.778mm
+/-0.127
3.81mm
+/-0.127
0.254mm
(min.)
5o~70
3.302mm
+/-0.254
6o +/-3o
16.256mm +/-0.508
2. 42 pin SDIP Unit: mm
Dimension in mm
Symbol
Min
Nom
Max
4.2
A
3.937 4.064
1.78 1.842
0.914 1.270
36.78 36.83
A1
B1
D
1.88
1.118
36.88
E1
F
eB
13.945 13.970 13.995
15.19 15.240 15.29
15.24 16.510 17.78
0°
7.5°
15°
15.494mm +/-0.254
13.868mm +/-0.102
0.254mm
+/-0.102
5o~70
6o +/-3o
16.256mm +/-0.508
Revision 1.2
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MTV212M64
MYSON
TECHNOLOGY
(Rev. 1.2)
3. 44 pin PLCC Unit:
PIN #1 HOLE
0.045*450
0.180 MAX.
0.020 MIN.
0.013~0.021 TYP.
0.690 +/-0.005
0.610 +/-0.02
0.653 +/-0.003
0.500
70TYP.
0.070
0.010
0.050 TYP.
0.026~0.032 TYP.
0.070
0.653 +/-0.003
0.690 +/-0.005
Ordering Information
Standard configurations:
Prefix
Part Type
Package Type
ROM Size (K)
USB Option
N: PDIP
S:SDIP
V: PLCC
64
Non-USB: N/A
USB: U
MTV
212M
Part Numbers:
Prefix
MTV
Part Type
212M
Package Type
ROM Size (K)
USB Option
N
S
V
N
S
V
64
64
64
64
64
64
MTV
MTV
MTV
MTV
212M
212M
212M
212M
U
U
U
MTV
212M
Revision 1.2
- 27 -
2000/07/04
相关型号：
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