MTV118_技术文档

MYSON

MTV118

TECHNOLOGY

On-Screen-Display for LCD Monitor

FEATURES

GENERAL DESCRIPTION

•

Horizontal sync input may be up to 120 KHz.

MTV118 is designed for LCD monitor appli-

cations to display the built-in characters or fonts

onto an LCD monitor screen. The display oper-

ates by transferring data and control information

from the micro controller to the RAM through a

serial data interface. It can execute full screen

displays automatically and specific functions such

as character bordering, shadowing, blinking, dou-

ble height and width, font by font color control,

frame positioning, frame size control by character

height and windowing effect. Moreover, MTV118

also provides 8 PWM DAC channels with 8-bit

resolution and a PWM clock output for external

digital-to-analog control.

Acceptable wide-range pixel clock up to 96MHz

from XIN pin.

•

Full-screen display consists of 15 (rows) by 30 (col-

umns) characters.

•

12 x 18 dot matrix per character.

Total of 256 characters and graphic fonts including

248 mask ROM fonts and 8 programmable RAM

fonts.

•

8 color selection maximum per display character.

Double character height and/or width control.

Programmable positioning for display screen cen-

ter.

•

Bordering, shadowing and blinking effect.

Programmable vertical character height (18 to 71

lines) control.

•

Row to row spacing register to manipulate the con-

stant display height.

4 programmable background windows with multi-

level operation.

•

Software clears for display frame.

Half tone and fast blanking output.

8-channel/8-bit PWM D/A converter output.

2

•

Compatible with SPI bus or I C interface with

address 7AH (slave address is mask option).

16 or 24-pin PDIP/SOP package.

•

BLOCK DIAGRAM

SSB

SCK

SDA

VDD

8

9

8

LUMAR

LUMAG

LUMAB

BLINK

DATA

DISPLAY & ROW

CONTROL

REGISTERS

SERIAL DATA

INTERFACE

ROW, COL

ACK

VSS

CWS

CHS

8

CRADDR

VDDA

VSSA

8

CHARACTER ROM

USER FONT RAM

DATA

LUMA

5

9

5

RCADDR

DADDR

FONTADDR

WINADDR

PWMADDR

5

ARWDB

HDREN

VDREN

NROW

LPN

CWS

BORDER

ADDRESS BUS

ADMINISTRATOR

LUMINANCE &

BORDGER

GENERATOR

VCLKS

5

8

VFLB

LPN

DATA

BSEN

VERTICAL

DISPLAY

CONTROL

WINDOWS &

FRAME

CONTROL

SHADOW

OSDENB

HSP

7

8

7

CH

CHS

VERTD

NROW

VDREN

VERTD

HORD

CH

VSP

HSP

VSP

ARWDB

HDREN

HFLB

ROUT

GOUT

BOUT

FBKG

HTONE

HORIZONTAL

DISPLAY CONTROL

8

HORD

LUMAR

LUMAG

LUMAB

BLINK

COLOR

ENCODER

NC

CLOCK

GENERATOR

VCLKX

XIN

VCLKX

PWM0

PWM1

PWM2

PWM3

PWM4

PWM5

PWM6

PWM7

PWM D/A

CONVERTER

POWER ON

RESET

PRB

8

DATA

This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification

without notice. No liability is assumed as a result of the use of this product. No rights under any patent accompany the sales of

the product.

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MTV118

TECHNOLOGY

1.0 PIN CONNECTION

1

16

1

24

23

22

21

20

19

VSS

XIN

VSS

XIN

VSS

2

3

4

5

6

7

8

15

14

13

12

11

2

ROUT

GOUT

BOUT

FBKG

3

NC

GOUT

NC

4

VDD

HFLB

SSB

SDA

SCK

BOUT

VDD

MTV118

5

FBKG

HFLB

SSB

6

HTONE/PWMCK

MTV118N24

10 VFLB

VDD

SDA

7

18 VFLB

17 VDD

16 PWM7

9

SCK

8

PWM0

PWM1

PWM2

PWM3

9

PWM6

PWM5

PWM4

10

11

12

15

14

13

2.0 PIN DESCRIPTIONS

Pin #

Name

I/O

Descriptions

N16 N24

VSS

-

1

2

3

4

1

2

3

4

Ground. This ground pin is used for internal circuitry.

Pixel Clock Input. This is a clock input pin. MTV118 is driven by

an external pixel clock source for all the logics inside. The fre-

quency of XIN must be the integral time of pin HFLB.

XIN

NC

I

No connection.

Power supply. Positive 5 V DC supply for internal circuitry. A

0.1uF decoupling capacitor should be connected across VDD and

VSS.

VDD

-

Horizontal Input. This pin is used to input the horizontal synchro-

nizing signal. It is a leading edge trigger and has an internal pull-

up resistor.

HFLB

SSB

I

5

6

7

5

6

7

Serial Interface Enabler. It is used to enable the serial data and

is also used to select the operation of I²C or SPI bus. If this pin is

left floating, I²C bus is enabled, otherwise the SPI bus is enabled.

Serial Data Input. The external data transfers through this pin to

internal display registers and control registers. It has an internal

pull-up resistor.

SDA

Serial Clock Input. The clock-input pin is used to synchronize the

data transfer. It has an internal pull-up resistor.

SCK

I

8

-

8

9

Open-Drain PWM D/A Converter 0. The output pulse width is

programmable by the register of row 15, column 19.

PWM0

PWM1

PWM2

O

Open-Drain PWM D/A Converter 1. The output pulse width is

programmable by the register of row 15, column 20.

-

10

11

Open-Drain PWM D/A Converter 2. The output pulse width is

programmable by the register of row 15, column 21.

-

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Pin #

I/O

Name

Descriptions

N16 N24

Open-Drain PWM D/A Converter 3. The output pulse width is

programmable by the register of row 15, column 22.

PWM3

PWM4

PWM5

PWM6

PWM7

O

-

12

13

14

15

16

Open-Drain PWM D/A Converter 4. The output pulse width is

programmable by the register of row 15, column 23.

Open-Drain PWM D/A Converter 5. The output pulse width is

programmable by the register of row 15, column 24.

Open-Drain PWM D/A Converter 6. The output pulse width is

programmable by the register of row 15, column 25.

Open-Drain PWM D/A Converter 7. The output pulse width is

programmable by the register of row 15, column 26.

Power Supply. Positive 5 V DC supply for internal circuitry and a

VDD

-

I

9

17 0.1uF decoupling capacitor should be connected across VDD and

VSS.

Vertical Input. This pin is used to input the vertical synchronizing

VFLB

10

18

signal. It is triggered by lead and has an internal pull-up resistor.

Half Tone Output / PWM Clock Output. This is a multiplexed pin

HTONE /

PWMCK

selected by the PWMCK bit. This pin can be a PWM clock or used

to attenuate R, G, B gain of VGA for the transparent windowing

O

11

19

effect.

Fast Blanking Output. It is used to cut off external R, G, B sig-

nals of VGA while this chip is displaying characters or windows.

FBKG

O

12

20

BOUT

GOUT

ROUT

VSS

O

-

13

14

15

16

21 Blue Color Output. This is a blue color video signal output.

22 Green Color Output. This is a green color video signal output.

23 Red Color Output. This is a red color video signal output.

24 Ground. This ground pin is used for internal circuitry.

3.0 FUNCTIONAL DESCRIPTIONS

3.1 Serial Data Interface

The serial data interface receives data transmitted from an external controller. There are 2 types of bus

which can be accessed through the serial data interface: SPI bus and I²C bus.

3.1.1 SPI Bus

When the SSB pin is pulled to a HIGH or LOW level, the SPI bus operation is selected. A valid trans-

mission should start from pulling SSB to LOW level, enabling the MTV118 receiving mode and retaining

the LOW level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1

on page 4.

There are 3 transmission formats as shown below:

Format (a) R - C - D ® R - C - D ® R - C - D

Format (b) R - C - D ® C - D ® C - D ® C - D

Format (c) R - C - D ® D ® D ® D ® D ® D

R=row address, C=column address, D=display data

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SSB

SCK

MS

B

LSB

SDA

first byte

last byte

FIGURE 1. Data Transmission Protocol (SPI)

3.1.2 I²C Bus

I²C bus operation is only selected when the SSB pin is left floating. A valid transmission should begin

from writing the slave address 7AH, which is mask option, to MTV118. The protocol is shown in Figure

2 on page 4..

SCK

SDA

B7

B6

B0

B7

B0

¡

@¡ @¡ @¡ @

START

ACK

STOP

first byte

¡

@

second byte

last byte

FIGURE 2. Data Transmission Protocol (I²C)

There are 3 transmission formats as shown below:

Format (a) S - R - C - D ® R - C - D ® R - C - D

Format (b) S - R - C - D ® C - D ® C - D ® C - D

Format (c) S - R - C - D ® D ® D ® D ® D ® D

S=slave address, R=row address, C=column address, D=display data

Each arbitrary length of data packet consists of 3 portions: row address (R), column address (C) and

display data (D). Format (a) is suitable for updating small amounts of data which will be allocated with

different row and column addresses. Format (b) is recommended for updating data that has the same

row address but a different column address. Massive data updating or full screen data changes should

be done in format (c) to increase transmission efficiency. The row and column addresses will be incre-

mented automatically when format (c) is applied. Furthermore, the undefined locations in display or font

RAM should be filled with dummy data.

There are 3 types of data which should be accessed through the serial data interface: address bytes of

display registers, attribute bytes of display registers and user font RAM data. The protocol is the same

for all except bits 5 and 6 of the row addresses. The MSB(b7) is used to distinguish row and column

addresses when transferring data from an external controller. Bit 6 of the row address is used to distin-

guish display registers and user font RAM data and bit6 of the column address is used to differentiate

the column address for formats (a), (b) and (c), respectively. Bit 5 of the row address for display regis-

ters is used to distinguish the address byte when it is set to "0" and the attribute byte when it is set to

"1". The configuration of transmission formats is shown in Table 1 on page 5.

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TABLE 1. Configuration of Transmission Formats

Address

b7

1

b6

0

b5

0

b4

x

b3

R3

C3

b2

R2

C2

b1

R1

C1

b0

R0

C0

Format

a,b,c

a,b

Address

Bytes of

Display

Reg.

Row

Column

0

x

C4

ab

Column

Row

0

1

x

C4

C3

C2

C1

C0

c

Attribute

Bytes of

Display

Reg.

1

0

1

x

R3

C3

R2

C2

R1

C1

R0

C0

a,b,c

a,b

Column

C4

ab

Column

Row

0

1

x

C4

C3

C2

C1

C0

c

User

Fonts

RAM

1

0

1

0

x

R2

C2

R1

C1

R0

C0

a,b,c

a,b

Column

C5

C4

C3

ab

Column

0

1

C5

C4

C3

C2

C1

C0

c

The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to

format (a), but not from format (c) back to format (a) and (b). The alternation between transmission for-

mats is configured as the state diagram shown in Figure 3 on page 5.

0, X

Input = b7, b6

Initiate

1, X

format (a)

1, X

ROW

format (b)

format (c)

0, 1

0, 0

COL_c

COL_ab

1, X

X, X

DA_c

DA_ab

FIGURE 3. Transmission State Diagram

3.2 Address Bus Administrator

The administrator manages bus address arbitration of internal registers or user font RAM during exter-

nal data write-in. The external data write through serial data interface to registers must be synchronized

by internal display timing. In addition, the administrator also provides automatic incrementation to the

address bus when external writing occurs using format (c).

3.3 Vertical Display Control

The vertical display control can generate different vertical display sizes for most display standards in

current monitors. The vertical display size is calculated with the information of a double character height

bit(CHS) and a vertical display height control register(CH6-CH0).The algorithms of a repeating charac-

ter line display are shown in Tables 2 and 3. The programmable vertical size range is 270 lines to max-

imum 2130 lines.

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The vertical display center for a full-screen display may be figured out according to the information of

the vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the lead-

ing edge of VFLB is calculated using the following equation:

Vertical delay time = ( VERTD * 4 + 1 ) * H

Where H = 1 horizontal line display time

TABLE 2. Repeat Line Weight of Character

CH6-CH0

CH6,CH5=11

CH6,CH5=10

CH6,CH5=0x

CH4=1

Repeat Line Weight

+18*3

+18*2

+18

+16

+8

CH3=1

CH2=1

+4

CH1=1

+2

CH0=1

+1

TABLE 3. Repeat Line Number of Character

Repeat Line #

RepeaterLine

Weight

0

-

1

-

2

-

3

-

4

-

5

-

6

-

7

-

8

v

-

9

-

10 11 12 13 14 15 16 17

+1

+2

-

v

-

v

-

+4

-

v

-

v

-

v

-

v

-

+8

-

v

-

v

-

v

-

v

-

+16

+17

+18

-

v

-

v

-

v

Note: “v” means the nth line in the character would be repeated once, while “-” means the nth line in the

character would not be repeated.

3.4 Horizontal Display Control

The horizontal display control is used to generate control timing for a horizontal display based on dou-

ble character width bit (CWS), horizontal positioning register (HORD) and HFLB input. A horizontal dis-

play line includes 360 dots for 30 display characters and the remaining dots for a blank region. The

horizontal delay starting from the HFLB leading edge is calculated using the following equation:

Horizontal delay time = ( HORD * 6 + 49) * P

Where P = 1 XIN pixel display time

3.5 Display & Row Control Registers

The internal RAM contains display and row control registers. The display registers have 450 locations

which are allocated between row 0/column 0 and row 14/column 29 as shown in Figure 4. Each display

register has its corresponding character address on the address byte, and 1 blink bit and its corre-

sponding color bits on attribute bytes. The row control register is allocated at column 30 for row 0 to row

14; it is used to set character size for each respective row. If the double width character (CWS) is cho-

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sen, only even column characters may be displayed on-screen and the odd column characters will be

hidden.

COLUMN #

ROW #

0 1

28 29

30

31

0

1

ROW CTRL

REG

DISPLAY REGISTERS

RESERVED

13

14

COLUMN#

8 9

0

2 3

5 6

WINDOW2

11 12

18 19

26

ROW 15

FRAMECRTL PWM D/A

WINDOW1

WINDOW3

WINDOW4

REG

CRTL REG

FIGURE 4. Memory map

3.5.1 Register Descriptions

1. (i) Display Register, (Row 0 - 14, Column 0 - 29)

ADDRESS BYTE

b7

b6

b5

b4

CRADDR

b3

b2

b1

b0

LSB

MSB

CRADDR - Defines ROM character and user-programmable fonts address.

(a) 0 ~ 247 Þ 248 built-in characters and graphic symbols

(b) 248 ~ 255 Þ 8 user-programmable fonts

ATTRIBUTE BYTE

b7 b6 b5

b4

-

b3

BLINK

b2

R1

b1

G1

b0

B1

-

BLINK - Enables blinking effect when this bit is set to " 1 ". The blinking is alternated per 32 vertical

frames.

R1, G1, B1 - These bits are used to specify its relative address character color 1.

2. Row Control Registers, (Row 0 - 14)

b7

-

b6

-

b5

-

b4

R2

b3

G2

b2

B2

b1

b0

COLN 30

CHS CWS

R2, G2, B2 - These bits are used to specify its relative row character color 2. While the corresponding

CCS bit is set to 1, color 2 should be chosen.

CHS - Defines double height character to the respective row.

CWS - Defines double width character to the respective row.

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3.6 User Font RAM

The user font RAM has 288 locations which are allocated between row 0/column 0 and row 7/column

35 to specify 8 user-programmable fonts, as shown in Figure 5. Each programmable font consists of a

12x18 dot matrix. Each row of dot matrix consists of 2 bytes of data which include 4 dummy bits as

shown in figure 6. That is, the dot matrix data of each font is stored in 36-byte registers. For example,

font 0 is stored in row 0 from column 0 to column 35 and font 1 is stored in row 1 from column 0 to col-

umn 35, etc.

ROW #

COLUMN #

34 35 36

0

1

63

0

1

USER FONT RAM

RESERVED

6

7

FIGURE 5. User Font RAM Memory Map

Nth byte

leftmost dot of font

(N+1)th byte

rightmost dot of font

b7 b6

b5 b4 b3 b2 b1 b0 b7 b6

12 bits for 1-row data of font dot matrix

b5 b4 b3 b2 b1 b0

Dummy bits

N=even number

FIGURE 6. Data Format of Font Dot Matrix

3.7 Character ROM

The character ROM contains 248 built-in characters and symbols from addresses 0 to 247. Each char-

acter and symbol consists of a 12x18 dot matrix. The detail pattern structures for each character and

symbol are shown in 10.0“ CHARACTER AND SYMBOL PATTERN” on page 15.

3.8 Luminance & Border Generator

There are 2 shift registers included in the design which can shift out of luminance and border dots to the

color encoder. The bordering and shadowing feature is configured in this block. For bordering effect,

the character will be enveloped with blackedge on 4 sides. For shadowing effect, the character is envel-

oped with blackedge on right and bottom sides only.

3.9 Window and Frame Control

The display frame position is completely controlled by the contents of VERTD and HORD. The window

size and position control are specified in columns 0 to 11 on row 15 of the memory map, as shown in

Figure 4. Window 1 has the highest priority and window 4 has the least, when 2 windows are overlap-

ping. More detailed information is described as follows:

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1. Window control registers:

ROW 15

Column

b7

MSB

b7

b6

b5

b4

LSB MSB

b4 b3

LSB

b3

LSB

b3

b2

b1

b0

ROW START ADDR

ROW END ADDR

0,3,6,OR 9

LSB

b6

b5

b2

b1

b0

-

Column

COL START ADDR

WEN

CCS

1,4,7,OR 10

MSB

b7

b6

b5

b4

b2

R

b1

G

b0

B

Column

COL END ADDR

2,5,8,OR 11

MSB

START(END) ADDR - These addresses are used to specify the window size. It should be noted that

when the start address is greater than the end address, the window will be disa-

bled.

WEN - Enables the window display.

CCS - When a window is overlapping with the character, character color 2 should be chosen while this

bit is set to 1. Color 1 is selected otherwise.

R, G, B - Specifies the color of the relative background window.

2. Frame control registers:

ROW 15

b7

b6

b5

b4

b3

b2

b1

b0

VERTD

Column 12

MSB

LSB

VERTD - Specifies the starting position for vertical display. The total steps are 256, and the increment

of each step is 4 horizontal display lines. The initial value is 4 after power-up.

b7

b6

b5

b4

b3

b2

b1

b0

HORD

Column 13

MSB

LSB

HORD - Defines the starting position for horizontal display. The total steps are 256 and the increment of

each step is 6 dots. The initial value is 15 after power-up.

b7

-

b6

CH6

b5

CH5

b4

CH4

b3

CH3

b2

CH2

b1

CH1

b0

CH0

Column 14

CH6-CH0 - Defines the character vertical height, which is programmable from 18 to 71 lines. The char-

acter vertical height is at least 18 lines if the contents of CH6-CH0 are less than 18. For

example, when the content is " 2 ", the character vertical height is regarded as equal to 20

lines. If the contents of CH4-CH0 are greater than or equal to 18, it will be regarded as equal

to 17. See Tables 2 and 3 for a detailed description of this operation.

b7

b6

b5

b4

Reserved

b3

b2

b1

b0

Column 15

This byte is reserved for internal testing.

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b7

-

b6

-

B5

-

b4

b3

b2

RSPACE

b1

b0

Column 16

MSB

LSB

RSPACE - Defines the row to row spacing in each unit of the horizontal line. That is, extra RSPACE

horizontal lines will be appended below each display row, and the maximum space is 31

lines. The initial value is “0” after power-up.

b7

b6

b5

b4

b3

b2

b1

b0

Column 17

OSDEN BSEN SHADOW TRIC BLANK WENCLR RAMCLR FBKGC

OSDEN - Activates the OSD operation when this bit is set to "1". The initial value is” 0” after power-up.

BSEN - Enables the bordering and shadowing effect.

SHADOW - Activates the shadowing effect if this bit is set, otherwise the bordering is chosen.

TRIC - Defines the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled.

That is, while OSD is disabled, these 4 pins will drive LOW if this bit is set to “1”, otherwise these

pins are in high-impedance state. The initial value is “0” after power-up.

BLANK - Forces the FBKG pin output to HIGH while this bit is set to "1".

WENCLR - Clears all WEN bits of window control registers when this bit is set to "1". The initial value is

“0” after power-up.

RAMCLR - Clears all ADDRESS bytes of display registers when this bit is set to "1". The initial value is

“0” after power-up.

FBKGC - Defines the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during

the display of characters or windows, otherwise, it outputs only during the display of charac-

ters.

B7

b6

b5

b4

DWE

b3

HSP

b2

VSP

b1

b0

Column 18

TEST FBKGP PWMCK

PWM1 PWM0

TEST - = 0 Þ Normal mode.

= 1 Þ Test mode, not allowed in applications.

FBKGP - Selects the polarity of the output pin FBKG.

= 1 Þ Positive polarity FBKG output is selected.

= 0 Þ Negative polarity FBKG output is selected.

The initial value is “1” after power-up.

PWMCK - Selects the output options to the HTONE/PWMCK pin.

= 0 Þ ? HTONE option is selected.

= 1 Þ ? PWMCK option is selected with 50/50 duty cycle and is synchronous with the input

HFLB. The frequency is selected by PWM1, PWM0 as shown in table 4.

The initial value is “0” after power-up.

DWE - Enables double width. When the bit is set to “1”, the display of the OSD menu can change to half

resolution for double character width, and then the number of pixels of each line should be even.

HSP -

= 1 Þ Accepts positive polarity Hsync input.

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= 0 Þ Accepts negative polarity Hsync input.

VSP - = 1 Þ Accepts positive polarity Vsync input.

= 0 Þ Accepts negative polarity Vsync input.

PWM1, PWM0 - Selects the PWMCK output frequency.

= (0, 0) Þ XIN frequency /8

= (0, 1) Þ XIN frequency /4

= (1, 0) Þ XIN frequency /2

= (1, 1) Þ XIN frequency /1

The initial value is 0, 0 after power-up.

Notes : When XIN is not present, don't write data in any address. If data is written in any address, a

malfunction may occur.

TABLE 4. PWMCK Frequency and PWMDA Sampling Rate

(PWM1, PWM0)

( 0, 0 )

PWMCK Freq.

XIN frequency /8

XIN frequency /4

XIN frequency /2

XIN frequency /1

PWMDA sampling rate

XIN frequency /(8 * 256)

XIN frequency /(4 * 256)

XIN frequency /(2 * 256)

XIN frequency /(1 * 256)

( 0, 1 )

( 1, 0 )

( 1 ,1 )

3.10 PWM D/A Converter

There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). The PWM D/A converter output pulse

width is programmable by writing data to columns 19-26 registers of row 15 with 8-bit resolution to con-

trol the pulse width duration from 0/256 to 255/256. The sampling rate is selected by PWM1, PWM0 as

shown in table 4. In applications, all open-drain output pins should be pulled up by external resistors to

supply voltage (5V to 9V) for the desired output range.

ROW 15

b7

b6

b5

b4

b3

b2

b1

b0

PWMDA0

Column 19

|

PWMDA7

Column 26

MSB

LSB

PWMDA0 - PWMDA7 - Defines the output pulse width of pins PWM0 to PWM7.

3.11 Color Encoder

The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, bor-

der blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.

4.0 ABSOLUTE MAXIMUM RATINGS

DC Supply Voltage(VDD,VDDA)

Ground Voltage

-0.3 to +7 V

-0.3 to VDD+0.3 V

o

Storage Temperature

-65 to +150 C

o

Ambient Operating Temperature

0 to +70 C

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MTV118 Revision 2.0 01/01/1999

MYSON

MTV118

TECHNOLOGY

5.0 OPERATING CONDITIONS

DC Supply Voltage(VDD,VDDA)

Operating Temperature

+4.75 to +5.25 V

o

0 to +70 C

6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)

Symbol

Parameter

Conditions(Notes)

Min.

Max.

Unit

V

Input High Voltage

-

0.7 * VDD

VDD+0.3

V

IH

0.3 * VDD

(0.2*VDD

for SSB pin )

V

Input Low Voltage

-

VSS-0.3

VDD-0.8

-

V

IL

Output High Volt-

age

I

³ -24 mA

-

OH

OL

OH

Output Low Volt-

age

I

£ 24 mA

0.5

OL

-

(For all OD pins, pulled

up by external 5 to 9V

power supply)

Open Drain Out-

put High Voltage

5

9

V

ODH

5 mA ³ I

Open Drain Out-

put Low Voltage

DOL

V

I

-

0.5

12

20

V

ODL

( For all OD pins )

Vin = VDD,

Standby Current

Operating Current

mA

SB

I

l

load = 0uA

Pixel rate=96MHz

I

CC

I

load = 0uA

7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)

Symbol

f_HFLB

Parameter

HFLB input frequency

Min.

15

Typ.

Max.

Unit

-

120

KHz

ns

T_r

Output rise time

-

5

-

T_f

Output fall time

-

t_BCSU

t_BCH

t_DCSU

t_DCH

SSB to SCK set-up time

SSB to SCK hold time

SDA to SCK set-up time

SDA to SCK hold time

SCK HIGH time

200

100

200

100

500

-

t_SCKH

t_SCKL

t_SU:STA

t_HD:STA

t_SU:STO

-

SCK LOW time

-

START condition set-up time

START condition hold time

STOP condition set-up time

-

12/15

MTV118 Revision 2.0 01/01/1999

MYSON

MTV118

TECHNOLOGY

Symbol

t_HD:STO

Parameter

STOP condition hold time

Min.

500

2

Typ.

Max.

Unit

ns

-

t_SETUP

t_HOLD

t_pd

HFLB delay to rising edge of pixel clock

minimum pulse width of HFLB

propagation delay of output to pixel clock

pixel clock input

6

ns

25

ns

10

96

ns

PIXin

6

MHz

8.0 TIMING DIAGRAMS

t_SCKH

SCK

SSB

SDA

t_SCKL

t_BCSU

t_BCH

t_DCSU

t_DCH

FIGURE 7. Data Interface Timing (SPI)

t_SCKH

SCK

t_SCKL

t_SU:STA

t_HD:STO

SDA

t_HD:STA

t_DCSU

t_DCH

t_SU:STO

2

FIGURE 8. Data Interface Timing (I C)

PlXin

R,G,B, FBKG

HTONE

t

pd:: Propagation Delay to R,G,B, FBKG

and HTONE outputs

t

pd

HFLB

t

SETUP

t

HOLD

FIGURE 9. Output and HFLB Timing to Pixel Clock

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MTV118 Revision 2.0 01/01/1999

MYSON

MTV118

TECHNOLOGY

9.0 PACKAGE DIMENSION

9.1 16 PDIP 300Mil

Unit:Mil

R10Max

(4X

)

312 +/-12

55 +/-20

250 +/-4

90 +/-20

350 +/-20

R40

10

65 +/-4

55 +/-4

310Max

75 +/-20

90 +/-20

750 +/-10

7

15 Max

Typ

35 +/-5

115 Min

15 Min

60 +/-

5Typ

100Ty

p

18 +/-

2Typ

9.2 24 PDIP 300Mil

Unit: Mil

R10Max

(4X)

312+/-12

55+/-20

80+/-20

350+/-20

250+/-4

R40

10

930+/-10

65+/-4

1245+/-10

7Ty

p

15Max

35+/-5

115Min

15Min.

100Ty

p

18+/-

2Typ

60+/-

5Typ

14/15

MTV118 Revision 2.0 01/01/1999

MYSON

MTV118

TECHNOLOGY

9.3 16-pin SOP 300Mil

Unit: Mil

0.406 +/-0.013

0.295 +/-0.004

7^o(4x)

0.015x45^o

0.406 +/-0.008

(4x)

0.098 +/-0.006

0.091

0.028 +0.022 /-0.013

0.016 +/-0.004 0.050

9.4 24-pin SOP 300Mil

15.0mm /+0.4 -0.1

1.85mm/+0.4 -0.15

24

13

7.9mm+/-0.4

5.3mm +0.3/-0.1

0.1mm +0.2/-0.05

0.5mm+/-0.2

6.9mm

0.2mm

1

12

+0.1/-0.05

0.45mm +/-0.1

1.27mm

10.0 CHARACTER AND SYMBOL PATTERN

Please see the attachment.

Myson Technology, Inc.

No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A.

R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002 Tel:408-252-8788 FAX: 408-252-8789 Sales@myson.com

http://www.myson.com.tw

Myson Technology USA, Inc.

http://www.myson.com

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