MR27V12852L [ETC]
8M-Word à 16-Bit or 16M-Word à 8-Bit Page mode P2ROM;
| 型号： | MR27V12852L |
| 厂家： | 
ETC |
| 描述： | 8M-Word à 16-Bit or 16M-Word à 8-Bit Page mode P2ROM |
| 文件： | 总8页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDR27V12852L-002-01
Issue Date: Oct 01, 2008
MR27V12852L
8M-Word × 16-Bit or 16M-Word × 8-Bit Page mode P2ROM
FEATURES
· 8,388,608-word × 16-bit/16,777,216-word × 8-bit electrically
switchable configuration
PIN CONFIGURATION (TOP VIEW)
· Page size of 8-word x 16-Bit or 16-word x 8-Bit
· 3.0 V to 3.6 V power supply
1
56 NC
55 NC
54 A16
53 BYTE#
52 VSS
51 D15/A-1
50 D7
· Access time .....................85 ns MAX
· Page Access time ............30 ns MAX
· Operating current ............50 mA MAX(5MHz)
· Standby current ...............10 µA MAX
· Input/Output TTL compatible
NC
A22
A15
A14
A13
A12
A11
A10
A9
2
3
4
5
6
7
· Three-state output
8
49 D14
48 D6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
47 D13
46 D5
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
PACKAGES
45 D12
44 D4
· MR27V12852L-xxxTA
43 VCC
42 D11
41 D3
56-pin plastic TSOP (TSOP I 56-P-1420-0.50-K)
40 D10
39 D2
38 D9
P2ROM ADVANCED TECHNOLOGY
37 D1
36 D8
A6
P2ROM stands for Production Programmed ROM. This
exclusive LAPIS Semiconductor technology utilizes factory
test equipment for programming the customers code into the
P2ROM prior to final production testing.
Advancements in this technology allows production costs to be
equivalent to MASKROM and has many advantages and added
benefits over the other non-volatile technologies, which
include the following;
35 D0
A5
34 OE#
33 VSS
32 CE#
31 A0
A4
A3
A2
A1
30 NC
29 NC*
NC
NC
56TSOP(Type-I)
· Short lead time, since the P2ROM is programmed at the
final stage of the production process, a large P2ROM
inventory "bank system" of un-programmed packaged
products are maintained to provide an aggressive
lead-time and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom
mask for storing customer code, no mask charges apply.
· No additional programming charge, unlike Flash and
OTP that require additional programming and handling
costs, the P2ROM already has the code loaded at the
factory with minimal effect on the production throughput.
The cost is included in the unit price.
*:Different from FLASH products.
· Custom Marking is available at no additional charge.
· Pin Compatible with some FLASH products except for
29-pin.
1/8
FEDR27V12852L-002-01
MR27V12852L / P2ROM
BLOCK DIAGRAM
A–1
× 8/× 16 Switch
CE#
CE
OE#
OE
BYTE#
A0
A1
A2
Memory Cell Matrix
A3
A4
A5
A6
8M × 16-Bit or 16M × 8-Bit
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
Multiplexer
Output Buffer
D0
D2
D4
D6
D8 D10 D12 D14
D7 D9 D11 D13 D15
D1
D3
D5
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
PIN DESCRIPTIONS
Pin name
D15 / A–1
A0 to A22
D0 to D14
CE#
Functions
Data output / Address input
Address inputs
Data outputs
Chip enable input
Output enable input
Word / Byte select input
Power supply voltage
Ground
OE#
BYTE#
VCC
VSS
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FEDR27V12852L-002-01
MR27V12852L / P2ROM
FUNCTION TABLE
Mode
Read (16-Bit)
Read (8-Bit)
CE#
L
OE#
BYTE#
VCC
D0 to D7
DOUT
D8 to D14
DOUT
D15/A–1
L
L
H
L
L
Hi–Z
L/H
∗
3.0 V
to
3.6 V
H
L
Output disable
Standby
L
H
Hi–Z
Hi–Z
H
L
H
∗
∗
∗: Don’t Care (H or L)
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating temperature under bias
Storage temperature
Symbol
Condition
Value
0 to 70
Unit
°C
°C
V
Ta
Tstg
VI
—
–55 to 125
–0.5 to VCC+0.5
–0.5 to VCC+0.5
–0.5 to 5
Input voltage
relative to VSS
Output voltage
VO
V
Power supply voltage
Power dissipation per package
Output short circuit current
VCC
PD
V
Ta = 25°C
—
1.0
W
IOS
10
mA
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter
VCC power supply voltage
Input “H” level
Symbol
VCC
Condition
Min.
3.0
Typ.
—
Max.
3.6
Unit
V
VCC = 3.0 to 3.6 V
VIH
2.2
—
VCC+0.5∗
V
V
Input “L” level
VIL
–0.5∗∗
—
0.6
Voltage is relative to VSS
.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
PIN CAPACITANCE
(VCC = 3.0 V, Ta = 25°C, f = 1 MHz)
Parameter
Input
Symbol
CIN1
Condition
VI = 0 V
Min.
—
Typ.
—
Max.
10
Unit
pF
BYTE#
Output
CIN2
—
—
200
10
COUT
VO = 0 V
—
—
3/8
FEDR27V12852L-002-01
MR27V12852L / P2ROM
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
(VCC = 3.0 to 3.6 V, Ta = 0 to 70°C)
Parameter
Symbol
ILI
Condition
VI = 0 to VCC
VO = 0 to VCC
CE# = VCC
CE# = VIH
CE# = VIL, OE# = VIH
f=5MHz
Min.
—
Typ.
—
Max.
10
10
10
1
Unit
μA
Input leakage current
Output leakage current
ILO
—
—
μA
ICCSC
ICCST
—
—
μA
VCC power supply current
(Standby)
—
—
mA
VCC power supply current
(Read)
ICCA
—
—
50
mA
Input “H” level
Input “L” level
Output “H” level
Output “L” level
VIH
VIL
—
2.2
–0.5∗∗
2.4
—
—
—
—
VCC+0.5∗
0.6
V
V
V
V
—
VOH
VOL
IOH = –1 mA
IOL = 2 mA
—
—
0.4
Voltage is relative to VSS
.
∗ : Vcc+1.5V (Max.) when pulse width of overshoot is less than 10ns.
∗∗ : -1.5V (Min.) when pulse width of undershoot is less than 10ns.
AC CHARACTERISTICS
(VCC = 3.0 to 3.6 V, Ta = 0 to 70°C)
Parameter
Address cycle time
Address access time
Page cycle time
Symbol
tC
Condition
—
Min.
85
—
30
—
—
—
0
Max.
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tACC
tPC
tPAC
tCE
CE# = OE# = VIL
—
85
—
Page access time
CE# access time
OE# access time
—
30
85
30
20
20
—
OE# = VIL
CE# = VIL
OE# = VIL
CE# = VIL
CE# = OE# = VIL
tOE
tCHZ
tOHZ
tOH
Output disable time
Output hold time
0
0
Measurement conditions
Input signal level-------------------------------- 0 V/3 V
Input timing reference level ------------------ 1/2Vcc
Output load -------------------------------------- 50 pF
Output timing reference level---------------- 1/2Vcc
Output load
Output
50 pF
(Including scope and jig)
4/8
FEDR27V12852L-002-01
MR27V12852L / P2ROM
TIMING CHART (READ CYCLE)
RANDOM ACCESS MODE READ CYCLE
tC
tC
A0 to A22 (Word mode)
A-1 to A22 (Byte mode)
tOH
tCE
tACC
CE#
tCHZ
tOE
tOH
OE#
tOHZ
tACC
D0 to D15(Word mode)
D0 to D7(Byte mode)
D8 to D15 : Hi-Z(Byte mode)
Valid Data
Valid Data
Hi-Z
Hi-Z
PAGE ACCESS MODE READ CYCLE
tC
A3 to A22
tPC
tPC
A0 to A2 (Word mode)
A-1 to A2 (Byte mode)
tCE
tOH
CE#
OE#
tOE
tCHZ
tPAC
tOHZ
tACC
tPAC
D0 to D15(Word mode)
D0 to D7(Byte mode)
D8 to D15 : Hi-Z(Byte mode)
Hi-Z
Hi-Z
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FEDR27V12852L-002-01
MR27V12852L / P2ROM
PACKAGE DIMENSIONS
(Unit: mm)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
6/8
FEDR27V12852L-002-01
MR27V12852L / P2ROM
REVISION HISTORY
Page
Previous
Document
No.
Date
Description
Current
Edition
Edition
FEDR27V12852L-02-01 May 10, 2006
FEDR27V12852L-002-01 Oct. 01, 2008
–
–
–
Final edition 1
Changed company logo and name
to OKI SEMICONDUCTOR
–
7/8
FEDR27V12852L-002-01
MR27V12852L / P2ROM
NOTICE
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The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be
obtained from LAPIS Semiconductor upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall
bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
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Copyright 2008 - 2011 LAPIS Semiconductor Co., Ltd.
8/8
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