J111/D [ETC]
JFET Chopper Transistors ; JFET晶体管斩波\n
| 型号： | J111/D |
| 厂家： | 
ETC |
| 描述： | JFET Chopper Transistors
|
| 文件： | 总4页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ON Semiconductort
1 DRAIN
J111
J112
J113
JFET Chopper Transistors
N–Channel — Depletion
3
GATE
2 SOURCE
MAXIMUM RATINGS
Rating
Drain–Gate Voltage
Symbol
Value
–35
–35
50
Unit
V
V
Vdc
Vdc
DG
Gate–Source Voltage
Gate Current
GS
I
G
mAdc
Total Device Dissipation @ T = 25°C
Derate above 25°C
P
D
350
2.8
mW
mW/°C
1
A
2
3
Lead Temperature
T
300
°C
°C
L
CASE 29–11, STYLE 5
TO–92 (TO–226AA)
Operating and Storage Junction
Temperature Range
T , T
stg
–65 to +150
J
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
A
Characteristic
Symbol
Min
Max
Unit
OFF CHARACTERISTICS
Gate–Source Breakdown Voltage
(I = –1.0 µAdc)
G
V
35
—
—
Vdc
nAdc
Vdc
(BR)GSS
Gate Reverse Current
I
–ā1.0
GSS
(V
GS
= –15 Vdc)
Gate Source Cutoff Voltage
(V = 5.0 Vdc, I = 1.0 µAdc)
V
GS(off)
J111
J112
J113
–ā3.0
–ā1.0
–ā0.5
–ā10
–ā5.0
–ā3.0
DS
D
Drain–Cutoff Current
(V = 5.0 Vdc, V
I
—
1.0
nAdc
D(off)
= –10 Vdc)
GS
DS
ON CHARACTERISTICS
(1)
Zero–Gate–Voltage Drain Current
I
mAdc
DSS
(V
DS
= 15 Vdc)
J111
J112
J113
20
5.0
2.0
—
—
—
Static Drain–Source On Resistance
(V = 0.1 Vdc)
r
Ω
DS(on)
J111
J112
J113
—
—
—
30
50
100
DS
Drain Gate and Source Gate On–Capacitance
(V = V = 0, f = 1.0 MHz)
C
—
28
pF
dg(on)
+
DS GS
C
sg(on)
Drain Gate Off–Capacitance
(V = –10 Vdc, f = 1.0 MHz)
C
—
—
5.0
5.0
pF
pF
dg(off)
GS
Source Gate Off–Capacitance
(V = –10 Vdc, f = 1.0 MHz)
C
sg(off)
GS
1. Pulse Width = 300 µs, Duty Cycle = 3.0%.
Semiconductor Components Industries, LLC, 2001
1
Publication Order Number:
June, 2001 – Rev. 1
J111/D
J111 J112 J113
TYPICAL SWITCHING CHARACTERISTICS
1000
500
1000
T
= 25°C
J
T
= 25°C
J
500
J111
J112
J113
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
R
K
= R ′
D
R
K
= R ′
D
J111
J112
J113
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
200
100
50
200
100
50
20
10
20
10
R
K
= 0
R
K
= 0
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
I , DRAIN CURRENT (mA)
D
I , DRAIN CURRENT (mA)
D
Figure 1. Turn–On Delay Time
Figure 2. Rise Time
1000
500
1000
500
T
= 25°C
T
= 25°C
J
J
R
K
= R ′
D
J111
V
= 12 V
= 7.0 V
= 5.0 V
J111
V
= 12 V
= 7.0 V
= 5.0 V
GS(off)
GS(off)
200
100
50
200
100
50
J112
J113
J112
J113
R
K
= R ′
D
20
10
20
10
R
K
= 0
R
K
= 0
5.0
5.0
2.0
1.0
2.0
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
I , DRAIN CURRENT (mA)
D
I , DRAIN CURRENT (mA)
D
Figure 3. Turn–Off Delay Time
Figure 4. Fall Time
NOTE 1
The switching characteristics shown above were measured using a test cir-
cuit similar to Figure 5. At the beginning of the switching interval, the gate
+V
DD
voltage is at Gate Supply Voltage (–V ). The Drain–Source Voltage
GG
(V ) is slightly lower than Drain Supply Voltage (V ) due to the voltage
DS DD
R
D
divider. Thus Reverse Transfer Capacitance (C ) or Gate–Drain Capaci-
rss
SET V
DS(off)
= 10 V
tance (C ) is charged to V
gd GG
+ V .
DS
During the turn–on interval, Gate–Source Capacitance (C ) discharges
INPUT
gs
R
R
K
T
through the series combination of R
and R . C must discharge to
gd
Gen
K
R
V
through R and R in series with the parallel combination of ef-
OUTPUT
GEN
DS(on)
G
K
50 Ω
fective load impedance (R′ ) and Drain–Source Resistance (r ). During
R
GG
D
ds
50 Ω
50 Ω
the turn–off, this charge flow is reversed.
V
Predicting turn–on time is somewhat difficult as the channel resistance
is a function of the gate–source voltage. While C discharges, V ap-
V
GEN
GG
r
ds
gs
GS
proaches zero and r decreases. Since C discharges through r , turn–on
ds gd ds
time is non–linear. During turn–off, the situation is reversed with r in-
ds
INPUT PULSE
≤ 0.25 ns
R
& R
GG
K
creasing as C charges.
gd
t
r
The above switching curves show two impedance conditions; 1) R is
K
R
D
(R ) 50)
T
t
≤ 0.5 ns
f
R Ȁ +
D
equal to R , which simulates the switching behavior of cascaded stages
D
PULSE WIDTH = 2.0 µs
DUTY CYCLE ≤ 2.0%
R
) R ) 50
T
D
where the driving source impedance is normally the load impedance of the
previous stage, and 2) R = 0 (low impedance) the driving source imped-
K
ance is that of the generator.
Figure 5. Switching Time Test Circuit
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2
J111 J112 J113
20
15
10
J112
J111
C
C
gs
10
7.0
5.0
7.0
5.0
J113
gd
T
= 25°C
channel
= 15 V
V
DS
3.0
2.0
T
= 25°C
channel
(C IS NEGLIGIBLE)
ds
3.0
2.0
1.5
1.0
0.5 0.7 1.0
2.0 3.0
5.0 7.0 10
20 30
50
0.03 0.05 0.1
0.3 0.5
1.0
3.0 5.0
10
30
I , DRAIN CURRENT (mA)
D
V , REVERSE VOLTAGE (VOLTS)
R
Figure 6. Typical Forward Transfer Admittance
Figure 7. Typical Capacitance
200
160
120
80
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
I
25 50ĂmA 75ĂmA 100ĂmA
mA
125ĂmA
DSS
= 10
I
= 1.0 mA
= 0
D
V
GS
mA
T
= 25°C
40
channel
0
0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
-ā70
-ā40
-ā10
20
50
80
110
140
170
V , GATE-SOURCE VOLTAGE (VOLTS)
GS
T
channel
, CHANNEL TEMPERATURE (°C)
Figure 8. Effect of Gate–Source Voltage
On Drain–Source Resistance
Figure 9. Effect of Temperature On
Drain–Source On–State Resistance
100
90
10
T
= 25°C
channel
NOTE 2
9.0
8.0
7.0
The Zero–Gate–Voltage Drain Current (I
terminant of other J-FET characteristics. Figure 10 shows the
relationship of Gate–Source Off Voltage (V and Drain–
), is the principle de-
DSS
80
70
GS(off)
. Most of the devices will
r
@ V = 0
GS
DS(on)
Source On Resistance (r
) to I
ds(on)
DSS
60
50
40
30
20
10
0
6.0
5.0
4.0
3.0
2.0
be within ±10% of the values shown in Figure 10. This data will
V
be useful in predicting the characteristic variations for a given
GS(off)
part number.
For example:
Unknown
r
and V range for an J112
ds(on)
GS
The electrical characteristics table indicates that an J112 has
an I rangeof25to75mA.Figure10,showsr = 52 Ohms
1.0
0
DSS ds(on)
for I = 75 mA. The corre-
= 25 mA and 30 Ohms for I
DSS
sponding V
DSS
values are 2.2 volts and 4.8 volts.
10 20 30 40 50 60
80
100
90 110 120 130 140 150
70
GS
I , ZERO-GATE-VOLTAGE DRAIN CURRENT (mA)
DSS
Figure 10. Effect of I
On Drain–Source
Resistance and Gate–Source Voltage
DSS
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3
J111 J112 J113
PACKAGE DIMENSIONS
TO–92 (TO–226)
CASE 29–11
ISSUE AL
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
A
B
2. CONTROLLING DIMENSION: INCH.
3. CONTOUR OF PACKAGE BEYOND DIMENSION R
IS UNCONTROLLED.
4. LEAD DIMENSION IS UNCONTROLLED IN P AND
BEYOND DIMENSION K MINIMUM.
R
P
L
INCHES
DIM MIN MAX
MILLIMETERS
SEATING
PLANE
K
MIN
4.45
4.32
3.18
0.407
1.15
2.42
0.39
12.70
6.35
2.04
---
MAX
5.20
5.33
4.19
0.533
1.39
2.66
0.50
---
A
B
C
D
G
H
J
0.175
0.170
0.125
0.016
0.045
0.095
0.015
0.500
0.250
0.080
---
0.205
0.210
0.165
0.021
0.055
0.105
0.020
---
D
X X
G
J
H
V
K
L
---
---
C
N
P
R
V
0.105
0.100
---
2.66
2.54
---
SECTION X–X
0.115
0.135
2.93
3.43
1
N
---
---
N
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