ISL84523IR-T [ETC]
Analog Switch ; 模拟开关\n
| 型号： | ISL84523IR-T |
| 厂家： | 
ETC |
| 描述： | Analog Switch
|
| 文件： | 总14页 (文件大小：817K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISL84521, ISL84522, ISL84523
®
Data Sheet
September 2002
FN6031
Low-Voltage, Single and Dual Supply,
Quad SPST, Analog Switches
Features
• Drop-in Replacements for MAX4521 - MAX4523
• Four Separately Controlled SPST Switches
• Pin Compatible with DG411/DG412/DG413
The Intersil ISL84521–ISL84523 devices are CMOS,
precision, quad analog switches designed to operate from a
single +2V to +12V supply or from a ±2V to ±6V supply.
Targeted applications include battery powered equipment that
benefit from the devices’ low power consumption (<1µW), low
leakage currents (1nA max), and fast switching speeds
• ON Resistance (R
Max.) . . . . . . . . . . . . . . . . . . . 100Ω
Matching Between Channels. . . . . . . . . . . . . . . . . .<1Ω
ON
• R
ON
(t
= 45ns, t
= 15ns). A12Ω maximum R flatness
• Low Power Consumption (P ). . . . . . . . . . . . . . . . . . . .<1µW
ON
OFF
ON
D
ensures signal fidelity, while channel-to-channel mismatch is
guaranteed to be less than 4Ω. The 3mm x 3mm Quad No-
Lead Flatpack (QFN) package alleviates board space
limitations, making this newest line of low-voltage switches an
ideal solution.
• Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA
• Fast Switching Action
- t
- t
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45ns
ON
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns
OFF
• Minimum 2000V ESD Protection per Method 3015.7
• TTL, CMOS Compatible
The ISL84521/ISL84522/ISL84523 are quad single-pole/
single-throw (SPST) devices. The ISL84521 has four normally
closed (NC) switches; the ISL84522 has four normally open
(NO) switches; the ISL84523 has two NO and two NC
switches and can be used as a dual SPDT, or a dual 2:1
multiplexer.
Applications
• Battery Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
Table 1 summarizes the performance of this family. For higher
performance, pin compatible versions, see the ISL43140-42
data sheet.
- Pagers
- Laptops, Notebooks, Palmtops
• Communications Systems
- Military Radios
TABLE 1. FEATURES AT A GLANCE
- RF “Tee” Switches
ISL84521
4
ISL84522
4
ISL84523
4
• Test Equipment
- Ultrasound
Number of Switches
Configuration
All NC
65Ω
All NO
65Ω
2 NC / 2 NO
65Ω
- Electrocardiograph
±5V R
• Heads-Up Displays
ON
±5V t
/ t
ON OFF
45ns / 15ns 45ns / 15ns 45ns / 15ns
125Ω 125Ω 125Ω
60ns / 20ns 60ns / 20ns 60ns / 20ns
260Ω 260Ω 260Ω
• Audio and Video Switching
5V R
ON
• General Purpose Circuits
5V t
/ t
- +3V/+5V DACs and ADCs
- Digital Filters
ON OFF
3V R
ON
- Operational Amplifier Gain Switching Networks
- High Frequency Analog Switching
- High Speed Multiplexing
3V t
/ t
120ns / 40ns 120ns / 40ns 120ns / 40ns
ON OFF
16 Ld SOIC (N), 16 Ld 3x3 QFN,
16 Ld TSSOP
Packages
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
1
ISL84521, ISL84522, ISL84523
Pinouts (Note 1)
ISL84521 (SOIC, TSSOP)
TOP VIEW
ISL84521 (QFN)
TOP VIEW
IN1
COM1
NC1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NC2
13 V+
16 15 14 13
NC1
V-
1
2
3
4
12 NC2
11 V+
GND
NC4
COM4
IN4
12 N.C.
11 NC3
10 COM3
GND
NC4
10 N.C.
9
NC3
5
6
7
8
9
IN3
ISL84522 (SOIC, TSSOP)
ISL84522 (QFN)
TOP VIEW
TOP VIEW
IN1
COM1
NO1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NO2
13 V+
16 15 14 13
NO1
V-
1
12 NO2
11 V+
2
3
4
GND
NO4
COM4
IN4
12 N.C.
11 NO3
10 COM3
GND
NO4
10 N.C.
9
NO3
9
IN3
5
6
7
8
ISL84523 (SOIC, TSSOP)
ISL84523 (QFN)
TOP VIEW
TOP VIEW
IN1
COM1
NO1
V-
1
2
3
4
5
6
7
8
16 IN2
15 COM2
14 NC2
13 V+
16 15 14 13
NO1
V-
1
2
3
4
12 NC2
11 V+
GND
NO4
COM4
IN4
12 N.C.
11 NC3
10 COM3
GND
NO4
10 N.C.
9
NC3
9
IN3
5
6
7
8
NOTE:
1. Switches Shown for Logic “0” Input.
2
ISL84521, ISL84522, ISL84523
Truth Table
ISL84521
ISL84522
ISL84523
LOGIC SW 1, 2, 3, 4 SW 1, 2, 3, 4 SW 1, 4 SW 2, 3
0
1
ON
OFF
ON
OFF
ON
ON
OFF
OFF
NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V.
Pin Descriptions
PIN
V+
V-
FUNCTION
Positive Power Supply Input
Negative Power Supply Input. Connect to GND for
Single Supply Configurations.
GND
IN
Ground Connection
Digital Control Input
COM
NO
Analog Switch Common Pin
Analog Switch Normally Open Pin
Analog Switch Normally Closed Pin
No Internal Connection
NC
N.C.
Ordering Information
PART NO.
(BRAND)
(NOTE 2)
TEMP.
RANGE ( C)
o
PACKAGE
16 Ld SOIC (N)
16 Ld QFN
PKG. NO.
M16.15
ISL84521IB
-40 to 85
ISL84521IR*
(521I)
-40 to 85
L16.3x3
ISL84521IV
ISL84522IB
-40 to 85
-40 to 85
-40 to 85
16 Ld TSSOP
16 Ld SOIC (N)
16 Ld QFN
M16.173
M16.15
L16.3x3
ISL84522IR*
(522I)
ISL84522IV
ISL84523IB
-40 to 85
-40 to 85
-40 to 85
16 Ld TSSOP
16 Ld SOIC (N)
16 Ld QFN
M16.173
M16.15
L16.3x3
ISL84523IR*
(523I)
ISL84523IV
NOTES:
-40 to 85
16 Ld TSSOP
M16.173
2. Most surface mount devices are available on tape and reel; add
“-T” to suffix.
* In Development.
3
ISL84521, ISL84522, ISL84523
Absolute Maximum Ratings
Thermal Information
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V
V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -15 to 0.3V
All Other Pins (Note 3). . . . . . . . . . . . . ((V-) - 0.3V) to ((V+) + 0.3V)
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA
Peak Current, IN, NO, NC, or COM
Thermal Resistance (Typical, Note 4)
θ
( C/W)
JA
16 Ld SOIC Package . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld QFN Package. . . . . . . . . . . . . . . . . . . . . . . . .
16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature (Plastic Package) . . . . . . . 150 C
Moisture Sensitivity (See Technical Brief TB363)
All Other Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2
Maximum Storage Temperature Range. . . . . . . . . . . . -65 C to 150 C
115
75
150
o
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA
ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV
o
o
o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
(SOIC and TSSOP - Lead Tips Only)
Operating Conditions
Temperature Range
ISL8452XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to 85 C
o
o
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. Signals on NC, NO, COM, or IN exceeding V+ or V- are clamped by internal diodes. Limit forward diode current to maximum current ratings.
4. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Electrical Specifications: ±5V Supply Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
= 2.4V, V
= 0.8V (Note 5),
INL
SUPPLY
Unless Otherwise Specified
INH
TEMP (NOTE 6)
(NOTE 6)
MAX
o
PARAMETER
TEST CONDITIONS
( C)
MIN
TYP
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
V-
-
-
V+
100
125
4
V
Ω
ANALOG
ON Resistance, R
V
= ±5V, I
= 1.0mA, V
= 1.0mA, V
= 1.0mA, V
= ±3V,
65
ON
S
COM
COM
COM
COM
See Figure 5
Full
25
-
-
Ω
R
Matching Between Channels,
V
V
= ±5V, I
= ±5V, I
= ±3V
-
1
Ω
ON
∆R
S
S
S
S
S
COM
COM
ON
Full
25
-
-
6
Ω
R
Flatness, R
= ±3V, Note 8
-
7
12
15
1
Ω
ON
FLAT(ON)
Full
25
-
-
Ω
NO or NC OFF Leakage Current,
or I
V
7
= ±5.5V, V
= ±5.5V, V
= ±4.5V, V
= ±4.5V, V
or V
= +4.5V, Note
= +4.5V, Note
-1
-10
-1
-10
-2
-20
0.01
nA
nA
nA
nA
nA
nA
COM
COM
NO
NC
NC
I
NO(OFF)
NC(OFF)
Full
25
-
0.01
-
10
1
COM OFF Leakage Current,
V
7
or V
NO
I
COM(OFF)
Full
25
10
2
COM ON Leakage Current,
V
= ±5.5V, V
= V
or V = ±4.5V, Note 7
NC
0.01
-
COM
NO
I
COM(ON)
Full
20
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V
= ±5.5V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
S
V
V
= ±4.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
45
-
80
100
30
40
-
ns
ns
ns
ns
ns
ON
S
NO
NC
L
L
= 0 to 3V, See Figure 1
IN
Turn-OFF Time, t
V
V
= ±4.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
-
15
-
OFF
S
NO
NC
L
L
= 0 to 3V, See Figure 1
IN
Full
25
-
Break-Before-Make Time Delay
(ISL84523), t
V
V
= ±5.5V, V
or V
= ±3V, R = 300Ω, C = 35pF,
5
20
S
NO
NC
L
L
= 0 to 3V, See Figure 3
D
IN
Charge Injection, Q
C
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
25
25
-
-
-
1
2
2
5
-
pC
pF
pF
L
G
G
NO or NC OFF Capacitance, C
f = 1MHz, V
f = 1MHz, V
or V
or V
= V
= 0V, See Figure 7
= 0V, See Figure 7
OFF
NO
NC
COM
COM
COM OFF Capacitance,
= V
-
NO
NC
C
COM(OFF)
COM ON Capacitance, C
f = 1MHz, V
or V
= V
= 0V, See Figure 7
25
-
5
-
pF
COM(ON)
NO
NC
COM
4
ISL84521, ISL84522, ISL84523
Electrical Specifications: ±5V Supply Test Conditions: V
= ±4.5V to ±5.5V, GND = 0V, V
Unless Otherwise Specified (Continued)
= 2.4V, V
= 0.8V (Note 5),
INL
SUPPLY
INH
TEMP (NOTE 6)
(NOTE 6)
MAX
o
PARAMETER
OFF Isolation
Crosstalk, Note 9
TEST CONDITIONS
( C)
MIN
TYP
>90
UNITS
dB
R
= 50Ω, C = 15pF, f = 100kHz,
25
25
-
-
-
-
L
L
V
or V
= 1V
, See Figures 4 and 6
NO
NC
RMS
<-90
dB
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Full
25
±2
-1
-1
-1
-1
-
0.05
-
±6
1
V
Positive Supply Current, I+
Negative Supply Current, I-
NOTES:
V
= ±5.5V, V = 0V or V+, Switch On or Off
IN
µA
µA
µA
µA
S
Full
25
1
0.05
-
1
Full
1
5. V = Input voltage to perform proper function.
IN
6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
o
7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25 C.
8. Flatness is defined as the delta between the maximum and minimum R
9. Between any two switches.
values over the specified voltage range.
ON
Electrical Specifications: 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
V+
200
250
8
V
Ω
ANALOG
ON Resistance, R
V+ = 4.5V, I
= 1.0mA, V or V
NO NC
= 3.5V,
125
ON
COM
See Figure 5
Full
25
-
-
Ω
R
Matching Between Channels, V+ = 5V, I
COM
= 1.0mA, V
NO
or V
NC
= 3.5V
-
2
Ω
ON
∆R
ON
Full
25
-
-
10
1
Ω
NO or NC OFF Leakage Current,
V+ = 5.5V, V
Note 7
= 1V, 4.5V, V
= 1V, 4.5V, V
or V
or V
= 4.5V, 1V,
-1
-10
-1
-10
-2
-20
0.01
nA
nA
nA
nA
nA
nA
COM
COM
COM
NO
NO
NC
I
or I
NO(OFF)
NC(OFF)
Full
25
-
10
1
COM OFF Leakage Current,
V+ = 5.5V, V
Note 7
= 4.5V, 1V,
0.01
NC
I
COM(OFF)
Full
25
-
-
-
10
2
COM ON Leakage Current,
V+ = 5.5V, V
= 1V, 4.5V, Note 7
I
COM(ON)
Full
20
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V+ = 5.5V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 4.5V, V
or V
= 3V, R = 300Ω, C = 35pF,
25
Full
25
-
-
60
-
100
150
50
75
-
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to 3V, See Figure 1
IN
Turn-OFF Time, t
V+ = 4.5V, V
or V
= 3V, R = 300Ω, C = 35pF,
-
20
-
OFF
NO
NC
L
L
V
= 0 to 3V, See Figure 1
IN
Full
25
-
Break-Before-Make Time Delay
(ISL84523), t
V+ = 5.5V, V
or V
= 3V, R = 300Ω, C = 35pF,
10
30
NO
= 0 to 3V, See Figure 3
IN
NC
L
L
V
C
D
Charge Injection, Q
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
-
1
5
pC
L
G
G
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 5.5V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
µA
µA
µA
µA
-
0.05
-
Negative Supply Current, I-
Full
5
ISL84521, ISL84522, ISL84523
Electrical Specifications: 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, V- = GND = 0V, V
Unless Otherwise Specified
= 2.4V, V
= 0.8V (Note 5),
INL
INH
TEMP
( C)
MIN
(NOTE 6)
MAX
(NOTE 6) UNITS
o
PARAMETER
TEST CONDITIONS
TYP
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, V
Full
25
0
-
-
260
-
V+
500
600
V
Ω
Ω
ANALOG
ON Resistance, R
V+ = 2.7V, I
= 0.1mA, V
NO
or V = 1V
NC
ON
COM
Full
-
DIGITAL INPUT CHARACTERISTICS
Input Voltage High, V
Full
Full
Full
-
1.6
1.6
2.4
-
V
V
INH
Input Voltage Low, V
Input Current, I , I
0.8
-1
INL
V+ = 3.6V, V = 0V or V+
IN
0.03
1
µA
INH INL
DYNAMIC CHARACTERISTICS
Turn-ON Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
25
Full
25
-
-
120
-
250
300
80
ns
ns
ns
ns
ns
ON
NO
NC
L
L
V
= 0 to V+, See Figure 1
IN
Turn-OFF Time, t
V+ = 2.7V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
-
40
-
OFF
NO
NC
L
L
V
= 0 to V+, See Figure 1
IN
Full
25
-
100
-
Break-Before-Make Time Delay
(ISL84523), t
V+ = 3.6V, V
or V
= 1.5V, R = 300Ω, C = 35pF,
15
50
NO
= 0 to 3V, See Figure 3
IN
NC
L
L
V
C
D
Charge Injection, Q
= 1.0nF, V = 0V, R = 0Ω, See Figure 2
25
-
0.5
5
pC
L
G
G
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+
V+ = 3.6V, V = 0V or V+, Switch On or Off
IN
25
Full
25
-1
-1
-1
-1
0.05
1
1
1
1
µA
µA
µA
µA
-
0.05
-
Negative Supply Current, I-
Full
Test Circuits and Waveforms
V+
3V
t < 20ns
r
t < 20ns
f
C
LOGIC
INPUT
50%
SWITCH
INPUT
0V
NX
C
t
V
OFF
OUT
NO or NC
IN
SWITCH
INPUT
V
NX
V
COM
V
OUT
90%
90%
C
35pF
R
300Ω
L
L
GND
SWITCH
OUTPUT
0V
LOGIC
INPUT
t
ON
C
V-
Repeat test for all switches. C includes fixture and stray
L
Logic input waveform is inverted for switches that have the opposite
logic sense.
capacitance.
R
L
------------------------------
V
= V
OUT
(NO or NC)
R
+ R
(ON)
L
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1. SWITCHING TIMES
6
ISL84521, ISL84522, ISL84523
Test Circuits and Waveforms (Continued)
V+
C
SWITCH
OUTPUT
∆V
OUT
V
R
OUT
G
COM
NO or NC
V
OUT
3V
0V
ON
ON
LOGIC
INPUT
V
GND
OFF
G
IN
C
L
LOGIC
INPUT
C
Q = ∆V
x C
L
OUT
V-
Logic input waveform is inverted for switches that have the opposite
logic sense.
Repeat test for all switches. C includes fixture and stray
L
capacitance.
FIGURE 2B. TEST CIRCUIT
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
V+
C
C
3V
LOGIC
INPUT
V
OUT1
NO1
NC2
IN1
V
NX
COM1
COM2
0V
C
V
R
L1
L1
35pF
OUT2
300Ω
90%
90%
SWITCH
OUTPUT
R
C
L2
300Ω
L2
V
35pF
0V
0V
OUT1
IN2
LOGIC
INPUT
GND
90%
90%
SWITCH
OUTPUT
V
OUT2
C
t
t
D
D
V-
C
includes fixture and stray capacitance.
L
Reconfigure accordingly to test SW3 and SW4.
FIGURE 3B. TEST CIRCUIT
FIGURE 3A. MEASUREMENT POINTS
FIGURE 3. BREAK-BEFORE-MAKE TIME (ISL84523 ONLY)
V+
C
V+
C
R
= V /1mA
1
SIGNAL
GENERATOR
ON
NO or NC
NO or NC
V
NX
0V or 2.4V
IN
1mA
0.8V or 2.4V
IN
V
1
COM
COM
ANALYZER
GND
GND
R
L
C
C
V-
V-
Repeat test for all switches.
Repeat test for all switches.
FIGURE 5. R
FIGURE 4. OFF ISOLATION TEST CIRCUIT
TEST CIRCUIT
ON
7
ISL84521, ISL84522, ISL84523
Test Circuits and Waveforms (Continued)
V+
V+
C
SIGNAL
GENERATOR
50Ω
NO1 or NC1
IN2
COM1
NO or NC
0V or 2.4V
IN
0V or 2.4V
0V or 2.4V
IMPEDANCE
ANALYZER
IN2
NO
COM
CONNECTION
NO2 or NC2
COM2
ANALYZER
GND
GND
R
L
C
V-
V-
FIGURE 6. CROSSTALK TEST CIRCUIT
FIGURE 7. CAPACITANCE TEST CIRCUIT
unaffected by this approach, but the switch resistance may
increase, especially at low supply voltages.
Detailed Description
The ISL84521–ISL84523 quad analog switches offer precise
switching capability from a bipolar ±2V to ±6V or a single 2V
to 12V supply with low on-resistance (65Ω) and high speed
OPTIONAL PROTECTION
DIODE
switching (t
= 45ns, t = 15ns). The devices are
ON
OFF
especially well suited to portable battery powered equipment
thanks to the low operating supply voltage (2V), low power
consumption (1µW), low leakage currents (1nA max), and the
tiny QFN packaging. High frequency applications also benefit
from the wide bandwidth, and the very high OFF isolation and
crosstalk rejection.
V+
OPTIONAL
PROTECTION
RESISTOR
IN
V
X
V
NO or NC
COM
Supply Sequencing And Overvoltage Protection
V-
As with any CMOS device, proper power supply sequencing
is required to protect the device from excessive input
currents which might permanently damage the IC. All I/O
pins contain ESD protection diodes from the pin to V+ and to
V- (see Figure 8). To prevent forward biasing these diodes,
V+ and V- must be applied before any input signals, and
input signal voltages must remain between V+ and V-. If
these conditions cannot be guaranteed, then one of the
following two protection methods should be employed.
OPTIONAL PROTECTION
DIODE
FIGURE 8. OVERVOLTAGE PROTECTION
Power-Supply Considerations
The ISL8452X construction is typical of most CMOS analog
switches, in that they have three supply pins: V+, V-, and
GND. V+ and V- drive the internal CMOS switches and set
their analog voltage limits, so there are no connections
between the analog signal path and GND. Unlike switches
with a 13V maximum supply voltage, the ISL8452X 15V
maximum supply voltage provides plenty of room for the
10% tolerance of 12V supplies (±6V or 12V single supply),
as well as room for overshoot and noise spikes.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
Adding a series resistor to the switch input defeats the
purpose of using a low R
switch, so two small signal
ON
diodes can be added in series with the supply pins to provide
overvoltage protection for all pins (see Figure 8). These
additional diodes limit the analog signal from 1V below V+ to
1V above V-. The low leakage current performance is
This family of switches performs equally well when operated
with bipolar or single voltage supplies, and bipolar supplies
need not be symmetrical. The minimum recommended
8
ISL84521, ISL84522, ISL84523
supply voltage is 2V or ±2V. It is important to note that the
is the resistance to this feedthrough, while Crosstalk
indicates the amount of feedthrough from one switch to
another. Figure 16 details the high OFF Isolation and
Crosstalk rejection provided by this family. At 10MHz, OFF
isolation is about 50dB in 50Ω systems, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease OFF Isolation and
Crosstalk rejection due to the voltage divider action of the
switch OFF impedance and the load impedance.
input signal range, switching times, and ON-resistance
degrade at lower supply voltages. Refer to the electrical
specification tables and Typical Performance Curves for
details.
V+ and GND power the internal logic (thus setting the digital
switching point) and level shifters. The level shifters convert
the logic levels to switched V+ and V- signals to drive the
analog switch gate terminals, so switch parameters -
especially R
ON
- are strong functions of both supplies.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and V-. One
of these diodes conducts if any analog signal exceeds V+
or V-.
Logic-Level Thresholds
V+ and GND power the internal logic stages, so V- has no
affect on logic thresholds. This switch family is TTL
compatible (0.8V and 2.4V) over a V+ supply range of 2.5V
to 10V. At 12V the V level is about 2.7V, so for best results
Virtually all the analog leakage current comes from the ESD
diodes to V+ or V-. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or V- and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and V- pins constitutes the analog-signal-
path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and GND.
IH
use a logic family the provides a V
greater than 3V.
OH
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat even past
300MHz (see Figure 15), with a small signal -3dB bandwidth
in excess of 400MHz, and a large signal bandwidth
exceeding 300MHz.
An off switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. OFF Isolation
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified
A
90
80
70
60
50
300
250
200
150
100
V
= (V+) - 1V
I
= 1mA
V- = -5V
COM
= 1mA
COM
I
COM
o
85 C
o
85 C
o
25 C
o
25 C
o
-40 C
V+ = 2.7V
V- = 0V
o
-40 C
40
50
225
250
V- = 0V
o
85 C
200
150
100
50
175
125
o
o
85 C
25 C
V+ = 3.3V
V- = 0V
o
o
-40 C
25 C
75
140
o
V+ = 5V
V- = 0V
85 C
o
-40 C
110
80
o
25 C
o
-40 C
0
50
3
4
5
6
7
8
9
10
11
12
0
1
2
V
3
4
5
V+ (V)
(V)
COM
FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE
FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE
9
ISL84521, ISL84522, ISL84523
o
Typical Performance Curves T = 25 C, Unless Otherwise Specified (Continued)
A
180
5
V
= ±2V
I
= 1mA
S
COM
140
100
o
85 C
o
25 C
2.5
o
-40 C
60
120
V+ = 3.3V
V+ = 5V
V
= ±3V
0
S
100
80
o
85 C
o
25 C
o
2.5
60
-40 C
40
90
V
= ±5V
S
o
V
= ±5V
85 C
-5
S
70
50
30
o
25 C
o
-40 C
4
-7.5
-5
-2.5
0
2.5
5
-5
-4
-3
-2
-1
0
1
2
3
5
V
(V)
COM
V
(V)
COM
FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE
FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE
250
125
o
o
V
= (V+) - 1V
V
= (V+) - 1V
COM
V- = -5V
25 C
o
V- = -5V
25 C
COM
200
150
100
50
100
-40 C
o
-40 C
75
o
o
25 C
50
25 C
o
o
85 C
85 C
25
o
o
-40 C
-40 C
0
0
300
50
V- = 0V
V- = 0V
250
200
150
100
50
40
30
20
10
o
85 C
o
85 C
o
25 C
o
25 C
o
o
-40 C
-40 C
0
2
3
4
5
6
7
8
9
10
11
12
2
3
4
5
6
7
8
9
10
11
12
V+ (V)
V+ (V)
FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE
FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE
-10
-20
-30
-40
-50
-60
-70
-80
-90
10
V
= ±5V
S
V+ = 3V to 12V or
3
0
V
= ±2V to ±5V
= 50Ω
20
30
40
50
60
70
80
90
100
S
V
= 0.2V
P-P
GAIN
IN
R
L
V
= 5V
-3
IN P-P
0
PHASE
ISOLATION
45
90
V
= 0.2V
IN
P-P
= 5V
V
IN
P-P
CROSSTALK
135
180
-100
-110
R
= 50Ω
L
110
100M 500M
1
10
100
FREQUENCY (MHz)
600
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 15. FREQUENCY RESPONSE
FIGURE 16. CROSSTALK AND OFF ISOLATION
10
ISL84521, ISL84522, ISL84523
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
V-
TRANSISTOR COUNT:
ISL84521: 188
ISL84522: 188
ISL84523: 188
PROCESS:
Si Gate CMOS
11
ISL84521, ISL84522, ISL84523
Small Outline Plastic Packages (SOIC)
M16.15 (JEDEC MS-012-AC ISSUE C)
16 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
0.25(0.010)
M
B M
H
E
INCHES
MILLIMETERS
-B-
SYMBOL
MIN
MAX
0.0688
0.0098
0.020
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
NOTES
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
-
1
2
3
L
-
SEATING PLANE
A
9
-A-
0.0075
0.3859
0.1497
0.0098
0.3937
0.1574
-
o
h x 45
D
3
4
-C-
α
µ
0.050 BSC
1.27 BSC
-
e
A1
C
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
B
0.10(0.004)
5
0.25(0.010) M
C A M B S
L
6
N
α
16
16
7
NOTES:
°
°
°
°
0
8
0
8
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
12
ISL84521, ISL84522, ISL84523
Thin Shrink Small Outline Plastic Packages (TSSOP)
M16.173
N
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.201
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.10
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.193
0.169
0.05
0.80
0.19
0.09
4.90
4.30
-
L
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
α
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
16
16
7
°
°
°
°
NOTES:
0
8
0
8
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AB, Issue E.
Rev. 0 6/98
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
13
ISL84521, ISL84522, ISL84523
Quad No-Lead Flatpack (QFN)
2X
L16.3x3
0.15
E1/2
A2
C A
D
16 LEAD QUAD NO-LEAD FLAT PACKAGE
A
(COMPLIANT TO JEDEC MO-220-VEEC ISSUE C)
D/2
MILLIMETERS
D1
SYMBOL
MIN
NOMINAL
MAX
0.90
0.05
0.70
NOTES
D1/2
A
A1
A2
A3
b
-
-
-
-
-
2X
N
0.15 C
B
-
-
6
0.50 DIA.
-
-
1
2
3
E/2
0.20 REF
-
E1
0.23
0.95
0.95
0.28
0.35
1.25
1.25
5,8
E
B
D
3.00 BSC
-
D1
D2
E
2.75 BSC
-
0.15 C
B
1.10
7,8
2X
TOP VIEW
0.15 C
A
3.00 BSC
-
2X
E1
E2
e
2.75 BSC
-
0
1.10
7,8
A
NX
C
0.65 BSC
-
0.05 C
k
0.25
0.50
-
-
-
A1
A3
SIDE VIEW
SEATING
PLANE
L
0.60
0.75
8
N
16
4
4
-
2
5
NX b
0.10 M C A B
Nd
Ne
P
3
4X P
4X P
8
7
D2
D2
3
NX k
-
-
0.60
12
-
2
N
θ
-
-
Rev. 0 6/01
1
NOTES:
2
3
(Ne-1)Xe
REF.
1. Dimensioning and tolerancing per ASME Y14.5-1994.
2. N is the number of terminals.
E2
7
8
3. Nd is the number of terminals in the X direction, and Ne
is the number of terminals in the Y direction.
E2/2
NX L
8
4. Controlling dimension: Millimeters. Converted
dimensions to inches are not necessarily exact. Angles
are in degrees.
e
(Nd-1)Xe
REF.
5. Dimension b applies to the plated terminal and is
measured between 0.20mm and 0.25mm from the
terminal tip.
C
C
BOTTOM VIEW
A1
C
L
NX b
C
L
6. The Pin #1 identifier exists on the top surface as an
indentation mark in the molded body.
5
7. Dimensions D2 and E2 are the maximum exposed pad
dimensions for improved grounding and thermal
performance.
SECTION "C-C"
TERMINAL TIP
e
e
8. Nominal dimensions provided to assist with PCB Land
Pattern Design efforts, see Technical Brief TB389.
FOR ODD TERMINAL/SIDE
FOR EVEN TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
14
相关型号：
ISL84523IVZ
Low-Voltage, Single and Dual Supply, Quad SPST, Analog Switches; SOIC16, TSSOP16; Temp Range: -40° to 85°C
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