IP175ALF-DS-R03_技术文档

IP175A LF

Preliminary Data Sheet

5 Port 10/100 Ethernet Integrated Switch

Features

General Description

ꢀ

5 port 10/100 Ethernet switch with built in

transceivers and memory

Build in SSRAM for frame buffer

Built in storage of 1K MAC address

Support flow control

IP175A LF is a low cost 10/100 Ethernet single

chip switch. It integrates a 5-port switch controller,

SSRAM, and 5 10/100 Ethernet transceivers.

Each of the transceivers complies with the

ꢀ

IEEE802.3,

IEEE802.3u,

and

IEEE802.3x

–

Support IEEE802.3x for flow control for full

duplex mode operation

Support backpressure for flow control for

half duplex mode operation

specifications. The transceivers are designed in

DSP approach with 0.25um technology; they have

high noise immunity and robust performance.

–

ꢀ

5 port switching fabric

IP175A LF operates in store and forward mode. It

supports flow control, auto MDI/MDI-X, CoS, port

base VLAN, and LED functions, etc. Each port can

be configured to auto-negotiation or forced

10M/100M, full/half duplex, and it is also able to

configure to 100BaseFX transmission mode.

Using an EEPROM or pull up/down resistors on

specified pins can configure the desired options.

IP175A LF does not support “forced 10M half

mode”.

–

Support two-level hashing algorithm to

solve MAC address collision

Support MAC address aging

Store and forward mode

Broadcast storm protection

Full line speed capability of 148800 (14880)

packets/sec for 100M (10M)

Support 1536 byte data transfer for VLAN

packet traffic

–

Port base VLAN

Port base CoS configuration

IP175A LF supports two MII ports for router

application, which supports 4 LAN ports and one

WAN port. MII0 is for LAN traffic and MII1 is for

WAN traffic and no external PHY is needed. Both

MII can work in PHY mode and interface to the

external MAC in this application. The external

MAC can monitor or configure IP175A LF by

accessing MII registers through SMI.

ꢀ

Integrate 5 ports transceiver

–

Each port can be auto negotiable or forced

10M/100M, full/half duplex

Each port can be configured as 100BaseFX

Automatic MDI/MDI-X configuration

–

ꢀ

Support two MII, one SMI and extended MII

registers for router application

ꢀ

Built in regulator for 3.3v to 2.15v

LED status of Link, activity, Full/half duplex,

speed, and power on diagnostic function

Initial parameter setting by pin or EEPROM

(24LC01) configuration

MII0 also can be configured to be MAC mode. It is

used to interface an external PHY to work as a

4+1 switch.

ꢀ

Utilize single clock source (25Mhz)

0.25u technology

Support Lead Free package (Please refer to

the Order Information)

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Table Of Contents

Features ......................................................................................................................1

General Description.....................................................................................................1

Table Of Contents........................................................................................................2

Revision History...........................................................................................................3

1 Applications ...........................................................................................................4

Applications (continued) .................................................................................................5

Applications (continued) .................................................................................................6

2 Pin Diagram...........................................................................................................7

3 Pin Descriptions.....................................................................................................8

Pin Descriptions (continued)...........................................................................................9

Pin Descriptions (continued).........................................................................................10

Pin Descriptions (continued).........................................................................................11

Pin Descriptions (continued).........................................................................................12

Pin Descriptions (continued).........................................................................................13

Pin Descriptions (continued).........................................................................................14

Pin Descriptions (continued).........................................................................................15

Pin Descriptions (continued).........................................................................................17

Pin Descriptions (continued).........................................................................................18

4 Functional Description .........................................................................................19

4.1

4.2

4.3

4.4

4.5

4.6

4.7

5-port switch application.....................................................................................................19

Router application...............................................................................................................20

MII0 MAC mode..................................................................................................................21

MII, SMI and MII register ....................................................................................................22

Fiber port configuration.......................................................................................................25

CoS.....................................................................................................................................26

VLAN ..................................................................................................................................27

4.7.1

4.7.2

Port base VLAN.....................................................................................................27

Tag / un-tag............................................................................................................27

4.8

4.9

Initial value set by LED pins ...............................................................................................28

Built in regulator..................................................................................................................29

4.10 Extended MII registers........................................................................................................30

4.11 EEPROM register...............................................................................................................37

4.12 The basic MII registers .......................................................................................................48

4.13 LED Blink Timming .............................................................................................................52

5 Electrical Characteristics .....................................................................................53

5.1

5.2

5.3

Absolute Maximum Rating..................................................................................................53

DC Characteristic ...............................................................................................................53

AC Timing ...........................................................................................................................54

5.3.1

Reset Timing..........................................................................................................54

MII0 PHY Mode Timing..........................................................................................54

MII1 PHY Mode Timing..........................................................................................56

MII0 MAC Mode Timing.........................................................................................57

SMI Timing.............................................................................................................58

EEPROM Timing ...................................................................................................59

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

6 Order Information.................................................................................................59

7 Package Detail.....................................................................................................60

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Revision History

Revision #

Change Description

IP175A LF-DS-R01 Initial release.

IP175A LF-DS-R02 1. Update pin description of REG_OUT on page 14.

2. Add VCC_IO limitation to the operation condition on page 61.

3. Add VCC_IO_1, VCC_IO_2, VCC pin description on page 18

IP175A LF-DS-R03 Update pin description of Reg_out page 14.

IP175A LF-DS-R04 Remove MII register 16H.

IP175A LF-DS-R05 Remove VLAN from MII Register.

IP175A LF-DS-R06 1. ADD AC Timing

2. Change minimum VCC from 2.1v to 2.0v on page 14 & 50

IP175A LF-DS-R07 Add the order information for lead free package.

IP175A LF-DS-R08 ADD LED Blink Timing Table on page 52.

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

1

Applications

Application 1:

IP175A LF

5 x

Transformer

or

Fiber MAU

5 port Ethernet switch

Application 2:

Application 3:

MII0

MAC1

MAC2

IP175A LF

CPU

MII1

MII0

4 x

ADSL

or

Cable

Modem

PHY

1 x

Transformer

or

Fiber MAU

Transformer

or

Fiber MAU

4 LAN port + one WAN port (Router)

4 TP ports + one external PHY

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Applications (continued)

Application 1: 5 TP port switch

Switch

IP175A LF

5 port

switch controller

Use 5 builtin PHY.

MII0 and MII1 ports are not

used.

PHY

0

PHY

1

PHY

2

PHY

3

PHY

4

5 TP port

Application 1: 5 FX port switch

Switch

IP175A LF

Use 5 external fiber MAU.

MII0 and MII1 ports are not

used.

Fiber

MAU

0

Fiber

MAU

1

Fiber

MAU

2

Fiber

MAU

3

Fiber

MAU

4

5 FX port

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Applications (continued)

Application 2: 4 LAN port + one WAN port (Router)

R outer

IP 175A LF

5 port

M II0

M II1

(P H Y m ode M II)

sw itch controller

M A C 1

C P U

P H Y

0

P H Y

1

P H Y

2

P H Y

3

P H Y

4

M A C 2

4 X LA N port

1 W A N port

A D S L

or

W A N to IS P

C able m odem

E thernet

P C

Application 3: 4 TP port + one external PHY

Switch

IP175A LF

5 port

(MAC mode MII)

MII0

EXT

PHY

switch controller

Use 4 builtin PHY (0~3).

Use MII0 port to connected

the external PHY.

PHY

0

PHY

1

PHY

2

PHY

3

PHY

4

one external

PHY port

4 TP port

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

2

Pin Diagram

LED_SPEED[1] BF_STM_EN

LED_LINK[1] BK_EN

102

1

2

3

4

VCC

NC

101

100

LED_FULL[0] X_EN

GND_IO_1

TXOP0

TXOM0

99

98

97

96

95

94

93

92

91

VCC_IO_1

5

6

7

GND

VCC

LED_SPEED[0] UPDATE_R4_EN

LED_LINK[0] MII0_MAC_MODE

GND_SRAM

GND

TXOP1

TXOM1

VCC

8

VCC_SRAM

9

RESETB

10

11

12

13

14

15

16

LED_SEL[1]

RXIP1

RXIM1

GND

LED_SEL[0]

COL0 P0_FORCE

MII0_RXCLK

90

89

88

87

VCC

RXD0_0 P1_FORCE

RXD0_1 P2_FORCE

RXD0_2 P3_FORCE

RXD0_3 P4_FORCE

RXDV0

BGRES

GND

86

85

84

83

82

GND

17

18

RXIP2

RXIM2

VCC

19

GND

IP175A LF

20

21

22

VCC

TXOP2

TXOM2

GND

MII0_TXCLK

81

80

79

78

77

TXD0_0 P0_FORCE

TXD0_1 P1_FORCE

TXD0_2 P2_FORCE

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

VCC

GND

TXD0_3 P3_FORCE

TXOP3

TXEN0 P4_FORCE

P4MII_SNI

76

75

74

73

72

71

70

69

68

67

66

65

TXOM3

VCC

P4EXT

RXIP3

GND_IO_2

VCC_IO_2

MDC

RXIM3

GND

MDIO

RXIP4

RXIM4

VCC

COL1

MII1_RXCLK

RXD1_0 MAC_X_EN

RXD1_1

NC

TXOP4

TXOM

4

RXD1_2 AGING

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

3

Pin Descriptions

Type

Description

Type

Description

I

Input pin

IPL1 Input pin with internal pull low 22.8k ohm

IPH1 Input pin with internal pull high 22.8k ohm

IPL2 Input pin with internal pull low 92.6k ohm

IPH2 Input pin with internal pull high 113.8k ohm

O

Output pin

IPL

Input pin with internal pull low

IPH Input pin with internal pull high

Pin no.

Label

Type

Description

LED pins used as initial setting mode during reset

BF_STM_EN

BK_EN

IPL1 Broadcast storm protection enable

1: enable,

102

0: disable (default)

101

IPH1 Backpressure enable

1: enable (default),

0: disable

This pin doesn’t set the flow control of MII0 port. MAC_X_EN

sets the flow control of MII0 port.

IPH1 IEEE802.3X enable

100

97

X_EN

1: enable (default),

0: disable

This pin doesn’t set the flow control of MII0 port. MAC_X_EN

sets the flow control of MII0 port.

UPDATE_R4_EN IPL1 Change capability enable

A full duplex port will change its capability to half duplex, if the

remote full duplex port does not support IEEE802.3x then this

function is enabled. It should be pulled low for normal operation.

1: enable,

0: disable (default)

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

MII pins used as initial setting mode during reset

113

VLAN_ON

IPL

VLAN enable

1: enable,

0: disable (default)

IP175A LF is separated into 4 VLAN groups if this function is

enabled.

VLAN 1: port0, port 4;

VLAN 2: port 1, port 4;

VLAN 3: port 2, port 4;

VLAN 4: port 3, port 4;

Programming EEPROM registers 0Eh~12h or MII register

13h~15h will overwrite the VLAN configuration.

64

63

P4_HIGH

COS_EN

IPL2 Port4 is set to be high priority port

1: enable,

0: disabled (default)

Packets received from port4 are handled as high priority packets

if the feature is enabled. Please refer to EEPROM registers

0Eh~12h or MII register 13h~15h for detail information.

IPL2 Class of service enable

1: enable,

0: disabled (default)

Packets with high priority tag are handled as high priority

packets for all ports if the feature is enabled. Please refer to

EEPROM registers 0Eh~12h or MII register 13h~15h for detail

information.

65

AGING

IPH2 Address aging enable

1: enable, aging time 300s (default),

0: disable

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

External MII port setting

P4EXT

External MII port enable

74

IPL

1: Both MII interface are enabled for router application. MII1

supports PHY mode only. MII1 interfaces to internal PHY4 of

IP175A LF. It is connected to an external MAC device. MII0

supports both PHY mode and MAC mode depending on the

setting of MII0_MAC_MOD (pin 96).

0: External MII interface is disabled and IP175A LF works as a

5-port switch (default).

75

P4MII_SNI

IPL

External MII interface selection

1: SNI interface

IP175A LF supports PHY mode SNI (MII0_MAC_MOD=0),

i.e., it can be connected to an external MAC. IP175A LF

doesn’t support MAC mode SNI (MII0_MAC_MOD=1), i.e., it

should not be connected to an external PHY.

0: MII interface (default).

Pin no.

Label

Type

Description

External MII0 interface (P4EXT=1)

67

MAC_X_EN

Flow control enable for external MII0 port

1: enable (default),

IPH2

0: disable

96

MII0_MAC_MOD IPL1 External MII0 port MAC mode

1: MII0 works as a MAC and should be connected to an external

PHY.

0: MII0 works as a PHY and should be connected to an external

MAC device (default).

This pin does not affect MII1 port.

71, 70

MDC, MDIO

IPL

SMI

The external MAC device uses the interface to program basic and

extended MII register to configure PHY 4 and switch controller,

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

External MII0 interface (PHY mode, MII0_MAC_MOD=0, P4MII_SNI=0)

MII0_TXCLK

O

MII transmit clock

81

80, 79,

78, 77

TXD0_0, TXD0_1, IPL2 MII transmit data

TXD0_2, TXD0_3

It is sampled at the rising edge of MII0_TXCLK.

76

90

84

TXEN0

IPL2 MII transmit enable

It is used to frame TXD0[3:0]. It is sampled at the rising edge of

MII0_TXCLK.

COL0

O

MII collision

It is active when port 4 of switch controller is set to be half duplex

and a collision event happens.

RXDV0

MII receive data valid

It is used to frame RXD0[3:0]. It is sent out at the falling edge of

MII0_TXCLK.

88, 87,

86, 85

RXD0_0, RXD0_1,

RXD0_2, RXD0_3

O

MII receive data

It is sent out at the falling edge of MII0_TXCLK.

MII receive clock

89

MII0_RXCLK

There is no clock output in this mode.

Pin no.

Label

Type

Description

External MII0 interface (MAC mode, MII0_MAC_MOD=1, P4MII_SNI=0)

MII0_TXCLK

I

MII transmit clock

81

It is an input clock and it is connected to MII_TXCLK of external PHY.

MII transmit data

80, 79,

78, 77

TXD0_0, TXD0_1,

TXD0_2, TXD0_3

O

It is connected to MII_TXD of external PHY. It is sent out at the

rising edge of MII0_TXCLK.

76

TXEN0

O

MII transmit enable

It is an output signal and is connected to MII_TXEN of external

PHY. It is sent out at the rising edge of MII0_TXCLK.

90

84

COL0

IPL2 MII collision

It is an input signal and is connected to the MII_COL of external PHY.

RXDV0

I

MII receive data valid

It is an input signal and is connected to the MII_RXDV of

external PHY. RXDV0 is used to frame RXD0[3:0].

88, 87,

86, 85

RXD0_0, RXD0_1,

RXD0_2, RXD0_3

Receive data

It is NRZ data and is connected MII_RXD[3:0] of external PHY. It

is received at the rising edge of MII0_RXCLK.

MII0_RXCLK

MII receive clock

89

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

External MII1 interface (PHY mode only, P4EXT=1)

62

MII1_TXCLK

O

MII Transmit clock

61, 60,

59, 58

TXD1_0, TXD1_1, IPL2 MII transmit data

TXD1_2, TXD1_3

It is sampled at the rising edge of MII1_TXCLK.

57

69

63

TXEN1

IPL2 MII transmit enable

It is used to frame TXD1[3:0]. It is sampled at the rising edge of

MII1_TXCLK.

COL1

O

MII collision

It is active when PHY4 is set to be half duplex and a collision

event happens.

RXDV1

MII receive data valid

It is used to frame RXD1[3:0]. It is sent out at the falling edge of

MII1_RXCLK.

67, 66,

65, 64

RXD1_0, RXD1_1,

RXD1_2, RXD1_3

O

MII receive data

It is sent out at the falling edge of MII1_RXCLK.

MII receive clock

68

MII1_RXCLK

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

Force mode

P4_FORCE

IPL2 Port4 works at force mode.

85

1: force mode, disable port4 NWAY capability

0: auto-negotiation with all capability enabled (default)

It is used to force MII0 port PHY mode if P4EXT is pulled high.

76

It’s set by pin 85 if MII0 is in PHY mode and it’s set by pin 76 if

MII0 is in MAC mode.

86

77

P3_FORCE

P2_FORCE

P1_FORCE

P0_FORCE

IPL2 Port3 works at force mode.

1: force mode, disable port3 NWAY capability

0: auto-negotiation with all capability enabled (default)

It’s set by pin 86 if MII0 is in PHY mode and it’s set by pin 77 if

MII0 is in MAC mode.

87

78

IPL2 Port2 works at force mode.

1: force mode, disable port2 NWAY capability

0: auto-negotiation with all capability enabled (default)

It’s set by pin 87 if MII0 is in PHY mode and it’s set by pin 78 if

MII0 is in MAC mode.

88

79

IPL2 Port1 works at force mode.

1: force mode, disable port1 NWAY capability

0: auto-negotiation with all capability enabled (default)

It’s set by pin 88 if MII0 is in PHY mode and it’s set by pin 79 if

MII0 is in MAC mode.

90

80

IPL2 Port0 works at force mode.

1: force mode, disable port0 NWAY capability

0: auto-negotiation with all capability enabled (default)

It’s set by pin 90 if MII0 is in PHY mode and it’s set by pin 80 if

MII0 is in MAC mode.

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

Force mode

103

P4_FORCE100

IPL1 Force port4 work at 100M or 10M.

1: force 100M

0: force 10M (default)

It is used to force MII0 port PHY mode if P4EXT =1.

104

105

106

107

P3_FORCE100

P2_FORCE100

P1_FORCE100

P0_FORCE100

IPL1 Force port3 work at 100M or 10M.

1: force 100M

0: force 10M (default)

IPL1 Force port2 work at 100M or 10M.

1: force 100M

0: force 10M (default)

IPL1 Force port1 work at 100M or 10M.

1: force 100M

0: force 10M (default)

IPL1 Force port0 work at 100M or 10M.

1: force 100M

0: force 10M (default)

Pin no.

Label

Type

Description

Force mode

P4_FORCE_FULL IPL1 Force port4 work at full duplex or half duplex

1: force full duplex

108

0: force half duplex (default)

It is used to force MII0 port PHY mode if P4EXT=1.

IP175A LF does not support “force 10M half mode”.

109

110

111

112

P3_FORCE_FULL IPL1 Force port3 work at full duplex or half duplex

1: force full duplex

0: force half duplex (default)

IP175A LF does not support “force 10M half mode”.

P2_FORCE_FULL IPL1 Force port2 work at full duplex or half duplex

1: force full duplex

0: force half duplex (default)

IP175A LF does not support “force 10M half mode”.

P1_FORCE_FULL IPL1 Force port1 work at full duplex or half duplex

1: force full duplex

0: force half duplex (default)

IP175A LF does not support “force 10M half mode”.

P0_FORCE_FULL IPL1 Force port0 work at full duplex or half duplex

1: force full duplex

0: force half duplex (default)

IP175A LF does not support “force 10M half mode”.

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IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Label

Type

Description

Transceiver

RXIP0, RXIM0,

RXIP1, RXIM1,

RXIP2, RXIM2,

RXIP3, RXIM3,

RXIP4, RXIM4

TP receive

TP transmit

127,

128,

11, 12,

18,19,

29, 30,

33, 34

I

3, 4,

8, 9,

21, 22,

26, 27,

37, 38

O

TXOP0,

TXOM0,

TXOP1,

TXOM1,

TXOP2,

TXOM2,

TXOP3,

TXOM3,

TXOP4,

TXOM4

BGRES

14

O

I

Band gap resister.

It is connected to GND through a 6.2 k ohms resistor. Please

refer to application circuit for more information.

125, 41, FXSD0~4

100Base-FX Signal detect

42, 43,

44

IP175A LF will latch the value on FXSDx pins at the end of reset

to decide if the port works at 100BaseFX mode. A port works in

100BaseFX mode, if its corresponding signal FXSDx > 0.6v at

the end of reset. FXSDx should be connected to GND if the port

works in TP mode. That is, a port is a fiber port if its FXSDx is

connected to the SD of fiber MAU and a port is a TP port if its

FXSDx is connected to GND.

The SD of fiber port is active if the voltage of FXSDx is higher

than 1.2v. It is used to inform IP175A LF if the fiber is plugged or

not.

Pin no.

Misc.

Label

Type

Description

X1

X2

25M system clock input

123

122

93

I

O

I

Crystal pin

RESETB

Reset, low active

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin no.

Misc.

120

Label

Type

Description

REG_OUT

O

Regulator output

It is used to control external transistor to generate a 2.15v ±5%

voltage source when VCC_IO_1 and VCC_IO_2 are exactly 3.3v

and all ports are link on. To meet the specification of minimum VCC

(2.0v), VCC_IO_1 and VCC_IO_2 should be at least 3.3v. The

supply current of external transistor used should be at least 1A.

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

EEPROM

53

Label

Type

Description

SCL

SDA

I/O

After reset, it is used as clock pin SCL of EEPROM. Its period is

longer than 10us. IP175A LF stops reading EEPROM if it finds

there is no 55AA pattern in register 0. After reading EEPROM,

this pin becomes an input pin.

54

IO

After reset, it is used as data pin SDA of EEPROM. After reading

EEPROM, this pin becomes an input pin.

Pin no.

LED

Label

Type

Description

LED_SEL[1:0]

IPH LED output mode selection.

92, 91

LED_SEL[1:0]=00: LED mode 0,

LED_SEL[1:0]=01: LED mode 1,

LED_SEL[1:0]=10: LED mode 2,

LED_SEL[1:0]=11: LED mode 3 (default)

110,

LED_LINK[4:0]

O

Link, Activity (output after reset)

107,

104,

LED mode0: 100M Link + Activity (same as mode 2)

LED mode1: Receive activity

101, 96

(1: not receiving, flash: receiving)

LED mode2, 100M Link + Activity

(1: 100M Link fail, 0: 100M Link ok and no activity, flash: 100M

Link ok and TX/RX activity)

LED mode3: Link + Activity

(1: link fail, 0: link ok, flash: Link ok and TX/ RX activity)

111,

108,

105,

102, 97

LED_SPEED[4:0]

LED_FULL[4:0]

O

Speed (output after reset)

LED mode0: (1: no collision, flash: collision) (note*)

LED mode1: (1: speed=10M, 0: speed=100M)

LED mode2: Full/half: (1: half, 0: full, flash: collision)

LED mode3: (1: speed=10M, 0: speed=100M)

112,

Full/half, Link (output after reset)

109,

106,

103, 100

LED mode0, 10M Link + Activity (same as mode 2)

LED mode1, Link: (1: Link fail, 0: Link ok)

LED mode2, 10M Link + Activity

(1: 10M Link fail, 0: 10M Link ok and no activity, flash: 10M Link

ok and TX/RX activity)

LED mode3: Full/half: (1: half, 0: full, flash: collision)

Note: LED_SPEED[0] shows collision information for all ports. LED_SPEED[4:1] is undefined.

17/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Pin Descriptions (continued)

Pin no.

Power

Label

Type

Description

VCC_IO_1,

VCC_IO_2

I

98, 72

Power for output pins

They should be connected 3.3v if MII, EEPROM, or built in

regulator (REG_OUT) is used.

They can be connected to the same power source as VCC if

IP175A LF works as a 5-port switch without using bulilt in

regulator.

VCC

I

Power for core

2.15v~2.625v

Pin no.

Label

Type

Description

Test mode

TEST1, TEST2

IPL

Test mode selection

They should be connected to GND for normal operation.

51, 52

18/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4

Functional Description

5-port switch application

4.1

IP175A LF works as a 5 TP port auto MDI-MDIX switch when all fibers and MII function are disabled. In

this case, both FXSDx and P4EXT should be pulled low. Each port can be with auto-negotiation or force

mode in this application.

An example to illustrate the configuration setting of port4 when P4EXT is pulled low and MII is disabled

TP FX Nway Capability

FXSD4 P4_FORCE P4_FORCE100 P4_FORCE_FULL

Port

V

--

V

--

V

--

All capability

10M/ full

0

1

0

1

0

1

0

1

0

1

4

0

100M/ half

100M/ full

100M half

100M full

0

> 0.6v

4

Note:

1. The configuration not in the table is inhibited.

2. “--“: Not applicable

IP 175A LF

sw itch controller

port 4

port 0

port 1

port 2

port 3

P H Y

4

P H Y

0

P H Y

1

P H Y

2

P H Y

3

19/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.2

Router application

IP175A LF supports two MII ports, MII0 and MII1, for router application when P4EXT is pulled high. Pin

P4_FORCE, P4_FORCE100 and P4_FORCE_FULL decide the speed and duplex of MII0. The speed

and duplex of MII1 depend on the result of auto-negotiation of PHY4. But, programming basic MII

registers through SMI can modify them. MAC_X_EN pin decides the flow control option of MII0. It is

illustrated in the following table.

MII0

Flow

P4EXT MAC_X_EN P4_FORCE P4_FORCE100 P4_FORCE_FULL Speed Duplex

control

X

0

1

X

1

X

1

0

1

0

X

1

0

1

0

1

0

1

MII0 disabled.

0

1

100M

10M

Full

Half

Full

Half

Full

Half

Full

Off

On

10M

100M

10M

X: “don’t care”

IP175A LF can work as a router with 4 LAN ports and one WAN port, which use internal PHY (PHY4).

MII0 is the interface between port4 of internal switch controller and external MAC. MII1 is the interface

between internal transceiver PHY4 and external MAC. The switch controller forwards frames from

port0~3 to MII0 and vice versa. PHY4 works as an independent single PHY for external MAC. MII0 works

at PHY mode in this application (MII_MAC_MOD=0).

IP175A LF

(PHY m ode)

M II0

port 4

port 3

switch controller

port 1 port 2

M AC

(LAN)

port 0

CPU

PHY

0

PHY

1

PHY

2

PHY

3

PHY

4

M II1

M AC

(W AN)

LAN port

W AN port

20/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.3

MII0 MAC mode

MII0 works at MAC mode if MII_MAC_MOD is pulled high. MII0 is an interface between port4 of internal

switch controller and external PHY. It replaces an Ethernet PHY with a user specified PHY in this application.

The speed and duplex of MII0 are configured by P4_FORCE, P4_FORCE100 and P4_FORCE_FULL.

IP175A LF doesn’t read the status of external PHY via SMI at this mode.

IP 1 7 5 A L F

(M A C m o d e )

M II0

p o rt

4

s w itc h c o n tro lle r

p o rt 1 p o rt 2

P H Y

p o rt 0

p o rt 3

P H Y

0

P H Y

1

P H Y

2

P H Y

3

P H Y

4

(u n u s e d )

21/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.4

MII, SMI and MII register

IP175A LF supports two MII and one SMI (MDC and MDIO). Two MII interface to the external MAC for

data transfer and the SMI is used to program switch controller and PHY4.

IP175A LF provides basic MII registers for PHY4 and extended MII registers for switch controller. The

external MAC monitors or configures PHY4 by reading or writing the basic MII registers through SMI. The

external MAC monitors or configures switch controller by reading or writing the extended MII registers

through SMI.

The switch controller can be configured by pin and EEPROM, too. The operation is illustrated in the

following diagrams.

in itia l v a u le

fro m p in s

E E P R O M

S C L , S D A

IP 1 7 5 A L F

E E P R O M

re g is te rs

M A C

S w itc h

c o n tro lle r

C P U

M A C

M D C , M D IO

E x te n d e d M II

re g is te rs

B a s ic M II

re g is te rs

P H Y 4

T h re e w a y s to c o n fig u re IP 1 7 5 A , b y p in s , E E P R O M , o r p ro g ra m m in g M II re g is te rs

22/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Parameter setting with pins, EEPROM and MII registers in IP175A LF

Read default setting on

pins at the end of reset

EEPROM

exists ?

no

yes

Update the default

setting by reading

EEPROM

Enable MII

registers ?

no

yes

Change the setting by

programming SMI

Done

23/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Serial management interface (SMI)

User can access IP175A LF’s MII registers through serial management interface with pin MDC and

MDIO. A specific pattern on MDIO is used to access a MII register. Its format is shown in the following

table. When the SMI is idle, MDIO is in high impedance. To initialize the MDIO interface, the

management entity sends a sequence of 32 contiguous “1” and “start” on MDIO.

Syatem diagram

175A LF

MDI

MDC

O

CPU

Frame format

Read Operation <Idle><01><10><A₄A₃A₂A₁A₀><R₄R₃R₂R₁R₀><Z0>

<b₁₅b₁₄b₁₃b₁₂b₁₁b₁₀b₉b₈b₇b₆b₅b₄b₃b₂b₁b₀><Idle>

Write Operation <Idle><01><01><A₄A₃A₂A₁A₀><R₄R₃R₂R₁R₀><10>

<b₁₅b₁₄b₁₃b₁₂b₁₁b₁₀b₉b₈b₇b₆b₅b₄b₃b₂b₁b₀><Idle>

MDC

z

MDIO

1..1

0 0 0 0

0 0

0

0 0 1

0

0 1 1 0 0

0 1

1

0

0 1 0 0 0

0

0 1 1 0

op

code

A A A A A R R R R R

4 3 2 1 0 4 3 2 1 0

b b b b b b b b b b b b b b b b

1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0

idle

start

TA

write

PHY address =

01h

Reg address =

00h

5 4 3 2 1 0

Register data

MDC

z

MDIO

1..1

0 0 0 0

0 0

1

0

0 0 Z

0

0 0 1 0 0

0 1

0

0 1 0 0 0

0

0 1 1 0

op

code

A A A A A R R R R R

4 3 2 1 0 4 3 2 1 0

b b b b b b b b b b b b b b b b

1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0

idle

start

TA

read

PHY address =

01h

Reg address =

00h

5 4 3 2 1 0

Register data

24/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.5

Fiber port configuration

Each port of IP175A LF can be configured to be a fiber port or a TP port. A port becomes a fiber port if its

FXSDx is connected to a fiber MAU or it is pulled high. A port becomes a TP port if its FXSDx is pulled

low. It is illustrated in the following table.

Port configuration

Voltage on FXSDx

< 0.6v

TP port

Fiber port

Fiber signal detect

Condition

--

V

--

V

--

> 0.6v, < 1.2v

> 1.2v

Off

On

Fiber unplugged

Fiber plugged

The following is an example that IP175A LF is configured to be 3 TP ports and 2 fiber ports. In this case,

the speed and duplex of fiber ports are defined by pin P0_FORCE100, P0_FORCE_FULL,

P1_FORCE100, and P1_FORCE_FULL.

VCC

IP175A LF

VCC

Fiber MAU

FXSD0

Fiber MAU

FXSD1

FXSD4

FXSD3 FXSD2

25/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.6

CoS

IP175A LF supports two type of Cos. One is port base priority function and the other is frame base

priority function. IP175A LF supports two levels of priority queues. A high priority packet will be queued in

the memory as a high priority queue, this action will ensure more bandwidth for the high priority packets

in the transmission.

The packets received from high priority port will be handled as high priority frames if the port base priority

is enabled. It is enabled by programming the corresponding bit in EEPROM register 0Eh~12h of or MII

register 13h~15h. Each port of IP175A LF can be configured as a high priority port individually.

IP175A LF examines the specific bits of VLAN tag and TCP/IP TOS for priority frames if the frame base

priority is enabled. The packets will be handled as high priority frames if the value of VLAN tag or TCP/IP

TOS field meets the high priority requirement. It is enabled by programming the corresponding bit in

EEPROM register 16H~21H or MII register 17h~1Ch. The frame base priority function of each port can

be enabled individually.

The Cos function can be active even if there is no EEPROM. IP175A LF supports an easy way to enable

a sub set CoS function without EEPROM. Port 4 can be set as a high priority port if pin 64 (p4_high) is

pulled high. Frame base priority function of all ports is enabled if pin 63 (Cos_en) is pulled high. The

setting in register takes precedence of the setting on pins.

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.7

VLAN

Port base VLAN

4.7.1

IP175A LF supports port base VLAN functions. It separates IP175A LF into some groups (VLAN). A port

is limited to communicate with other ports within the same group when the function is enabled. Frames

are limited in a VLAN group and will not transmit out of this VLAN group. A port can be assigned to one or

more VLAN groups. The members (ports) of a VLAN group are assigned by programming EEPROM

register 0Eh~12h of or MII register 13h~15h.

The VLAN function can be active even if there is no EEPROM. IP175A LF supports an easy way to

enable a sub set VLAN function without EEPROM. A default configuration of VLAN is adopted if pin 113

(VLAN_on) is pulled high. The VLAN group in this mode is illustrated in the pin description of VLAN_on.

It is benefit in a router application that an individual LAN port can shares a WAN port. The setting in

register takes precedence of the setting on pins.

4.7.2

Tag / un-tag

IP175A LF supports tag / un-tag functions. When the function is enabled, IP175A LF inserts the

pre-defined tag into a forwarded frame if the frame is forwarded to a tagged field. IP175A LF strips the

tag of a frame if the frame is forwarded to an untagged field. The operation is illustrated as follows.

IP175A LF doesn’t support tag VLAN function.

Frame type of the

received packet

The operation of a output port

Forward to a untagged filed

Forward to a tagged field

Untagged

Transmit as received

1. Insert VLAN tag to the packet.

2. The inserted VLAN tag is defined in the

EEPROM register of source port.

Priority-tagged

(VLAN ID=0)

Strip tag

1. Keep priority field.

2. Modify the VLAN ID.

3. The modified VLAN tag is defined in the

EEPROM register of source port.

VLAN-tagged

Strip tag

Transmit as received

27/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.8

Initial value set by LED pins

Most configuration pins are shared with LED pin in IP175A LF. These multi-function pins are input during

reset period and are LED output after reset. IP175A LF reads initial value via pins during the reset period.

An initial value is set to 1 (0) by connecting a pin to vcc (gnd) through a 10kΩ (1kΩ) resistor as shown on

the following figure.

The application circuit is shown below.

VCC

1k

VCC

LED pin

220

1k

to set initial value = 1

with pull up 1k ohm resister to VCC

to set initial value = 0

with pull down 1k ohm resister to GND

VCC

LED pin

220

to use default value

(use no resistor to leave it open)

28/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.9

Built in regulator

IP175A LF built in a linear regulator to generate 2.15v power. The applications are shown below.

VCC = 3.6v (from adaptor)

(generated 2.15v )

R

REG_OUT

VCC

3.3v

VCC_IO_1

VCC_IO_2

linear

regulator

IP175A LF

Pure switch with a 3.6v power adaptor.

VCC = 3.3v

(from board )

generated

2.15v

VCC_IO_1

VCC_IO_2

REGOUT

VCC

linear

regulator

IP175A LF

Router with an on board 3.3v power source

VCC

(from board)

VCC

VCC_IO_1

VCC_IO_2

internal regulator

is not used

linear

regulator

IP175A LF

Pure switch uses on board single power source

29/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.10 Extended MII registers

MII ROM Function

R/W

Description

Default

MII register 12H (18D)

12.15 2.1 LED_SEL [1:0]

12.14 2.0

R/W Led_sel,

2’b11

LED mode selection.

LED_SEL[1:0]=2’b00: LED mode 0,

LED_SEL[1:0]=2’b01: LED mode 1,

LED_SEL[1:0]=2’b10: LED mode 2,

LED_SEL[1:0]=2’b11: LED mode 3 (default)

12.13 4.7 X_EN

R/W X_en,

1

IEEE 802.3x flow control enable

This signal is used as pause_en for digital parts.

1: enable, 0:disable

12.12 4.4 BK_EN

R/W Bk_en,

1

0

Backpressure enable

1: enable, 0: disable

12.11 4.2 BF_STM_EN

R/W Broadcast storm enable

1: enable

Drop the incoming packet if the number of queued

broadcast packet is over the threshold. The

threshold is defined in register 0AH[14:13].

0: disable

12.10 4.3 MAC_X_EN

R/W MII0 flow control enable

1: enable,

1

0

0: disable

12.7

12.6

--

MII_REGISTER_ R/W 1: select MII register

EN

0: select EEPROM register

This bit should not be enabled until the contents of

MII registers are all filled with correct value.

B.4 UPDATE_R4_EN

R/W Update_r4_en,

0

Change capability enable

A full duplex port will change its capability to half

duplex, if the remote full duplex port does not

support 802.3x and this function is enable.

1: enable, 0: disable

12.4

12.3

6.5 Reserved

6.4 AGING

R/W

R/W Aging time,

Aging time of address table selection

0

1

An address tag in hashing table will be dropped if

this function is turned on and its aging timer expires.

Aging =bit[4]

0: no aging

1: aging time 300sec (default)

12.2

--

MII0_SPEED

RO Speed of MII0

0

1: 100M

0: 10M

It is speed of MII0 if P4_EXT is enabled. It is speed

of port4 if P4EXT is disabled

30/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 12H (18D)

12.1

--

MII0_FDX

RO Speed of MII0

1: full duplex

0

0: half duplex

It is duplex of MII0 if P4_EXT is enabled. It is duplex

of port4 if P4EXT is disabled

12.0

6.6 Reserved

R/W

0

MII

ROM

Function

R/W

Description

Default

MII register 13H (19D)

13.15 --

R/W Don’t care

0

13.14 E.6 P0_COS

13.13 E.5 P0_HIGH

R/W Port0 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port0 are handled

as high priority packets.

R/W Port0 set to be high priority port

1: enable, 0: disabled (default)

0

Packets received from port0 are handled as high

priority packets.

13.12

≀

--

Reserved

Don’t care

13.7

13.6

F.6 P1_COS

F.5 P1_ HIGH

R/W Port1 Class of service enable

1: enable, 0: disabled (default)

0

Packets with high priority tag from port1 are handled

as high priority packets.

13.5

R/W Port1 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port1 are handled as high

priority packets.

13.4

≀

--

Reserved

Don’t care

13.0

MII

ROM

Function

R/W

Description

Default

MII register 14H (20D)

14.15 --

R/W Don’t care

0

14.14 10.6 P2_COS

14.13 10.5 P2_ HIGH

R/W Port2 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port2 are handled

as high priority packets.

R/W Port2 set to be high priority port

1: enable, 0: disabled (default)

0

Packets received from port2 are handled as high

priority packets.

31/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 14H (20D)

14.12

≀

--

Reserved

Don’t care

14.7

14.6 11.6 P3_COS

14.5 11.5 P3_ HIGH

R/W Port3 Class of service enable

1: enable, 0: disabled (default)

0

Packets with high priority tag from port3 are handled

as high priority packets.

R/W Port3 set to be high priority port

1: enable, 0: disabled (default)

0

Packets received from port3 are handled as high

priority packets.

14.4

≀

--

Reserved

Don’t care

14.0

MII

ROM

Function

R/W

Description

Default

MII register 15H (21D)

15.15 --

R/W Don’t care

0

15.14 12.6 P4_COS

15.13 12.5 P4_ HIGH

R/W Port4 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port4 are handled

as high priority packets.

R/W Port4 set to be high priority port

1: enable, 0: disabled (default)

0

Packets received from port4 are handled as high

priority packets.

15.12

≀

--

Reserved

Don’t care

15.0

MII

ROM

Function

R/W

Description

Default

MII register 16H (22D) is reserved

--

13.4 P4_FORCE

13.3 P3_FORCE

13.2 P2_FORCE

13.1 P1_FORCE

R/W Port4 force mode enable

0

1: enable force mode

0: disable force mode, port4 NWAY with all capability

R/W Port3 force mode enable

0

1: enable force mode

0: disable force mode, port3 NWAY with all capability

R/W Port2 force mode enable

1: enable force mode

0: disable force mode, port2 NWAY with all capability

R/W Port1 force mode enable

1: enable force mode

0: disable force mode, port1 NWAY with all capability

32/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 16H (22D) is reserved

--

13.0 P0_FORCE

R/W Port0 force mode enable

1: enable force mode

0

0: disable force mode, port0 NWAY with all capability

14.4 P4_FORCE100

R/W Force port4 to be 100M

1: force to be 100M

0

0: force to be 10M

It is valid only if p4_force (15h[15]) is set to 1’b1.

--

14.3 P3_FORCE100

14.2 P2_FORCE100

14.1 P1_FORCE100

14.0 P0_FORCE100

R/W Force port3 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p3_force (15h[14]) is set to 1’b1.

R/W Force port2 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p2_force (15h[13]) is set to 1’b1.

--

R/W Force port1 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p1_force (15h[12]) is set to 1’b1.

--

R/W Force port0 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p0_force (15h[11]) is set to 1’b1.

--

15.4 P4_FORCE_FULL R/W Force port4 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (15.15) is set to 1’b1.

--

15.3 P3_FORCE_FULL R/W Force port3 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (15.14) is set to 1’b1.

--

15.2 P2_FORCE_FULL R/W Force port2 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (15.13) is set to 1’b1.

--

15.1 P1_FORCE_FULL R/W Force port1 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (15.12) is set to 1’b1.

--

15.0 P0_FORCE_FULL R/W Force port0 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (15.11) is set to 1’b1.

16.0

--

Reserved

33/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 17H (23D)

17[15:11] 16[4:0]

R/W Add VLAN tag

17H[11]

5’b0

Add VLAN tag

1: port0 adds a VLAN tag to each outgoing packet.

0: port0 doesn’t add a VLAN tag.

17H[12]

1: port1 adds a VLAN tag to each outgoing packet.

0: port1 doesn’t add a VLAN tag.

17H[13]

1: port2 adds a VLAN tag to each outgoing packet.

0: port2 doesn’t add a VLAN tag.

17H[14]

1: port3 adds a VLAN tag to each outgoing packet.

0: port3 doesn’t add a VLAN tag.

17H[15]

1: port4 adds a VLAN tag to each outgoing packet.

0: port4 doesn’t add a VLAN tag.

17[10:6] 17[4:0]

R/W Remove VLAN tag

5’b0

Remove VLAN

tag

17H[6]

1: port0 removes the VLAN tag from each outgoing

packet.

0: port0 doesn’t remove the VLAN tag.

17H[7]

1: port1 removes the VLAN tag from each outgoing

packet.

0: port1 doesn’t remove the VLAN tag.

17H[8]

1: port2 removes the VLAN tag from each outgoing

packet.

0: port2 doesn’t remove the VLAN tag.

17H[9]

1: port3 removes the VLAN tag from each outgoing

packet.

0: port3 doesn’t remove the VLAN tag.

17H[10]

1: port4 removes the VLAN tag from each outgoing

packet.

0: port4 doesn’t remove the VLAN tag.

34/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 18H (24D)

18[15:8] 19[7:0]

R/W Vlan_tag_0_high

8’b0

Port 0

vlan_tag[15:8]

This register defines the high byte of VLAN tag for port 0.

18[7:0] 18[7:0]

R/W Vlan_tag_0_low

8’b0

Port 0

vlan_tag[7:0]

This register defines the low byte of VLAN tag for port 0.

MII

ROM

Function

R/W

R/W Vlan_tag_1_high

Description

Default

8’b0

MII register 19H (25D)

19[15:8] 1B[7:0]

Port 1

vlan_tag[15:8]

This register defines the high byte of VLAN tag for port 1.

19[7:0] 1A[7:0]

R/W Vlan_tag_1_low

This register defines the low byte of VLAN tag for port 1.

8’b0

Port 1

vlan_tag[7:0]

MII

ROM

Function

R/W

Description

Default

8’b0

MII register 1AH (26D)

1A[15:8] 1D[7:0]

R/W Vlan_tag_2_high

Port 2

vlan_tag[15:8]

This register defines the high byte of VLAN tag for port 2.

1A[7:0] 1C[7:0] Port 2 vlan_tag[7:0] R/W Vlan_tag_2_low

This register defines the low byte of VLAN tag for port 2.

8’b0

MII

ROM

Function

R/W

Description

Default

8’b0

MII register 1BH (27D)

1B[15:8] 1F[7:0]

R/W Vlan_tag_3_high

Port 3

vlan_tag[15:8]

This register defines the high byte of VLAN tag for port 3.

1B[7:0] 1E[7:0] Port 3 vlan_tag[7:0] R/W Vlan_tag_3_low

This register defines the low byte of VLAN tag for port 3.

8’b0

MII

ROM

Function

R/W

Description

Default

8’b0

MII register 1CH (28D)

1C[15:8] 21[7:0]

R/W Vlan_tag_4_high

Port 4

vlan_tag[15:8]

This register defines the high byte of VLAN tag for port 4.

1C[7:0] 20[7:0] Port 4 vlan_tag[7:0] R/W Vlan_tag_4_low

8’b0

This register defines the low byte of VLAN tag for port 4.

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

MII

ROM

Function

R/W

Description

Default

MII register 1DH (29D)

1D[15:12] --

RO Reserved

RO

0

1

0

1D.11

1D.10

--

Reserved

jab_on

R/W Jabber enabled.

1: jabber function enabled

0: jabber function disabled

R/W Heartbeat enabled.

1D.9

1D.8

1D.7

1D.6

1D.5

--

heartbt_en,

reptr_en

0

1

1: heartbeat function enabled

0: heartbeat function disabled

R/W Select NIC or repeater mode.

1: repeater mode

0: NIC mode

lp_nway_able

polrev

RO Link partner is auto-negotiation able.

1: link partner supports auto-negotiation

0: link partner doesn’t support auto-negotiation

0

RO Analog transmit/receive signal polarity

1: RX+- polarity reversed

0: RX+- polarity not reversed

phyaddr_fix

R/W PHY address fix or not.

1: MII registers can be accessed only if the PHY

address filed in management frame matches the

content of MII register 29[4:0].

0: MII registers can be accessed in spite of the PHY

address.

1D[4:0] --

phyaddr

R/W Define PHY address

5’b0

36/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.11 EEPROM register

ROM MII Pin name

EEPROM registers 00~01H

Description

EEPROM enable register

Default

0[7:0]

1[7:0]

--

AA

55

This register should be filled with 55AA. IP175A LF will

check the specified pattern to confirm a valid EEPROM

exists. The initial setting is updated after power on reset only

if the specified pattern 55AA is found.

Description

(LED output selection register)

ROM

MII

Pin name

Default

EEPROM registers 02H

2[7:2]

2[1:0]

--

Reserved

6’b0

11

12[15:14]

LED_SEL[1:0]

Led_sel,

LED mode selection.

LED_SEL[1:0]=00: LED mode 0,

LED_SEL[1:0]=01: LED mode 1,

LED_SEL[1:0]=10: LED mode 2,

LED_SEL[1:0]=11: LED mode 3 (default)

Please refer to pin description for detail LED definition.

ROM

MII

Pin name

Description

Default

EEPROM registers 03H

3[7:0]

--

Reserved

8’b0

Description

(Switch control register 1)

ROM

MII

Pin name

Default

EEPROM registers 04H

4.7 12.13 X_en

X_en,

1

(LED_FULL[0])

IEEE 802.3x flow control enable

This signal is used as pause_en for digital parts.

1: enable, 0:disable

4[6:5]

4.4 12.12 Bk_en

(LED_LINK[1])

--

Reserved

2’b0

1

Bk_en,

Backpressure enable

1: enable, 0: disable

4.3 12.10 Mac_x_en

Mac_x_en,

External Mac port flow control enable

1: enable, 0:disable

1

0

(RXD1_0)

4.2 12.11 Bf_stm_en

Broadcast storm enable

(LED_SPEED[1]) 1: enable

Drop the incoming packet if the number of queued broadcast

packet is over the threshold. The threshold is defined in

register 0AH[14:13].

0: disable

37/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Description

(Switch control register 1)

ROM

MII

Pin name

Default

EEPROM registers 04H

4.1

4.0

Reserved

0

1

Description

(Switch control register 2)

ROM

MII

Pin name

Default

EEPROM registers 05H

5[7:6]

5.5

--

Reserved

Bp_kind,

2’b0

1’b0

00

5[4:3]

Backpressure type selection

It is valid only if Bk_en (02H[4]) is set to 1’b1.

00: carrier base backpressure

01: collision base backpressure with hashing

10: collision base backpressure without hashing

5[2:0]

--

Reserved

3’b0

Description

(Switch control register 3)

ROM

MII

Pin name

Default

EEPROM registers 06H

6.7

--

No drop16,

1

A port will drop the transmitting packet after 16 consecutive

collisions if this function is turned on.

1: do not drop, 0: drop

6.6

6.5

6.4

12.0

--

0

1

12.4

12.3 Aging

Agetime,

(RXD1_2)

Aging time of address table selection

An address tag in hashing table will be dropped if this function

is turned on and its aging timer expires. Aging =bit[4]

0: no aging

1: aging time 300sec (default)

6.2

6.1

--

Twopart,

Turn on twopartD

IP175A LF examine the carrier idle for 64 bits only when it is

back off if this function is turned.

1: turn on, 0: turn off

1

Modbck,

Turn on modified back off algorithm

The maximum back off period is limited to 16-slot time if this

function is turned on.

1: turn on (default),

0: turn off

6.0

--

Reserved

0

38/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

ROM

MII

Pin name

Description

Default

EEPROM registers 07H

7[7:0]

--

Reserved

8’b0

ROM

MII

Pin name

Default

(Transceiver control register 1)

EEPROM registers 08H

8[7:0]

--

8’b0

Description

(Transceiver control register 2)

ROM

MII

Pin name

Default

EEPROM registers 09H

9[7:2]

9.1

--

6’b0

1

Savepw_a_en,

Save power mode

Digital sends wake up signal to analog before sending FLP if

this function is active.

0: disable, 1: enable

The default value must be adopted for normal operation.

9.0

--

MDI/MDI-X enable

1

1: enable (default), 0:disable

This function should be tuned on for normal operation.

Disable MDIX is inhibited.

Description

(Transceiver verification register 1)

ROM

MII

Pin name

Default

EEPROM registers 0AH

A[7:6]

A.5

--

Reserved

00

0

A.4

0

A.3

0

A.1

0

A.0

0

Description

(Transceiver verification register 2)

ROM

MII

Pin name

Default

EEPROM registers 0BH

B.7

B.6

B.5

--

Reserved

1’b0

0

39/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Description

(Transceiver verification register 2)

ROM

MII

Pin name

Default

EEPROM registers 0BH

B.4

12.6 Update_r4_en

(LED_SPEED[0]) Change capability enable

A full duplex port will change its capability to half duplex, if

Update_r4_en,

0

the remote full duplex port does not support 802.3x and this

function is enable.

1: enable, 0: disable

B.3

B.2

B.1

B.0

--

Reserved

0

Description

(Testing & verify mode register 1)

ROM

MII

Pin name

Default

EEPROM registers 0CH

C.7

C.6

--

Reserved

0

C[5:0]

6’b0

Description

(Testing & verify mode register 2)

ROM

MII

Pin name

Default

EEPROM registers 0DH

D[7:3]

D.2

--

Reserved

0

1

0

1

D.1

D.0

Description

(VLAN register 0)

ROM

MII

Pin name

Default

1’b0

EEPROM registers 0EH

E.7

--

Don’t care

E.6 13.14

Port0 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port0 are handled as high

priority packets.

E.5 13.13

--

Port0 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port0 are handled as high priority

packets.

1’b0

40/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Description

(VLAN register 0)

ROM

MII

Pin name

Default

EEPROM registers 0EH

E.4

--

Port0 VLAN look up table

1’b1

The register defines the ports in the same VLAN with port0.

The bit 0~4 are corresponding to port 0~4.

1: port 4 and port0 are in the same VLAN

0: port 4 and port0 are not in the same VLAN

E.3

E.2

E.1

E.0

--

Port0 VLAN look up table

1: port 3 and port0 are in the same VLAN

0: port 3 and port0 are not in the same VLAN

1’b1

Port0 VLAN look up table

1: port 2 and port0 are in the same VLAN

0: port 2 and port0 are not in the same VLAN

Port0 VLAN look up table

1: port 1 and port0 are in the same VLAN

0: port 1 and port0 are not in the same VLAN

Don’t care

Description

(VLAN register 1)

ROM

MII

Pin name

Default

1’b0

EEPROM registers 0FH

F.7

F.6

--

Don’t care

13.6

Port1 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port1 are handled as high

priority packets.

F.5

F.4

13.5

--

Port1 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port1 are handled as high priority

packets.

1’b0

Port1 VLAN look up table

1’b1

The register defines the ports in the same VLAN with port1.

The bit 8~12 are corresponding to port 0~4.

1: port 4 and port1 are in the same VLAN

0: port 4 and port1 are not in the same VLAN

F.3

F.2

--

Port1 VLAN look up table

1: port 3 and port1 are in the same VLAN

0: port 3 and port1 are not in the same VLAN

1’b1

Port1 VLAN look up table

1: port 2 and port1 are in the same VLAN

0: port 2 and port1 are not in the same VLAN

F.1

F.0

--

Don’t care

Port1 VLAN look up table

1’b1

1: port 0 and port1 are in the same VLAN

0: port 0 and port1 are not in the same VLAN

41/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Description

(VLAN register 2)

ROM

MII

Pin name

Default

EEPROM registers 10H

10.7

--

Don’t care

10.6 14.14

Port2 Class of service enable

1: enable, 0: disabled (default)

1’b0

Packets with high priority tag from port2 are handled as high

priority packets.

10.5 14.13

--

Port2 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port2 are handled as high priority

packets.

1’b0

1’b1

10.4

10.3

--

Port2 VLAN look up table

The register defines the ports in the same VLAN with port2.

The bit 0~4 are corresponding to port 0~4.

1: port 4 and port2 are in the same VLAN

0: port 4 and port2 are not in the same VLAN

--

Port2 VLAN look up table

1’b1

1: port 3 and port2 are in the same VLAN

0: port 3 and port2 are not in the same VLAN

10.2

10.1

--

Don’t care

Port2 VLAN look up table

1: port 1 and port2 are in the same VLAN

0: port 1 and port2 are not in the same VLAN

1’b1

10.0

--

Port2 VLAN look up table

1: port 0 and port2 are in the same VLAN

0: port 0 and port2 are not in the same VLAN

Description

(VLAN register 3)

ROM

MII

Pin name

Default

1’b0

EEPROM registers 11H

11.7

--

Don’t care

11.6 14.6

Port3 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port3 are handled as high

priority packets.

11.5 14.5

--

Port3 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port3 are handled as high priority

packets.

1’b0

11.4

--

Port3 VLAN look up table

1’b1

The register defines the ports in the same VLAN with port3.

The bit 8~12 are corresponding to port 0~4.

1: port 4 and port3 are in the same VLAN

0: port 4 and port3 are not in the same VLAN

11.3

11.2

--

Don’t care

Port3 VLAN look up table

1’b1

1: port 2 and port3 are in the same VLAN

0: port 2 and port3 are not in the same VLAN

42/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Description

(VLAN register 3)

ROM

MII

Pin name

Default

EEPROM registers 11H

11.1

11.0

--

Port3 VLAN look up table

1: port 1 and port3 are in the same VLAN

0: port 1 and port3 are not in the same VLAN

1’b1

Port3 VLAN look up table

1’b1

1: port 0 and port3 are in the same VLAN

0: port 0 and port3 are not in the same VLAN

Description

(VLAN register 4)

ROM

MII

Pin name

Default

1’b0

EEPROM registers 12H

12.7

--

Don’t care

12.6 15.14

Port4 Class of service enable

1: enable, 0: disabled (default)

Packets with high priority tag from port4 are handled as high

priority packets.

12.5 15.13 P4_high

Port4 set to be high priority port

1: enable, 0: disabled (default)

Packets received from port4 are handled as high priority

packets.

1’b0

12.4

12.3

--

Don’t care

Port4 VLAN look up table

1’b1

The register defines the ports in the same VLAN with port4.

The bit 0~4 are corresponding to port 0~4.

1: port 3 and port4 are in the same VLAN

0: port 3 and port4 are not in the same VLAN

12.2

12.1

12.0

--

Port4 VLAN look up table

1: port 2 and port4 are in the same VLAN

0: port 2 and port4 are not in the same VLAN

1’b1

Port4 VLAN look up table

1: port 1 and port4 are in the same VLAN

0: port 1 and port4 are not in the same VLAN

Port4 VLAN look up table

1: port 0 and port4 are in the same VLAN

0: port 0 and port4 are not in the same VLAN

ROM

MII

Pin name

Description

Default

EEPROM registers 13H

13[7:5]

13.4

--

Don’t care

P4_FORCE

Port4 force mode enable

0

1: enable force mode

0: disable force mode, port4 NWAY with all capability

43/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

ROM

MII

Pin name

Description

Default

EEPROM registers 13H

13.3

13.2

13.1

13.0

--

P3_FORCE

P2_FORCE

P1_FORCE

P0_FORCE

Port3 force mode enable

1: enable force mode

0: disable force mode, port3 NWAY with all capability

0

Port2 force mode enable

1: enable force mode

0: disable force mode, port2 NWAY with all capability

0

Port1 force mode enable

1: enable force mode

0: disable force mode, port1 NWAY with all capability

Port0 force mode enable

1: enable force mode

0: disable force mode, port0 NWAY with all capability

ROM

MII

Pin name

Description

Default

EEPROM registers 14H

14[7:5]

14.4

--

Don’t care

P4_FORCE100

Force port4 to be 100M

0

1: force to be 100M

0: force to be 10M

It is valid only if p4_force (13H[4]) is set to 1’b1.

14.3

14.2

14.1

14.0

--

P3_FORCE100

P2_FORCE100

P1_FORCE100

P0_FORCE100

Force port3 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p3_force (13H[3]) is set to 1’b1.

0

Force port2 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p2_force (13H[2]) is set to 1’b1.

Force port1 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p1_force (13H[1]) is set to 1’b1.

Force port0 to be 100M

1: force to be 100M

0: force to be 10M

It is valid only if p0_force (13H[0]) is set to 1’b1.

44/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

ROM

MII

Pin name

Description

Default

EEPROM registers 15H

15[7:5]

15.4

--

Don’t care

P4_FORCE_FULL Force port4 to be full duplex

1: force full duplex

0

0: force half duplex

It is valid only if p4_force (13H[4]) is set to 1’b1.

IP175A LF does not support “force 10M half mode”.

P3_FORCE_FULL Force port3 to be full duplex

15.3

15.2

15.1

15.0

--

0

1: force full duplex

0: force half duplex

It is valid only if p4_force (13H[3]) is set to 1’b1.

IP175A LF does not support “force 10M half mode”.

P2_FORCE_FULL Force port2 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (13H[2]) is set to 1’b1.

IP175A LF does not support “force 10M half mode”.

P1_FORCE_FULL Force port1 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (13H[1]) is set to 1’b1.

IP175A LF does not support “force 10M half mode”.

P0_FORCE_FULL Force port0 to be full duplex

1: force full duplex

0: force half duplex

It is valid only if p4_force (13H[0]) is set to 1’b1.

IP175A LF does not support “force 10M half mode”.

ROM

MII

Pin name

Description

Default

EEPROM registers 16H

16[4:0] 17[15:11] --

Add VLAN tag

5’b0

16H[0]

1: port0 adds a VLAN tag to each outgoing packet.

0: port0 doesn’t add a VLAN tag.

16H[1]

1: port1 adds a VLAN tag to each outgoing packet.

0: port1 doesn’t add a VLAN tag.

16H[2]

1: port2 adds a VLAN tag to each outgoing packet.

0: port2 doesn’t add a VLAN tag.

16H[3]

1: port3 adds a VLAN tag to each outgoing packet.

0: port3 doesn’t add a VLAN tag.

16H[4]

1: port4 adds a VLAN tag to each outgoing packet.

0: port4 doesn’t add a VLAN tag.

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February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

ROM

MII

Pin name

Description

Default

EEPROM registers 17H

17[4:0] 17[10:6]

--

Remove VLAN tag

17H[0]

5’b0

1: port0 removes the VLAN tag from each outgoing packet.

0: port0 doesn’t remove the VLAN tag.

17H[1]

1: port1 removes the VLAN tag from each outgoing packet.

0: port1 doesn’t remove the VLAN tag.

17H[2]

1: port2 removes the VLAN tag from each outgoing packet.

0: port2 doesn’t remove the VLAN tag.

17H[3]

1: port3 removes the VLAN tag from each outgoing packet.

0: port3 doesn’t remove the VLAN tag.

17H[4]

1: port4 removes the VLAN tag from each outgoing packet.

0: port4 doesn’t remove the VLAN tag.

ROM

MII

Pin name

Description

Default

EEPROM registers 18H~21H

18[7:0] 18[7:0]

19[7:0] 18[15:8]

1A[7:0] 19[7:0]

1B[7:0] 19[15:8]

1C[7:0] 1A[7:0]

1D[7:0] 1A[15:8]

1E[7:0] 1B[7:0]

1F[7:0] 1B[15:8]

--

Vlan_tag_0_low

This register defines the low byte of VLAN tag for port 0.

(i.e. Port 0 vlan_tag[7:0])

8’b0

Vlan_tag_0_high

This register defines the high byte of VLAN tag for port 0.

(i.e. Port 0 vlan_tag[15:8])

8’b0

Vlan_tag_1_low

This register defines the low byte of VLAN tag for port 1.

(i.e. Port 1 vlan_tag[7:0])

Vlan_tag_1_high

This register defines the high byte of VLAN tag for port 1.

(i.e. Port 1 vlan_tag[15:8])

Vlan_tag_2_low

This register defines the low byte of VLAN tag for port 2.

(i.e. Port 2 vlan_tag[7:0])

Vlan_tag_2_high

This register defines the high byte of VLAN tag for port 2.

(i.e. Port 2 vlan_tag[15:8])

Vlan_tag_3_low

This register defines the low byte of VLAN tag for port 3.

(i.e. Port 3 vlan_tag[7:0])

Vlan_tag_3_high

This register defines the high byte of VLAN tag for port 3.

(i.e. Port 3 vlan_tag[15:8])

46/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

ROM

MII

Pin name

Description

Default

EEPROM registers 18H~21H

20[7:0] 1C[7:0]

21[7:0] 1C[15:8]

--

Vlan_tag_4_low

This register defines the low byte of VLAN tag for port 4.

(i.e. Port 4 vlan_tag[7:0])

8’b0

Vlan_tag_4_high

8’b0

This register defines the high byte of VLAN tag for port 4.

(i.e. Port 4 vlan_tag[15:8])

Description

(Testing & verify mode register 3)

ROM

MII

Pin name

Default

EEPROM registers 22H

22[7:6]

22[5:4]

22[3:0]

--

Reserved

2’b01

2’b00

4’b0000

Description

(Testing & verify mode register 4)

ROM

MII

Pin name

Default

EEPROM registers 23H

23[7:0]

--

Reserved

8’h00

Description

(Testing & verify mode register 5)

ROM

MII

Pin name

Default

EEPROM registers 24H

24[7:0] -- --

Reserved

8’h01

47/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.12 The basic MII registers

Type

R/W

SC

Description

Read/Write

Self-Clearing

Read Only

Type

LL

Description

Latching Low

Latching High

LH

RO

Bit

Function

R/W

Description

Default

MII control register (address 00H)

15 Not supported

R/W 1 = Loopback mode

0 = normal operation

0

Reset

14 Loop back

When this bit set, IP175A LF will be isolated from the

network media, that is, the assertion of TXEN at the MII will

not transmit data on the network. All MII transmission data

will be returned to MII receive data path in response to the

assertion of TXEN.

13 Speed Selection

RW 1 = 100Mbps

1

0 = 10Mbps

It is valid only if bit 0.12 is set to be 0.

12 Auto-Negotiation

Enable

RW 1 = Auto-Negotiation Enable

0 = Auto-Negotiation Disable

If port 4 is a fiber port, FXSD higher than 0.6v, this bit is fixed

at 0.

11 Power Down

10 Isolate

R/W Not supported

Not supported

0

9

Restart Auto-

Negotiation

RW 1 = re-starting Auto-Negotiation

SC 0 = Auto-Negotiation re-start complete

Setting this bit to logic high will cause IP175A LF to restart

an Auto-Negotiation cycle, but depending on the value of bit

0.12 (Auto-Negotiation Enable). If bit 0.12 is cleared then

this bit has no effect, and it is Read Only. This bit is

self-clearing after Auto-Negotiation process is completed.

8

7

Duplex mode

Collision test

R/W 1 = full duplex

0

0 = half duplex

It is valid only if bit 0.12 is set to be 0.

R/W Not supported

0

-

6:0 Reserved

R/W Write as 0, ignore on read

Bit

Function

R/W

Description

Default

MII status register (address 01H)

15 100Base-T4

capable

RO 1 = 100Base-T4 capable

0 = not 100Base-T4 capable

0

IP175A LF does not support 100Base-T4. This bit is fixed to

be 0.

48/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Bit

Function

R/W

Description

Default

MII status register (address 01H)

14 100Base-X full

duplex Capable

RO 1 = 100Base-X full duplex capable

0 = not 100Base-X full duplex capable

1

The default of this bit will change depend on the external

setting of IP175A LF. If external pin setting without

100Base-X full duplex support, then this bit will change

default to logic 0.

13 100Base-X half

duplex Capable

RO 1 = 100Base-X half duplex capable

1

0 = not 100Base-X half duplex capable

The default of this bit will change depend on the external

setting of IP175A LF. If external pin setting without

100Base-X half duplex support, then this bit will change

default to logic 0

12 10Base-T full

duplex Capable

RO 1 = 10Base-T full duplex capable

1

0 = not 10Base-T full duplex capable

The default of this bit will change depend on the external

setting of IP175A LF. If external pin setting without 100Base-T

full duplex support, then this bit will change default to logic 0

11 10Base-T half

duplex Capable

RO 1 = 10Base-T half duplex capable

0 = not 10Base-T half duplex capable

The default of this bit will change depend on the external

setting of IP175A LF. If external pin setting without

100Base-X full duplex support, then this bit will change

default to logic 0

10:7 Reserved

RO Ignore on read

-

6

MF preamble

Suppression

RO 1 = preamble may be suppressed

0 = preamble always required

1

5

Auto-Negotiation

Complete

RO 1 = Auto-Negotiation complete

0

0 = Auto-Negotiation in progress

When read as logic 1, indicates that the Auto-Negotiation

process has been completed, and the contents of register 4

and 5 are valid. When read as logic 0, indicates that the

Auto-Negotiation process has not been completed, and the

contents of register

4 and 5 are meaningless. If

Auto-Negotiation is disabled (bit 0.12 set to logic 0), then this

bit will always read as logic 0.

4

3

Remote fault

RO 1 = remote fault detected

LH 0 = not remote fault detected

0

1

When read as logic 1, indicates that IP175A LF has detected

a remote fault condition. This bit is set until remote fault

condition gone and before reading the contents of the

register. This bit is cleared after IP175A LF reset.

Auto-Negotiation

Ability

RO 1 = Auto-Negotiation capable

0 = not Auto-Negotiation capable

When read as logic 1, indicates that IP175A LF has the

ability to perform Auto-Negotiation. The value of this bit will

depend on the external mode setting of IP175A LF operation

mode.

49/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Bit

Function

R/W

Description

Default

MII status register (address 01H)

2

1

Link Status

RO 1 = Link Pass

LL 0 = Link Fail

0

When read as logic 1, indicates that IP175A LF has

determined a valid link has been established. When read as

logic 0, indicates the link is not valid. This bit is cleared until

a valid link has been established and before reading the

contents of this registers.

Jabber Detect

1 = jabber condition detected

0

0 = no jabber condition detected

When read as logic 1, indicates that IP175A LF has detected

a jabber condition. This bit is always 0 for 100Mbps

operation and is cleared after IP113A reset. This bit is set

until jabber condition is cleared and reading the contents of

the register.

0

Extended

capability

RO 1 = Extended register capabilities

0 = No extended register capabilities

1

IP175A LF has extended register capabilities.

Bit

Function

R/W

Description

Default

PHY Identifier (address 02H)

15:0 PHY identifier

RO IP175A LF OUI (Organizationally Unique Identifier) ID, the 0243h

msb is 3^rdbit of IP175A LF OUI ID, and the lsb is 18^thbit of

IP175A LF OUI ID. IP175A LF OUI is 0090C3.

Bit

Function

R/W

Description

Default

PHY Identifier (address 03H)

15:10 PHY identifier

RO IP175A LF OUI ID, the msb is 19^thbit of IP175A LF OUI ID,

and lsb is 24^thbit of IP175A LF OUI ID.

3h

05h

0

9:4 Manufacture’s

Model Number

RO IP175A LF model number

3:0 Revision Number

RO IP175A LF revision number

Bit

Function

R/W

Description

Default

Auto-Negotiation Advertisement register (address 04H)

15 Next Page

14 Reserved

13 Remote Fault

12:11 Reserved

10 Pause

Not supported

0

RW Reserved by IEEE, write as 0, ignore on read

R/W Not supported

RO Reserved for future IEEE use, write as 0, ignore on read

RW 1 = Advertises that this device has implemented pause function

0 = No pause function supported

9

100BASE-T4

RW Not supported

0

50/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

Bit

Function

R/W

Description

Default

Auto-Negotiation Advertisement register (address 04H)

8

7

6

5

100BASE-TX full R/W 1 = 100BASE-TX full duplex is supported

1

duplex

0 = 100BASE-TX full duplex is not supported

100BASE-TX

R/W 1 = 100BASE-TX is supported

0 = 100BASE-TX is not supported

1

10BASE-T full duplex R/W 1 = 10BASE-T full duplex is supported

0 = 10BASE-T full duplex is not supported

10BASE-T

R/W 1 = 10BASE-T is supported

0 = 10BASE-T is not supported

4:0 Selector Field

R/W Use to identify the type of message being sent by 00001

Auto-Negotiation.

Bit

Function

R/W

Description

Default

Link partner ability register (address 05H) Base Page

15 Next Page

RO 1 = Next Page ability is supported by link partner

0 = Next Page ability does not supported by link partner

0

14 Acknowledge

13 Remote Fault

RO 1 = Link partner has received the ability data word

0 = Not acknowledge

RO 1 = Link partner indicates a remote fault

0 = No remote fault indicate by link partner

If this bit is set to logic 1, then bit 1.4 (Remote fault) will set

to logic 1.

12:11 Reserved

10 Pause

RO Reserved by IEEE for future use, write as 0, read as 0.

0

1

RO 1 = Link partner support IEEE802.3x

0 = Link partner does not support IEEE802.3x

IP175A LF will reload the default value after rest or link

failure.

9

8

7

6

5

100BASE-T4

RO 1 = Link partner support 100BASE-T4

0 = Link partner does not support 100BASE-T4

0

100BASE-TX full RO 1 = Link partner support 100BASE-TX full duplex

duplex

0

0 = Link partner does not support 100BASE-TX full duplex

100BASE-TX

RO 1 = Link partner support 100BASE-TX

0 = Link partner does not support 100BASE-TX

0

10BASE-T

duplex

full RO 1 = Link partner support 10BASE-T full duplex

0 = Link partner does not support 10BASE-T full duplex

0

10BASE-T

RO 1 = Link partner support 10BASE-T

0 = Link partner does not support 10BASE-T

4:0 Selector Field

RO Protocol selector of the link partner

00000

51/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

4.13 LED Blink Timming

LED mode

Active led blink

Blinking speed

On -> Off 80ms -> On 20ms -> Off 80ms …

Off -> On 20ms -> Off 80ms ->On 20ms …

Collision led blink

Neon like LED(initial setup LED) On 250ms -> Off 1.25s -> On 250ms -> Off 1.25s …

52/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5

Electrical Characteristics

Absolute Maximum Rating

5.1

Stresses exceed those values listed under Absolute Maximum Ratings may cause permanent damage to

the device. Functional performance and device reliability are not guaranteed under these conditions. All

voltages are specified with respect to GND.

Supply Voltage

Input Voltage

Output Voltage

Storage Temperature

Ambient Operating Temperature (Ta)

–0.3V to 4.0V

–0.3V to 5.0V

-65°C to 150°C

0°C to 70°C

5.2

DC Characteristic

Operating Conditions

Parameter

Sym.

Min.

2.0

Typ. Max.

Unit

Conditions

VCC

2.15 2.625

V

Supply Voltage

VCC_IO 3.1

VCC_IO 3.3

3.5

V

Pin 120 REG_OUT is not used.

Pin 120 REG_OUT is used.

Operation Junction

Temperature

Tj

0

70

125

℃

Power Consumption

1.485

W

VCC=2.25v

Input Clock

Parameter

Frequency

Sym.

Min.

Typ. Max.

Unit

Conditions

25

MHz

Frequency Tolerance

-50

+50

PPM

I/O Electrical Characteristics

Parameter

Sym.

Min.

Typ. Max.

Unit

Conditions

VIL

0.8

V

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

VIH

VOL

VOH

2.0

2.4

V

0.4

IOH=4mA, VCC_IO_x=3.3V

IOL=4mA, VCC_IO_x=3.3V

53/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5.3

AC Timing

5.3.1

Reset Timing

Description

Min.

Typ.

Max.

Unit

X1 valid period before reset released

Reset period

MII clock comes out period after reset released

10

-

1

-

ms

µs

Power on

VCC

OSCI (X1)

X1 valid period before reset released

Reset released

resetb

Reset period

MII clock

MII clock comes out period after reset released

5.3.2

MII0 PHY Mode Timing

a. Transmit Timing Requirements

Symbol

Description

Min.

Typ.

Max.

Unit

T_TxClk

T_sTxClk

T_hTxClk

Transmit clock period 100M MII

Transmit clock period 10M MII

TXEN0, TXD0 to MII0_TXCLK setup time

TXEN0, TXD0 to MII0_TXCLK hold time

-

2

40

400

-

ns

0.5

T

TxClk

MII0_TXCLK

ThTxClk

TXEN0,

TXD0[3:0]

T^sTxClk

54/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

b. Receive Timing

Symbol

Description

Min.

Typ.

Max.

Unit

T_RxClk

T_dRxClk

Receive clock period 100M MII

Receive clock period 10M MII

MII0_RXCLK falling edge to RXDV0, RXD0

-

1

40

400

-

4

ns

T^RxClk

MII0_RXCLK

TdRxClk

RXDV0,

RXD0[3:0]

55/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5.3.3

MII1 PHY Mode Timing

a. Transmit Timing Requirements

Symbol

Description

Min.

Typ.

Max.

Unit

T_TxClk

T_sTxClk

T_hTxClk

Transmit clock period 100M MII

Transmit clock period 10M MII

TXEN, TXD to MII1_TXCLK setup time

TXEN, TXD to MII1_TXCLK hold time

-

2

40

400

-

ns

0.5

T

TxClk

MII1_TXCLK

ThTxClk

TXEN1,

TXD1[3:0]

T^sTxClk

b. Receive Timing

Symbol

Description

Min.

Typ.

Max.

Unit

T_RxClk

T_dRxClk

Receive clock period 100M MII

Receive clock period 10M MII

MII1_RXCLK falling edge to RXDV1, RXD1

-

1

40

400

-

4

ns

T^RxClk

MII1_RXCLK

TdRxClk

RXDV1,

RXD1[3:0]

56/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5.3.4

a.

MII0 MAC Mode Timing

Receive Timing Requirements

Symbol

Description

Min.

Typ.

Max.

Unit

T_RxClk

T_sRxClk

T_hRxClk

Receive clock period 100M MII

Receive clock period 10M MII

RXDV, RXD to MII_RXCLK setup time

RXDV, RXD to MII_RXCLK hold time

-

2

40

400

-

ns

0.5

TRxClk

MII_RXCLK

ThRxClk

RXDV, RXD[3:0]

T^sRxClk

b.

Transmit Timing

Symbol

Description

Min.

Typ.

Max.

Unit

T_TxClk

T_dTxClk

Transmit clock period 100M MII

Transmit clock period 10M MII

MII_TXCLK rising edge to TXEN, TXD

-

1

40

400

-

4

ns

TTxClk

MII_TXCLK

TdTxClk

TXEN, TXD[3:0]

57/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5.3.5

a.

SMI Timing

MDC0/MDIO0 Timing

Symbol

Description

MDC0 High Time

MDC0 Low Time

MDC0 period

MDIO0 output delay

MDIO0 setup time

MDIO0 hold time

Min.

Typ.

Max.

Unit

T_ch

T_cl

T_cm

T_md

T_mh

T_ms

40

80

-

10

-

5

-

ns

M D C 0

T

m s

Tm h

M D IO 0

W rite C ycle

M D C 0

Tcl

Tch

Tm d

Tcm

M D IO 0

R ead C ycle

58/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

5.3.6

EEPROM Timing

a.

Symbol

Description

Receive clock period

SDA to SCL setup time

SDA to SCL hold time

Min.

Typ.

Max.

Unit

T_SCL

T_sSCL

T_hSCL

-

2

0.5

20480

-

ns

-

T

SCL

ThSCL

SDA

T^sSCL

Read data cycle

b.

Symbol

Description

Transmit clock period

SCL falling edge to SDA

Min.

Typ.

Max.

Unit

T_SCL

T_dSCL

-

20480

-

ns

5200

T^SCL

SCL

SDA

TdSCL

Comand cycle

6

Order Information

Part No.

IP175A

Package

Notice

-

128-PIN QFP

IP175A LF

Lead free

59/60

February 20, 2006

IP175A LF-DS-R08

IP175A LF

Preliminary Data Sheet

7

Package Detail

128 PQFP Outline Dimensions

H^D

D

103

128

102

1

65

38

39

64

e

b

GAGE

PLANE

L

L1

y

Dimensions In Inches

Min. Nom. Max.

0.010 0.014 0.018

0.107 0.112 0.117

0.007 0.009 0.011

0.004 0.006 0.008

0.669 0.677 0.685 17.00 17.20 17.40

0.547 0.551 0.555 13.90 14.00 14.10

0.906 0.913 0.921 23.00 23.20 23.40

0.783 0.787 0.791 19.90 20.00 20.10

Dimensions In mm

Note:

Symbol

Min.

0.25

Nom.

0.35

2.85

0.22

0.15

Max.

1. Dimension D & E do not include mold protrusion.

2. Dimension B does not include dambar protrusion.

Total in excess of the B dimension at maximum

material condition.

A1

A2

b

c

HD

D

0.45

2.97

0.27

0.20

2.73

0.17

0.09

Dambar cannot be located on the lower radius of

the foot.

HE

E

e

L

L1

y

-

0.020

-

0.50

0.88

1.60

-

0.025 0.035 0.041

-

0.65

-

1.03

-

0.10

12

0.063

-

0.004

12

0

-

IC Plus Corp.

Headquarters

Sales Office

10F, No.47, Lane 2, Kwang-Fu Road, Sec. 2,

Hsin-Chu City, Taiwan 300, R.O.C.

4F, No. 106, Hsin-Tai-Wu Road, Sec.1,

Hsi-Chih, Taipei Hsien, Taiwan 221, R.O.C.

TEL : 886-3-575-0275

FAX : 886-3-575-0475

TEL : 886-2-2696-1669

FAX : 886-2-2696-2220

Website: www.icplus.com.tw

60/60

February 20, 2006

IP175A LF-DS-R08


型号：	IP175ALF-DS-R03
厂家：	ETC
描述：	5 Port 10/100 Ethernet Integrated Switch 5端口10/100以太网交换机集成以太网局域网（LAN）标准
文件：	总60页 (文件大小：1518K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IP175ALF-DS-R03 [ETC]

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