IDT74LVC16540APA [ETC]
BUFFER/DRIVER|DUAL|8-BIT|LVC-CMOS|TSSOP|48PIN|PLASTIC ;
| 型号： | IDT74LVC16540APA |
| 厂家： | 
ETC |
| 描述： | BUFFER/DRIVER|DUAL|8-BIT|LVC-CMOS|TSSOP|48PIN|PLASTIC 驱动 |
| 文件： | 总6页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74LVC16540A
3.3V CMOS 16-BIT
BUFFER/DRIVER
WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
–
–
Typical tSK(0) (Output Skew) < 250ps
This 16-bit buffer driver is built using advanced dual metal CMOS
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
0.635mm pitch SSOP, 0.50mm pitch TSSOP
and 0.40mm pitch TVSOP packages
technology. The3-statecontrolgateis a2-inputANDgatewithactive-low
inputs so that if either output-enable (OE1 or OE2) input is high, all
correspondingoutputsareinthehigh-impedancestate.Toensurethehigh-
impedancestateduringpoweruporpowerdown,OEshouldbetiedtoVcc
througha pullupresistor;the minimumvalue ofthe resistoris determined
bythe current-sinkingcapabiltiyofthe driver.
–
–
–
–
–
–
–
Extended commercial range of -40°C to +85°C
VCC = 3.3V ±0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4µW typ. static)
All inputs, outputs and I/O are 5 Volt tolerant
Supports hot insertion
Allpins ofthis 16-bitbuffer/line drivercanbe drivenfromeither3.3Vor
5V devices. This feature allows the use of this device as a translator in a
mixed3.3V/5Vsupplysystem.
Drive Features for LVC16540A:
The LVC16540A has been designed with a ±24mA output driver. The
driver is capable of driving a moderate to heavy load while maintaining
speedperformance.
–
–
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
1
24
1OE1
2OE1
48
25
1OE2
2OE2
47
2
36
13
1Y1
2Y1
1A1
2A1
TO SEVEN OTHER CHANNELS
TO SEVEN OTHER CHANNELS
EXTENDED COMMERCIAL TEMPERATURE RANGE
OCTOBER 1999
1
c
1999 Integrated Device Technology, Inc.
DSC-4700/-
IDT74LVC16540A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
ABSOLUTE MAXIMUM RATINGS (1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Max.
Unit
V
Terminal Voltage with Respect to GND
Storage Temperature
– 0.5 to +6.5
– 65 to +150
1
2
48
47
46
45
44
1OE1
1Y1
1OE2
1A1
°C
IOUT
DC Output Current
– 50 to +50
– 50
mA
mA
3
IIK
Continuous Clamp Current,
VI < 0 or VO < 0
1Y2
1A2
IOK
ICC
GND
4
5
6
GND
1A3
Continuous Current through
±100
mA
ISS
each VCC or GND
1Y3
LVC Link
NOTE:
1Y4
1A4
43
42
41
40
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
VCC
7
VCC
1A5
8
1Y5
1Y6
9
1A6
GND
1A7
10
39
38
37
36
GND
1Y7
1Y8
2Y1
2Y2
CAPACITANCE (TA = +25OC, f = 1.0MHz)
11
12
13
14
15
16
17
18
SO48-1
SO48-2
SO48-3
Symbol
Parameter(1)
Conditions
Typ. Max. Unit
1A8
CIN
Input Capacitance
VIN = 0V
4.5
6.5
6
8
pF
2A1
COUT
CI/O
Output
Capacitance
I/O Port
VOUT = 0V
VIN = 0V
pF
35
34
2A2
6.5
8
pF
GND
GND
Capacitance
LVC Link
2A3
33
2Y3
2Y4
NOTE:
1. As applicable to the device type.
32
31
30
2A4
VCC
VCC
2A5
2Y5
2Y6
19
20
21
22
23
PIN DESCRIPTION
Pin Names
Description
29
28
27
26
25
2A6
xOEx
xAx
3–State Output Enable Inputs (Active LOW)
Data Inputs
GND
GND
2Y7
xYx
3-State Outputs
2A7
2A8
2Y8
FUNCTION TABLE (each 8-bit buffer) (1)
24
2OE1
2OE2
Inputs
xOE2
Outputs
xYx
xOE1
L
xAx
L
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
L
H
L
Z
Z
L
H
H
X
H
X
X
X
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
c 1998 Integrated Device Technology, Inc.
2
DSC-123456
IDT74LVC16540A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40OC to +85OC
Symbol
Parameter
Test Conditions
Min.
Typ.(1)
Max. Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V
1.7
—
—
—
V
2
—
—
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
—
—
—
0.7
0.8
±5
V
IIH
VI = 0 to 5.5V
µA
µA
IIL
IOZH
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
±10
IOZL
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
VCC = 2.3V, IIN = – 18mA
VCC = 3.3V
—
—
—
—
—
– 0.7
100
—
±50
– 1.2
—
µA
V
Input Hysteresis
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
10
(2)
—
—
—
—
10
3.6 ≤ VIN ≤ 5.5V
∆ICC
Quiescent Power Supply
Current Variation
One input at VCC - 0.6V
other inputs at VCC or GND
500
µA
LVC Link
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
Parameter
Output HIGH Voltage
Test Conditions(1)
Min.
Max.
Unit
VOH
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
VCC – 0.2
2
—
—
V
VCC = 2.3V
1.7
2.2
2.4
2.2
—
—
VCC = 2.7V
—
VCC = 3.0V
—
VCC = 3.0V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3.0V
—
—
LVC Link
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the
appropriate VCC range. TA = – 40°C to +85°C.
3
IDT74LVC16540A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
OPERATING CHARACTERISTICS, V
= 3.3V ± 0.3V, T = 25°C
CC
A
Symbol
Parameter
Test Conditions
CL = 0pF, f = 10Mhz
Typical
Unit
CPD
Power Dissipation Capacitance per buffer/driver Outputs enabled
Power Dissipation Capacitance per buffer/driver Outputs disabled
34
pF
CPD
2
pF
SWITCHING CHARACTERISTICS (1)
VCC = 2.7V
VCC = 3.3V±0.3V
Min.
Symbol
tPLH
Parameter
Min.
Max.
Max.
Unit
Propagation Delay
xAx to xYx
4.5
1
3.7
ns
tPHL
tPZH
Output Enable Time
xOEx to xYx
Output Disable Time
5.9
6.3
1.5
1.6
4.8
5.9
500
ns
tPZL
tPHZ
ns
ps
tPLZ
xOEx to xYx
(2)
tSK(o) Output Skew
NOTES:
1. See test circuits and waveforms. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC16540A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
TESTCIRCUITS ANDWAVEFORMS:
TESTCONDITIONS
PROPAGATIONDELAY
(1)
(1)
(2)
VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V
Symbol
Unit
VLOAD
6
6
2 xVcc
Vcc
V
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
VIH
VT
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
tPHL
tPHL
VCC / 2
150
tPLH
tPLH
VOH
VT
OUTPUT
VLZ
VHZ
CL
mV
mV
VOL
150
VIH
VT
0V
30
pF
LVC Link
OPPOSITE PHASE
INPUT TRANSITION
LVC Link
TEST CIRCUITS FOR ALL OUTPUTS
VLOAD
ENABLEANDDISABLETIMES
VCC
Open
GND
DISABLE
ENABLE
VIH
VT
500Ω
CONTROL
INPUT
VIN
VOUT
0V
Pulse (1, 2)
Generator
tPZL
tPLZ
D.U.T.
VLOAD/2
VT
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
500Ω
VOL+VLZ
VOL
RT
CL
tPHZ
tPZH
VOH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
LVC Link
VT
0V
VOH-VHZ
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
0V
RT = Termination resistance: should be equal to ZOUT of the Pulse
Generator.
LVC Link
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
SWITCHPOSITION
SET-UP, HOLD, AND RELEASE TIMES
Test
Switch
VIH
VT
0V
DATA
INPUT
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other tests
VLOAD
tSU
tH
VIH
VT
0V
TIMING
INPUT
GND
Open
tREM
VIH
VT
0V
ASYNCHRONOUS
CONTROL
LVC Link
VIH
VT
0V
SYNCHRONOUS
CONTROL
OUTPUT SKEW - tsk (x)
tSU
tH
LVC Link
VIH
VT
0V
INPUT
PULSEWIDTH
tPLH1
tPHL1
VOH
LOW-HIGH-LOW
PULSE
VT
VT
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
HIGH-LOW-HIGH
PULSE
VT
VOL
LVC Link
tPLH2
tPHL2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC16540A
EXTENDEDCOMMERCIALTEMPERATURERANGE
3.3VCMOS16-BITBUFFER/DRIVERWITH3-STATEOUTPUTS
ORDERINGINFORMATION
XX
X
XX
XXXX
XX
LVC
IDT
Device Type Package
Temp. Range
Bus-Hold
Family
Shrink Small Outline Package
Thin Shrink Small Outline Package
Thin Very Small Outline Package
PV
PA
PF
16-Bit Buffer/Driver with 3-State Outputs
Double-Density, ±24mA
540A
16
Blank No Bus-hold
74
-40°C to +85°C
CORPORATE HEADQUARTERS
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The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6
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