I1-1818A [ETC]
The Hl-1818A is a monolithic; HL- 1818A是一款单芯片
| 型号： | I1-1818A |
| 厂家： | 
ETC |
| 描述： | The Hl-1818A is a monolithic |
| 文件： | 总8页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HI-1818A
®
Data Sheet
November 19, 2004
FN3141.4
Low Resistance, Single 8-Channel, CMOS
Analog Multiplexer
Features
• Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+15V
• “ON” Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Ω
• Input Leakage (Max) . . . . . . . . . . . . . . . . . . . . . . . . .50nA
• Access Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350ns
• Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . .5mW
• DTL/TTL Compatible Address
The Hl-1818A is a monolithic, high performance CMOS
analog multiplexer offering built-in channel selection
decoding plus an inhibit (enable) input for disabling all
channels. Dielectric Isolation (Dl) processing is used for
enhanced reliability and performance. Substrate leakage
and parasitic capacitance are much lower, resulting in
extremely low static errors and high throughput rates. Low
output leakage (typically 0.1nA) and low channel ON
resistance (250Ω) assure optimum performance in low level
or current mode applications.
o
o
• Operation . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
Applications
The HI-1818A is a single-ended, 8-Channel multiplexer, and is
ideally suited for medical instrumentation, telemetry systems,
and microprocessor based data acquisition systems.
• Data Acquisition Systems
• Precision Instrumentation
• Demultiplexing
• Selector Switch
Ordering Information
TEMP.
PKG.
DWG. #
o
PART NUMBER RANGE ( C)
PACKAGE
HI1-1818A-2 -55 to 125 16 Ld CERDIP
F16.3
Pinout
HI-1818A (CERDIP)
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADDRESS A
ADDRESS A
0
1
+5V SUPPLY
ENABLE
-V
SUPPLY
+V
SUPPLY
ADDRESS A
IN 1
OUT
IN 2
IN 3
IN 4
2
IN 8
IN 7
IN 6
IN 5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002, 2004. All Rights Reserved
1
HI-1818A
Truth Table
HI-1818A TRUTH TABLE
HI-1818A TRUTH TABLE
ADDRESS
ADDRESS
A
A
A
EN
L
“ON” CHANNEL
A
A
A
0
EN
L
“ON” CHANNEL
2
1
0
2
1
L
L
L
1
2
3
4
5
H
L
H
6
7
L
L
L
H
H
L
H
L
L
H
H
X
H
H
X
L
H
X
L
L
L
8
L
H
L
L
H
None
H
L
Functional Block Diagram
HI-1818A
ENABLE
DIGITAL ADDRESS
A
A
A
2
0
1
ADDRESS
INPUT
BUFFERS
ENABLE
BUFFER
MULTIPLEX
SWITCHES
IN 1
N
P
DECODERS
OUT
IN 8
N
P
Schematic Diagrams
ADDRESS INPUT BUFFER
P3
P5
P1
N1
P4
V
CC
V+
A
D1
200Ω
All N-Channel Bodies to V-
All P-Channel Bodies to V+
Unless Otherwise Specified
P6 P7
N6 N7
P8
P9
N9
P10
N10
D2
ADDRESS
INPUT
N8
V-
P2
N2
N4
A
N5
N3
V-
FN3141.4
2
November 19, 2004
HI-1818A
Schematic Diagrams
ADDRESS DECODER
V+
EN
P11
P12
A2 OR
A2
A1 OR
A1
TO P-CHANNEL
SWITCH
All N-Channel Bodies to V-
All P-Channel Bodies to V+
P13
A0 OR
A0
P15
P16
N16
P14
N14
TO N-CHANNEL
SWITCH
N15
N11
N12
N13
V-
IN SWITCH CELL
MULTIPLEXER SWITCH
FROM DECODE
N18
V+
N17
All N-Channel Bodies to V-
All P-Channel Bodies to V+
Unless Otherwise Specified
IN
OUT
N19
V+
P17
P18
FROM DECODE
FN3141.4
November 19, 2004
3
HI-1818A
Absolute Maximum Ratings
Thermal Information
o
o
V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
Logic Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30V
Thermal Resistance (Typical, Note 1)
θ
( C/W)
θ
( C/W)
JA
JC
CERDIP Package. . . . . . . . . . . . . . . . .
Maximum Junction Temperature
80
20
Analog Signal (V , V
). . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V
IN OUT
o
Digital Input Voltage (V , V ) . . . . . . . . . . . . . . . . . . . . (V-) to (V+)
EN
A
Ceramic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 C
Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 C
o
o
o
Operating Conditions
o
o
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 C to 125 C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
JA
Electrical Specifications Supplies = +15V, -15V, +5V; V = 0.4V, V = 4.0V, Unless Otherwise Specified
AL
AH
o
PARAMETER
DYNAMIC CHARACTERISTICS
Access Time, t
TEST CONDITIONS TEMP ( C)
MIN
TYP
MAX
UNITS
Note 4
25
Full
25
-
-
-
-
-
-
-
-
-
-
-
-
-
350
-
500
ns
ns
ns
ns
ns
ns
ns
µs
µs
pF
pF
pF
pF
A
1000
Break-Before-Make Delay, t
25
300
-
-
OPEN
Enable Delay (ON), t
25
500
ON(EN)
Full
25
1000
Enable Delay (OFF), t
Settling Time
300
-
500
OFF(EN)
Full
25
1000
To 0.1%
To 0.025%
1.08
2.8
4
-
-
-
-
-
-
25
Channel Input Capacitance, C
25
S(OFF)
Channel Output Capacitance, C
25
20
0.6
5
D(OFF)
Input to Output Capacitance, C
25
DS(OFF)
Digital Input Capacitance, C
25
A
DIGITAL INPUT CHARACTERISTICS
Input Low Threshold, V
Full
Full
Full
-
4.0
-
-
-
-
0.4
-
V
V
AL
Input High Threshold, V
Note 3
AH
Input Leakage Current, I
1
µA
A
ANALOG CHANNEL CHARACTERISTICS
Analog Signal Range, V
Full
25
-15
-
+15
400
500
50
V
Ω
lN
ON Resistance, r
Note 2
-
-
-
-
-
250
ON
Full
Full
Full
Full
-
-
-
-
Ω
OFF Input Leakage Current, I
nA
nA
nA
S(OFF)
ON Channel Leakage Current, l
250
250
D(ON)
OFF Output Leakage Current, I
D(OFF)
FN3141.4
November 19, 2004
4
HI-1818A
Electrical Specifications Supplies = +15V, -15V, +5V; V = 0.4V, V = 4.0V, Unless Otherwise Specified (Continued)
AL
AH
o
PARAMETER
TEST CONDITIONS TEMP ( C)
MIN
TYP
MAX
UNITS
POWER SUPPLY CHARACTERISTICS
Power Dissipation, P
Current, I+
Full
Full
Full
Full
-
-
-
-
-
-
-
-
27.5
0.5
1
mW
mA
mA
mA
D
Current, I-
Current, I
NOTES:
1
L
±
2. V
OUT
= ±10V, I
=
1mA.
OUT
3. To drive from DTL/TTL circuits, 1kΩ pull-up resistors to 5.0V supply are recommended.
4. Time measured to 90% of final output level; V
= -5.0V to 5.0V, Digital Inputs = 0V to 4.0V.
OUT
Test Circuits and Waveforms
+15V -15V +5V
ENABLE DRIVE
2V/DIV.
V+ V-
V
L
A
A
A
2
1
0
+5V
IN 1
HI-1818A
V
= 4.0V
AH
ENABLE DRIVE
(V )
50%
IN 2-8
OUT
V
= 0V
AL
A
ENABLED
(S ON)
EN
1
OUTPUT
t
90%
ON
(EN)
OUTPUT
2V/DIV.
12.5
pF
50
Ω
200
Ω
DISABLED
V
A
10%
t
OFF
(EN)
100ns/DIV.
FIGURE 1B. TEST CIRCUIT
FIGURE 1A. MEASUREMENT POINTS
FIGURE 1C. WAVEFORMS
FIGURE 1. ENABLE DELAYS
+15V -15V +5V
V
INPUT
V+ V-
V
L
A
A
A
2
1
2V/DIV.
+5V
IN 1
4.0V
HI-1818A
IN 2
S
ON
S ON
2
1
EN
ADDRESS
DRIVE (V )
A
IN 3-8
OUT
0V
A
0
OUTPUT
1V/DIV.
12.5
pF
50
Ω
200
Ω
V
A
50%
50%
OUTPUT
t
OPEN
100ns/DIV.
FIGURE 2B. TEST CIRCUIT
FIGURE 2. BREAK-BEFORE-MAKE DELAY
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2C. WAVEFORMS
FN3141.4
November 19, 2004
5
HI-1818A
1mA
V
2
IN
A
OUT
OUT
V
V
2
V
IN
R
=
ON
1mA
350
300
250
60
40
20
0
o
-55 C
o
125 C
o
125 C
o
25 C
o
25 C
200
150
100
o
-55 C
-20
-40
-60
o
125 C
o
25 C
o
-55 C
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10 -8
-6
-4
-2
0
2
4
6
8
10
ANALOG INPUT (V)
VOLTAGE ACROSS SWITCH (V)
FIGURE 3. ON RESISTANCE vs ANALOG INPUT VOLTAGE
FIGURE 4. ON CHANNEL CURRENT vs VOLTAGE
ACCESS TIME TEST CIRCUIT
OFF LEAKAGE
EN
ON LEAKAGE
IN 1
+5V
4V
OUT
IN 2
OUT
OUT
10
-5V
I
D(OFF)
A
IN 3-8
I
EN
A
D(ON)
50pF
A
A
±10V
kΩ
1
0
+10V
HI-1818A
±10V
+10V
A
A
A
EN
0
1
2
0.4V
NOTE:
50Ω
0V TO 4V
OUT
4V
I
S(OFF)
Two measurements per channel:
±10V and 10V
±
A
EN
Two measurements per device for
±10V
+10V
±
I
: ±10V and 10V
D(OFF)
100nA
10nA
4V
A
INPUT
0
50%
2V/DIV.
I
- I
D(ON) D(OFF)
HI-1818A
1nA
100pA
10pA
+5V
I
S(OFF)
HI-1818A
OUTPUT
5V/DIV.
-5V
10%
t
A
25
50
75
TEMPERATURE ( C)
100
125
o
100ns/DIV.
FIGURE 5. LEAKAGE CURRENTS vs TEMPERATURE
FIGURE 6. ACCESS TIME
FN3141.4
6
November 19, 2004
HI-1818A
Die Characteristics
METALLIZATION:
PASSIVATION:
Type: Cu Al
Type: Nitride/Silox
Thickness: 16kÅ ±2kÅ
Thickness: Silox: 12kÅ ±2kÅ, Nitride: 3.5kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
5
2
1.43 x 10 A/cm at 25mA
Metallization Mask Layout
HI-1818A
A
0
V
A
1
L
-V
SUPPLY
EN
+V
A
2
SUPPLY
IN 1
OUTPUT
IN 8
IN 7
IN 6 IN 5
IN 4 IN 3 IN 2
FN3141.4
7
November 19, 2004
HI-1818A
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 LEAD FINISH
F16.3 MIL-STD-1835 GDIP1-T16 (D-2, CONFIGURATION A)
16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
-D-
E
-A-
INCHES
MIN
MILLIMETERS
BASE
(c)
METAL
SYMBOL
MAX
0.200
0.026
0.023
0.065
0.045
0.018
0.015
0.840
0.310
MIN
-
MAX
5.08
0.66
0.58
1.65
1.14
0.46
0.38
21.34
7.87
NOTES
b1
A
b
-
-
M
M
(b)
0.014
0.014
0.045
0.023
0.008
0.008
-
0.36
0.36
1.14
0.58
0.20
0.20
-
2
-B-
b1
b2
b3
c
3
SECTION A-A
bbb
C A - B
D
D
S
S
S
-
4
BASE
PLANE
Q
2
A
-C-
SEATING
PLANE
c1
D
3
L
α
5
S1
b2
eA
A A
e
E
0.220
5.59
5
b
C A - B
eA/2
aaa M C A - B S D S
c
e
0.100 BSC
2.54 BSC
-
eA
eA/2
L
0.300 BSC
0.150 BSC
7.62 BSC
3.81 BSC
-
ccc
D
S
M
S
-
NOTES:
0.125
0.200
0.060
-
3.18
5.08
1.52
-
-
1. Index area: A notch or a pin one identification mark shall be locat-
ed adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark.
Q
0.015
0.005
0.38
0.13
6
S1
7
o
o
o
o
90
105
90
105
-
α
aaa
bbb
ccc
M
2. The maximum limits of lead dimensions b and c or M shall be
measured at the centroid of the finished lead surfaces, when
solder dip or tin plate lead finish is applied.
-
-
-
-
0.015
0.030
0.010
0.0015
-
-
-
-
0.38
0.76
0.25
0.038
-
-
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness.
-
2, 3
8
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a
partial lead paddle. For this configuration dimension b3 replaces
dimension b2.
N
16
16
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN3141.4
8
November 19, 2004
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