HY628400ALT2-85 [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | HY628400ALT2-85 |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总9页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HY628400A Series
512Kx8bit CMOS SRAM
DESCRIPTION
FEATURES
The HY628400A is a high-speed, low power and
4M bits CMOS SRAM organized as 524,288
words by 8 bits. The HY628400A uses Hyundai's
high performance twin tub CMOS process
technology and was designed for high-speed and
low power circuit technology. It is particularly well
suited for use in high-density and low power
system applications. This device has a data
retention mode that guarantees data to remain
valid at the minimum power supply voltage of
2.0V.
·
·
·
·
Fully static operation and Tri-state outputs
TTL compatible inputs and outputs
Low power consumption
Battery backup(L/LL-part)
- 2.0V(min) data retention
Standard pin configuration
- 32pin 525mil SOP
·
- 32pin 400mil TSOP-II
(Standard and Reversed)
Product
No.
HY628400A
Voltage
(V)
Speed
(ns)
55/70/85
Operation
Current(mA)
10
Standby Current(uA)
Temperature
(°C)
0~70(Normal)
L
LL
30
5.0
100
Note 1. Normal : Normal Temperature
2. Current value are max.
PIN CONNECTION
A18
A16
A14
A12
A7
Vcc
32
A18
A16
A14
A12
A7
Vcc
A15
A17
/WE
A13
A8
Vcc
A15
A17
/WE
A13
A8
A18
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
1
2
A15
31
A16
A14
A12
A7
A17
30
3
3
3
/WE
29
4
4
4
A13
28
5
5
5
A8
27
A6
A6
A6
6
6
6
A5
A9
A5
A9
26
A9
A5
7
7
7
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A4
A11
25
A11
/OE
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
A4
A4
8
8
8
A3
/OE
24
A3
A3
9
9
9
A10
23
A2
A2
A2
10
11
12
13
14
15
16
10
11
12
13
14
15
16
10
11
12
13
14
15
16
/CS
22
A1
A1
A1
A0
A0
I/O8
21
A0
I/O1
I/O2
I/O3
Vss
I/O7
20
I/O1
I/O2
I/O3
Vss
I/O1
I/O2
I/O3
Vss
I/O6
19
I/O5
18
I/O4
17
SOP
TSOP-II(Standard)
TSOP-II(Reversed)
PIN DESCRIPTION
BLOCK DIAGRAM
ROW DECODER
I/O1
A0
Pin Name
Pin Function
/CS
Chip Select
Write Enable
/WE
MEMORY ARRAY
1024x4096
/OE
Output Enable
Address Input
Data Input/Output
Power(5.0V)
Ground
A0 ~ A18
I/O1 ~ I/O8
Vcc
A18
I/O8
/CS
/OE
/WE
Vss
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev.0 /Jan.99
Hyundai Semiconductor
HY628400A Series
ORDERING INFORMATION
Part No.
HY628400ALG
HY628400ALLG
HY628400ALT2
HY628400ALLT2
HY628400ALR2
HY628400ALLR2
Speed
55/70/85
Power
L-part
LL-part
L-part
LL-part
L-part
LL-part
Temp
Package
SOP
SOP
55/70/85
55/70/85
55/70/85
55/70/85
55/70/85
TSOP-II(Standard)
TSOP-II(Standard)
TSOP-II(Reversed)
TSOP-II(Reversed)
ABSOLUTE MAXIMUM RATING (1)
Symbol
Vcc, VIN, VOUT
TA
Parameter
Power Supply, Input/Output Voltage
Operating Temperature
Rating
-0.5 to 7.0
0 to 70
Unit
V
°C
Remark
HY628400A
TSTG
PD
Storage Temperature
Power Dissipation
-65 to 125
1.0
°C
W
TSOLDER
Lead Soldering Temperature & Time
260 · 10
°C·sec
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied.
Exposure to the absolute maximum rating conditions for extended period may affect reliablity.
RECOMMENDED DC OPERATING CONDITION
TA=0¡ Éto 70¡ É(Normal)
Symbol
Vcc
Vss
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5(1)
Typ.
5.0
0
-
-
Max.
5.5
0
Vcc+0.5
0.8
Unit
V
V
V
V
Note :
1. VIL = -3.0V for pulse width less than 30ns
TRUTH TABLE
/CS1 /WE /OE
MODE
Standby
Output Disabled High-Z
Read
Write
I/O OPERATION
High-Z
H
L
L
L
X
H
H
L
X
H
L
Data Out
Data In
X
Note :
1. H=VIH, L=VIL, X=don't care
Rev.0/Jan99
2
HY628400A Series
DC ELECTRICAL CHARACTERISTICS
Vcc = 5.0V ± 10%, TA = 0°C to 70°C (Normal) unless otherwise specified
Symbol
Parameter
Test Condition
Min Typ Max Unit
.
-1
-1
.
-
-
.
1
1
ILI
ILO
Input Leakage Current
Output Leakage Current
Vss < VIN < Vcc
uA
uA
Vss < VOUT < Vcc, /CS = VIH or
or /OE = VIH or /WE = VIL
/CS = VIL,
VIN = VIH or VIL, II/O = 0mA
/CS = VIL
Icc
Operating Power Supply
Current
Average Operating Current
-
-
5
10
80
mA
mA
ICC1
50
Min Duty Cycle = 100%, II/O =
0Ma
ISB
TTL Standby Current
(TTL Input)
/CS = VIH
-
0.4
2
mA
ISB1
Standby Current HY628400A
(CMOS Input)
Output Low Voltage
Output High Voltage
/CS > Vcc - 0.2V
L
LL
-
-
-
-
-
-
-
100
30
0.4
-
uA
uA
V
VOL
VOH
IOL = 2.1Ma
IOH = -1Ma
2.4
V
Note : Typical values are at Vcc = 5.0V, TA = 25°C
AC CHARACTERISTICS
Vcc = 5.0V ± 10%, TA = 0°C to 70°C (Normal) unless otherwise specified
-55
-70
Max. Min
-85
#
Symbol
Parameter
Unit
Min.
Max. Min.
Max.
READ CYCLE
1
2
3
4
5
6
7
8
9
tRC
tAA
tACS
tOE
tCLZ
tOLZ
tCHZ
tOHZ
tOH
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Deselecting to Output in High Z
Out Disable to Output in High Z
Output Hold from Address Change
55
-
-
-
10
5
0
0
10
-
70
-
-
-
10
5
0
0
10
-
85
-
-
-
10
5
0
0
10
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
55
55
25
-
70
70
35
-
85
85
45
-
-
-
-
20
20
-
25
25
-
30
30
-
WRITE CYCLE
10 tWC
11 tCW
12 tAW
13 tAS
14 tWP
15 tWR
16 tWHZ
17 tDW
18 tDH
19 tOW
Write Cycle Time
55
45
45
0
40
0
0
25
0
-
-
-
-
-
-
20
-
-
-
70
60
60
0
50
0
0
30
0
-
-
-
-
-
-
25
-
-
-
85
70
70
0
55
0
0
35
0
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Selection to End of Write
Address Valid to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
5
5
5
Rev.0/Jan99
3
HY628400A Series
AC TEST CONDITIONS
TA = 0°C to 70°C (Normal) unless otherwise specified
PARAMETER
Input Pulse Level
Value
0.8V to 2.4V
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load
5ns
1.5V
CL = 100pF + 1TTL Load
AC TEST LOADS
TTL
CL(1)
Note : Including jig and scope capacitance
CAPACITANCE
Temp = 25°C, f= 1.0MHz
Symbol
CIN
COUT
Parameter
Input Capacitance
Output Capacitance
Condition
VIN = 0V
VI/O = 0V
Max.
6
8
Unit
pF
pF
Note : This parameter is sampled and not 100% tested
Rev.0/Jan99
4
HY628400A Series
TIMING DIAGRAM
READ CYCLE 1
tRC
ADDR
OE
tAA
tOE
tOH
tOLZ
CS
tACS
tCLZ
tOHZ
tCHZ
High-Z
Data
Out
Data Valid
Note(READ CYCLE):
1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are
not referenced to output voltage levels
2. At any given temperature and voltage condition, tCHZ max. is less than tCLZ min. both for a given
device and from device to device.
3. /WE is high for the read cycle.
READ CYCLE 2
tRC
ADDR
tAA
tOH
tOH
Data
Out
Previous Data
Data Valid
Note(READ CYCLE):
1. /WE is high for the read cycle.
2. Device is continuously selected /CS = VIL
3. /OE =VIL.
Rev.0/Jan99
5
HY628400A Series
WRITE CYCLE 1(/OE Clocked)
tWC
ADDR
OE
tAW
tCW
CS
tAS
tWR
tWP
WE
tDW
tDH
Data Valid
Data In
tOHZ
Data
Out
WRITE CYCLE 2 (/OE Low Fixed)
tWC
ADDR
tAW
tCW
tWR
CS
tAS
tWP
WE
tDW
tDH
Data Valid
tOW
Data In
tWHZ
(8)
(7)
Data
Out
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and low /WE. A write begins at the latest transition among
/CS going low /WE going low: A write end at the earliest transition among /CS going high and /WE going
high. tWP is measured from the beginning of write to the end of write.
2. tCW is measured from the later of /CS going low to the end of write .
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state.
Inputs of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, the outputs remain in high impedance state.
7. Dout is the read data of the new address.
8. When /CS is low, I/O pins are in the output state. The input signals in the opposite phase
leading to the outputs should not be applied.
Rev.0/Jan99
6
HY628400A Series
Typ Max Unit
DATA RETENTION ELECTRIC CHARATERISTIC
TA=0°C to 70°C (Normal)
Symbol
VDR
Parameter
Vcc for Data Retention
Test Condition
/CS > Vcc - 0.2V
Vss<VIN<Vcc
Min
2.0
-
-
V
ICCDR
Data Retention
Current
HY628400A
Vcc = 3.0V,
/CS >Vcc - 0.2V
Vss<VIN<Vcc
L
LL
-
-
-
-
50
15
uA
uA
tCDR
tR
Chip Deselect to Data Retention Time
Operating Recovery Time
0
-
-
-
-
ns
ns
tRC(2)
Notes:
1. Typical values are at the comdition of TA = 25°C.
2. tRC is read cycle time.
DATA RETENTION TIMING DIAGRAM
DATA RETENTION MODE
VCC
4.5V
tCDR
tR
2.2V
VDR
CS>VCC-0.2V
CS
VSS
RELIABILITY SPEC.
TEST MODE
TEST SPEC.
ESD
HBM
MM
> 2000V
> 250V
LATCH - UP
< -100mA
> 100mA
Rev.0/Jan99
7
HY628400A Series
PACKAGE INFORMATION
32pin 400mil Thin Small Outline Package Standard(T2)
MAX.
0.404(10.2620)
0.396(10.0580()
UNIT : INCH(mm)
MIN.
0.470(11.9380)
0.462(11.7350)
0.829(21.0570)
0.822(20.8790)
GAGE PLANE
BASE PLANE
0-5
0.0235(0.5970)
0.0160(0.4060)
0.050BSC
(1.2700)
0.017(0.4500)
0.012(0.3050)
SEATING PLANE
0.0059(0.1500)
0.0020(0.0500)
0.0083(0.2100)
0.0047(0.1200)
0.047(1.1940)
0.039(0.9910)
32pin 400mil Thin Small Outline Package Reversed(R2)
MAX.
0.404(10.2620)
0.396(10.0580)
UNIT : INCH(mm)
MIN.
0.470(11.9380)
0.462(11.7350)
0.829(21.0570)
0.822(20.8790)
GAGE PLANE
BASE PLANE
0-5
0.0235(0.5970)
0.0160(0.4060)
0.0083(0.2100)
0.0047(0.1200)
0.050 BSC
(1.2700)
0.017(0.4500)
0.012(0.3050)
SEATING PLANE
0.0059(0.1500)
0.0020(0.0500)
0.047(1.1940)
0.039(0.9910)
Rev.0/Jan99
8
HY628400A Series
32pin 525mil Small Outline Package(G)
UNIT : INCH(mm)
0.444(11.278)
0.438(11.125)
0.564(14.326)
0.810(20.574)
0.804(20.422)
0.546(13.868)
0.109(2.769)
0.0125(0.318)
0.0061(0.155)
0.099(2.515)
0.011(0.279)
0.004(0.102)
0 deg
8 deg
0.0425(1.080)
0.0235(0.597)
0.020(0.508)
0.014(0.356)
0.050(1.27)BSC
Rev.0/Jan99
9
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