HT9032C(16SOP) [ETC]
Telecomm/Datacomm ; 电信/数据通信\n
| 型号： | HT9032C(16SOP) |
| 厂家： | 
ETC |
| 描述： | Telecomm/Datacomm
|
| 文件： | 总14页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HT9032C/HT9032D
Calling Line Identification Receiver
Features
·
·
Operating voltage: 3.5V~5.5V
Power down mode
·
·
Bell 202 FSK and V.23 demodulation
High input sensitivity
·
·
Ring detection input and output
HT9032C: 16-pin DIP/SOP package
HT9032D: 8-pin DIP/SOP package
·
Carrier detection output
Applications
·
·
Feature phones
Computer telephony interface products
·
·
Caller ID adjunct boxes
ADSI products
·
Fax and answering machines
General Description
The HT9032 calling line identification receiver is a low
power CMOS integrated circuit designed for receiving
physical layer signals transmitted according to Bellcore
TR-NWT-000030 and ITU-T V.23 specifications. The
primary application of this device is for products used to
receive and display the calling number, or message
waiting indicator sent to subscribers from the central of-
fice facilities. The device also provides a carrier detec-
tion circuit and a ring detection circuit for easier system
applications.
Block Diagram
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Rev. 1.40
1
September 30, 2002
HT9032C/HT9032D
Pin Assignment
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6
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A
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8
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A
Pin Description
Pin Name
Power Inputs
VDD
I/O
Description
Power-VDD is the input power for the internal logic.
Ground-VSS is ground connection for the internal logic.
¾
¾
VSS
A logic ²1² on this pin puts the chip in power down mode. When a logic ²0² is on this pin, the
PDWN
Clock
X1
I
chip in power up mode. This is a Schmitt trigger input.
A crystal or ceramic resonator should be connected to this pin and X2.
This pin may be driven from an external clock source.
I
X2
O
A crystal or ceramic resonator should be connected to this pin and X1.
Ring Detections
It detects ring energy on the line through an attenuating network and enables the oscillator and
ring detection. This is a Schmitt trigger input.
RDET1
RDET2
I
It couples the ring signal to the precision ring detector through an attenuating network.
I
RDET=²0² if a valid ring signal is detected. This is a Schmitt trigger input.
An RC network may be connected to this pin in order to hold the pin voltage below 2.2V be-
tween the peaks of the ringing signal. This pin controls internal power up and activates the par-
tial circuitry needed to determine whether the incoming ring is valid or not. The input is a
Schmitt trigger input. The output cell structure is an NMOS output.
RTIME
I/O
FSK Signal Inputs
This input pin is connected to the tip side of the twisted pair wires. It is internally biased to 1/2
TIP
I
I
V
DD when the device is in power up mode. This pin must be DC isolated from the line.
This input pin is connected to the ring side of the twisted pair wires. It is internally biased to 1/2
DD when the device is in power up mode. This pin must be DC isolated from the line.
RING
V
Detection Results
This open drain output goes low when a valid ringing signal is detected. When connected to
PDWN pin, this pin can be used for auto power up.
RDET
CDET
O
O
This open drain output goes low indicating that a valid carrier is present on the line. A hyster-
esis is built-in to allow for a momentary drop out of the carrier. When connected to PDWN pin,
this pin can be used for auto power up.
This pin presents the output of the demodulator when chip in power up mode. This data stream
includes the alternate ²1² and ²0² pattern, the marking, and the data. At all other times, this pin
is held high.
DOUT
O
O
This output presents the output of the demodulator when chip in power up mode and when an
internal validation sequence has been successfully passed. This data stream does not include
the alternate ²1² and ²0² pattern. This pin is always held high.
DOUTC
TEST
NC
O
Output pin for testing purposes only.
No connection
¾
Rev. 1.40
2
September 30, 2002
HT9032C/HT9032D
Absolute Maximum Ratings
Voltages are referenced to VSS, except where noted.
Supply Voltage .........................................-0.5V to 6.0V
Operating Temperature Range ...................0°C to 70°C
All Input Voltages.................................................25mW
Storage Temperature Range ................-40°C to 150°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Crystal=3.58MHz, Ta=0~70°C
Test Conditions
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
VDD
IDD1
Supply Voltage
Supply Current
3.5
5
5.5
5
V
¾
¾
5V PDWN=0 (3.58MHz OSC on)
3.2
mA
¾
PDWN=1 and RTIME=0
5V (3.58MHz OSC on and internal
circuits partially on)
IDD2
Supply Current
Standby Current
1.9
2.5
1
mA
¾
¾
PDWN=1 and RTIME=1
5V
ISTBY
¾
mA
(3.58MHz OSC off)
VIL
VIH
IOL
IOH
IIN
VDD
VDD
VDD
VDD
Input Voltage Logic 0
Input Voltage Logic 1
Output Voltage Logic 0
Output Voltage Logic 1
5V
5V
5V
5V
0.2V
¾
¾
¾
¾
0.8V
¾
¾
¾
IOL=1.6mA
IOH=0.8mA
0.1V
¾
0.9V
¾
¾
1
Input Leakage Current, All Inputs 5V
¾
-1
2.0
2.5
1.0
¾
¾
mA
V
VT-
VT+
Input Low Threshold Voltage
Input High Threshold Voltage
5V RDET1, RTIME, PDWN
5V RDET1, RTIME, PDWN
5V RDET2
2.3
2.75
1.1
500
2.6
3.0
1.2
¾
V
VTRDET2 Input Threshold Voltage
RIN
V
Input DC Resistance
5V TIP, RING
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Rev. 1.40
3
September 30, 2002
HT9032C/HT9032D
A.C. Characteristics - FSK Detection
VSS=0V, Crystal=3.58MHz, Ta=0 to 70°C, 0dBm=0.7746Vrms @ 600W
Test Conditions
Conditions
Symbol
Parameter
Min. Typ. Max. Unit
VDD
5V
Input Sensitivity: TIP, RING
Signal to Noise Ratio
dBm
dB
-40 -45
¾
¾
S/N
5V
20
¾
Band Pass Filter
60Hz
-64
-4
Frequency Response
550Hz
5V
dB
¾
¾
Relative to 1700Hz @ 0dBm
2700Hz
-3
3300Hz
-34
Carrier Detect Sensitivity
Oscillator Start Up Time
5V
5V
dBm
ms
¾
¾
15
¾
8
-48
2
¾
¾
¾
¾
¾
tDOSC
tSUPD
tDAQ
¾
¾
¾
¾
Power Up to FSK Signal Set Up Time 5V
ms
¾
14
¾
Carrier Detect Acquisition Time
5V
5V
ms
tDCH
End of Data to Carrier Detect High
ms
2
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Rev. 1.40
4
September 30, 2002
HT9032C/HT9032D
Functional Description
·
·
The HT9032 is designed to be the physical layer de-
modulator for products targeted for the caller ID market.
The data signaling interface should conform to Bell 202,
which is described as follows:
Logical 0 (Space)=2100Hz
Transmission rate=1200bps
Since the band pass filter of the HT9032 can pass the
V.23 signal, hence the HT9032 also can demodulate the
V.23 signal.
·
·
·
·
·
Analog, phase coherent, frequency shift keying
Logical 1 (Mark)=1200+/-12Hz
Ring detection
Logical 0 (Space)=2200+/-22Hz
The data will be transmitted in the silent period between
the first and second power ring before a voice path is es-
tablished. The HT9032 should first detect a valid ring
and then perform the FSK demodulation. The typical
ring detection circuit of the HT9032 is depicted below.
The power ring signal is first rectified through a bridge
circuit and then sent to a resistor network that attenu-
ates the incoming power ring. The values of resistors
and capacitor given in the figure have been chosen to
provide a sufficient voltage at RDET1 pin to turn on the
Schmitt trigger input with approximately a 40 Vrms or
greater power ring input from tip and ring. When VT+ of
the Schmitt is exceeded, the NMOS on the pin RTIME
will be driven to saturation discharging capacitor on
RTIME. This will initialize a partial power up, with only
the portions of the part involved with the ring signal anal-
ysis enabled, including RDET2 pin. With RDET2 pin en-
abled, a portion of the power ring above 1.2V is fed to
the ring analysis circuit. Once the ring signal is qualified,
the RDET pin will be sent low.
Transmission rate=1200bps
Data application=serial, binary, asynchronous
The interface should be arranged to allow simple data
transmission from the terminating central office, to the
CPE (Customer Premises Equipment), only when the
CPE is in an on-hook state. The data will be transmitted
in the silent period between the first and second power
ring before a voice path is established. The transmission
level from the terminating C.O. will be -13.5dBm+/-1.0.
The worst case attenuation through the loop is expected
to be -20dB. The receiver therefore, should have a sen-
sitivity of approximately -34.5dBm to handle the worst
case installations. The ITU-T V.23 is also using the FSK
signaling scheme to transmit data in the general
switched telephone network. For mode 2 of the V.23, the
modulation rate and characteristic frequencies are listed
below:
·
Analog, phase coherent, frequency shift keying
·
Logical 1 (Mark)=1300Hz
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0
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2
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1
.
2
V
Operation mode
There are three operation modes of the HT9032. They are power down mode, partial power up mode, and power up
mode. The three modes are classified by the following conditions:
Modes
Conditions
PDWN=²1² and RTIME=²1²
PDWN=²1² and RTIME=²0²
PDWN=²0²
Current Consumption
Power down
<1mA
Partial power up
Power up
1.9mA typically
3.2mA typically
Rev. 1.40
5
September 30, 2002
HT9032C/HT9032D
Normally, the PDWN pin and the RTIME pin control the
operation mode of the HT9032. When both pins are
HIGH, the HT9032 is set at the power down mode, con-
suming less than 1mA of supply current. When a valid
power ring arrives, the RTIME pin will be driven below
VT- and the portions of the part involved in the ring signal
analysis are enabled. This is partial power up mode,
consuming approximately 1.9mA typically. Once the
PDWN pin is below VT-, the part will be fully powered up,
and ready to receive FSK. During this mode, the device
current will increase to approximately 3.2mA (typ). The
state of the RTIME pin is now a ²don¢t care² as far as the
part is concerned. After the FSK message has been re-
ceived, the PDWN pin can be allowed to return to VDD
and the part will return to the power down mode.
Application Circuits
Application circuit 1
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~
~
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1
0
5
0
0
.
0
1
m
ꢀ
2
0
0
k
9
V
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0 . 1 ꢀ
4
7
0
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m
0 . 2 ꢀ
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0
.
0
1
m
ꢀ
2
0
0
k
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1
5
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1
2
3
1
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0
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D
3
0
p
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3
0
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Application circuit 2
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0 . 2 ꢀ
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~
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1
0
5
0
0
.
0
1
m
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2
0
0
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9
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m
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7
0
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m
0 . 2 ꢀ
2
0
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2
0
k
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2
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5
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1
2
3
1
.
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0
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0
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2
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0
p
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p
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Rev. 1.40
6
September 30, 2002
HT9032C/HT9032D
Application circuit 3 ¾ power on reset
T
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D D
m
0 . 2 ꢀ
~
~
H
T
1
0
5
0
0
.
0
1
m
ꢀ
2
0
0
k
9
V
m
0 . 1 ꢀ
4
7
0
k
m
0 . 2 ꢀ
R
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0
.
0
1
m
ꢀ
2
0
0
k
W
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1
8
k
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1
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5
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1
2
3
1
.
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1
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0
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3
2
D
3
0
p
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3
0
p
ꢀ
Application circuit 4 ¾ power on reset
T
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m
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~
~
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1
0
5
0
0
.
0
1
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0
k
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0
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2
3
1
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5
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2
7
0
k
S
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0
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0
3
2
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m
0 . 2 ꢀ
3
0
p
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p
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Note: reference C1=0.1mF R1=81kW
Rev. 1.40
7
September 30, 2002
HT9032C/HT9032D
Package Information
8-pin DIP (300mil) outline dimensions
A
8
5
B
1
4
H
C
D
I
a
G
E
ꢀ
Dimensions in mil
Nom.
Symbol
Min.
355
240
125
125
16
Max.
375
260
135
145
20
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
50
70
¾
100
¾
¾
¾
295
335
0°
315
375
15°
¾
a
¾
Rev. 1.40
8
September 30, 2002
HT9032C/HT9032D
16-pin DIP (300mil) outline dimensions
A
1
6
9
8
B
1
H
C
D
a
G
E
I
ꢀ
Dimensions in mil
Nom.
Symbol
Min.
745
240
125
125
16
Max.
775
260
135
145
20
A
B
C
D
E
F
G
H
I
¾
¾
¾
¾
¾
50
70
¾
100
¾
¾
¾
295
335
0°
315
375
15°
¾
a
¾
Rev. 1.40
9
September 30, 2002
HT9032C/HT9032D
8-pin SOP (150mil) outline dimensions
8
1
5
A
B
4
C
C
'
G
H
D
a
E
ꢀ
Dimensions in mil
Nom.
Symbol
Min.
228
149
14
189
53
¾
Max.
244
157
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
197
69
¾
4
10
G
H
a
22
4
28
12
0°
10°
Rev. 1.40
10
September 30, 2002
HT9032C/HT9032D
16-pin SOP (300mil) outline dimensions
1
6
9
A
B
1
8
C
C
'
G
H
D
a
E
ꢀ
Dimensions in mil
Nom.
Symbol
Min.
394
290
14
390
92
¾
Max.
419
300
20
A
B
C
C¢
D
E
F
¾
¾
¾
¾
¾
50
¾
¾
¾
¾
413
104
¾
4
¾
G
H
a
32
4
38
12
0°
10°
Rev. 1.40
11
September 30, 2002
HT9032C/HT9032D
Product Tape and Reel Specifications
Reel dimensions
D
T
2
C
A
B
T
1
SOP 8N
Symbol
Description
Dimensions in mm
A
B
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
330±1.0
62±1.5
C
12.75+0.15
2.0±0.15
12.4+0.2
16.8-0.4
D
T1
T2
Space Between Flange
Reel Thickness
SOP 16W
Symbol
Description
Dimensions in mm
330±3.0
A
B
C
D
Reel Outer Diameter
Reel Inner Diameter
Spindle Hole Diameter
Key Slit Width
100±2.0
13.0±0.5
2.0+0.5
16.4+0.3
-0.2
T1
T2
Space Between Flange
Reel Thickness
22.4+0.4
Rev. 1.40
12
September 30, 2002
HT9032C/HT9032D
Carrier tape dimensions
P
0
P
1
t
D
E
ꢀ
W
B
0
C
D
1
P
K
0
A
0
SOP 8N
Symbol
Description
Dimensions in mm
12.0+0.3
-0.1
W
Carrier Tape Width
P
E
Cavity Pitch
8.0±0.1
1.75±0.1
5.5±0.1
1.55±0.1
1.5+0.25
4.0±0.1
2.0±0.1
6.4±0.1
5.20±0.1
2.1±0.1
0.3±0.05
9.3
Perforation Position
F
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
D
D1
P0
P1
A0
B0
K0
t
Cavity to Perforation (Length Direction)
Cavity Length
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
C
SOP 16W
Symbol
Description
Carrier Tape Width
Dimensions in mm
16.0±0.2
12.0±0.1
1.75±0.1
7.5±0.1
W
P
Cavity Pitch
E
Perforation Position
Cavity to Perforation (Width Direction)
Perforation Diameter
Cavity Hole Diameter
Perforation Pitch
F
D
1.5+0.1
D1
P0
P1
A0
B0
K0
t
1.5+0.25
4.0±0.1
Cavity to Perforation (Length Direction)
Cavity Length
2.0±0.1
10.9±0.1
10.8±0.1
3.0±0.1
Cavity Width
Cavity Depth
Carrier Tape Thickness
Cover Tape Width
0.3±0.05
13.3
C
Rev. 1.40
13
September 30, 2002
HT9032C/HT9032D
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2002 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.40
14
September 30, 2002
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