HM62V256LT-8SL [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | HM62V256LT-8SL |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总17页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HM62V256 Series
256 k SRAM (32-kword × 8-bit)
ADE-203-136F (Z)
Rev. 6.0
Nov. 1997
Features
•
Low voltage operation SRAM
Operating Supply Voltage: 2.7 V to 3.6 V
•
•
0.8 µm Hi-CMOS process
High speed
Access time: 70/85/100 ns (max)
Low power
•
•
•
Standby: 0.15 µW (typ)
Completely static memory
No clock or timing strobe required
Directly LVTTL compatible: All inputs and outputs
Ordering Information
Type No.
Access Time
Package
HM62V256LFP-10T
100 ns
450 mil 280 pin plastic SOP (FP-28DA)
HM62V256LFP-7SLT
HM62V256LFP-10SLT
70 ns
100 ns
HM62V256LFP-8ULT
HM62V256LT-10
85 ns
100 ns
85 ns
8 mm × 14 mm 32 pin TSOP (normal type) (TFP-32DA)
8 mm × 13.4 mm 28-pin TSOP (normal type) (TFP-28DA)
HM62V256LT-8SL
HM62V256LTM-10
100 ns
HM62V256LTM-7SL
HM62V256LTM-10SL
70 ns
100 ns
HM62V256LTM-8UL
85 ns
HM62V256 Series
Pin Arrangement
HM62V256LT Series
HM62V256LFPSeries
OE
A11
NC
A9
A10
CS
1
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A14
A12
A7
2
2
NC
3
3
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A0
4
A8
5
4
A6
A13
WE
VCC
A14
A12
A7
6
5
A9
A5
7
8
6
A11
OE
A10
A4
9
7
A3
10
11
12
13
14
15
16
8
A2
A6
A5
9
CS
A1
NC
A4
NC
10
11
12
13
14
I/O7
I/O6
I/O5
I/O4
I/O3
A0
A1
I/O0
I/O1
I/O2
VSS
A3
A2
(Top view)
HM62V256LTM Series
A10
CS
OE
A11
A9
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
(Top view)
I/O7
I/O6
I/O5
I/O4
I/O3
A8
A13
WE
V
CC
V
A14
A12
A7
SS
I/O2
I/O1
I/O0
A0
2
3
A6
4
A5
5
A1
A2
A4
6
A3
7
8
(Top view)
Pin Description
Pin name
A0 to A14
I/O0 to I/O7
CS
Function
Address inputs
Data input/output
Chip select
WE
Write enable
Output enable
No connection
Power supply
Ground
OE
NC
VCC
VSS
2
HM62V256 Series
Block Diagram
V CC
V SS
(MSB) A12
A5
•
•
•
•
•
•
•
A7
•
•
•
Memory Matrix
A6
Row
Decoder
×
512 512
A8
A13
A14
A4
(LSB) A3
I/O0
•
•
•
•
Column I/O
•
•
•
•
•
•
Input
Data
Control
Column Decoder
•
•
•
•
•
•
•
•
•
I/O7
A1 A0 A10 A9 A11
A2
(LSB)
(MSB)
•
•
Timing Pulse Generator
Read/Write Control
CS
WE
OE
3
HM62V256 Series
Function Table
WE
X
CS
H
L
OE
X
Mode
VCC Current
I/O Pin
High-Z
High-Z
Dout
Ref. Cycle
—
Not selected
Output disable
Read
ISB, ISB1
ICC
H
H
L
—
H
L
ICC
Read cycle (1)–(3)
Write cycle (1)
Write cycle (2)
L
L
H
L
Write
ICC
Din
L
L
Write
ICC
Din
Note: X: H or L
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
V
Power supply voltage*1
Terminal voltage*1
VCC
–0.5 to 4.6
–0.5*2 to VCC+0.5*3
1.0
VT
V
Power dissipation
PT
W
Operating temperature
Storage temperature
Storage temperature under bias
Notes: 1. Relative to VSS
Topr
Tstg
Tbias
0 to + 70
°C
°C
°C
–55 to +125
–10 to +85
2. VT min: –3.0 V for pulse half-width ≤ 50 ns
3. Maximum voltage is 4.6V
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter
Symbol
VCC
Min
2.7
Typ
3.0
0
Max
Unit
V
Supply voltage
3.6
VSS
0
0
V
Input high(logic 1) voltage
Input low(logic 0) voltage
VIH
0.7VCC
–0.3 *1
—
VCC+0.3
0.2VCC
V
VIL
—
V
Note: 1. VT min: –3.0 V for pulse half-width ≤ 50 ns
4
HM62V256 Series
DC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6V, VSS = 0 V)
Parameter
Symbol Min
Typ*1 Max Unit Test conditions
Input leakage current
Output leakage current
|ILI|
—
—
—
—
1
1
µA
µA
VSS ≤ Vin ≤ VCC
|ILO|
CS = VIH or OE = VIH or WE = VIL,
VSS ≤ VI/O ≤ VCC
Operating power supply current
(DC)
ICCDC1
ICCDC2
—
—
—
—
—
—
15
10
30
mA
mA
mA
CS = VIL, others = V /VIL
IH
II/O = 0 mA
CS ≤ 0.2 V, VIH ≥ VCC – 0.2 V,
VIL ≤ 0.2 V, II/O = 0 mA
Average
HM62V256-7 ICCAC1
min cycle, duty = 100 %,
operating power
supply current
II/O = 0 mA CS = VIL,
others = VIH/VIL
HM62V256-8 ICCAC1
HM62V256-10 ICCAC1
ICCAC2
—
—
—
—
—
—
27
24
15
mA
Cycle time ≥ 1 µs, duty = 100%
II/O = 0 mA, CS ≤ 0.2 V,
VIH ≥ VCC – 0.2 V, VIL ≤ 0.2 V
Standby power supply current
ISB
—
—
—
—
—
0.1
1
mA
CS = VIH
ISB1
0.05 50
0.05 10*2
0.05 4*3
µA
Vin ≥ 0 V, CS ≥ VCC – 0.2 V,
Output low voltage
Output high voltage
VOL
VOH
—
0.2
—
V
V
IOL = 20 µA
VCC – 0.2 —
IOH = –20 µA
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
2. This characteristic is guaranteed only for L-SL version.
3. This characteristic is guaranteed only for L-UL version.
Capacitance (Ta = 25°C, f = 1.0 MHz)
Parameter
Symbol
Cin
Min
—
Typ
—
Max
5
Unit
pF
Test Conditions
Vin = 0 V
Input capacitance*1
Input/output capacitance*1
CI/O
—
—
8
pF
VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
5
HM62V256 Series
AC Characteristics (Ta = 0 to +70°C, VCC = 2.7 V to 3.6 V, unless otherwise noted.)
Test Conditions
•
•
•
Input pulse levels: 0.4 V to 2.4 V
Input rise and fall time: 5 ns
Input and output timing reference level: 1.4 V
Output Load
500Ω
Dout
1.4 V
50 pF*
(Including scope & jig)
Read Cycle
HM62V256
-7
-8
-10
Parameter
Symbol Min
Max Min
Max Min
Max Unit Notes
Read cycle time
tRC
70
—
—
—
10
5
—
70
70
35
—
—
25
25
—
85
—
—
—
10
5
—
85
85
45
—
—
30
30
—
100
—
—
—
10
5
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
100
100
50
—
Chip select access time
tACS
tOE
Output enable to output valid
Chip selection to output in low-Z
Output enable to output in low-Z
Chip deselection to output in high-Z
Output disable to output in high-Z
Output hold from address change
tCLZ
tOLZ
tCHZ
tOHZ
tOH
2
—
2
0
0
0
35
35
—
1, 2
1, 2
0
0
0
10
10
10
Notes: 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
6
HM62V256 Series
Read Timing Waveform (1) (WE = VIH)
Error! Unknown switch argument.
Read Timing Waveform (2) (WE = VIH, CS = VIL, OE = VIL)
t
RC
Valid address
Address
Dout
t
t
AA
OH
t
OH
Valid data
Read Timing Waveform (3) (WE = VIH, OE = VIL)*1
t
ACS
CS
t
CLZ
t
CHZ
High impedance
Valid data
Dout
Notes:
1. Address must be valid prior to or simultaneously with CS going low.
7
HM62V256 Series
Write Cycle
HM62V256
-7
-8
-10
Parameter
Symbol Min
Max Min
Max Min
Max Unit Notes
Write cycle time
tWC
tCW
tAS
70
50
0
—
—
—
—
—
—
25
—
—
—
25
85
75
0
—
—
—
—
—
—
30
—
—
—
30
100
80
0
—
—
—
—
—
—
35
—
—
—
35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip selection to end of write
Address setup time
4
5
Address valid to end of write
Write pulse width
tAW
tWP
tWR
tWHZ
tDW
tDH
50
45
0
75
55
0
80
60
0
3, 8
6
Write recovery time
Write to output in high-Z
Data to write time overlap
Data hold from write time
Output active from end of write
Output disable to output in high-Z
0
0
0
1, 2, 7
30
0
35
0
40
0
tOW
tOHZ
10
0
10
0
10
0
2
1, 2, 7
Notes: 1. tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. A write occurs during the overlap (tWP) of a low CS and a low WE. A write begins at the
later transition of CS going low or WE going low. A write ends at the earlier transition of CS
going high or WE going high. tWP is measured from the beginning of write to the end of write.
4. tCW is measured from CS going low to the end of write.
5. tAS is measured from the address valid to the beginning of write.
6. tWR is measured from the earlier of WE or CS going high to the end of write cycle.
7. During this period, I/O pins are in the output state so that the input signals of the opposite phase
to the outputs must not be applied.
8. In the write cycle with OE low fixed, tWP must satisfy the following equation to avoid a problem of
data bus contention, tWP ≥ tWHZ max + tDW min.
8
HM62V256 Series
Write Timing Waveform (1) (OE Clock)
tWC
Address
Valid address
tAW
tWR
OE
tCW
CS
*1
tWP
tAS
WE
tOHZ
High impedance
tDW
Dout
tDH
High impedance
Din
Valid data
Notes:
1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain
in the high impedance state.
9
HM62V256 Series
Write Timing Waveform (2) (OE Low Fixed)
tWC
Address
Valid address
tCW
tWR
CS
*1
tAW
tOH
tWP
WE
tAS
tWHZ
tOW
*3
*2
Dout
tDW
tDH
*4
High impedance
Din
Valid data
Notes:
1. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain
in the high impedance state.
2. Dout is the same phase of the write data of this write cycle.
3. Dout is the read data of next address.
4. If CS is low during this period, I/O pins are in the output state. Therefore, the input signals
of the opposite phase to the output must not be applied to them.
10
HM62V256 Series
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
Parameter
Symbol
VDR
Min
2.0
—
Typ*1 Max Unit Test conditions*6
VCC for data retention
Data retention current
—
3.6
V
CS ≥ VCC – 0.2 V, Vin ≥ 0 V
ICCDR
0.05 27*2
µA
VCC = 2.7 V, Vin ≥ 0 V
CS ≥ VCC – 0.2 V
—
—
0
0.05 7*3
0.05 2*4
Chip deselect to data retention time
Operation recovery time
tCDR
tR
—
—
—
—
ns
ns
See retention waveform
*5
tRC
Notes: 1. Typical values are at VCC = 2.7 V, Ta = 25°C and not guaranteed.
2. 9 µA max at Ta = 0 to 40°C.
3. This characteristics guaranteed for only L-SL version. 2.0 µA max at Ta = 0 to 40°C.
4. This characteristics guaranteed for only L-UL version. 0.4 µA max at Ta = 0 to 40°C.
5. tRC = read cycle time.
6. CS controls address buffer, WE buffer, OE buffer, and Din buffer. If CS controls data retention
mode, other input levels (address, WE, OE, I/O) can be in the high impedance state.
Low VCC Data Retention Timing Waveform
Data retention mode
VCC
2.7 V
tR
tCDR
0.7 V
CC
VDR
CS
>
CS VCC – 0.2 V
0 V
11
HM62V256 Series
Package Dimensions
HM62V256LFP Series (FP-28DA)
Unit: mm
18.00
18.75 Max
15
28
1
14
11.80 ± 0.30
1.12 Max
1.70
0° – 8°
1.27
1.00 ± 0.20
0.15
0.40 ± 0.08
0.38 ± 0.06
M
0.20
Hitachi Code
FP-28DA
JEDEC
EIAJ
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.82 g
12
HM62V256 Series
Package Dimensions (cont.)
HM62V256LT Series (TFP-32DA)
Unit: mm
8.00
8.20 Max
17
32
1
16
0.50
0.22 ± 0.08
0.20 ± 0.06
0.08
M
0.80
14.00 ± 0.20
0.45 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
JEDEC
EIAJ
TFP-32DA
Conforms
Conforms
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.26 g
13
HM62V256 Series
Package Dimensions (cont.)
HM62V256LTM Series (TFP-28DA)
Unit: mm
8.00
8.20 Max
8
21
22
7
28
1
0.55
0.22 ± 0.05
0.20 ± 0.04
0.10 M
0.80
13.40 ± 0.30
0.63 Max
0° – 5°
0.50 ± 0.10
0.10
Hitachi Code
TFP-28DA
JEDEC
EIAJ
—
—
Dimension including the plating thickness
Base material dimension
Weight (reference value) 0.22 g
14
HM62V256 Series
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company.
Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1897
U S A
Hitachi Europe GmbH
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 01628-585000
Fax: 01628-585160
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Tel: 800-285-1601
Fax:303-297-0447
Tel: 089-9 91 80-0
Fax: 089-9 29 30-00
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
Copyright © Hitachi, Ltd., 1997. All rights reserved. Printed in Japan.
15
HM62V256 Series
Revision Record
Rev. Date
Contents of Modification
Drawn by Approved by
1.0
2.0
3.0
Dec. 25, 1992
Initial issue
Y. Saito
Y. Saito
Y. Saito
Y. Kawashima
K. Yoshizaki
T. Matumoto
Sep. 10, 1993
Mar. 17, 1994
Addition of full specification
DC Characteristics
I
CCDR2 (max): 10 mA to 15 mA
4.0
Nov. 17 1994
Jun. 19, 1995
Addition of HM62V256LTM Series (TFP-28DA)
Addition of Block Diagram
Absolute maximum ratings
Addition of note 3
AC Characteristics
Addition of note 12
Y. Saito
K. Yoshizaki
5.0
Change of format
M. Higuchi K. Yoshizaki
Features
Access time: 85/100 ns to 70/85/100 ns
Low power standby: 0.60 µW to 0.15 µW
Deletion of HM62V256LFP-8/8SL
Deletion of HM62V256LT-8/10SL
Deletion of HM62V256LTM-8/8SL
Addition of HM62V256LFP-7SLT/8ULT
Addition of HM62V256LTM-7SL/8UL
Change of Block Diagram
Absolute Maximum Ratings
Terminal voltage VT: –0.5 to VCC + 0.3 to
Terminal voltage VT: –0.5 to VCC + 0.5
DC Characteristics
Addition of note 3
t
I
I
CCAC1 (min): 27/24 mA to 30/ 27/ 24 mA
SB1 (typ): 0.2/0.2 µA to 0.05/0.05/0.05 µA
SB1 (max): 50/10 µA to 50/10/4 µA
Capacitance
Input Capacitance
Cin (max): 8 pF to 5 pF
Input/output Capacitance
CI/O (max): 10 pF to 8 pF
AC Characteristics
Change order of notes
t
RC (min): 85/100 ns to 70/85/100 ns
tAA (max): 85/100 ns to 70/85/100 ns
t
t
t
t
t
ASC (max): 85/100 ns to 70/85/100 ns
OE (max): 45/50 ns to 35/45/50 ns
CLZ (min): 10/10 ns to 10/10/10 ns
OLZ (min): 5/5 ns to 5/5/5 ns
CHZ (max): 30/35 ns to 25/30/35 ns
tOHZ (max): 30/35 ns to 25/30/35 ns
tOH (min): 10/10 ns to 10/10/10 ns
t
t
t
WC (min): 85/100 ns to 70/85/100 ns
CW (min): 75/80 ns to 50/75/80 ns
AW (min): 75/80 ns to 50/75/80 ns
16
HM62V256 Series
Revision Record (cont)
Rev. Date
5.0 Jun. 19, 1995
Contents of Modification
Drawn by Approved by
AC Characteristics
M. Higuchi K. Yoshizaki
tWP (min): 55/60 ns to 45/55/60 ns
t
t
WHZ (max): 30/35 ns to 25/30/35 ns
DW (min): 35/40 ns to 30/35/40 ns
tOW (min): 10/10 ns to 10/10/10 ns
tOHZ (max): 30 35 ns to 25/30/35 ns
Low VCC Data Retention Characteristics
Addition of note 4
t
t
CCDR (typ): 0.2/0.2 µA to 0.05/0.05/0.05 µA
CCDR (max): 27/7 µA to 27/7/2 µA
6.0
Nov. 1997
Change of format
Change of Subtitle
17
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