GVT71256B36T-7 [ETC]
x36 Synchronous SRAM ; X36同步SRAM\n
| 型号： | GVT71256B36T-7 |
| 厂家： | 
ETC |
| 描述： | x36 Synchronous SRAM
|
| 文件： | 总27页 (文件大小：301K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM
and a 2-bit counter for internal burst operation. All synchro-
Features
nous inputs are gated by registers controlled by a positive-
edge-triggered Clock Input (CLK). The synchronous inputs in-
clude all addresses, all data inputs, address-pipelining Chip
• Fast access times: 6.0, 6.5, 7.0, and 8.0 ns
• Fast clock speed: 150, 133, 117, and 100 MHz
• 1 ns set up time and hold time
• Fast OE access times: 3.5 ns and 4.0 ns
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
Enable (CE), depth-expansion Chip Enables (CE and CE ),
2
2
Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables
(BWa, BWb, BWc, BWd, and BWE), and Global Write (GW).
However, the CE chip enable input is only available for
2
TA(GVTI)/A(CY) package version.
• 5V tolerant inputs except I/Os
Asynchronous inputs include the Output Enable (OE) and
burst mode control (MODE). The data outputs (Q), enabled by
OE, are also asynchronous.
• Clamp diodes to V at all inputs and outputs
SS
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa. BWb controls DQb. BWc controls DQc. BWd
controls DQd. BWa, BWb, BWc, and BWd can be active only
with BWE being LOW. GW being LOW causes all bytes to be
written. The x18 version only has 18 data inputs/outputs (DQa
and DQb) along with BWa and BWb (no BWc, BWd, DQc, and
DQd).
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mmx 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
Functional Description
The Cypress Synchronous Burst SRAM family employs high-
speed, low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The GVT71256B36/CY7C1361A and GVT71512B18/
CY7C1363A SRAMs integrate 262,144x36 and 524,288x18
SRAM cells with advanced synchronous peripheral circuitry
The GVT71256B36 and GVT71512B18 operate from a +3.3V
power supply. All inputs and outputs are LVTTL compatible.
Selection Guide
7C1361A-150
7C1361A-133
7C1363A-133
71256B36-6.5
71512B18-6.5
7C1361A-117
7C1363A-117
71256B36-7
71512B18-7
7C1361A-100
7C1363A-100
71256B36-8
71512B18-8
7C1363A-150
71256B36-6
71512B18-6
Maximum Access Time (ns)
6.0
400
10
6.5
360
10
7.0
320
10
8.0
270
10
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
May 17, 2000
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 (CY7C1361A/GVT71256B36) Functional Block Diagram[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
BWd#
D
Q
Q
ENABLE
CE#
CE2
[2]CE2#
D
OE#
ZZ
Power Down Logic
Input
Register
ADSP#
16
A
Address
Register
ADSC#
DQa,DQb
DQc,DQd
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
512K x 18 (CY7C1363A/GVT71512B18)Functional Block Diagram
BYTE b
WRITE
BWb#
BWE#
D
Q
BYTE a
WRITE
BWa#
GW#
D
Q
ENABLE
CE#
CE2
D
Q
[2]CE2#
ZZ
Power Down Logic
OE#
ADSP#
Input
Register
17
A
Address
Register
ADSC#
DQa,D
Qb
CLR
ADV#
A1-A0
MODE
Binary
Counter
& Logic
Notes:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions, and timing diagrams for detailed information.
2. CE2 is for AJ/TA version only.
2
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Pin Configurations
CY7C1361A/GVT71256B36
256Kx36 100-Pin TQFP
T(AJ) Package Version
TA(A) Package Version
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
NC
VCC
NC
100-pin TQFP
TA version
100-pin TQFP
VCC
ZZ
VCC
ZZ
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CY7C1363A/GVT71512B18
TA(A) Package Version
512Kx18 100-Pin TQFP
T(AJ) Package Version
10
0
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
1
2
3
4
5
6
7
8
9
80
NC
NC
NC
VCCQ
VSS
NC
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
NC
NC
NC
VCCQ
VSS
NC
A
NC
NC
VCCQ
VSS
NC
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
VSS
NC
2
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
4
5
6
NC
7
NC
8
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
DQb
DQb
VSS
VCCQ
DQb
DQb
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VCC
NC
VCC
NC
100-pin TQFP
TA version
100-pin TQFP
VCC
ZZ
VCC
ZZ
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
VSS
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
NC
VSS
VCCQ
NC
NC
NC
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
DQa
DQa
VCCQ
VSS
DQa
DQa
NC
NC
NC
VSS
VCCQ
NC
NC
NC
VSS
VCCQ
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Pin Configurations (continued)
CY7C1361A/GVT71256B36
256Kx36 119-Ball BGA
Top View
1
2
A
3
A
A
A
4
5
A
A
A
6
7
A
B
C
D
E
F
V
ADSP
ADSC
A
V
CCQ
CCQ
NC
NC
CE
A
A
NC
NC
2
V
A
CC
DQc
DQc
DQc
DQc
DQc
DQc
DQc
V
NC
CE
V
DQb
DQb
DQb
DQb
DQb
DQb
DQb
SS
SS
SS
SS
SS
SS
V
V
V
V
V
OE
V
CCQ
CCQ
G
H
J
DQc
BWc
ADV
GW
BWb
DQb
DQc
V
V
DQb
SS
SS
V
V
NC
V
NC
V
V
CCQ
CCQ
CC
CC
CC
K
L
DQd
DQd
DQd
DQd
DQd
DQd
A
V
CLK
NC
V
DQa
DQa
DQa
DQa
DQa
A
DQa
SS
SS
DQd
BWd
BWa
DQa
M
N
P
R
T
V
V
V
V
BWE
A1
V
V
V
V
CCQ
CCQ
SS
SS
SS
SS
SS
SS
DQd
DQa
DQd
NC
A0
DQa
NC
ZZ
MODE
A
V
NC
A
CC
NC
NC
A
NC
U
V
TMS
TDI
TCK
TDO
NC
V
CCQ
CCQ
CY7C1361A/GVT71256B36
512Kx18 119-Ball BGA
Top View
1
2
A
3
A
A
A
4
5
A
A
A
6
A
7
A
B
C
D
E
F
V
ADSP
ADSC
V
CCQ
CCQ
NC
NC
CE
A
A
NC
NC
2
V
A
CC
DQb
NC
NC
DQb
NC
V
NC
CE
V
DQa
NC
DQa
NC
DQa
NC
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
DQa
V
OE
V
CCQ
CCQ
G
H
J
NC
DQb
NC
BWb
ADV
GW
DQa
DQb
V
NC
SS
V
V
NC
V
NC
V
V
CCQ
CCQ
CC
CC
CC
K
L
NC
DQb
NC
DQb
NC
DQb
A
V
V
V
V
V
CLK
NC
V
NC
DQa
NC
DQa
NC
A
DQa
SS
SS
SS
SS
SS
SS
DQb
BWa
NC
M
N
P
R
T
V
BWE
A1
V
V
V
V
CCQ
CCQ
SS
SS
SS
DQb
NC
NC
NC
NC
A0
DQa
NC
ZZ
MODE
A
V
NC
A
CC
A
A
A
U
V
TMS
TDI
TCK
TDO
NC
V
CCQ
CCQ
4
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions
Pin
x36 PBGA Pins x36 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the set-
Synchronous up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C, 100, 99, 82, 81,
35, 34, 33, 32,
3C, 5C, 6C, 2R,
6R, 3T, 4T, 5T
44, 45, 46, 47,
48, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
5L
5G
3G
3L
93
94
95
96
BWa
Input-
Byte Write: A byte write is LOW for a WRITE cycle and HIGH for
BWb Synchronous a READ cycle. BWa controls DQa. BWb controls DQb. BWc con-
BWc
BWd
trols DQc. BWd controls DQd. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being LOW.
4M
4H
4K
87
88
89
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set-up and hold times around the rising edge
of CLK.
GW
Input-
Global Write: This active LOW input allows a full 36-bit WRITE to
Synchronous occur independent of the BWE and BWn lines and must meet the
set up and hold times around the rising edge of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All syn-
chronous inputs must meet set up and hold times around the
clock’s rising edge.
4E
2B
98
97
CE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
CE
CE
Input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
2
2
(not available for
PBGA)
92 (for AJ/TA
version only)
Input-
Chip Enable: This active LOW input is used to enable the device.
Synchronous Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and
a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device
Synchronous to be deselected or selected along with new external address to
be registered. A READ or WRITE cycle is initiated depending
upon write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. A NC or HIGH on this pin selects interleaved
burst.
Input-
Asynchro-
nous
Snooze: This active HIGH input puts the device in low power
consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
5
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
256K x 36 Pin Descriptions (continued)
Pin
x36 PBGA Pins x36 QFP Pins Name
Type
Description
(a) 6P, 7P, 7N,
6N, 6M, 6L, 7L,
6K, 7K,
(b) 7H, 6H, 7G,
6G, 6F, 6E, 7E,
7D, 6D,
(a) 51, 52, 53,
56, 57, 58, 59,
62, 63
(b) 68, 69, 72,
73, 74, 75, 78,
79, 80
DQa
DQb
DQc
DQd
Input/
Output
Data Inputs/Outputs: First Byte is DQa. Second Byte is DQb.
Third Byte is DQc. Fourth Byte is DQd. Input data must meet set
up and hold times around the rising edge of CLK.
(c) 2D, 1D, 1E,
2E, 2F, 1G, 2G,
1H, 2H,
(d) 1K, 2K, 1L,
2L, 2M, 1N, 2N,
1P, 2P
(c) 1, 2, 3, 6, 7,
8, 9, 12, 13
(d) 18, 19, 22,
23, 24, 25, 28,
29, 30
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for
AJ/TA package version.
for BG/B and
A/T version
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for
AJ/TA package version.
for BG/B and
A/T version
4C, 2J, 4J, 6J,
4R
15, 41,65, 91
V
V
Supply
Ground
Core power Supply: +3.3V –5% and +10%
CC
3D, 5D, 3E, 5E,
3F, 5F, 3H, 5H,
3K, 5K, 3M, 5M,
3N, 5N, 3P, 5P
5, 10, 17, 21,
26, 40, 55, 60,
67, 71, 76, 90
Ground: GND.
SS
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
4, 11, 20, 27,
54, 61, 70, 77
V
I/O Supply
-
Output Buffer Supply: +2.5V or +3.3V.
CCQ
1B, 7B, 1C, 7C,
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 6U
14, 16, 66
NC
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V or V
.
CC
SS
38, 39, 42 for
AJ/TA Version
512K X 18 Pin Descriptions
Pin
x18 PBGA Pins X18 QFP Pins Name
Type
Description
4P
4N
37
36
A0
A1
A
Input-
Addresses: These inputs are registered and must meet the set
Synchronous up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and A1,
during burst cycle and wait cycle.
2A, 3A, 5A, 6A,
3B, 5B, 6B, 2C, 100, 99, 82, 81,
35, 34, 33, 32,
3C, 5C, 6C, 2R,
6R, 2T, 3T, 5T,
6T
80, 48, 47, 46,
45, 44, 49, 50
92 (A/T version)
43 (AJ/TA ver-
sion)
5L
3G
93
94
BWa
Input-
Byte Write Enables: A byte writeenable isLOW fora WRITE cycle
BWb Synchronous and HIGH for a READ cycle. BWa controls DQa. BWb controls
DQb. Data I/O are high impedance if either of these inputs are
LOW, conditioned by BWE being LOW.
4M
87
BWE
Input-
Write Enable: This active LOW input gates byte write operations
Synchronous and must meet the set up and hold times around the rising edge
of CLK.
6
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
512K X 18 Pin Descriptions (continued)
Pin
x18 PBGA Pins X18 QFP Pins Name
Type
Description
4H
88
GW
Input-
Global Write: This active LOW input allows a full 18-bit WRITE to
Synchronous occur independent of the BWE# and WEn# lines and must meet
the set up and hold times around the rising edge of CLK.
4K
89
CLK
Input-
Clock: This signal registers the addresses, data, chip enables,
Synchronous write control and burst control inputs on its rising edge. All syn-
chronous inputs must meet set up and hold times around the
clock’s rising edge.
4E
2B
98
97
CE
Input-
Chip Enable: This active LOW input is used to enable the device
Synchronous and to gate ADSP.
CE
CE
input-
Synchronous
Chip Enable: This active HIGH input is used to enable the device.
Chip Elnable: This active LOW input is used to enable the device.
2
2
(not available for
PBGA)
92 (for AJ/TA
Version only)
input-
Synchronous Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables the
data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
4B
84
85
ADSP
ADSC
Input-
Address Status Processor: This active LOW input, along with CE
Synchronous being LOW, causes a new external address to be registered and
a READ cycle is initiated using the new address.
Input-
Address Status Controller: This active LOW input causes device
Synchronous to be deselected or selected along with new external address to
be registered. A READ or WRITE cycle is initiated depending
upon write control inputs.
3R
7T
31
64
MODE
ZZ
Input-
Static
Mode: This input selects the burst sequence. A LOW on this pin
selects linear burst. A NC or HIGH on this pin selects interleaved
burst.
Input-Asyn- Snooze: This active HIGH input puts the device in low power
chronous
consumption standby mode. For normal operation, this input has
to be either LOW or NC (No Connect).
(a) 6D, 7E, 6F,
7G, 6H, 7K, 6L,
6N, 7P
(a) 58, 59, 62,
63, 68, 69, 72,
73, 74
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input
data must meet setup and hold times around the rising edge of
CLK.
(b) 1D, 2E, 2G, (b) 8, 9, 12, 13,
1H, 2K, 1L, 2M, 18, 19, 22, 23,
1N, 2P
24
2U
3U
4U
38
39
43
TMS
TDI
TCK
Input
IEEE 1149.1 Test Inputs. LVTTL-level inputs. Not available for
AJ/TA package version.
for B and T ver-
sion
5U
42
for B and T ver-
sion
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. Not available for
AJ/TA package version.
4C, 2J, 4J, 6J,
4R
15, 41,65, 91
V
V
Supply
Ground
Core power Supply: +3.3V –5% and +10%
CC
3D, 5D, 3E, 5E,
3F, 5F, 5G, 3H,
5H, 3K, 5K, 3L,
3M, 5M, 3N, 5N,
3P, 5P
5, 10, 17, 21,
26, 40, 55, 60,
67, 71, 76, 90
Ground: GND.
SS
7
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
512K X 18 Pin Descriptions (continued)
Pin
x18 PBGA Pins X18 QFP Pins Name
Type
Description
1A, 7A, 1F, 7F,
1J, 7J, 1M, 7M,
1U, 7U
4, 11, 20, 27,
54, 61, 70, 77
V
I/O Supply
Output Buffer Supply: +2.5V or +3.3V.
CCQ
1B, 7B, 1C, 7C, 1-3, 6, 7, 14, 16,
NC
-
No Connect: These signals are not internally connected. User
can leave it floating or connect it to V or V
2D, 4D, 7D, 1E,
6E, 2F, 1G, 6G,
2H, 7H, 3J, 5J,
1K, 6K, 2L, 4L,
7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R,
7R, 1T, 4T, 6U
25, 28-30, 51-
53, 56, 57, 66,
75, 78, 79, 80,
95, 96
.
SS
CC
38, 39, 42 for
AJ/TA version
Burst Address Table (MODE = NC/V
)
Burst Address Table (MODE = GND)
CC
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A00
A...A01
A...A10
A...A11
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A11
A...A00
A...A01
A...A10
8
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Truth Table[3, 4, 5, 6, 7, 8, 9]
Address
Used
Operation
CE
H
L
CE
X
X
H
X
H
L
CE
X
L
ADSP ADSC ADV WRITE OE CLK
DQ
2
2
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
Deselected Cycle, Power Down
READ Cycle, Begin Burst
None
None
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
L
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
X
L
L
None
L
H
H
L
None
L
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
L
External
External
External
External
External
Next
L
X
X
L
L-H
Q
READ Cycle, Begin Burst
L
L
L
H
X
L
L-H High-Z
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L-H
L-H
D
Q
L
L
L
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L
L
L
H
L
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
H
H
X
H
X
X
H
H
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
Q
Next
L
H
L
Next
L
Q
Next
L
H
X
X
L
Next
L
L-H
L-H
L-H
D
D
Q
Next
L
L
Current
Current
Current
Current
Current
Current
H
H
H
H
H
H
H
H
H
H
L
H
L
L-H High-Z
L-H
L-H High-Z
Q
H
X
X
L-H
L-H
D
D
H
X
X
L
Partial Truth Table for Read/Write[10]
FUNCTION
GW
BWE
BWa
BWb
BWc
BWd
READ
READ
H
H
H
H
L
H
L
L
L
X
X
H
L
X
H
H
L
X
H
H
L
X
H
H
L
WRITE one byte
WRITE all bytes
WRITE all bytes
L
X
X
X
X
Notes:
3. X = “Don’t Care.” H = logic HIGH. L = logic LOW.
For x36 product, WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
For x18 product, WRITE = L means [BWE + BWa*BWb]*GW equals LOW. WRITE = H means [BWE + BWa*BWb]*GW equals HIGH.
4. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
5. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
6. Suspending burst generates wait cycle.
7. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
8. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
9. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
10. For X18 product, There are only BWa and BWb.
9
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Performing a TAP Reset
IEEE 1149.1 Serial Boundary Scan (JTAG)
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
Overview
This device incorporates a Serial Boundary Scan Access Port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modi-
fied or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Stan-
dard 1149.1 compliant TAPs. The TAP operates using
LVTTL/LVCMOS logic level signaling.
performed for the TAP controller by forcing TMS HIGH (V
)
CC
for five rising edges of TCK and pre-loads the instruction reg-
ister with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (V ) to pre-
SS
vent clocking the device. TDI and TMS are internally pulled up
and may be unconnected. They may alternately be pulled up
Instruction Register
to V
through a resistor. TDO should be left unconnected.
CC
The instruction register holds the instructions that are execut-
ed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruc-
tion upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Cap-
ture-IR state, the two least significant bits of the serial instruc-
tion register are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK - Test Clock (Input)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS - Test Mode Select (Input)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
TDI - Test Data In (Input)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruc-
tion that is currently loaded in the TAP instruction register (refer
to Figure 1, TAP Controller State Diagram). It is allowable to
leave this pin unconnected if it is not used in an application.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI is connected to the most significant bit (MSB) of any reg-
ister. (See Figure 2.)
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the con-
trol of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the con-
troller is moved to Shift-DR state. The EXTEST, SAM-
PLE/PRELOAD and SAMPLE-Z instructions can be used to
capture the contents of the I/O ring.
TDO - Test Data Out (Output)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO. TDO is connected to the least significant
bit (LSB) of any register. (See Figure 2.)
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s posi-
tion in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name, the third column is the TQFP pin
number, and the fourth column is the PBGA bump number.
10
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Identification (ID) Register
ture-DR mode and places the ID register between the TDI and
TDO pins in Shift-DR mode. The IDCODE instruction is the
default instruction loaded in the instruction upon power-up and
at any time the TAP controller is placed in the test-logic reset
state.
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
TAP Controller Instruction Set
SAMPLE/PRELOAD
Overview
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
There are two classes of instructions defined in the IEEE Stan-
dard 1149.1-1990; the standard (public) instructions and de-
vice specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
When the SAMPLE/PRELOAD instruction is loaded in the in-
struction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, IN-
TEST, or the preload portion of the SAMPLE/PRELOAD com-
mand.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the in-
struction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
controller’s capture setup plus hold time (t
plus t ). The
CS
CH
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
Moving the controller to Shift-DR state then places the bound-
ary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction reg-
ister has the same effect as the Pause-DR command.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
BYPASS
When the BYPASS instruction is loaded in the instruction reg-
ister and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instruc-
tions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
Reserved
Do not use these instructions. They are reserved for future
use.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in Cap-
11
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
TEST-LOGIC
RESET
1
0
0
1
1
1
REUN-TEST/
IDLE
SELECT
SELECT
DR-SCAN
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
0
1
1
EXIT1-DR
0
1
EXIT1-IR
0
1
0
0
PAUSE-DR
1
PAUSE-IR
1
0
0
EXIT2-DR
1
EXIT2-IR
1
UPDATE-DR
UPDATE-IR
1
1
0
0
[11]
Figure 1. TAP Controller State Diagram
Note:
11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
12
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
0
Bypass Register
Selection
Circuitry
Selection
Circuitry
TDO
2
1
0
TDI
Instruction Register
29
Identification Register
31 30
.
.
2
1
1
0
0
.
x
.
.
.
2
[12]
Boundary Scan Register
TDI
TDI
TAP Controller
Figure 2. TAP Controller Block Diagram
TAP Electrical Characteristics (20°C < T < 110°C; V = 3.3V –0.2V and +0.3V unless otherwise noted)
j
CC
Parameter
Description
Test Conditions
Min.
2.0
Max.
V + 0.3
CC
Unit
V
[13, 14]
V
V
Input High (Logic 1) Voltage
IH
Il
[13, 14]
Input Low (Logic 0) Voltage
Input Leakage Current
–0.3
–5.0
–30
–5.0
0.8
5.0
30
V
IL
0V < V < V
µA
µA
µA
I
IN
CC
CC
IL
TMS and TDI input Leakage Current
Output Leakage Current
0V < V < V
IN
I
IL
Output disabled,
0V < V < V
5.0
O
IN
CCQ
[13, 15]
V
LVCMOS Output Low Voltage
I
I
I
I
= 100 µA
0.2
0.4
V
V
V
V
OLC
OLC
OHC
OLT
[13, 15]
V
LVCMOS Output High Voltage
= 100 µA
= 8.0 mA
= 8.0 mA
V
– 0.2
CC
OHC
[13]
V
LVTTL Output Low Voltage
OLT
[13]
V
LVTTL Output High Voltage
2.4
OHT
OHT
Notes:
12. X = 69 for the x36 configuration;
X = 50 for the x18 configuration.
13. All Voltage referenced to VSS (GND).
14. Overshoot: VIH(AC)<VDD+1.5V for t<tKHKH/2, Undershoot:VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<+3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
15. This parameter is sampled.
13
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
[16, 17]
TAP AC Switching Characteristics Over the Operating Range
Parameter
Clock
Description
Min.
Max.
Unit
t
f
t
t
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
20
ns
MHz
ns
THTH
TF
50
8
8
THTL
TLTH
ns
Output Times
t
t
t
t
TCK LOW to TDO Unknown
TCK LOW to TDO Valid
TDI Valid to TCK HIGH
TCK HIGH to TDI Invalid
0
ns
ns
ns
ns
TLQX
TLQV
DVTH
THDX
10
5
5
Set-up Times
t
t
TMS Set-Up
5
5
ns
ns
MVTH
CS
Capture Set-Up
Hold Times
t
t
TMS Hold
5
5
ns
ns
THMX
Capture Hold
CH
Notes:
16. CS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions.
t
14
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
TAP Timing and Test Conditions
1.5V
50
Ω
ALL INPUT PULSES
TDO
3.0V
Z =50
Ω
0
1.5V
=20 pF
C
L
VSS
1.5 ns
1.5 ns
GND
(a)
t
t
THTL
TLTH
t
THTH
TEST CLOCK
(TCK)
t
t
MV T H
T HM X
TEST MODE SELECT
(TMS)
t
t
DVTH
THDX
TEST DATA IN
(TDI)
t
TLQV
t
TLQX
TEST DATA OUT
(TDO)
15
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Identification Register Definitions
Instruction Field
256K x 36
512K x 18
Description
REVISION NUMBER
(31:28)
XXXX
XXXX
Reserved for revision number.
DEVICE DEPTH
(27:23)
00110
00111
00011
Defines depth of 256K or 512K words.
Defines width of x36 or x18 bits.
DEVICE WIDTH
(22:18)
00100
RESERVED
(17:12)
XXXXXX
00011100100
1
XXXXXX
00011100100
1
Reserved for future use.
CYPRESS JEDEC ID CODE
(11:1)
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
ID Register Presence Indicator (0)
Scan Register Sizes
Register Name
Instruction
Bit Size (x36)
Bit Size (x18)
3
1
3
1
Bypass
ID
32
70
32
51
Boundary Scan
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
010
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
100
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
RESERVED
BYPASS
101
110
111
Do not use these instructions; they are reserved for future use.
Do not use these instructions; they are reserved for future use.
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
16
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Boundary Scan Order (256K x 36)
Boundary Scan Order (256K x 36)
Signal
Name
Signal
Bit#
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
TQFP
92
93
94
95
96
97
98
99
100
1
Bump ID
6B
5L
Bit#
1
Name
TQFP
44
45
46
47
48
49
50
51
52
53
56
57
58
59
62
63
64
68
69
72
73
74
75
78
79
80
81
82
83
84
85
86
87
88
89
Bump ID
2R
3T
A
A
BWa
BWb
BWc
BWd
2
A
5G
3G
3L
3
A
4T
4
A
5T
5
A
6R
3B
5B
6P
7N
6M
7L
CE
2
2B
4E
3A
2A
2D
1E
2F
6
A
CE
A
7
A
8
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
ZZ
A
9
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
2
3
6K
7P
6N
6L
6
1G
2H
1D
2E
2G
1H
5R
2K
1L
7
8
9
7K
7T
12
13
14
18
19
22
23
24
25
28
29
30
31
32
33
34
35
36
37
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
A
6H
7G
6F
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
MODE
A
7E
6D
7H
6G
6E
7D
6A
5A
4G
4A
4B
4F
2M
1N
2P
1K
2L
2N
1P
3R
2C
3C
5C
6C
4N
4P
A
ADV
ADSP
ADSC
OE
A
A
A
BWE
GW
CLK
4M
4H
4K
A1
A0
17
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Boundary Scan Order (512K x 18)
Boundary Scan Order (512K x 18)
Signal
Name
Signal
Bit#
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
TQFP
89
92
93
94
97
98
99
100
8
Bump ID
4K
Bit#
1
Name
TQFP
44
45
46
47
48
49
50
58
59
62
63
64
68
69
72
73
74
80
81
82
83
84
85
86
87
88
Bump ID
2R
2T
CLK
A
A
6B
2
A
BWa
BWb
5L
3
A
3T
3G
2B
4
A
5T
CE
5
A
6R
3B
5B
7P
6N
6L
2
CE
A
4E
6
A
3A
7
A
A
2A
8
DQa
DQa
DQa
DQa
ZZ
DQb
DQb
DQb
DQb
NC
DQb
DQb
DQb
DQb
DQb
MODE
A
1D
2E
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
12
13
14
18
19
22
23
24
31
32
33
34
35
36
37
2G
1H
5R
2K
7K
7T
DQa
DQa
DQa
DQa
DQa
A
6H
7G
6F
1L
2M
1N
2P
7E
6D
6T
3R
2C
3C
5C
6C
4N
4P
A
6A
5A
4G
4A
4B
4F
A
A
ADV
ADSP
ADSC
OE
BWE
GW
A
A
A1
A0
4M
4H
18
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Power Dissipation.......................................................... 1.0W
Maximum Ratings
Short Circuit Output Current ....................................... 50 mA
.
(Above which the useful life may be impaired. For user guide-
lines only, not tested.)
Operating Range
Voltage on V Supply Relative to V ......... –0.5V to +4.6V
CC
SS
[10]
Range
Ambient Temperature
V
CC
V ............................................................–0.5V to V +0.5V
IN
CC
Com’l
0°C to +70°C
3.3V –5%/+10%
Storage Temperature (plastic)........................–55°C to +150°
Junction Temperature ..................................................+150°
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Data Inputs (DQx)
All Other Inputs
Min.
2.0
Max.
+0.3
CC
Unit
V
[13, 19]
V
Input High (Logic 1) Voltage
V
IHD
IH
Il
V
V
2.0
4.6
V
[13, 19]
Input Low (Logic 0) Voltage
–0.5
–5
0.8
5
V
[13, 19]
IL
Input Leakage Current
0V < V < V
µA
µA
I
IN
CC
CC
IL
MODE and ZZ Input Leakage
0V < V < V
–30
30
I
IN
[20]
Current
IL
Output Leakage Current
Output(s) disabled, 0V < V
< V
CC
–5
5
µA
V
O
OUT
[13]
V
Output High Voltage
I
I
= –5.0 mA
2.4
OH
OH
OL
[13]
V
Output Low Voltage
= 8.0 mA
0.4
3.6
V
OL
[13]
V
Supply Voltage
3.135
3.135
2.375
V
CC
[13]
V
V
I/O Supply Voltage (3.3V)
V
V
CCQ
CCQ
CC
CC
[13]
I/O Supply Voltage (2.5V)
V
V
Parameter
Description
Conditions
Typ.
-6
-6.5
-7
-8
Unit
I
Power Supply Current:
Operating
Device selected;
all inputs < V or > V ;
150
400
360
320
270
mA
CC
[21, 22, 23]
IL
IH
cycle time > t Min.; V = Max.;
KC
CC
outputs open
[22, 23]
I
I
I
CMOS Standby
Device deselected; V = Max.;
5
10
30
90
10
30
80
10
30
70
10
30
60
mA
mA
mA
SB2
SB3
SB4
CC
all inputs < V + 0.2 or > V – 0.2;
SS
CC
all inputs static; CLK frequency = 0
[22, 23]
TTL Standby
Device deselected; all inputs < V
15
40
IL
or > V ; all inputs static;
IH
V
= Max.; CLK frequency = 0
CC
[22, 23]
Clock Running
Device deselected;
all inputs < V or > V ; V = Max.;
IL
IH CC
CLK cycle time > t Min.
KC
Thermal Consideration
Parameter
Description
Conditions
TQFP Typ.
Unit
Θ
Θ
Thermal Resistance - Junction to Ambient
Thermal Resistance - Junction to Case
Still air, soldered on 4.25 x 1.125
inch 4-layer PCB
25
9
°C/W
°C/W
JA
JC
Notes:
18. A is the case temperature.
T
19. Overshoot: VIH < +6.0V for t < tKC /2.
Undershoot: VIL < –2.0V for t < tKC /2.
20. Output loading is specified with CL= 5 pF as in AC Test Loads.
21. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
22. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
23. Typical values are measured at 3.3V, 25°C and 20-ns cycle time.
19
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Capacitance
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Typ.
Max.
Unit
pF
[15]
C
C
Input Capacitance
5
7
7
8
I
A
V
= 3.3V
CC
[15]
Input/Output Capacitance (DQ)
pF
O
Typical Output Buffer Characteristics
Output High Voltage
(V)
Pull-up Current
Output Low Voltage
(V)
Pull-down Current
V
I
(mA) Min.
I
(mA) Max.
–105
–105
–105
–83
V
I
(mA) Min.
I
(mA) Max.
ΟL
OH
OH
OH
OL
OL
–0.5
0
–38
–38
–38
–26
–20
0
–0.5
0
0
0
0
0
0.8
1.25
1.5
2.3
2.7
2.9
3.4
0.4
0.8
1.25
1.6
2.8
3.2
3.4
10
20
31
40
40
40
40
20
40
63
80
80
80
80
–70
–30
0
–10
0
0
0
0
AC Test Loads and Waveforms (3.3V I/O)
R = 317
Ω
3.3V
[13]
DQ
ALL INPUT PULSES
90%
DQ
3.0V
90%
Z = 50
Ω
0
R = 50
10%
1.0 ns
Ω
10%
L
0V
5 pF
R = 351
Ω
1.0 ns
≤
≤
V = 1.5V
t
(c)
(a)
(b)
AC Test Loads and Waveforms (2.5V I/O)
DQ
ALL INPUT PULSES
90%
2.5V
90%
10%
Z = 50
Ω
0
R = 50
10%
1.0 ns
Ω
L
0V
1.0 ns
≤
≤
V = 1.25V
t
(c)
(a)
20
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
[24]
Switching Characteristics Over the Operating Range
-6
-6.5
Max.
-7
-8
Parameter
Clock
Description
Min.
Max.
Min.
Min.
Max.
Min.
Max.
Unit
t
t
t
Clock Cycle Time
6.7
2.5
2.5
7.5
2.5
2.5
8.5
3.0
3.0
10
ns
ns
ns
KC
KH
KL
Clock HIGH Time
Clock LOW Time
3.5
3.5
Output Times
VCCQ=3.3V
VCCQ=2.5V
t
Clock to Output Valid
6.0
6.5
6.5
7.0
7.0
7.5
8.0
9.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
KQ
t
t
t
t
Clock to Output Invalid
Clock to Output in Low-Z
Clock to Output in High-Z
2
0
2
2
0
2
2
0
2
2
0
2
KQX
[15, 20, 25]
KQLZ
KQHZ
OEQ
[15, 20, 25]
3.5
3.5
4.5
3.5
3.5
4.5
3.5
3.5
4.5
3.5
4.0
5.0
[26]
VCCQ=3.3V
VCCQ=2.5V
OE to Output Valid
[15, 20, 25]
t
t
OE to Output in Low-Z
OE to Output in High-Z
0
0
0
0
OELZ
[15, 20, 25]
3.5
3.5
3.5
3.5
OEHZ
Set-Up Times
[27]
[27]
t
Address, Controls and Data In
1.5
0.5
1.5
0.5
1.8
0.5
2.0
0.5
ns
ns
S
Hold Times
t
Address, Controls and Data In
H
Notes:
24. Test conditions as specified with the output loading as shown in AC Test Loads unless otherwise noted.
25. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ
.
26. OE is a “Don’t Care” when a byte write enable is sampled LOW.
27. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “Don’t Care” as defined in the truth table.
21
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Timing Diagrams
[28, 29]
Read Timing
tKC
tKL
CLK
ADSP#
tS
tKH
tH
ADSC#
tS
ADDRESS
A1
A2
tH
BWa#, BWb#,
BWc#, BWd#,[29]
BWE#, GW#
CE#[30]
tS
ADV#
OE#
DQ
tH
tKQ
tKQ
tOEQ
tOELZ
tKQLZ
Q(A1)
Q(A2)
Q(A2+1)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A2+2)
SINGLE READ
BURST READ
Notes:
28. For X18 product, there are only BWa and BWb for byte write control.
29. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. CE2 is only available for TA package version.
22
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Timing Diagrams (continued)
Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
A1
A2
A3
ADDRESS
tH
BWa#, BWb#,
BWc#, BWd#,
[29]
BWE#
GW#
CE#[30]
ADV#
tS
tH
OE#
tOEHZ
tKQX
Q
D(A1)
D(A2)
D(A2+2)
D(A2+2)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
DQ
SINGLE WRITE
BURST WRITE
BURST WRITE
23
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Timing Diagrams (continued)
Read/Write Timing
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A2
A3
A4
A5
A1
tH
BWa#, BWb#,
BWc#, BWd#,
[29]
BWE#, GW#
[30]
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
D(A3)
Q(A4)
Q(A4+1)
Q(A4+2)
Q(A4+3)
D(A5)
D(A5+1)
Single Reads
Single Write
Burst Read
Burst Write
Ordering Information
Speed
(MHz)
Package
Name
Operating
Range
Ordering Code
Package Type
150
CY7C1361A-150AC
GVT71256B36TA-6
CY7C1361A-150AJC
GVT71256B36T-6
A101
100-Lead Thin Quad Flat Pack
Commercial
CY7C1361A-150BGC
GVT71256B36B-6
BG119
A101
119-Ball BGA
133
CY7C1361A-133AC
GVT71256B36TA-6.5
CY7C1361A-133AJC
GVT71256B36T-6.5
CY7C1361A-133BGC
GVT71256B36B-6.5
100-Lead Thin Quad Flat Pack
Commercial
BG119
119-Ball BGA
24
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Ordering Information (continued)
Speed
Package
Name
Operating
(MHz)
Ordering Code
CY7C1361A-117AC
GVT71256B36TA-7
CY7C1361A-117AJC
GVT71256B36T-7
Package Type
Range
117
A101
100-Lead Thin Quad Flat Pack
Commercial
CY7C1361A-117BGC
GVT71256B36B-7
CY7C1361A-100AC
GVT71256B36TA-8
CY7C1361A-100AJC
GVT71256B36T-8
BG119
A101
119-Ball BGA
100
150
133
117
100
100-Lead Thin Quad Flat Pack
Commercial
Commercial
Commercial
Commercial
Commercial
CY7C1361A-100BGC
GVT71256B36B-8
CY7C1363A-150AC
GVT71512B36TA-6
CY7C1363A-150AJC
GVT71512B36T-6
BG119
A101
119-Ball BGA
100-Lead Thin Quad Flat Pack
CY7C1363A-150BGC
GVT71512B36B-6
CY7C1363A-133AC
GVT71512B36TA-6.5
CY7C1363A-133AJC
GVT71512B36T-6.5
CY7C1363A-133BGC
GVT71512B36B-6.5
CY7C1363A-177AC
GVT71512B36TA-7
CY7C1363A-177AJC
GVT71512B36T-7
BG119
A101
119-Ball BGA
100-Lead Thin Quad Flat Pack
BG119
A101
119-Ball BGA
100-Lead Thin Quad Flat Pack
CY7C1363A-177BGC
GVT71512B36B-7
CY7C1363A-100AC
GVT71512B36TA-8
CY7C1363A-100AJC
GVT71512B36T-8
BG119
A101
119-Ball BGA
100-Lead Thin Quad Flat Pack
CY7C1363A-100BC
GVT71512B36B-8
BG119
119-Ball BGA
Document #: 38-00991-**
25
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
26
CY7C1361A/GVT71256B36
CY7C1363A/GVT71512B18
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
相关型号：
GVT71256B36T-7I
Standard SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36T-8
Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36T-8I
Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36TA-6
Cache SRAM, 256KX36, 6.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36TA-6.5
Standard SRAM, 256KX36, 7ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36TA-7
Standard SRAM, 256KX36, 7.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36TA-8
Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256B36TA-8I
Standard SRAM, 256KX36, 9ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, TQFP-100
CYPRESS
GVT71256C36B-5I
Cache SRAM, 256KX36, 3.5ns, CMOS, PBGA119, 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119
CYPRESS
©2020 ICPDF网 联系我们和版权申明