GS8160Z18T-180T [ETC]
x18 Fast Synchronous SRAM ; X18高速同步SRAM\n
| 型号： | GS8160Z18T-180T |
| 厂家： | 
ETC |
| 描述： | x18 Fast Synchronous SRAM
|
| 文件： | 总24页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
100-Pin TQFP
Commercial Temp
Industrial Temp
16Mb Pipelined and Flow through 225 MHz–133 MHz
2.5 V VDD
Synchronous NBT SRAM
2.5 V or 3.3 V I/O
late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
read-write-read bus utilization; Fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
• 2.5 V +10%/–5% core power supply
• 2.5 V or 3.3 V I/O supply
• 3.3 V-compatible inputs
• LBO pin for Linear or Interleave Burst mode
• Pin compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• Clock Control, registered, address, data, and control
• ZZ Pin for automatic power-down
when the device is switched from read to write cycles.
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
• JEDEC-standard 100-lead TQFP package
The GS8160Z18/36T may be configured by the user to operate
in Pipeline or Flow Through mode. Operating as a pipelined
synchronous device, meaning that in addition to the rising edge
triggered registers that capture input signals, the device
incorporates a rising-edge-triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
-225 -200 -180 -166 -150 -133 Unit
Pipeline tCycle 4.4
5
5.5
6
6.6 7.5
ns
ns
3-1-1-1
tKQ
IDD
2.5
3.0 3.2 3.5 3.8 4.0
410 375 340 310 290 260 mA
Flow
Through
2-1-1-1
tKQ
tCycle
IDD
7.0
8.5
7.5
10
8
10
8.5
10
10
10
11
15
ns
ns
255 235 235 235 235 220 mA
The GS8160Z18/36T is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
Standard 100-pin TQFP package.
Functional Description
The GS8160Z18/36T is a 16Mbit Synchronous Static SRAM.
GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other
pipelined read/double late write or flow through read/single
Flow Through and Pipelined NBT SRAM Back-to-Back Read/Write Cycles
Clock
Address
A
R
B
C
R
D
E
R
F
Read/Write
W
W
W
Flow Through
Data I/O
QA
DB
QC
DD
QE
DD
Pipelined
Data I/O
QA
DB
QC
QE
Rev: 2.06 8/2000
1/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
NoBL is a trademark of Cypress Semiconductor Corp.. NtRAM is a trademark of Samsung Electronics Co.. ZBT is a trademark of Integrated Device Technology, Inc.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
GS8160Z18T Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A19
NC
NC
VDDQ
VSS
NC
DQA9
DQA8
DQA7
VSS
VDDQ
DQA6
DQA5
VSS
NC
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
NC
NC
DQB1
DQB2
VSS
VDDQ
DQB3
DQB4
FT
VDD
VDD
VSS
DQB5
DQB6
5
6
7
8
9
1M x 18
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top View
VDD
ZZ
DQA4
DQA3
VDDQ
VSS
DQA2
DQA1
NC
VDDQ
VSS
DQB7
DQB8
DQB9
NC
VSS
VDDQ
NC
NC
VSS
VDDQ
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.06 8/2000
2/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
GS8160Z36T Pinout
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQB9
DQB8
DQB7
VDDQ
VSS
DQB6
DQB5
DQB4
DQB3
VSS
VDDQ
DQB2
DQB1
VSS
NC
VDD
DQC9
DQC8
DQC7
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
3
VDDQ
4
VSS
DQC6
DQC5
DQC4
DQC3
VSS
VDDQ
DQC2
DQC1
FT
VDD
VDD
VSS
DQD1
DQD2
VDDQ
5
6
7
8
9
512K x 36
Top View
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
ZZ
DQA1
DQA2
VDDQ
VSS
DQA3
DQA4
DQA5
DQA6
VSS
VDDQ
DQA7
DQA8
DQA9
VSS
DQD3
DQD4
DQD5
DQD6
VSS
VDDQ
DQD7
DQD8
DQD9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Rev: 2.06 8/2000
3/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
100 Pin TQFP Pin Descriptions
Pin Location
Symbol Type
Description
37, 36
A0, A1
In
Burst Address Inputs; Preload the burst counter
35, 34, 33, 32, 100, 99, 84, 83,
82, 81, 44, 45, 46,47, 48, 49, 50
A2–A18
In
Address Inputs
80
89
93
94
95
96
88
98
97
92
86
85
87
A19
CK
BA
In
In
In
In
In
In
In
In
In
In
In
In
In
I/O
I/O
Address Input (x18 Version Only)
Clock Input Signal
Byte Write signal for data inputs DQA1-DQA9; active low
Byte Write signal for data inputs DQB1-DQB9; active low
Byte Write signal for data inputs DQC1-DQC9; active low (x36 Versions Only)
Byte Write signal for data inputs DQD1-DQD9; active low (x36 Versions Only)
Write Enable; active low
BB
BC
BD
W
E1
Chip Enable; active low
E2
Chip Enable; Active High. For self decoded depth expansion
Chip Enable; Active Low. For self decoded depth expansion
Output Enable; active low
E3
G
ADV
CKE
Advance/Load; Burst address counter control pin
Clock Input Buffer Enable; active low
58, 59, 62,63, 68, 69, 72, 73, 74 DQA1–DQA9
8, 9, 12, 13, 18, 19, 22, 23, 24 DQB1–DQB9
Byte A Data Input and Output pins (x18 Version Only)
Byte B Data Input and Output pins (x18 Version Only)
51, 52, 53, 56, 57, 75, 78, 79,
NC
—
I/O
I/O
No Connect (x18 Version Only)
1, 2, 3, 6, 7, 25, 28, 29, 30
51, 52, 53, 56, 57, 58, 59, 62,63 DQA1–DQA9
Byte A Data Input and Output pins (x36 Versions Only)
Byte B Data Input and Output pins (x36 Versions Only)
68, 69, 72, 73, 74, 75,
DQB1–DQB9
78, 79, 80
1, 2, 3, 6, 7, 8, 9, 12, 13
DQC1–DQC9
I/O
I/O
In
Byte C Data Input and Output pins (x36 Versions Only)
Byte D Data Input and Output pins (x36 Versions Only)
Power down control; active high
18, 19, 22, 23, 24, 25, 28, 29, 30 DQD1–DQD9
64
ZZ
FT
14
31
In
Pipeline/Flow Through Mode Control; active low
Linear Burst Order; active low
LBO
VDD
In
15, 16, 41, 65, 91
In
3.3 V power supply
5,10, 17, 21, 26, 40, 55, 60, 67,
71, 76, 90
VSS
In
Ground
VDDQ
NC
4, 11, 20, 27, 54, 61, 70, 77
38, 39, 42, 43, 66
In
3.3 V output power supply for noise reduction
No Connect
—
Rev: 2.06 8/2000
4/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
GS8160Z18/36 NBT SRAM Functional Block Diagram
s p m A e s n e S
s r e v i r D e t i r W
Rev: 2.06 8/2000
5/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Functional Details
Clocking
Deassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to
suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.
Pipeline Mode Read and Write Operations
All inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle
read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device
activation is accomplished by asserting all three of the Chip Enable inputs (E1, E2 and E3). Deassertion of any one of the Enable
inputs will deactivate the device.
Function
Read
W
H
L
BA
X
BB
X
BC
X
BD
X
Write Byte “a”
Write Byte “b”
Write Byte “c”
Write Byte “d”
Write all Bytes
Write Abort/NOP
L
H
L
H
H
L
H
H
H
L
L
H
H
H
L
L
H
H
L
L
H
L
L
L
L
H
H
H
H
Read operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three
chip enables (E1, E2, and E3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address
presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control
logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At
the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.
Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock.
The Byte Write Enable inputs (BA, BB, BC, & BD) determine which bytes will be written. All or none may be activated. A write
cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,
matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At
the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is
required at the third rising edge of clock.
Flow Through Mode Read and Write Operations
Operation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the
use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after
new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow
Through mode the read pipeline is one cycle shorter than in Pipeline mode.
Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability
to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late
write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address
and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of
clock.
Rev: 2.06 8/2000
6/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Synchronous Truth Table
Operation
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Power Down
Deselect Cycle, Continue
Read Cycle, Begin Burst
Read Cycle, Continue Burst
NOP/Read, Begin Burst
Dummy Read, Continue Burst
Write Cycle, Begin Burst
Write Cycle, Continue Burst
NOP/Write Abort, Begin Burst
Write Abort, Continue Burst
Clock Edge Ignore, Stall
Sleep Mode
Type Address E1 E2 E3 ZZ ADV W Bx G CKE CK DQ Notes
D
D
D
D
R
B
None
None
H
X
X
X
L
X
X
L
X
H
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
X
X
X
X
H
X
H
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
None
L
None
X
H
X
H
X
H
X
H
X
X
X
H
L
1
External
Next
L-H
L-H
Q
Q
X
L
X
L
H
L
L
1,10
2
R
B
External
Next
H
H
X
X
X
X
X
X
L-H High-Z
X
L
X
L
H
L
L-H High-Z 1,2,10
W
B
External
Next
L-H
L-H
D
D
3
X
L
X
L
H
L
X
L
L
1,3,10
2,3
W
B
None
H
H
X
X
L-H High-Z
Next
X
X
X
X
X
X
H
X
X
X
X
X
L-H High-Z 1,2,3,10
Current
None
L-H
X
-
4
High-Z
Notes:
1. Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-
lect cycle is executed first.
2. Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the W
pin is sampled low but no Byte Write pins are active so no write operation is performed.
3. G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off during
write cycles.
4. If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the bus
will remain in High Z.
5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Write
signals are Low
6. All inputs, except G and ZZ must meet setup and hold times of rising clock edge.
7. Wait states can be inserted by setting CKE high.
8. This device contains circuitry that ensures all outputs are in High Z during power-up.
9. A 2-bit burst counter is incorporated.
10. The address counter is incriminated for all Burst continue cycles.
Rev: 2.06 8/2000
7/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Pipeline and Flow Through Read Write Control State Diagram
D
B
Deselect
R
D
D
W
New Read
New Write
R
R
W
B
B
R
W
W
R
Burst Read
Burst Write
B
B
D
D
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes ,as indicated in the Synchronous Truth Table.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for Pipeline and Flow Through Read/Write Control State Diagram
Rev: 2.06 8/2000
8/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Pipeline Mode Data I/O State Diagram
Intermediate
Intermediate
R
B
W
B
Intermediate
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
Intermediate
D
Intermediate
W
R
High Z
B
D
Intermediate
Key
Notes:
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
Transition
2. W, R, B, and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+2)
Intermediate State (N+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Intermediate
State
Current State
Next State
Current State and Next State Definition for Pipeline Mode Data I/O State Diagram
Rev: 2.06 8/2000
9/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Flow Through Mode Data I/O State Diagram
R
B
W
B
R
Data Out
(Q Valid)
High Z
(Data In)
W
D
D
W
R
High Z
B
D
Key
Notes
Input Command Code
1. The Hold command (CKE Low) is not
shown because it prevents any state change.
ƒ
Transition
2. W, R, B and D represent input command
codes as indicated in the Truth Tables.
Current State (n)
Next State (n+1)
n
n+1
n+2
n+3
Clock (CK)
Command
ƒ
ƒ
ƒ
ƒ
Current State
Next State
Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram
Rev: 2.06 8/2000
10/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Burst Cycles
Although NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from
read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address
generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when
driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write
the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into
Load mode.
Burst Order
The burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have been
accessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst
sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables
below for details.
Mode Pin Functions
Pin
Mode Name
Burst Order Control
Output Register Control
Power Down Control
State
Function
Name
L
Linear Burst
Interleaved Burst
Flow Through
Pipeline
LBO
H or NC
L
FT
ZZ
H or NC
L or NC
H
Active
Standby, IDD = ISB
Note:
There are pull-up devices on the LBO and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected
and the chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
A[1:0] A[1:0] A[1:0] A[1:0]
1st address
2nd address
3rd address
4th address
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
1st address
2nd address
3rd address
4th address
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Sleep Mode
During normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high,
the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to
low, the SRAM operates normally after 2 cycles of wake up time.
Rev: 2.06 8/2000
11/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of
Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become
disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode.
When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending
operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated
until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands
may be applied while the SRAM is recovering from Sleep mode.
Sleep Mode Timing Diagram
CK
tZZR
ZZ
Sleep
tZZS
tZZH
Designing for Compatibility
The GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found
on Pin 14. Not all vendors offer this option, however most mark Pin 14 as VDD or VDDQ on pipelined parts and VSS on flow
through parts. GSI NBT SRAMs are fully compatible with these sockets.
Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS8161Z18/36
NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked VDD or VDDQ
on pipelined parts and VSS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity
feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline mode
applications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open. By
using the pull-up resistor, rather than tying the pin to one of the power rails, users interested in upgrading to GSI’s ByteSafe NBT
SRAMs (GS8161Z18/36), featuring Parity Error detection and JTAG Boundary Scan, will be ready for connection to the active
low, open drain Parity Error output driver at Pin 66 on GSI’s TQFP ByteSafe RAMs.
Rev: 2.06 8/2000
12/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS
)
Symbol
VDD
Description
Value
–0.5 to 3.6
Unit
V
Voltage on VDD Pins
VDDQ
VCK
Voltage in VDDQ Pins
–0.5 to 3.6
V
Voltage on Clock Input Pin
Voltage on I/O Pins
–0.5 to 6
V
VI/O
–0.5 to VDDQ+0.5 (≤ 3.6 V max.)
V
VIN
Voltage on Other Input Pins
Input Current on Any Pin
Output Current on Any I/O Pin
Package Power Dissipation
Storage Temperature
–0.5 to 3.6
+/–20
V
IIN
mA
mA
W
IOUT
PD
+/–20
1.5
oC
oC
TSTG
–55 to 125
–55 to 125
TBIAS
Temperature Under Bias
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to
Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of
time, may affect reliability of this component.
Recommended Operating Conditions
Parameter
Supply Voltage
Symbol
VDD
VDDQ
VIH
Min.
2.375
Typ.
2.5
2.5
—
Max.
2.7
Unit
V
Notes
I/O Supply Voltage
2.375
3.6
V
0.7 * VDD
Input High Voltage
3.6
V
1
1
2
2
VIL
Input Low Voltage
–0.3
0
—
0.3 * VDD
70
V
TA
Ambient Temperature (Commercial Range Versions)
Ambient Temperature (Industrial Range Versions)
25
°C
°C
TA
–40
25
85
Note:
1. The part number of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifications
quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be –2 V > Vi < VDD+2 V with a pulse width not to exceed 20% tKC.
Rev: 2.06 8/2000
13/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Undershoot Measurement and Timing
Overshoot Measurement and Timing
V
IH
20% tKC
V
+ 2.0 V
50%
DD
V
SS
50%
V
DD
V
– 2.0 V
SS
20% tKC
V
IL
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 2.5 V)
Parameter
Control Input Capacitance
Input Capacitance
Symbol
CI
Test conditions
VDD = 2.5 V
VIN = 0 V
Typ.
Max.
Unit
pF
3
4
6
4
5
7
CIN
pF
COUT
VOUT = 0 V
Output Capacitance
pF
Note: This parameter is sample tested.
Package Thermal Characteristics
Rating
Junction to Ambient (at 200 lfm)
Junction to Ambient (at 200 lfm)
Junction to Case (TOP)
Notes:
Layer Board
Symbol
RΘJA
Max
40
Unit
Notes
1,2
single
four
—
°C/W
°C/W
°C/W
RΘJA
24
1,2
RΘJC
9
3
1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temper-
ature air flow, board density, and PCB thermal resistance.
2. SCMI G-38-87
3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 2.06 8/2000
14/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
AC Test Conditions
Parameter
Input high level
Input low level
Conditions
2.3 V
0.2 V
Input slew rate
1 V/ns
Input reference level
Output reference level
Output load
1.25 V
1.25 V
Fig. 1& 2
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ
4. Device is deselected as defined by the Truth Table.
Output Load 2
2.5 V
Output Load 1
DQ
225Ω
225Ω
DQ
30pF*
50Ω
5pF*
VT = 1.25 V
* Distributed Test Jig Capacitance
DC Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
(except mode pins)
IIL
VIN = 0 to VDD
–1 uA
1 uA
VDD ≥ VIN ≥ VIH
0 V ≤ VIN ≤ VIH
–1 uA
–1 uA
1 uA
300 uA
IINZZ
ZZ Input Current
VDD ≥ VIN ≥ VIL
0 V ≤ VIN ≤ VIL
–300 uA
–1 uA
1 uA
1 uA
IINM
Mode Pin Input Current
IOL
Output Disable, VOUT = 0 to VDD
IOH = –8 mA, VDDQ = 2.375 V
IOH = –8 mA, VDDQ = 3.135 V
IOL = 8 mA
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
–1 uA
1.7 V
2.4 V
—
1 uA
—
VOH
VOH
VOL
—
0.4 V
Rev: 2.06 8/2000
15/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Rev: 2.06 8/2000
16/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
AC Electrical Characteristics
-225
-200
-180
-166
-150
-133
Parameter
Symbol
Unit
Min Max Min Max Min Max Min Max Min Max Min Max
Clock Cycle Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock Cycle Time
tKC
tKQ
4.4
—
1.5
1.5
8.5
—
3.0
3.0
1.3
1.5
1.5
—
0
—
2.5
—
—
—
7.0
—
—
—
—
2.5
2.5
—
5.0
—
—
3.0
—
—
—
7.5
—
—
—
—
5.5
—
—
3.2
—
—
—
8.0
—
—
—
—
6.0
—
—
3.5
—
—
—
8.5
—
—
—
—
3.5
3.5
—
6.7
—
—
3.8
—
—
—
10.0
—
—
—
—
3.8
3.8
—
7.5
—
1.5
1.5
15.0
—
3.0
3.0
1.7
2
—
4.0
—
—
—
11.0
—
—
—
—
4.0
4.0
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Pipeline
tKQX
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
1.5
1.5
10.0
—
tLZ1
tKC
Clock to Output Valid
Clock to Output Invalid
Clock to Output in Low-Z
Clock HIGH Time
tKQ
Flow
Through
tKQX
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.3
1.5
3.0
3.0
1.3
1.5
1.5
—
3.0
3.0
1.5
1.7
1.5
—
tLZ1
tKH
tKL
Clock LOW Time
tHZ1
tOE
Clock to Output in High-Z
G to Output Valid
3.0 1.5 3.2
1.5
—
0
3.2
—
3.2
tOLZ1
G to output in Low-Z
0
—
0
—
0
0
tOHZ1
tS
G to output in High-Z
Setup time
—
1.5
0.5
5
2.5
—
—
—
—
1.5
0.5
5
3.0
—
—
—
—
1.5
0.5
5
3.2
—
—
—
—
1.5
0.5
5
3.5
—
—
—
—
1.5
0.5
5
3.8
—
—
—
—
1.5
0.5
5
4.0
—
—
—
ns
ns
ns
ns
Hold time
tH
tZZS2
ZZ setup time
tZZH2
tZZR
ZZ hold time
ZZ recovery
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
1
—
—
ns
ns
100
100
100
100
100
100
Rev: 2.06 8/2000
17/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Pipeline Mode Read/Write Cycle Timing
1
2
3
4
5
6
7
8
9
10
CK
tH
tS
tS
tS
tS
tS
tS
tKH tKL tKC
CKE
E*
tH
tH
tH
tH
ADV
W
Bn
tH
A1
A2
A3
A4
A5
A6
A7
A0–An
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
(A4+1)
DQA–DQD
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
tKQX
tH
tS
tOEHZ
tOELZ
G
Write
D(A5)
Write
D(A2) Write
D(A2+1)
BURST Read
Q(A3)
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.06 8/2000
18/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Pipeline Mode No-Op, Stall and Deselect Timing
2
8
4
3
5
6
10
7
9
1
CK
tH
tH
tH
tS
tS
tS
CKE
E*
ADV
tS
tH
W
Bn
A0–An
DQ
A1
A2
A3
A4
A5
tKHQZ
Q(A2)
D(A1)
Q(A3)
D(A4)
Q(A5)
tKQHZ
NOP
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
CONTINUE
DESELECT
Write
D(A1)
DESELECT
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.06 8/2000
19/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Flow Through Mode Read/Write Cycle Timing
4
3
5
6
8
10
7
9
1
2
CK
CKE
E*
tH
tH
tH
tH
tH
tS
tS
tS
tS
tS
tS
tKH tKL
tKC
ADV
W
Bn
tH
A7
A0–An
A1
A2
A3
A4
A5
A6
tKQ
tKHQZ
tGLQV
tKQHZ
tKQLZ
D
Q
DQ
D(A2)
Q(A3)
Q(A4)
Q(A6)
D(A1)
D(A5)
(A2+1)
(A4+1)
tOELZ
tKQX
tH
tS
tOEHZ
G
Write
D(A5)
Write
D(A2)
BURST Read
Read
Q(A4) Read
Q(A4+1)
BURST
Read
Q(A6)
DESELECT
Write
D(A1)
Write
D(A7)
COMMAND
Write
Q(A3)
D(A2+1)
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.06 8/2000
20/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Flow Through Mode No-Op, Stall and Deselect Timing
4
3
5
6
8
10
7
9
1
2
CK
tH
tS
tS
tS
CKE
E*
tH
tH
ADV
W
Bn
A1
A2
A3
A4
A5
A0–An
DQ
tKHQZ
Q(A2)
D(A1)
Q(A5)
Q(A3)
D(A4)
NOP
tKQHZ
Read
Q(A2)
STALL Read
Q(A3)
Write
D(A4)
STALL
Read
Q(A5)
DESELECT
CONTINUE
DESELECT
Write
D(A1)
COMMAND
DON’T CARE
UNDEFINED
*Note: E = High (False) if E1 = 1 or E2 = 0 or E3 = 1
Rev: 2.06 8/2000
21/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
TQFP Package Drawing
θ
L
c
L1
Symbol
Description
Standoff
Min. Nom. Max
A1
A2
b
0.05
1.35
0.20
0.09
0.10
1.40
0.30
—
0.15
1.45
0.40
0.20
20.1
20.1
16.1
14.1
—
Body Thickness
Lead Width
c
Lead Thickness
D
Terminal Dimension 21.9
Package Body 19.9
Terminal Dimension 15.9
22.0
20.0
16.0
14.0
0.65
0.60
1.00
—
e
D1
E
b
E1
e
Package Body
Lead Pitch
13.9
—
L
Foot Length
Lead Length
Coplanarity
Lead Angle
0.45
—
0.75
—
L1
Y
A1
A2
E1
E
—
0.10
7°
θ
0°
—
Notes:
1. All dimensions are in millimeters (mm).
2. Package width and length do not include mold protrusion.
BPR 1999.05.18
Rev: 2.06 8/2000
22/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
Ordering Information—GSI NBT Synchronous SRAM
2
Speed
3
1
Org
Type
Package
Status
T
Part Number
A
(MHz/ns)
1M x 18
1M x 18
GS8160Z18T-225
GS8160Z18T-200
GS8160Z18T-180
GS8160Z18T-166
GS8160Z18T-150
GS8160Z18T-133
GS8160Z36T-225
GS8160Z36T-200
GS8160Z36T-180
GS8160Z36T-166
GS8160Z36T-150
GS8160Z36T-133
GS8160Z18T-225I
GS8160Z18T-200I
GS8160Z18T-180I
GS8160Z18T-166I
GS8160Z18T-150I
GS8160Z18T-133I
GS8160Z36T-225I
GS8160Z36T-200I
GS8160Z36T-180I
GS8160Z36T-166I
GS8160Z36T-150I
GS8160Z36T-133I
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
NBT Pipeline/Flow Through
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
TQFP
225/7
200/7.5
180/8
C
C
C
C
C
C
C
C
C
C
C
C
I
1M x 18
1M x 18
166/8.5
150/10
133/11
225/7
1M x 18
1M x 18
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
1M x 18
200/7.5
180/8
166/8.5
150/10
133/11
225/7
Not Available
Not Available
1M x 18
200/7.5
180/8
I
1M x 18
I
1M x 18
166/8.5
150/10
133/11
225/7
I
1M x 18
I
1M x 18
I
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
512K x 36
Notes:
I
Not Available
Not Available
200/7.5
180/8
I
I
166/8.5
150/10
133/11
I
I
I
1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8160Z36T-100IT.
2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each
device is Pipeline/Flow Through mode-selectable by the user.
3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range.
4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are
covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings
Rev: 2.06 8/2000
23/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
Preliminary
GS8160Z18/36T-225/200/180/166/150/133
0.18u 16M Sync SRAM Data Sheet Revision History
DS/DateRev. Code: Old;
New
Types of Changes
Format or Content
Page;Revisions;Reason
• Converted from 0.25u 3.3V process to 0.18u 2.5V process. Master
File Rev B
• Added x72 Pinout.
GS8160Z18/36T 1.00 9/
1999A;GS8160Z18/36T2.0012/
1999B
Content
Format
• Added new GSI Logo
GS8160Z18/36T2.00 12/
1999BGS8160Z18/36T2.01 1/
2000C
• Front page; Features - changed 2.5V I/O supply to 2.5V or3.3V I/O
supply; Completeness
• Absolute Maximum Ratings; Changed VDDQ - Value: From: -.05 to
VDD : to : -.05 to 3.6; Completeness.
GS8160Z18/36T2.01 1/
2000DGS8160Z18/36T2.03 2/
2000E
• Recommended Operating Conditions;Changed: I/O Supply Voltage-
Max. from VDD to 3.6; Input High Voltage- Max. from VDD +0.3 to
3.6; Same page - took out Note 1;Completeness
• Electrical Characteristics - Added second Output High Voltage line to
table; completeness.
• Note: There was not a Rev 2.02 for the 8160Z or the 8161Z.
• Removed pin 14 from V in pin description table.
GS8160Z18/36T2.03 2/2000E;
8160Z18_r2_04
SS
Content
Content
• ADV changed to pin 85 in pin description table.
• Changed the value of ZZ recovery in the AC Electrical Characteristics
table on page 17 from 20 ns to 100 ns
8160Z18_r2_04;
8160Z18_r2_05
• Added 225 MHz speed bin
8160Z18_r2_05;
8160Z18_r2_06
• Updated Pg. 1 table, AC Characteristics table, and Operating Cur-
rents table to match 815xxx
Content
• Updated format to comply with Technical Publications standards
Rev: 2.06 8/2000
24/24
© 1998, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
This Material Copyrighted by Its Respective Manufacturer
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