GM71V17800CT-7 [ETC]
x8 Fast Page Mode DRAM ; X8快速页模式DRAM\n
| 型号： | GM71V17800CT-7 |
| 厂家： | 
ETC |
| 描述： | x8 Fast Page Mode DRAM
|
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71V17800C
GM71VS17800CL
2,097,152 WORDS x 8 BIT
CMOS DYNAMIC RAM
Description
Features
The GM71V(S)17800C/CL is the new
generation dynamic RAM organized 2,097,152
x 8 bit. GM71V(S)17800C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71V(S)17800C/CL offers
Fast Page Mode as a high speed access mode.
Multiplexed address inputs permit the
GM71V(S)17800C/CL to be packaged in
standard 400 mil 28pin plastic SOJ, and
standard 400mil 28pin plastic TSOP II. The
package size provides high system bit densities
and is compatible with widely available
automated testing and insertion equipment.
* 2,097,152 Words x 8 Bit Organization
* Fast Page Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC
tCAC
t
RC
tPC
50
60
70
13
15
18
90
110
130
35
40
45
GM71V(S)17800C/CL-5
GM71V(S)17800C/CL-6
GM71V(S)17800C/CL-7
* Low Power
Active : 468/432/396mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.54mW (L- version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L-version)
* Self Refresh Operation (L-version)
* Battery Back Up Operation (L- version)
Pin Configuration
28 SOJ
28 TSOP II
1
2
3
4
5
6
28
27
1
2
3
4
5
6
28
27
VCC
VSS
VCC
VSS
I/O0
I/O1
I/O7
I/O0
I/O1
I/O7
26 I/O6
26 I/O6
25
24
23
22
21
20
19
18
17
16
15
25
24
23
22
I/O2
I/O3
I/O5
I/O4
CAS
OE
A9
I/O2
I/O3
I/O5
I/O4
CAS
OE
WE
WE
7
8
7
RAS
NC
RAS
NC
8
21 A9
9
9
20
A10
A0
A8
A10
A0
A8
10
11
12
13
14
10
11
12
13
14
19
18
17
16
15
A7
A7
A6
A5
A4
VSS
A1
A6
A1
A2
A5
A2
A3
A4
A3
VCC
VSS
VCC
(Top View)
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Pin Description
Pin
A0-A10
A0-A10
I/O0-I/O7
RAS
Function
Pin
WE
OE
Function
Read/Write Enable
Output Enable
Power (+3.3V)
Ground
Address Inputs
Refresh Address Inputs
Data Input / Data Output
Row Address Strobe
V
CC
V
SS
CAS
Column Address Strobe
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71V(S)17800CJ/CLJ-5
GM71V(S)17800CJ/CLJ-6
GM71V(S)17800CJ/CLJ-7
50ns
60ns
70ns
400 Mil
28 Pin
Plastic SOJ
GM71V(S)17800CT/CLT-5
GM71V(S)17800CT/CLT-6
GM71V(S)17800CT/CLT-7
50ns
60ns
70ns
400 Mil
28 Pin
Plastic TSOP II
Absolute Maximum Ratings
Symbol
TA
Parameter
Rating
0 ~ +70
Unit
C
Ambient Temperature under Bias
TSTG
VIN/OUT
VCC
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Supply Voltage Relative to VSS
Short Circuit Output Current
-55 ~ +125
-0.5 ~ +4.6
C
V
V
-0.5 ~ +4.6
IOUT
50
mA
W
PD
1.0
Power Dissipation
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol
VCC
Parameter
Min
3.0
Typ
Max
3.6
Unit
Supply Voltage
3.3
V
V
V
VIH
Input High Voltage
Input Low Voltage
2.0
-
-
Vcc+0.3
0.8
VIL
-0.3
Note: All voltage referred to Vss.
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
DC Electrical Characteristics (VCC = 3.3V+/-0.3, Vss = 0V, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
V
OH
Output Level
Output "H" Level Voltage (IOUT = -2mA)
2.4
0
V
CC
V
V
Output Level
Output "L" Level Voltage (IOUT = 2mA)
V
OL
0.4
50ns
60ns
70ns
-
-
-
110
100
90
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
I
CC1
mA
mA
mA
1, 2
I
I
CC2
CC3
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
-
2
50ns
60ns
70ns
50ns
-
-
-
110
100
90
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
2
I
CC4
Fast Page Mode Current
Average Power Supply Current
Fast Page Mode
-
-
-
-
100
90
mA
1, 3
60ns
70ns
(tPC = tPC min)
85
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >= VCC - 0.2V, DOUT = High-Z)
I
I
CC5
CC6
1
mA
uA
-
-
-
-
150
5
CAS-before-RAS Refresh Current
(tRC = tRC min)
50ns
60ns
110
100
mA
70ns
90
Battery Back Up Operating Current
(Standby with CBR Refresh)
(tRC=62.5us, tRAS<=0.3us, DOUT=High-Z)
I
I
CC7
CC8
-
-
400
uA
4,5
Standby Current RAS = VIH
CAS = VIL
5
mA
1
5
D
OUT = Enable
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z)
I
CC9
-
250
10
uA
uA
uA
I
L(I)
Input Leakage Current
Any Input (0V<=VIN<= 4.6V)
-10
-10
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 4.6V)
I
L(O)
10
Note: 1. ICC depends on output load condition when the device is selected.
CC(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL
I
.
3. Address can be changed once or less while CAS = VIH
4. CAS = L (<=0.2V) while RAS = L (<=0.2V).
5. L-version.
.
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Capacitance (VCC = 3.3V+/-0.3V, TA = 25C)
Symbol
CI1
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
Max
Unit
pF
Note
1
-
-
-
5
7
7
CI2
pF
1
CI/O
pF
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT
.
AC Characteristics (VCC = 3.3V+/-0.3V, TA = 0 ~ +70C, Vss = 0V, Note 1, 2,18)
Test Conditions
Input rise and fall times : 5 ns
Input timing reference levels : 0.8V, 2.0V
Output timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + CL (100 pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5
C/CL-6
C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
Random Read or Write Cycle Time
RAS Precharge Time
90
30
-
-
110
40
-
-
130
50
-
-
ns
ns
t
RC
tRP
CAS Precharge Time
8
-
10
60
-
13
70
-
ns
t
CP
ns
ns
ns
ns
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
ODD
DZO
DZC
RAS Pulse Width
50 10,000
10,000
10,000
t
CAS Pulse Width
13 10,000 15 10,000 18 10,000
t
Row Address Set up Time
Row Address Hold Time
0
8
0
8
-
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
-
t
t
Column Address Set-up Time
Column Address Hold Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
10
15
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
18 45
13 30
20 45
15 30
20 52
15 35
3
4
t
t
t
13
50
5
-
-
15
60
5
-
-
18
70
5
-
-
CAS Hold Time
t
CAS to RAS Precharge Time
OE to DIN Delay Time
-
-
-
t
t
13
0
-
15
0
-
18
0
-
5
6
6
7
t
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
-
-
-
0
-
0
-
0
-
t
tT
3
50
3
50
3
50
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Read Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
Access Time from RAS
-
-
-
-
50
13
25
13
-
-
-
-
-
60
15
30
15
-
-
-
-
-
70
18
35
18
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8,9
9,10,17
9,11,17
9
t
RAC
CAC
AA
OAC
RCS
RCH
Access Time from CAS
t
Access Time from Address
Access Time from OE
t
t
Read Command Setup Time
Read Command Hold Time to CAS
0
0
t
0
0
-
0
-
0
-
12
12
t
-
-
-
-
-
Read Command Hold Time to RAS
Column Address to RAS Lead Time
5
5
5
t
RRH
RAL
CAL
CLZ
OH
OHO
OFF
OEZ
CDD
25
-
30
35
t
-
Column Address to CAS Lead Time
CAS to Output in Low-Z
25
0
30
0
-
-
35
0
-
-
-
-
t
-
t
3
-
Output Data Hold Time
3
-
3
t
3
-
Output Data Hold Time from OE
Output Buffer Turn-off Time
Output Buffer Turn-off Time to OE
CAS to DIN Delay Time
3
-
3
t
-
-
13
13
-
15
15
-
-
15
15
-
13
13
5
t
-
-
-
t
13
15
18
t
Write Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
14
0
8
-
-
-
-
-
-
-
0
10
10
15
15
0
-
-
-
-
-
-
-
0
15
10
18
18
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WCS
tWCH
8
t
t
WP
RWL
CWL
13
13
0
t
15
15
tDS
Data-in Hold Time
8
10
15
t
D
H
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Read- Modify-Write Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
t
RWC
RWD
CWD
AWD
OEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
131
73
-
-
-
-
-
155
85
-
-
-
-
-
181
98
-
-
-
-
-
ns
ns
ns
ns
ns
t
14
14
14
t
CAS to WE Delay Time
36
40
46
t
Column Address to WE Delay Time
OE Hold Time from WE
48
55
63
t
13
15
18
Refresh Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
t
CSR
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
5
8
0
-
-
-
5
10
0
-
-
-
5
10
0
-
-
-
ns
ns
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tWRP
WE Setup Time
(CAS-before-RAS Refresh Cycle)
t
WRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
10
5
-
-
10
5
-
-
10
5
-
-
ns
ns
tRPC
RAS Precharge to CAS Hold Time
Fast Page Mode Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
35
-
-
40
-
-
45
-
-
ns
ns
ns
ns
t
PC
RASP
ACP
RHCP
Fast Page Mode Cycle Time
100,000
100,000
100,000
Fast Page Mode RAS Pulse Width
16
t
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
-
30
-
-
35
-
-
40
-
9,17
t
30
35
40
t
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Fast Page Mode Read-Modify-Write Cycle
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
PRWC
Fast Page Mode Read-Modify-Write
Cycle Time
76
53
-
-
85
60
-
-
96
68
-
-
ns
tCPW
14
WE Delay Time from CAS Precharge
ns
Refresh
GM71V(S)17800 GM71V(S)17800 GM71V(S)17800
C/CL-5 C/CL-6 C/CL-7
Unit
Symbol
Parameter
Note
Min Max Min Max Min Max
2048
cycles
t
REF
Refresh Period
-
-
32
-
-
32
-
-
32
ms
ms
2048
cycles
tREF
Refresh Period(L-series)
128
128
128
Self Refresh Mode(L-version)
GM71VS17800
CL-5
GM71VS17800
CL-6
GM71VS17800
CL-7
Symbol
Parameter
Unit
Note
Min Max Min Max Min Max
t
RASS
-
-
-
-
-
-
-
-
-
us
ns
RAS Pulse Width(Self-Refresh)
RAS Precharge Time(Self-Refresh)
CAS Hold Time(Self-Refresh)
100
90
100
110
100
130
tRPS
tCHS
-50
-50
-50
ns
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Notes:
1.
AC Measurements assume tT = 5ns
An initial pause of 200uA is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh). if the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
2.
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
3.
4.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
Either tODD or tCDD must be satisfied.
5.
6.
7.
Either tDZO or tDZC must be satisfied.
VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH(min) and VIL(max).
Assumes that tRCD <= tRCD(max) and tRAD <= tRAD(max). If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
Measured with a load circuit equivalent to 1TTL loads and 100pF.(VOH =2.0V , V= 0.8V)
Assumes that tRCD >= tRCD(max) and tRAD <= tRAD(max).
8.
9.
10.
11.
12.
13.
Assumes that tRCD <= tRCD(max) and tRAD >= tRAD(max).
Either tRCH or tRRH must be satisfied for a read cycles.
tOFF(max) and tOEZ(max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
tWCS, tRWD, tCWD and tAWD and tCPW are not restrictive operating parameters. They are included in
the data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write
cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle;
if tRWD>=tRWD(min), tCWD>=tCWD(min), and tAWD>=tAWD(min) or tCWD>=tCWD(min),
14.
tAWD>=tAWD(min), and tCPW>=tCPW(min), the cycle is a read -modify- write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is
satisfied, the condition of the data out (at access time) is indeterminate.
These parameters are referred to CAS leading edge in early write cycle and to WE leading edge
in a delayed write or a read modify write cycle.
15.
tRASP defines RAS pulse width in fast page mode cycles.
16.
17.
18.
Access time is determined by the longer of tAA or tCAC or tACP.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance): if tOEH<=tCWL, invalid data will be out at each I/O.
Rev 0.1 / Apr’01
GM71V17800C
GM71VS17800CL
Unit: Inches (mm)
Package Dimensions
28 SOJ
0.025(0.64)
MIN
0.083(2.10)
MIN
0.710(18.04) MIN
0.720(18.30) MAX
0.128(3.25) MIN
0.148(3.75) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.032(0.81) MAX
0.015(0.38) MIN
0.020(0.50) MAX
28 TSOP (TYPE II)
0 ~ 5¡ £
0.016(0.40) MIN
0.024(0.60) MAX
0.720(18.28) MIN
0.730(18.54) MAX
0.004(0.12) MIN
0.008(0.21) MAX
0.037(0.95) MIN
0.041(1.05) MAX
0.047(1.20)
MAX
0.050(1.27)
TYP
0.012(0.30) MIN
0.020(0.50) MAX
0.003(0.08) MIN
0.007(0.18) MAX
Rev 0.1 / Apr’01
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