GM71CS17803CLJ-6 [ETC]
x8 EDO Page Mode DRAM ; X8 EDO页模式DRAM\n
| 型号： | GM71CS17803CLJ-6 |
| 厂家： | 
ETC |
| 描述： | x8 EDO Page Mode DRAM
|
| 文件： | 总9页 (文件大小：105K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
GM71C17803C
GM71CS17803CL
2,097,152 WORDS x 8 BIT
CMOS DYNAMIC RAM
Description
Features
The GM71C(S)17803C/CL is the new
generation dynamic RAM organized 2,097,152
x 8 bit. GM71C(S)17803C/CL has realized
higher density, higher performance and various
functions by utilizing advanced CMOS process
technology. The GM71C(S)17803C/CL offers
Extended Data out(EDO) Page Mode as a high
speed access mode. Multiplexed address inputs
permit the GM71C(S)17803C/CL to be
packaged in standard 400 mil 28 pin plastic
SOJ, and standard 400mil 28pin plastic TSOP
II. The package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment.
* 2,097,152 Words x 8 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (5V+/-10%)
* Fast Access Time & Cycle Time
(Unit: ns)
tRAC
tCAC
t
RC
tHPC
50
60
70
13
15 104
18 124
84
20
25
30
GM71C(S)17803C/CL-5
GM71C(S)17803C/CL-6
GM71C(S)17803C/CL-7
* Low Power
Active : 715/660/605/550mW (MAX)
Standby : 11mW (CMOS level : MAX)
0.83mW (L-version : MAX)
* RAS Only Refresh, CAS before RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 2048 Refresh Cycles/32ms
* 2048 Refresh Cycles/128ms (L- version)
* Battery Back Up Operation (L- version)
* Self Refresh Operation (L-version)
Pin Configuration
28 SOJ
28 TSOP II
1
2
3
4
5
6
28
27
1
2
3
4
5
6
28
27
VCC
VSS
VCC
VSS
I/O0
I/O1
I/O7
I/O0
I/O1
I/O7
26 I/O6
26 I/O6
25
24
23
22
21
20
19
18
17
16
15
25
24
23
22
I/O2
I/O3
I/O5
I/O4
CAS
OE
A9
I/O2
I/O3
I/O5
I/O4
CAS
OE
WE
WE
7
8
7
RAS
NC
RAS
NC
8
21 A9
9
9
20
A10
A0
A8
A10
A0
A8
10
11
12
13
14
10
11
12
13
14
19
18
17
16
15
A7
A7
A6
A5
A4
VSS
A1
A6
A1
A2
A5
A2
A3
A4
A3
VCC
VSS
VCC
(Top View)
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Pin Description
Pin
A0-A10
A0-A10
I/O0-I/O7
RAS
Function
Pin
WE
OE
Function
Read/Write Enable
Output Enable
Power (+5V)
Address Inputs
Refresh Address Inputs
Data-In/Out
V
CC
V
SS
Ground
Row Address Strobe
Column Address Strobe
CAS
NC
No Connection
Ordering Information
Type No.
Access Time
Package
GM71C(S)17803CJ/CLJ -5
GM71C(S)17803CJ/CLJ -6
GM71C(S)17803CJ/CLJ -7
50ns
60ns
70ns
400 Mil
28 Pin
Plastic SOJ
GM71C(S)17803CT/CLT -5
GM71C(S)17803CT/CLT -6
GM71C(S)17803CT/CLT -7
50ns
60ns
70ns
400 Mil
28 Pin
Plastic TSOP II
Absolute Maximum Ratings*
Symbol
TA
Parameter
Rating
Unit
C
Ambient Temperature under Bias
0 ~ +70
-55 ~ +125
-1.0 ~ +7.0
TSTG
Storage Temperature (Plastic)
Voltage on any Pin Relative to VSS
Supply voltage Relative to VSS
Short Circuit Output Current
C
V
VIN/VOUT
VCC
V
-1.0 ~ +7.0
IOUT
50
mA
W
PT
1.0
Power Dissipation
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Recommended DC Operating Conditions (TA = 0 ~ +70C)
Symbol
VCC
Parameter
Min
4.5
Typ
Max
5.5
Unit
Supply Voltage
5.0
V
V
V
VIH
Input High Voltage
Input Low Voltage
2.4
-
-
6.0
VIL
-1.0
0.8
Note: All voltage referred to Vss.
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
DC Electrical Characteristics (VCC = 5V+/-10%, Vss = 0V, TA = 0 ~ 70C)
Symbol
Parameter
Min Max Unit Note
V
OH
Output Level
Output "H" Level Voltage (IOUT = -2mA)
2.0
0
V
CC
V
V
Output Level
Output "L" Level Voltage (IOUT = 2mA)
V
OL
0.4
50ns
60ns
70ns
-
-
-
130
120
110
I
CC1
Operating Current
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC = tRC min)
mA
mA
mA
1, 2
I
I
CC2
CC3
Standby Current (TTL)
Power Supply Standby Current
(RAS, CAS = VIH, DOUT = High-Z)
-
2
50ns
60ns
70ns
-
-
-
130
120
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(tRC = tRC min)
2
110
130
120
110
1
I
CC4
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
50ns
60ns
70ns
-
-
-
mA
1, 3
(tHPC = tHPC min)
Standby Current (CMOS)
Power Supply Standby Current
(RAS, CAS >VCC - 0.2V, DOUT = High-Z)
I
I
I
CC5
CC6
CC7
-
-
mA
uA
150
5
50ns
60ns
-
-
130
120
CAS-before-RAS Refresh Current
(tRC = tRC min)
mA
uA
70ns
110
-
-
Battery Back Up Operating Current(Standby with CBR Refresh)
(CBR refresh, tRC=62.5us, tRAS<=0.3us,
500
4,5
D
OUT=High-Z ,CMOS interface)
Standby Current RAS = VIH
CAS = VIL
I
I
CC8
CC9
-
5
mA
uA
uA
uA
1
5
D
OUT = Enable
Self-Refresh Mode Current
(RAS, CAS<=0.2V, DOUT=High-Z)
-
300
10
Input Leakage Current
Any Input (0V<=VIN<= 6V)
I
L(I)
-10
-10
Output Leakage Current
(DOUT is Disabled, 0V<=VOUT<= 6V)
I
L(O)
10
Note: 1. ICC depends on output load condition when the device is selected.
CC(max) is specified at the output open condition.
2. Address can be changed once or less while RAS = VIL
I
.
3. Address can be changed once or less while CAS = VIH
4. CAS = L (<=0.2V) while RAS = L (<=0.2V).
5. L-version.
.
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Capacitance (VCC = 5V+/ - 10%, TA = 25C)
Symbol
Parameter
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
Min
Max
Unit
pF
Note
1
CI1
-
-
-
5
7
7
pF
CI2
1
pF
CI/O
1, 2
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable DOUT
.
AC Characteristics (VCC = 5V+/-10%, TA = 0 ~ +70C, Vss = 0V Note 1, 2, 18)
Test Conditions
Input rise and fall times : 2 ns
Input timing reference levels : 0.8V, 2.4V
Output timing reference levels : 0.8V, 2.0V
Output load : 1TTL gate + CL (100 pF)
(Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5
C/CL-6
C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
Random Read or Write Cycle Time
RAS Precharge Time
84
30
-
-
104
40
-
-
124
50
-
-
ns
ns
t
RC
tRP
CAS Precharge Time
7
-
10
60
-
13
70
-
ns
t
CP
ns
ns
ns
ns
t
RAS
CAS
ASR
RAH
ASC
CAH
RCD
RAD
RSH
CSH
CRP
ODD
DZO
DZC
RAS Pulse Width
50 10,000
10,000
10,000
t
CAS Pulse Width
7
0
7
0
10,000 10 10,000 13 10,000
t
Row Address Set up Time
Row Address Hold Time
Column Address Set-up Time
-
-
-
0
10
0
-
-
-
-
0
10
0
-
-
-
-
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Column Address Hold Time
RAS to CAS Delay Time
RAS to Column Address Delay Time
RAS Hold Time
7
11
9
-
37
25
-
10
13
14 45
12 30
14 52
12 35
3
4
t
t
t
10
35
5
13
40
5
-
-
13
45
5
-
-
CAS Hold Time
-
t
CAS to RAS Precharge Time
OE to DIN Delay Time
-
-
-
t
t
13
0
-
15
0
-
18
0
-
5
6
6
7
t
OE Delay Time from DIN
CAS Delay Time from DIN
Transition Time (Rise and Fall)
-
-
-
0
-
0
-
0
-
t
tT
2
50
2
50
2
50
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Read Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
Access Time from RAS
-
-
-
-
50
13
25
13
-
-
-
-
-
60
15
30
15
-
-
-
-
-
70
18
35
18
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
8,9
9,10,17
9,11,17
9
t
RAC
CAC
AA
OAC
RCS
RCH
Access Time from CAS
t
Access Time from Address
Access Time from OE
t
t
Read Command Setup Time
Read Command Hold Time to CAS
0
0
t
0
0
-
0
-
0
-
12
12
t
-
-
-
-
-
Read Command Hold Time to RAS
Column Address to RAS Lead Time
5
5
5
t
RRH
RAL
CAL
CLZ
OH
OHO
OFF
OEZ
CDD
RCHR
25
-
30
35
t
-
Column Address to CAS Lead Time
CAS to Output in Low-Z
15
0
18
0
-
-
23
0
-
-
-
-
t
-
t
3
-
Output Data Hold Time
3
-
3
t
3
-
Output Data Hold Time from OE
Output Buffer Turn-off Time
Output Buffer Turn-off Time to OE
CAS to DIN Delay Time
3
-
3
t
-
-
13
13
-
15
15
-
-
15
15
-
13
13
5
t
-
-
-
t
13
50
3
15
60
18
t
t
-
-
-
-
70
3
Read Command Hold Time from RAS
Output Data hold Time from RAS
Output Buffer turn off to RAS
Output Buffer turn off to WE
-
-
3
-
t
OHR
-
-
-
15
13
15
t
OFR
-
t
WEZ
-
ns
ns
13
-
15
-
15
-
t
WDD
13
15
18
WE to DIN Delay Time
RAS to DIN Delay Time
t
RDD
13
-
15
-
18
-
ns
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Write Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Symbol
Parameter
Unit
Note
Min Max Min Max Min Max
Write Command Setup Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
Data-in Setup Time
14
0
7
7
7
7
0
7
-
-
-
-
-
-
-
0
10
10
10
10
0
-
-
-
-
-
-
-
0
13
10
13
13
0
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
t
WCS
tWCH
t
t
WP
RWL
CWL
t
15
15
tDS
Data-in Hold Time
10
13
tDH
Read- Modify-Write Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
t
RWC
RWD
CWD
AWD
OEH
Read-Modify-Write Cycle Time
RAS to WE Delay Time
111
67
-
-
-
-
-
136
79
-
-
-
-
-
161
92
-
-
-
-
-
ns
ns
ns
ns
ns
t
14
14
14
t
CAS to WE Delay Time
30
34
40
t
Column Address to WE Delay Time
OE Hold Time from WE
42
49
57
t
13
15
18
Refresh Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
t
CSR
CAS Setup Time
(CAS-before-RAS Refresh Cycle)
5
7
0
-
-
-
5
10
0
-
-
-
5
10
0
-
-
-
ns
ns
ns
tCHR
CAS Hold Time
(CAS-before-RAS Refresh Cycle)
tWRP
WE Setup Time
(CAS-before-RAS Refresh Cycle)
t
WRH
WE Hold Time
(CAS-before-RAS Refresh Cycle)
10
5
-
-
10
5
-
-
10
5
-
-
ns
ns
tRPC
RAS Precharge to CAS Hold Time
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
EDO Page Mode Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
t
HPC
EDO Page Mode Cycle Time
20
-
-
25
-
-
30
-
-
ns
ns
ns
ns
ns
19
16
100,000
100,000
100,000
EDO Page Mode RAS Pulse Width
Access Time from CAS Precharge
RAS Hold Time from CAS Precharge
tRASP
-
30
-
-
35
-
-
40
-
9,17
tACP
30
35
40
tRHCP
9
tDOH
Output data Hold Time from CAS low
3
7
5
-
3
10
5
-
3
13
5
tCOL
CAS Hold Time referred OE
CAS to OE Setup Time
-
-
-
-
ns
ns
tCOP
Read command Hold Time
from CAS Precharge
30
-
35
-
ns
tRCHP
40
EDO Page Mode Read-Modify-Write Cycle
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Symbol
Parameter
Unit Note
Min Max Min Max Min Max
t
HPRWC
EDO Page Mode Read-Modify-Write
Cycle Time
57
45
-
-
68
54
-
-
79
62
-
-
ns
ns
14
tCPW
WE Delay Time from CAS Precharge
Refresh
GM71C(S)17803 GM71C(S)17803 GM71C(S)17803
C/CL-5 C/CL-6 C/CL-7
Unit Note
Symbol
Parameter
Min Max Min Max Min Max
2048
ms
t
REF
Refresh period
-
-
32
-
-
32
-
-
32
cycles
2048
ms
Refresh period (L -Series)
128
128
128
tREF
cycles
Self Refresh Mode ( L-version )
GM71CS17803 GM71CS17803 GM71CS17803
CL-5 CL-5 CL-5
Unit
Note
Symbol
Parameter
Min Max Min Max Min Max
RAS Pulse Width ( Self-refresh )
100
-
100
-
100
-
ms
t
RASS
RPS
CHS
RAS Precharge Time ( Self-refresh )
CAS Hold Time ( Self-refresh )
90
-
-
110
-50
-
-
130
-50
-
-
ns
ns
t
-50
t
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Notes:
1. AC Measurements assume tT = 2ns.
2.
An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS only refresh or CAS-before-
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
3.
4.
Operation with the tRCD(max) limit insures that tRAC(max) can be met, tRCD(max) is specified as a
reference point only; if tRCD is greater than the specified tRCD(max) limit, then access time is
controlled exclusively by tCAC.
Operation with the tRAD(max) limit insures that tRAC(max) can be met, tRAD(max) is specified as a
reference point only; if tRAD is greater than the specified tRAD(max) limit, then access time is
controlled exclusively by tAA.
5.
6.
Either tODD or tCDD must be satisfied.
Either tDZO or tDZC must be satisfied.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also,
transition times are measured between VIH (min) and VIL (max).
8.
Assumes that tRCD <= tRCD (max) and tRAD <= tRAD (max). If tRCD or tRAD is greater than the
maximum recommended value shown in this table, tRAC exceeds the value shown.
9.
Measured with a load circuit equivalent to 1TTL loads and 100pF.
Assumes that tRCD >= tRCD (max) and tRAD <= tRAD (max).
Assumes that tRCD <= tRCD (max) and tRAD >= tRAD (max).
Either tRCH or tRRH must be satisfied for a read cycles.
10.
11.
12.
tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition
and are not referred to output voltage levels.
13.
tWCS, tRWD, tCWD , tAWD and tCPW are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if tWCS >=tWCS(min), the cycle is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
tRWD>=tRWD(min), tCWD>=tCWD(min) and tAWD>=tAWD(min), or tCWD>=tCWD(min), tAWD>=tAWD(min)
and tCPW>=tCPW(min), the cycle is a read modify write and the data output will contain data read
from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the
data out (at access time) is indeterminate.
14.
These parameters are referred to CAS leading edge in early write cycle and to WE leading edge
in a delayed write or a read modify write cycle.
15.
tRASP defines RAS pulse width in EDO page mode cycles.
16.
17.
18.
Access time is determined by the longest among tAA , tCAC and tACP.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if tOEH>=tCWL, the I/O pin will remain open circuit (high
impedance): if tOEH<=tCWL, invalid data will be out at each I/O.
19.
tHPC (min ) can be achieved during a series of EDO page mode write cycles or EDO page
mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle
(EDO page mode mix cycle (1)(2) ),minimum value of CAS cycle( tCAS + tCP + 2tT) becomes
greater than the specified tHPC (min) value. The value of CAS cycle time of mixed EDO page
mode is shown in EDO page mode mix cycle(1) and (2).
Rev 0.1 / Apr’01
GM71C17803C
GM71CS17803CL
Unit: Inches (mm)
Package Dimensions
28 SOJ
0.025(0.64)
MIN
0.083(2.10)
MIN
0.710(18.04) MIN
0.720(18.30) MAX
0.128(3.25) MIN
0.148(3.75) MAX
0.050(1.27)
TYP
0.026(0.66) MIN
0.032(0.81) MAX
0.015(0.38) MIN
0.020(0.50) MAX
28 TSOP (TYPE II)
0 ~ 5 o
0.016(0.40) MIN
0.024(0.60) MAX
0.720(18.28) MIN
0.730(18.54) MAX
0.004(0.12) MIN
0.008(0.21) MAX
0.037(0.95) MIN
0.041(1.05) MAX
0.047(1.20)
MAX
0.050(1.27)
TYP
0.012(0.30) MIN
0.020(0.50) MAX
0.003(0.08) MIN
0.007(0.18) MAX
Rev 0.1 / Apr’01
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