GLT41316-60PL [ETC]
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE; 64K ×16的CMOS动态RAM具有快速页面模式
| 型号： | GLT41316-60PL |
| 厂家： | 
ETC |
| 描述： | 64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE |
| 文件： | 总22页 (文件大小：1498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Features :
Description :
The GLT41316 is a 65,536 x 16 bit high-
performance CMOS dynamic random access
memory. The GLT41316 offers Fast Page
mode ,and has both BYTE WRITE and
*
*
65,536 words by 16 bits organization.
Fast access time and cycle time.
WE
Input.
*
*
Dual
Low power dissipation.
RAS
-Only Refresh,
WE
WORD WRITE access cycles via two
*
Read-Modify-Write,
pins. The GLT41316 has symmetric address
and accepts 256-cycle refresh in 4ms
interval.
All inputs are TTL compatible. Fast
Page Mode operation allows random access
up to 256x16 bits, within a page, with cycle
times as short as 18ns.
The GLT41316 is best suited for
graphics, and DSP applications requiring
high performance memories.
CAS -Before-RAS Refresh, Hidden
Refresh and Test Mode Capability.
256 refresh cycles per 4ms.
Available in 40-pin 400 mil SOJ,and 40/44
pin TSOP (II).
*
*
*
*
Single 5.0V±10% Power Supply.
All inputs and Outputs are TTL
compatible. * Fast Page Mode operation.
HIGH PERFORMANCE
30
35
40
45
30 ns
35 ns
40 ns
45 ns
Max. RAS Access Time, (tRAC
)
Max. Column Address Access Time, (tAA)
Min. Fast Page Mode Cycle Time, (tPC)
Min. Read/Write Cycle Time, (tRC)
15 ns
18 ns
65 ns
10 ns
18 ns
21 ns
70 ns
11 ns
20 ns
23 ns
75 ns
12 ns
22 ns
25 ns
80 ns
12 ns
Max. CAS Access Time (tCAC
)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 1 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Pin Configuration :
TSOP(Type II)
Top View
GLT41316
SOJ Top View
Pin Descriptions:
Name
Function
Address Inputs
A0 - A7
RAS
CAS
UW
Row Address Strobe
Column Address Strobe
Read / Upper Byte Write Enable
Read / Lower Byte Write Enable
Output Enable
LW
OE
DQ0 - DQ15
VCC
Data Inputs / Outputs
+5V Power Supply
Ground
VSS
NC
No Connection
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 2 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Absolute Maximum Ratings*
Capacitance*
TA=25°C, VCC=5V±10%, VSS=0V
Operating Temperature, TA (ambient)
Symbol
Parameter
Max. Unit
.......................................-0°C to +70°C
CIN1 Address Input
5
7
7
pF
pF
pF
Storage Temperature(plastic)....-55°C to +150°C
Voltage Relative to VSS...............-1.0V to + 7.0V
Short Circuit Output Current......................50mA
Power Dissipation......................................1.0W
CIN2
RAS CAS UW LW OE
,
,
,
,
COUT
Data Input/Output
*Note: Operation above Absolute Maximum Ratings *Note: Capacitance is sampled and not 100% tested
can adversely affect device reliability.
Electrical Specifications
WE
UW
LW
and .
l
means
l All voltages are referenced to GND.
CAS
RAS
RAS
or -only
l After power up, wait more than 100ms and then, execute eight
-before-
refresh cycles as dummy cycles to initialize internal circuit.
Block Diagram :
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 3 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Truth Table: GLT41316
Function
ADDRESS
DQs
Note
s
RAS
CAS
UW
LW
OE
Standby
H
L
L
X
H
L
X
H
L
X
L
High-Z
H® X
Read: Word
L
ROW/COL Data Out
ROW/COL Data-In
Write: Word(Early Write)
L
L
X
Write: Lower Byte (Early)
Write: Upper Byte (Early)
Read Write
L
H
L
X
ROW/COL Lower Byte,Data-In
Upper Byte,High-Z
L
L
L
H
X
ROW/COL Lower Byte,High-Z
Upper Byte,Data-In
L
L
L
L
ROW/COL Data-Out,Data-In
1,2
1
H® L H® L L® H
Fast-Page-
Mode Read
1st Cycle
2nd Cycle
H
H
H
L
L
ROW/COL Data-Out
H® L
H® L
COL
Data-Out
1
Fast-Page-
Mode Write
1st Cycle
2nd Cycle
L
L
L
L
L
L
X
X
ROW/COL Data-In
COL Data-In
2
2
H® L
H® L
Fast-Page-
Mode Read-
Write
1st Cycle
L
ROW/COL Data-Out,Data-In
1,2
H® L H® L H® L L® H
2nd Cycle
Read
L
COL
Data-Out,Data-In
1,2
1
H® L H® L H® L L® H
Hidden
L
H
H
L
ROW/COL Data-Out
L® H® L
Refresh
Write
L
L
L
X
X
ROW/COL Data-In
2,3
L® H® L
L
H
X
X
ROW
High-Z
High-Z
RAS -Only Refresh
CBR Refresh
L
X
X
X
H® L
Notes:
1. These READ cycles are always WORD READ cycles .
UW
LW
active).
2. These WRITE cycles may also be BYTE READ cycles (either
3. EARLY WRITE only.
or
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 4 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
DC and Operating Characteristics (1-2)
TA = 0°C to 70°C, VCC=5V±10%, VSS=0V, unless otherwise specified.
Sym.
Parameter
Test Conditions
Access Min. Typ Max. Unit Notes
Time
ILI
Input Leakage Current
(any input pin)
-10
+10
0V £ VIN £ 5.5V
(All other pins not under
test=0V)
mA
ILO
Output Leakage Current
(for High-Z State)
-10
+10
0V £ Vout £ 5.5V
Output is disabled (Hiz)
mA
ICC1
Operating Current,
Random READ/WRITE
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
tRC = tRC (min.)
mA
1,2
ICC2
Standby Current,(TTL)
RAS CAS
,
at VIH
4
mA
mA
other inputs ³ VSS
ICC3
Refresh Current,
RAS-Only
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
tRAC = 30ns
tRAC = 35ns
tRAC = 40ns
tRAC = 45ns
180
170
160
150
180
170
160
150
180
170
160
150
RAS
VIH
CAS
cycling,
at
=
2
tRC = tRC (min.)
ICC4
ICC5
ICC6
Operating Current,
EDO Page Mode
RAS CAS
at VIL,
,
mA
mA
1,2
1
address cycling: tPC
tPC(min.)
Refresh Current,
CAS Before RAS
RAS CAS
,
,
address cycling:
tRC = tRC (min.)
Standby Current, (CMOS)
RAS
CAS
³ VCC-0.2V,
³ VCC-0.2V,
2
mA
All other inputs ³ VSS
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-1
2.4
+0.8
VCC+1
0.4
V
V
V
V
3
3
IOL = 4.2mA
IOH = -5mA
VOH Output High Voltage
2.4
Notes:
1. ICC is dependent on output loading when the device output is selected. Specified ICC(max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions specified ICC(max.) is measured with a maximum of
one transition per address cycle in random Read/Write and Fast Page Mode.
3. Specified VIL(min.) is steady state operation. During transitions VIL(min.) may undershoot to -1.0V for a period not
to exceed 20ns. All AC parameters are measured with VIL(min.)³ VSS and VIH(max.)£VCC.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 5 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
AC Characteristics (0°C £ TA £ 70°C, See note 1,2)
Test condition:VCC=5.0V±10%, VIH/VIL=2.4V/0.8V,VOH/VOL=2.4V/0.4V
Parameter
tRAC = 30 ns tRAC = 35 ns tRAC = 40 ns tRAC = 45 ns
Symbo MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes
l
Read/Write Cycle Time
Read Midify Write Cycle Time
tRC
tRWC
tRAC
65
80
-
-
-
30
70
99
-
-
-
35
75
105
-
-
-
40
80
110
-
-
-
45
ns
ns
ns 3,4
RAS
Access Time from
Access Time from
tCAC
-
10
15
-
11
-
12
-
12
ns 3,4
ns 3,4
CAS
Access Time from Column Address
tAA
tCLZ
-
0
-
0
18
-
-
0
20
-
-
0
22
-
ns
3
7
2
CAS
to Output in Low-Z
tOFF
3
8
3
8
3
8
3
8
ns
CAS
Output Buffer Turn-off Delay from
Transition Time(Rise and Fall)
tT
tRP
3
25
50
-
3
25
50
-
3
25
50
-
3
25
50
-
ns
ns
RAS
RAS
RAS
CAS
CAS
RAS
RAS
CAS
Precharge Time
Pulse Width
Hold Time
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
30
10
30
100k
35
12
36
100k
40 100K 45 100K ns
-
-
-
-
12
40
-
-
13
46
-
-
ns
ns
Hold Time
10 10000 12 10000 12 10000 13 10000 ns
Pulse Width
13
10
5
20
15
-
17
12
5
24
17
-
18
13
5
28
20
-
18
13
5
33
23
-
ns
ns
ns
4
4
8
CAS
to
to Column Address Delay Time
RAS
Delay Time
to
Precharge Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time Referenced
tASR
tRAH
tASC
tCAH
tAR
0
7
0
6
26
-
-
-
-
-
0
7
0
6
30
-
-
-
-
-
0
8
0
6
34
-
-
-
-
-
0
8
0
6
39
-
-
-
-
-
ns
ns
ns
ns
ns
RAS
to
Column Address Lead Time Referenced tRAL
RAS
15
-
18
-
20
-
23
-
ns
to
Read Command Setup Time
Read Command Hold Time Referenced tRRH
RAS
tRCS
0
0
-
-
0
0
-
-
0
0
-
-
0
0
-
-
ns
ns
9
9
to
Read Command Hold Time Referenced tRCH
CAS
0
-
0
-
0
-
0
-
ns
to
WE
tWCH
6
-
-
6
-
-
6
-
-
6
-
-
ns
ns
10
5
CAS
Hold Time Referenced to
Write Command Hold Time Referenced
RAS
tWCR
26
30
34
39
to
WE
tWP
6
-
6
-
6
-
6
-
ns
10
Pulse Width
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 6 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Parameter
tRAC = 30 ns tRAC = 35 ns tRAC = 40 ns tRAC = 45 ns
Symbo MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Unit Notes
l
tRWL
10
-
11
-
12
-
12
-
ns
WE
WE
RAS
CAS
Lead Time Referenced to
Lead Time Referenced to
tCWL
10
-
11
-
12
-
12
-
ns
Data-In Setup Time
Data-In Hold Time
tDS
tDH
tDHR
0
7
27
-
-
-
0
7
31
-
-
-
0
8
36
-
-
-
0
8
41
-
-
-
ns
ns
ns
11
11
6
RAS
Data Hold Time Referenced to
tWCS
tRWD
tCWD
tAWD
tCSR
0
-
-
-
-
-
0
-
-
-
-
-
0
-
-
-
-
-
0
-
-
-
-
-
ns
ns
ns
ns
ns
5
5
5
5
WE
Setup Time
47
24
29
5
58
29
36
5
63
30
38
5
68
30
40
5
RAS
CAS
WE
WE
to
to
Delay Time
Delay Time
WE
Column Address to
Delay Time
CAS CAS
Setup Time(
Refresh)
RAS
before
tCHR
10
-
10
-
10
-
10
-
ns
CAS
Hold Time(
Refresh)
CAS
RAS
before
tRPC
tCPT
5
-
-
5
-
-
5
-
-
5
-
-
ns
ns
RAS
CAS
to
Precharge Time
20
20
20
20
CAS
Precharge Time(CBR Counter Test
Cycle)
tCPA
-
18
-
21
-
23
-
25
ns
3
CAS
Access Time from
Precharge
Fast Page mode Read/Write Cycle Time
tPC
18
48
-
-
21
60
-
-
23
63
-
-
25
65
-
-
ns
ns
Fast Page mode Read Modify Write
Cycle Time
tPRWC
tCP
5.5
30
25
-
-
6
35
25
-
-
7
40
25
-
-
7
45
30
-
-
ns
ns
ns
ns
ns
ns
CAS
RAS
RAS
Precharge Time(Fast Page mode)
Pulse Width(Fast Page mode)
100K
100K
tRASP
tRHCP
tOEA
tOED
tOEZ
100k
100k
-
10
-
-
11
-
-
12
-
-
12
-
CAS
Hold Time from
Precharge
OE
Access Time from
OE
8
8
8
8
to Delay Time
Output Buffer Turn-off Delay Time from
3
8
3
8
3
8
3
8
7
OE
tOEH
tWHR
tREF
6
15
-
-
-
6
15
-
-
-
7
15
-
-
-
7
15
-
-
-
ns
ns
OE
Hold Time
WE
Hold Time(Hidden Refresh Cycle)
Refresh Time(256cycles)
4
4
4
4
ms
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 7 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Notes
RAS
CAS
only Refresh or
1. An initial pause of 100ms is required after power-up followed by any 8
RAS
before
Refresh cycles to initialize the internal circuit.
2. VIH(min.) and VIL(min.) are reference levels for measuring timing of input signals. Transition times
are measured between VIH(min.) and VIL(max.), AC measurements assume tT = 3ns.
3. Measured with an equivalent to 2 TTL loads and 100pF.
4. For read cycles, the access time is defined as follows:
Input Conditions
RAD £ tRAD(MAX.) and tRCD £ tRCD(MAX.)
Access Time
tRAC(MAX.)
t
tAA(MAX.)
tRAD(max.)< tRAD and tRCD £ tRCD(MAX.)
tRCD(max.)< tRCD
tCAC(MAX.)
tRAD(MAX.) and tRCD(MAX.) indicate the points which the access time changes and are not the limits of
operation.
5. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data
sheet
as electric characteristics only. If tWCS ³ tWCS(min.), the cycle is an early write cycle and the data output
will remain high impedance for the duration of the cycle. If tCWD ³ tCWD(min.),tRWD ³ tRWD (min.) and
tAWD ³ tAWD(min.), then the cycle is a read-modify-write cycle and the data output will contain the data
read from the selected address. If neither of the above conditions is satisfied, the condition of the
data
out is indeterminate.
6. tAR, tWCR, and tDHR are referenced to tRAD(max.)
.
7. tOFF(max.) and tOEZ(max.) define the time at which the output achieves the open circuit condition and are
not referenced to VOH or VOL.
RAS CAS
cycle preceded by any cycles.
8. tCRP(min) requirement should be applicable for
,
9. Either tRCH(min.) or tRRH(min.) must be satisfied for a read cycle.
10. tWP(min.) is applicable for late write cycle or read modify write cycle. In early write cycles, tWCH(min.)
should be satisfied.
CAS
WE
falling edge in
11.This specification is referenced to
late write or read modify write cycles.
falling edge in early write cycles and to
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 8 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Read Cycle
Note : DIN = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 9 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Early Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 10 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Late Write Cycle (OE Controlled Write)
NOET : DOUT = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 11 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Read - Modify - Write Cycle
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 12 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Read Cycle
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 13 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Early Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 14 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Mode Late Write Cycle
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 15 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Fast Page Read-Modify-Write Cycle
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 16 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
CAS Before RAS Refresh Cycle
RAS-Only Refresh Cycle
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 17 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Hidden Refresh Cycle ( Read )
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 18 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Hidden Refresh Cycle ( Write )
NOTE : DOUT = OPEN
UW,LW
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 19 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Ordering Information
Part Number
SPEED
30ns
35ns
40ns
45ns
30ns
35ns
40ns
45ns
POWER
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
FEATURE
FPM
PACKAGE
GLT41316-30J4
GLT41316-35J4
GLT41316-40J4
GLT41316-45J4
GLT41316-30TC
GLT41316-35TC
GLT41316-40TC
GLT41316-45TC
SOJ 400mil 40L
SOJ 400mil 40L
SOJ 400mil 40L
SOJ 400mil 40L
TSOP 400mil 44L
TSOP 400mil 44L
TSOP 400mil 44L
TSOP 400mil 44L
FPM
FPM
FPM
FPM
FPM
FPM
FPM
Parts Numbers (Top Mark) Definition :
GLT 4 13
16 - 40 J4
PACKAGE
4 : DRAM
6 : Standard
SRAM
7 : Cache SRAM
8 : Synchronous
Burst SRAM
-SRAM
064 : 8K
256 : 256K
512 : 512K
100 : 1M
-DRAM
10 : 1M(C/EDO)*
11 : 1M(C/FPM)*
12 : 1M(H/EDO)*
13 : 1M(H/FPM)*
20 : 2M(EDO)
21 : 2M(FPM)
40 : 4M(EDO)
41 : 4M(FPM)
80 : 8M(EDO)
81 : 8M(FPM)
*See note
CONFIG.
04 : x04
08 : x08
16 : x16
32 : x32
SPEED
-SRAM
T : PDIP(300mil)
TS : TSOP(Type I)
TC : TSOP(Type ll)
PL : PLCC
FA : 300mil SOP
FB : 330mil SOP
FC : 445mil SOP
J3 : 300mil SOJ
J4 : 400mil SOJ
P : PDIP(600mil)
Q : PQFP
12 : 12ns
15 : 15ns
20 : 20ns
70 : 70ns
-DRAM
30 : 30ns
35 : 35ns
40 : 40ns
45 : 45ns
50 : 50ns
60 : 60ns
VOLTAGE
Blank : 5V
L : 3.3V
TQ : TQFP
M : Mix Voltage
Ù
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Note : C CDROM , H HDD.
Example :
1.GLT710008-15T 1Mbit(128Kx8)15ns 5V SRAM PDIP(300mil)Package type.
2.GLT44016-40J4 4Mbit(256Kx16)40ns 5V DRAM SOJ(400mil)Package type.
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 20 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
Package Information
400mil 40 pin Small Outline J-form Package (SOJ)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 21 -
G-LINK
GLT41316
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE
June 1998 (Rev 2)
40/44 Lead Thin Small Outline Package TSOP(Type II)
G-Link Technology Corporation
2701Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
G-Link Technology Corporation, Taiwan
2F, No.12, R&D Rd. II, Science-Based Industrial Park,
Hsin Chu, Taiwan, R.O.C.
- 22 -
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