ETHERNET-10_技术文档

Ethernet-10 Core

Technical Manual

February 1997

®

Order Number R14006

ii

February 1997 - Rev. A

This document is preliminary. As such, it contains data derived from functional

simulations and performance estimates. LSI Logic has not veriﬁed either the

functional descriptions, or the electrical and mechanical speciﬁcations using

production parts.

Document DB14-000063-00, First Edition (February 1997)

This document describes revision A of LSI Logic Corporation’s Ethernet-10

(E-10) Core and will remain the ofﬁcial reference source for all revisions/releases

of this product until rescinded by an update.

To receive product literature, call us at 1.800.574.4286 (U.S. and Canada);

+32.11.300.531 (Europe); 408.433.7700 (outside U.S., Canada, and Europe)

and ask for Department JDS; or visit us at http://www.lsilogic.com.

LSI Logic Corporation reserves the right to make changes to any products herein

at any time without notice. LSI Logic does not assume any responsibility or

liability arising out of the application or use of any product described herein,

except as expressly agreed to in writing by LSI Logic; nor does the purchase or

use of a product from LSI Logic convey a license under any patent rights,

copyrights, trademark rights, or any other of the intellectual property rights of LSI

Logic or third parties.

TRADEMARK ACKNOWLEDGMENT

LSI Logic logo design, CoreWare, are registered trademarks and G10, and Right-

First-Time are trademarks of LSI Logic Corporation. All other brand and product

names may be trademarks of their respective companies.

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

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February 1997 - Rev. A

Contents

Preface

Chapter 1

Introduction

1.1

1.2

CoreWare Program

Local Area Networks Overview

1.2.1 Ethernet Standards

1-1

1-3

1.3

1.4

General Description

Features

1-4

1-8

1.4.1

1.4.2

1.4.3

1.4.4

1.4.5

General Features and Beneﬁts

1-8

Media Access Control (MAC) Features

Encoder/Decoder (ENDEC) Features

Twisted-Pair Transceiver Interface Features

Attachment Unit Interface Features

1-8

1-9

1-10

1.5

Other Key E-10 Features

Chapter 2

Signal Descriptions

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

Logic Symbol

2-1

2-3

Transceiver Interface Signals

Receiver Signals

2-6

Receiver Status Signals

Multicast Filter Signals

Transmitter Signals

2-8

2-9

2-10

2-13

2-15

2-17

Transmitter Status Signals

General MAC Signals

Timing and Test Signals

Chapter 3

E-10 Functional Description

3.1 Media Access Control (MAC)

3-1

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Ethernet-10 (E-10) Core Technical Manual

February 1997 - Rev. A

3.1.1

3.1.2

3.1.3

Frame Data Encapsulation and Decapsulation

Frame Transmission

3-1

3-4

Frame Reception

3-9

3.2

3.3

Encoder/Decoder (ENDEC)

3.2.1 PLL Characteristics

Twisted-Pair Interface

3-13

3-14

3-16

3-19

3-20

3-21

3-23

3-25

3.3.1

3.3.2

3.3.3

3.3.4

3.3.5

4-Wire Twisted-Pair Interface

8-Wire Twisted-Pair Interface

Squelch

Link Test Function

Polarity Detection And Correction

3.4

Attachment Unit Interface (AUI)

3.4.1

3.4.2

3.4.3

6-Wire AUI Interface

9-Wire AUI Interface

Signal Quality Error (SQE) Function (Heartbeat)

Chapter 4

Functional Timing

4.1

MAC Transmission and Reception Timing

4-1

4.1.1

4.1.2

4.1.3

MAC Transmission Timing

MAC Reception Timing

ENDEC Timing

4-5

4-9

4.2

4.3

E-10 Clock Timing

4-10

4-11

4-12

Multiple Core Clocking

4.3.1

4.3.2

4.3.3

4.3.4

Core Clocks

80-MHz Clock

10- and 20-MHz Clocks

E-10 Testing

Chapter 5

Speciﬁcations

5.1

5.2

5.3

Derivation of AC Timing and Loading

AC Timing

5-1

5-4

Pin Summary

Appendix A

Glossary

Customer Feedback

vi

Contents

February 1997 - Rev. A

Figures

1.1

1.2

2.1

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Ethernet-10 MAC Relationship to the OSI Model

E-10 Block Diagram

1-3

1-7

E-10 Logic Symbol

2-2

MAC Frame Format

3-2

Alternate One-Zero Manchester Encoding

Host Multicast Filter Implementation

4-Wire Twisted-Pair Interface Using Mixed Signal Cores

8-Wire Twisted-Pair Interface

Manchester Encoding

3-3

3-11

3-15

3-17

3-18

3-19

3-21

3-22

3-24

4-2

Squelch Signal

10BASE-5 AUI Connection

AUI 6-Wire Interface

3.10 AUI 9-Wire Interface

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

Successful Transmission

Transmission Aborted by a Collision

Transmission Aborted by TABORTP

Successful Reception

4-3

4-4

4-5

Reception With No Individual Address Filter Match

Reception With External Multicast Filter Match

Reception With No External Multicast Filter Match

Twisted Pair Serial Output Data

4-6

4-7

4-8

4-9

Twisted Pair Link Integrity Pulses

4-9

4.10 E-10 Clock Buffers

4-10

4-13

5-4

4.11 Multiple-Core Clock Multiplexing

5.1

5.2

A.1

E-10 Core Setup and Hold Timing Diagram

E-10 Core Reset Timing Diagram

Router OSI Interconnect Level

5-4

A-7

Tables

5.1

5.2

E-10 Core AC Timing Parameters

E-10 Pin Summary

5-2

5-5

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

viii

Contents

February 1997 - Rev. A

Preface

This book is the primary reference and Technical Manual for the

Ethernet-10 Core. It contains a complete functional description for the

E-10 core and includes complete physical and electrical speciﬁcations.

Audience

This document assumes that you have some familiarity with

microprocessors and related support devices. The people who beneﬁt

from this manual are:

♦

Engineers and managers who are evaluating the E-10 core for

possible use in value-added local area network (LAN) applications,

such as network hubs, routers, and adapter cards

♦

Engineers with motherboard designs requiring system integration of

an Ethernet core function

Organization

This document has the following chapters and appendixes:

♦

Chapter 1, Introduction, describes the general characteristics and

capabilities of the E-10 core.

Chapter 2, Signal Descriptions, describes each of the input and

output signals of the E-10 core.

Chapter 3, E-10 Functional Description, provides information on

the architecture and functional blocks of the E-10 core.

Chapter 4, Functional Timing, provides a detailed description of the

E-10 Media Access Control (MAC) timing and the E-10 clock timing.

Chapter 5, Speciﬁcations, contains the complete electrical and

mechanical speciﬁcations of the E-10 core.

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

♦

Appendix A, Glossary, gives a list of terms applicable to the E-10

core.

Appendix B, Customer Feedback, includes a form that you may use

to fax us your comments about this document.

Related Publications

IEEE Standard 802.3 10 Mbits/s Ethernet Speciﬁcation

CoreWare® Mixed Signal 10 Mbits/s Ethernet Transceiver for 10BASE-T

and AUI Datasheet, Order Number R15003

Conventions Used in This Manual

The ﬁrst time a word or phrase is used in this manual, it is italicized. See

the glossary at the end of this manual for deﬁnitions of italicized words.

The word assert means to drive a signal true or active. The word

deassert means to drive a signal false or inactive.

The following signal naming conventions are used throughout this

manual:

♦

A signal whose name ends with a P (positive) is true or valid when

the signal is HIGH.

A signal whose name ends in an N (negative) is true or valid when

the signal is LOW.

If a signal can be either active-HIGH or active-LOW and is an input, the

signal name ends in I (input).

If a signal can be either active-HIGH or active-LOW and is an output,

the signal name ends in O (output).

The following register bit conventions are used throughout this manual:

♦

A register bit that is set has a binary value of one.

A register bit that is cleared has a binary value of zero.

Hexadecimal numbers are indicated by the preﬁx “0x” before the

number—for example, 0x32CF. Binary numbers are indicated by the

preﬁx “0b” before the number—for example, 0b0011.0010.1100.1111.

x

Preface

February 1997 - Rev. A

Chapter 1

Introduction

LSI Logic’s CoreWare® library consists of leading-edge microprocessors,

ﬂoating-point processors, digital signal processing (DSP) functions, and

peripheral functions. Designers can combine CoreWare building blocks

with other LSI Logic library elements to implement highly integrated

systems in silicon for a wide variety of applications. This document

describes the function, operation, and features of the Ethernet-10 (E-10)

building block that is part of the CoreWare library.

This chapter provides an overview of LSI Logic’s CoreWare program and

the CoreWare building blocks, introduces some networking concepts,

describes in general terms the E-10 core, and then provides a summary

of the core’s features.

The chapter contains the following sections:

♦

Section 1.1, “CoreWare Program”

Section 1.2, “Local Area Networks Overview”

Section 1.3, “General Description”

Section 1.4, “Features”

1.1 CoreWare Program

An LSI Logic core is a fully deﬁned, optimized, and reusable block of

logic. It supports industry-standard functions and has predeﬁned timing

and layout. The core is also an encrypted RTL simulation model for a

wide range of VHDL and verilog simulators.

The CoreWare library contains an extensive set of complex cores for the

communications, consumer, and computer markets. The library consists

of high-speed interconnect functions such as the GigaBlaze G10™-p

core, MIPS embedded microprocessors, MPEG-2 decoders, a PCI core,

and many more.

Ethernet-10 (E-10) Core Technical Manual

1-1

February 1997 - Rev. A

The library also includes megafunctions or building blocks, which provide

useful functions for developing a system on a chip. Through the

CoreWare program, you can create a system on a chip uniquely suited

to your applications.

Each core has an associated set of deliverables, including:

♦

RTL simulation models for the Verilog and HDL environments

A System Veriﬁcation Environment (SVE) for RTL-based simulation

Synthesis and timing shells

Netlists for full timing simulation

Complete documentation

LSI Logic ToolKit support

LSI Logic's ToolKit provides seamless connectivity between products

from leading electronic design automation (EDA) vendors and LSI Logic's

manufacturing environment. Standard interfaces for formats and

languages such as VHDL, Verilog, Waveform Generation Language

(WGL), Physical Design Exchange Format (PDEF), and Standard Delay

Format (SDF) allow a wide range of tools to interoperate within the

LSI Logic ToolKit environment. In addition to design capabilities, full scan

Automatic Test Pattern Generation (ATPG) tools and LSI Logic's

specialized test solutions can be combined to provide high-fault coverage

test programs that assure a fully functional design.

Because your design requirements are unique, LSI Logic is ﬂexible in

working with you to develop your system-on-a-chip CoreWare design.

Three different work relationships are available:

♦

You provide LSI Logic with a detailed speciﬁcation and LSI Logic

does all of the design

You design some functions while LSI Logic provides you with the

cores and megafunctions, and LSI Logic completes the integration

You perform the entire design and integration, and LSI Logic

provides the core and associated deliverables

Whatever the working relationship, LSI Logic’s advanced CoreWare

methodology and ASIC process technologies consistantly produce

Right-First-Time™ silicon.

1-2

Introduction

February 1997 - Rev. A

1.2 Local Area Networks Overview

If you are already familiar with networking and local area networks, you

may skip this section and proceed directly to Section 1.3 on page 1-4.

1.2.1 Ethernet Standards

Standards organizations govern the development of speciﬁcations for

Ethernet LAN technology. The standard having the greatest inﬂuence

over LAN design and speciﬁcations is the ANSI/IEEE 802.3 Ethernet

standard, which is available from the IEEE in published form.

Each major LAN system technology has gained acceptance by the

IEEE 802 Standards Committee. The IEEE 802 standards are compati-

ble with the International Standards Organization’s (ISO) Open System

Interconnect (OSI) reference model, shown in Figure 1.1.

Figure 1.1 Ethernet-10 MAC Relationship to the OSI Model

OSI

REFERENCE

MODEL

LAN

CSMA/CD

LAYERS

HIGHER LAYERS

APPLICATION

LLC - LOGICAL LINK

CONTROL

PRESENTATION

MAC - MEDIA ACCESS

CONTROL

SESSION

RECONCILIATION

MII

TRANSPORT

NETWORK

DATA LINK

PCS

PMA

PMD

PHY

E-10

Core

PHYSICAL

MDI

MEDIUM

MDI = Media-Dependent Interface

MII = Media-Independent Interface

PCS = Physical Coding Sublayer

PMA = Physical Medium Attachment

PHY = Physical Layer Device

PMD = Physical Medium Dependent

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

The E-10 core complies with the Media Access Control (MAC) sublevel

within the Data Link layer of the OSI reference model and also contains

a Manchester Encoder/Decoder (ENDEC) and transceivers for

10BASE-T or AUI interfaces. The ENDEC and transceivers are part of

the Physical layer of the OSI model.

1.3 General Description

The IEEE 802.3 E-10 core provides the designer ﬂexibility in integrating

an Ethernet port into an LSI Logic application-speciﬁc design. An

Ethernet port includes the following:

♦

Media Access Control (MAC)

Manchester Encoder/Decoder (ENDEC)

Network Transceivers

The E-10 core is part of the LSI Logic CoreWare Library. The CoreWare

program provides the critical building blocks, CAD tools, and applications

support necessary to achieve high levels of system integration and

product differentiation using LSI Logic’s Right-First-Time ASIC design

methodology.

As a CoreWare product, the E-10 core provides a highly-integrated

Ethernet core implementation using submicron CMOS process

technology. This optimization of size and functionality enables designers

to easily integrate multiple Ethernet cores onto a single chip.

The E-10 core is fully synchronous, therefore providing predictable and

reliable operation.

The E-10 core processes data at 10 Mbit/s at half-duplex and 10 Mbit/s

simultaneously in each direction in full-duplex mode, provides a

comprehensive solution for 10BASE-T based systems, and is designed

for easy interface to 10BASE-2, 10BASE-5, or 10BASE-F (ﬁber) media

through an Attachment Unit Interface (AUI). The E-10 core engine gives

the designer a very effective systems integration building block for

developing next-generation networking products for switched hub or

router applications. The E-10 core also enables the highest form of

system integration for workstation or high-end PCs by converting all the

I/O and system logic into a single-chip motherboard solution.

1-4

Introduction

February 1997 - Rev. A

The functional blocks within the E-10 core are:

♦

Media Access Control (MAC). The Media Access Control function

provides simple and independent frame transmission and reception

control by means of parallel eight-bit data interfaces.

♦

Manchester Encoder/Decoder (ENDEC). The E-10 core contains an

integrated ENDEC function that performs Manchester encoding and

decoding and utilizes a digital phase-locked loop for decoding data

at 10 Mbit/s.

♦

Network Transceivers. LSI Logic provides two methods for integrating

AUI/TP transceivers:

–

LSI library cells (best for single-port applications)

Mixed signal cells (best for multiport applications)

Ethernet-10 (E-10) Core Technical Manual

1-5

February 1997 - Rev. A

LSI Logic provides the following mixed signal cores for interfacing to

a network:

–

10BASE-T/AUI driver

10BASE-T/AUI receiver

Bias generator.

These cores perform all the analog interface functions for a 10BASE-T

four-wire twisted pair or AUI six-wire connection, reduce requirements for

external components, and reduce emissions, which is especially useful

for multiport devices. The E-10 core provides inputs and outputs that are

easily connected to the mixed signal cores, which are compatible with

IEEE 802.3 networks. The core has pins that can be connected to an

8-wire twisted-pair interface or a 9-wire AUI interface using transmit

drivers and differential receivers.

Figure 1.2 is a block diagram of the E-10 core.

1-6

Introduction

February 1997 - Rev. A

Figure 1.2 E-10 Block Diagram

1

10BASE-2, 10BASE-5, or 10BASE-F Network

Medium Attachment Unit (MAU)

Attachment Unit Interface (AUI)

Transceivers

E-10 Core

Predistort Shaping

and Link Integrity

Generation

Squelch and Link

Integrity Detection

Manchester Encoder/Decoder (ENDEC)

Function

Phase-Locked Loop

Data Recovery Unit

Manchester Encoder

Media Access Control (MAC)

Function

802.3 Receive Engine

- CRC and Other Error Checking

- Collision Detection Unit

802.3 Transmit Engine

- CRC Generation

- Deferral and Collision Backoff Control

Control

Host Interface Unit

1. With the proper transceiver implementation, the E-10 can be compatible with 10BASE-F, 10BASE-FL and 10BASE-FX.

Ethernet-10 (E-10) Core Technical Manual

1-7

February 1997 - Rev. A

1.4 Features

This section summarizes the key features of the E-10 core.

1.4.1 General Features and Beneﬁts

The E-10 core contains the following general features and associated

beneﬁts:

♦

Certiﬁcation to IEEE 802.3 Ethernet requirements by a recognized

Ethernet Interoperability Lab. Compliance with other Ethernet

products at the MAC and PHY layers of the OSI Model is assured.

Deep submicron CMOS process technology. Submicron technology

allows optimized core size and functionality, which enables

integration of multiple cores.

System Veriﬁcation Environment (SVE) for E-10 simulation. Verilog

SVE allows designers to rapidly simulate with the E-10 core, and

includes an Ethernet emulator, packet analyzer, and host interface

bus emulator for performing system analysis.

♦

VHDL and Verilog HDL simulation model support.

LSI Logic-created core test vectors. The core test vectors are

guaranteed to provide a minimum 95% fault coverage.

♦

CoreWare engineering support for applications, development, and

test needs. Expert engineering assistance is available for integrating

the E-10 core into an ASIC design.

1.4.2 Media Access Control (MAC) Features

The MAC contains the following features:

♦

IEEE 802.3 Ethernet standards compliance

Functionality at the MAC sublevel of OSI layer 2

Support for an external Multicast Hash ﬁlter

Automatic internal Frame Check Sequence (FCS) generator and

checker

1-8

Introduction

February 1997 - Rev. A

♦

Programmable source address insertion

Programmable pad insertion

Separate, parallel eight-bit host interfaces for transmit and receive data

1.4.3 Encoder/Decoder (ENDEC) Features

The ENDEC contains the following features:

♦

Manchester encoding/decoding

10 Mbit/s receive or transmit (half-duplex)

10 Mbit/s receive and transmit (full-duplex—twisted-pair mode only)

–

♦

Frame decoding up to 4,500 bytes

Digital phase-locked loop with synchronous data recovery

Manchester data decoding of incoming signals containing up to ± 18

ns of jitter

♦

PLL with fast lock time (seven bit times)—one bit at 10 Mbit/s equals

100 ns

Randomized collision backoff algorithm

1.4.4 Twisted-Pair Transceiver Interface Features

The E-10 twisted-pair transceiver interface has the following features:

♦

Integrated transceiver, which provide:

Transmitter and receiver (four-wire or eight-wire interface) for

–

10BASE-T

–

Collision detection

Link integrity test

♦

Internal loopback test capability

Link polarity detection and correction

Smart receive squelch for receive data

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

1.4.5 Attachment Unit Interface Features

The E-10 AUI interface contains the following features:

♦

Signal Quality Error test (Heartbeat)

Smart receive squelch for receive data

♦

Smart SQE squelch for collision detection

10BASE-2, 10BASE-5, or 10BASE-F interface

1.5 Other Key E-10 Features

Following are some additional key features of the E-10 core:

Three Address Filtering Modes:

♦

–

Individual address ﬁltering (matches 48-bit destination address

to 48-bit host-supplied address)

Multicast address ﬁltering (provides nine-bit polynomial output for

matching by an external multicast hashing table)

Promiscuous address ﬁltering (matches to any individual

address)

♦

Status Pins

–

Frame size checking/runt frame detection

Dribble bit error

Frame check sequence error

Phase-locked loop error

1-10

Introduction

February 1997 - Rev. A

Chapter 2

Signal Descriptions

This chapter provides detailed descriptions of the E-10 signals. These

descriptions are useful for designers who are interfacing the E-10 core

with other core logic or logic external to the core. This chapter contains

the following sections:

♦

Section 2.1, “Logic Symbol”

Section 2.2, “Transceiver Interface Signals”

Section 2.3, “Receiver Signals”

Section 2.4, “Receiver Status Signals”

Section 2.5, “Multicast Filter Signals”

Section 2.6, “Transmitter Signals”

Section 2.7, “Transmitter Status Signals”

Section 2.8, “General MAC Signals”

Section 2.9, “Timing and Test Signals”

Please see the subsection entitled “Conventions Used in This Manual,”

in the preface of this manual for a description of how signals are named.

2.1 Logic Symbol

The logic diagram for the E-10 core is shown in Figure 2.1.

Ethernet-10 (E-10) Core Technical Manual

2-1

February 1997 - Rev. A

Figure 2.1 E-10 Logic Symbol

E-10 Core

Transceiver Interface

DATAP

DATAN

PREEP

PREEN

DATAI

DATATP

DATATN

COLLINP

COLLINN

LCORPP

LFORCEP

DRIVEENN

LPBADP

LPASSP

Receiver

RLOCKEDP

RCVNGP

RENABP

RMCENP

RDONEP

RPMENP

RSNOOPENP

RCLEANP

RBYTEP

RDATAO[7:0]

RSPLLEP

RSFCSEP

Status RSDRBLEP

RSMATIP

RSMATMP

RSTARTP

Multicast Filter

MDONEP

MBITP

MSTARTP

MINDEXO[8:0]

Transmitter

TRNSMTP

TSTARTP

TDONEP

TAVAILP

TFINISHP

TDATAI[7:0]

TLASTP

TREADDP

TSECOLP

TSLCOLP

TSMCOLP

TSOCOLP

TSSQEEP

TSNCLBP

TSIDEFP

TABORTP

TCTRI[3:0]

Status

General MAC Functions

SELIO

COLLOUTP

NOADDRI[47:0]

TP/AUI

DUPLEXP

LOOPBKP

Timing/Test Functions

CLK80I

CLK20I

CLK10I

RESETN

TEST1N

TEST2N

CLK20O

CLK10O

TESTSO

TMODE

TESTSEP

TESTSIP

FASTESTN

GNDN

VCC

2-2

Signal Descriptions

February 1997 - Rev. A

2.2 Transceiver Interface Signals

The E-10 transceiver interface signals connect to Ethernet transceivers

or transceiver control lines that are external to the E-10 core. The

descriptions of each individual signal are given below.

COLLINN

COLLINP

DATAI

Negative Collision Threshold

Input

COLLINN is one of two pins (the other is COLLINP) used

to detect collisions. It is used for the AUI mode only and

must be connected to the negative threshold output of the

off-core collision differential receiver.

Positive Collision Threshold

Input

COLLINP is one of two pins (the other pin is COLLINN)

used to detect collisions. It is used for the AUI mode only

and must be connected to the positive threshold output

of the off-core collision differential receiver.

Data In

Input

This input pin receives the serial data from the network

and is used by the E-10 ENDEC PLL logic for data

recovery. It should be connected to the zero offset output

of the off-core differential input data receiver.

DATAP

Data Positive

Output

The E-10 core ENDEC transmits positive Manchester-

encoded data on the DATAP pin. DATAP is used in

conjunction with the PREEP signal and operates in both

AUI and TP modes. DATAP must be connected to the

data input of the off-core transmit driver.

DATAN

Data Negative

Output

The E-10 core ENDEC transmits negative Manchester-

encoded data on the DATAN pin. DATAN is used in test

mode and is not needed for interfacing to the mixed

signal transmit driver.

DATATN

Data Threshold Negative

Input

DATATN is used in conjunction with DATATP to control

the E-10 core ENDEC squelch function and link integrity

pulse detection. It should be connected to the negative

threshold output of the off-core differential input data

receiver.

Ethernet-10 (E-10) Core Technical Manual

2-3

February 1997 - Rev. A

DATATP

Data Threshold Positive

Input

DATATP is one of two pins (the other pin is DATATN) that

control the E-10 core ENDEC squelch function and link

integrity pulse detection. It should be connected to the

positive threshold output of the off-core differential input

data receiver.

DRIVEENN

LCORPP

Drive Enable

Output

DRIVEENN is the enable output signal needed for

enabling the mixed signal drivers in a four-wire solution

when frame data or link pulses are to be transmitted from

the E-10 core. DRIVEEN is an active-LOW signal and

must be connected to the enable input of the driver.

Link Correct Polarity

Input

LCORPP is used in the Twisted-Pair mode only. When

this input is HIGH in Twisted-Pair mode and the polarity

of the link integrity pulses is inverted, the received data

is inverted to correct for inverted wiring. The E-10 core

ENDEC monitors Link Integrity pulses, which may be

sent on a regular basis from any other device on the

network when the channel is idle. The Link Integrity

pulses received by the core normally must be positive-

going pulses spaced from 6 to 96 milliseconds apart. If

the E-10 core ENDEC detects eight consecutive pulses

of the wrong polarity and the LCORPP pin is HIGH, the

E-10 core ENDEC inverts the received data. When

LCORPP is LOW, the E-10 core ENDEC does not correct

for inverted wiring.

LFORCEP

LPASSP

Link Control Force

Input

LFORCEP is used in the Twisted-Pair mode only. When

LFORCEP is asserted HIGH, the E-10 core ENDEC

allows a transmission even in a link integrity fail situation

(occurs when link pulses are not present due to a broken

or missing wire).

Link State Pass

Output

LPASSP is used in the Twisted-Pair mode only to indicate

the link status. LPASSP is HIGH when the link is active

(data or link integrity pulses received). LPASSP is LOW

when there is a link failure (no data or link integrity pulses

received for more than 96 milliseconds). When in the link

fail state (LPASSP is LOW), the transmit function within

the E-10 core ENDEC is disabled. The disabling of the

2-4

Signal Descriptions

February 1997 - Rev. A

receive operation has to be done in the MAC logic, using

this output. The collision output is invalid during the link

fail state.

LPBADP

Link Polarity Bad

Output

LPBADP is used in the Twisted-Pair mode only to

indicate the link polarity status. LPBADP is HIGH when

eight consecutive link integrity pulses of inverted polarity

are received. If LCORPP is HIGH, the E-10 core ENDEC

automatically inverts the data coming from the link to

compensate for inverted wiring.

PREEP

Positive Data Pre-Emphasis

Output

This pin is used in Twisted-Pair mode only and is the

positive pre-emphasis output from the core. The purpose

of PREEP is to increase the amplitude of the higher

frequencies in the output signal. Data pre-emphasis

guarantees that Twisted-Pair mode can drive signals

properly at 10 Mbit/s on cable up to 100 meters long.

PREEP is used in conjunction with DATAP and must be

connected to the pre-emphasis input of the off-core mixed

signal transmit driver. The mixed signal cell uses DATAP

with PREEP to generate the proper transmit signals.

PREEN

Negative Data Pre-Emphasis

Output

This pin is used in Twisted-Pair mode only and is the

negative pre-emphasis output from the core. The

purpose of PREEN is to increase the amplitude of the

higher frequencies in the output signal. It is used in test

mode and is not needed for interfacing to the mixed sig-

nal transmit driver.

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2.3 Receiver Signals

The receiver signals connect to the parallel interface and the control

circuitry of the system. The description of each signal follows.

RLOCKEDP Receiver Locked

Output

The E-10 core ENDEC asserts this output HIGH when

the receiver phase-locked loop is locked onto an input

signal and is receiving frame bits. It takes a minimum of

six bits and a maximum of eight bits for lock to occur. At

least three bits are required for the smart squelch

operation and the remaining bits are required for the PLL

to operate.

RBYTEP

Received Byte

Output

A 100-ns positive pulse on this pin indicates that a new

receive data byte is valid and available on the RDATAO[7:0]

pins. RBYTEP pulses for 100 ns every 800 ns (a byte time)

as long as the E-10 core is receiving data.

RCLEANP

Receiver Cleanup

Output

The E-10 core drives RCLEANP with a 100-ns positive

pulse when the end of an invalid frame is encountered. An

invalid frame is a frame that failed the address filter or was

shorter than a minimum length frame. RCLEANP indicates

to the host that the bytes received and stored by the host

since the last RSTARTP pulse can be discarded.

RCVNGP

Receiving

Output

The E-10 core asserts RCVNGP HIGH when the receiver

is receiving valid Manchester-encoded input data. Every

valid Manchester-encoded bit contains a transition (either

HIGH-to-LOW or LOW-to-HIGH) in the middle of the 100-ns

bit time. The E-10 core asserts RCVNGP HIGH directly

following the start of frame delimiter and deasserts it LOW

when a bit cell is received without a transition in the center

of the bit time.

RDATAO[7:0] Received Data

Output

The E-10 core drives the RDATAO[7:0] receive data bus

with a new data byte when the RBYTEP pin is pulsed

HIGH. The data on these pins is valid and stable for

800 ns until the next RBYTEP pulse is received.

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Signal Descriptions

February 1997 - Rev. A

RDONEP

Receiver Done

Output

The E-10 core drives RDONEP with a 100-ns positive

pulse after the reception of a complete frame. The

RDONEP pulse indicates that all data bytes have been

written and all receive status bits are valid.

RENABP

RMCENP

Receive Enable

Input

When RENABP is HIGH, the receive engine is enabled,

frames are able to be received, and address checking is

performed.

Receive Multicast Enable

Input

When RMCENP is HIGH and the multicast ﬁlter logic

external to the E-10 receiver is enabled, the E-10 core

continues to receive the frame. Multicast addressing is

used when it is necessary to transmit to a selected group

of destinations with a single individual address. The ﬁrst

bit of a multicast address is always a one. However, even

if RMCENP is HIGH, an individual address (ﬁrst address

bit is a zero) can still be recognized.

The external multicast ﬁlter logic supplied by the host

uses the nine-bit polynomial supplied on the

MINDEXO[8:0] E-10 pins to create an index into a hash

table. The nine bits are the nine MSBs of the E-10 linear

feedback shift register (LFSR), which generates the

32-bit FCS. The host hash table result (MBITP,

MDONEP) determines whether or not the E-10 core

should continue to receive the frame.

RPMENP

Receive Promiscuous Mode Enable

Input

When this input is HIGH, the E-10 core disables individual

address checking. All frames with an individual address

are accepted. The least-significant bit of the most-

significant byte of an individual address is always a zero.

RSNOOPENP

Receiver Lookback Enable

Input

When RSNOOPENP is HIGH, all transmitted frames are

routed back through the receiver. Operation is similar to

that of loopback except that the phase-locked loop is

bypassed. A lookback frame is indicated when both the

RSMATIP and RSMATMP receiver output pins are

asserted HIGH.

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2.4 Receiver Status Signals

The E-10 receiver status signals may be used by the host to monitor

various conditions regarding the reception of a data frame.

RSDRBLEP Receive Status Dribble Bits

Output

When RSDRBLEP is HIGH, the number of bits in the

received frame was not a multiple of eight, or contained

dribble bits.

RSFCSEP

Receive Status Frame Check Sequence Error Output

When this signal is HIGH, the frame check sequence

(FCS), which consists of the last four bytes of the

received frame, did not correspond with the expected

value. The FCS is also known as a Cyclic Redundancy

Check (CRC). The E-10 core preloads a 32-bit LFSR with

all ones. It then uses the incoming source address,

destination address, length, data, pad, and FCS ﬁelds to

update the 32-bit LFSR. If the contents of the 32-bit

LFSR are incorrect after all bits are received, the E-10

core asserts RSFCSEP HIGH.

RSMATIP

Receive Status Match Individual Address

Output

When this signal is HIGH, all 48 destination address bits

of the received frame matched the 48 bits of the node or

individual address. In promiscuous mode, RSMATIP goes

HIGH only if the address received matches the individual

address. RSMATIP is not asserted for multicast

addresses.

RSMATMP

RSPLLEP

Receive Status Match Multicast Address

Output

When this signal is HIGH, the frame was received

because the external multicast ﬁlter logic accepted the

frame. RSMATMP is not asserted for individual or

promiscuous address modes.

Receive Status Phase-Locked Loop (PLL)

Error

Output

When this pin is HIGH, the phase-locked loop

encountered a clock rate error during the reception of the

frame. The state of RSPLLEP is a “don’t care” prior to the

time that the PLL acquires phase-lock.

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Signal Descriptions

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A phase-locked loop error signals that the data recovery

circuit ran out of elasticity during the reception of the

frame. Elasticity is a measure of the tolerance of the

phase-locked loop to the cumulative bit shift due to small

differences in the free-running clock oscillator frequencies

of the transmitting source and receiving destination. If the

oscillator frequencies are not exactly the same, it is

possible that the centers of the bits during lengthy frames

will drift apart so much that the phase-locked loop cannot

properly recover the data. The PLL runs out of elasticity

after a bit shift between the transmitter and receiver of

exactly six bit times or a clock period difference of

± .05%. For more information on elasticity, see the

subsection entitled “PLL Characteristics” on page 3-13.

RSTARTP

Receiver Start

Output

The E-10 core drives this pin with a 100-ns positive pulse

immediately following the start of frame delimiter. The

pulse may be used to prepare the external logic for the

reception of data.

2.5 Multicast Filter Signals

The multicast ﬁlter signals connect to the parallel interface and the

control circuitry of the system. The description of each signal follows.

MBITP

Multicast Hash Table Bit

Input

While the MDONEP pulse is asserted HIGH, the MAC

samples MBITP. When MBITP is HIGH, it indicates that

the external logic has determined that the destination

multicast address is valid.

MDONEP

Multicast Filter Done

Input

External host logic must examine the E-10 MINDEXO[8:0]

lines to determine if a destination multicast address is

valid. The host may use MINDEXO[8:0] as an index into

a multicast hash lookup table. When the external logic

decides to accept or reject the multicast message based

on the hash table results, the logic indicates it to the E-10

receive engine by asserting the MBITP pin HIGH (if the

multicast address is accepted) or by deasserting the

MBITP pin LOW (if the multicast address is rejected) and

asserting a 100-ns positive pulse on the MDONEP pin.

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MINDEXO[8:0] Multicast Hash Function

Output

These nine output pins contain the nine-bit hash function

computed from the destination address. The E-10 core

uses the nine MSBs of the 32-bit LFSR that is used to

generate the FCS to create the nine-bit hash function.

The nine-bit hash function is generated after the ﬁnal

destination address bit is received.

MSTARTP

Multicast Filter Start

Output

When multicast is enabled (RMCENP is HIGH) and a

frame is received with a destination multicast address, the

E-10 core places a 100-ns pulse on MSTARTP to indicate

to the external logic that a new nine-bit hash function has

been computed from the destination address.

2.6 Transmitter Signals

The MAC transmitter signals connect to the parallel interface and the

control circuitry of the system. The description of each signal follows.

TABORTP

Transmit Abort

Input

The host asserts TABORTP to indicate that an underﬂow

condition exists, which signiﬁes that the host is not

supplying transmit data fast enough to the core. The host

is responsible for detecting the underﬂow condition.

Assertion of TABORTP forces an invalid end to the frame.

The host may assert TABORTP for any reason in order

to stop transmission of data. As soon as TABORTP is

received, the E-10 core transmits 32 bits of alternating

ones and zeros, starting with a one, before stopping

transmission.

TAVAILP

Transmit Packet Available

Input

TAVAILP should be asserted HIGH when the host has

one or more data packets available to be transmitted.

This signal is sampled only once per frame, so it can be

deasserted LOW by the host after the E-10 core asserts

the TRNSMTP and TSTARTP output pins. The E-10 core

continues to attempt to transmit the frame until it is

transmitted successfully, an error occurs, or the

transmission is aborted.

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Signal Descriptions

February 1997 - Rev. A

After the TAVAILP signal is ﬁrst sampled, it is not

sampled again until a minimum of 800 ns after the

TDONEP pulse, to give external logic time to do buffer

housekeeping, and to determine whether or not another

buffer is ready to be transmitted.

TCTRI[3:0]

Transmit Control

Input

The bits in this four-bit control bus are described in the

following table.

Bit Description

0

1

2

3

Insert Source Address Enable

Insert FCS Field Enable

Automatic Frame Padding Enable

SQE Test Enable

The TCTRI[3:0] signals come from the host. They are

normally static signals that the E-10 core uses to

determine transmission operation.

TCTRI[0] is the Insert Source Address Enable signal.

When TCTRI[0] is HIGH, the E-10 core inserts the source

address into a transmitted frame from the 48-bit

NOADDRI[47:0] bus supplied at the E-10 input pins by

the host. If TCTRI[0] is LOW, the host itself must place

the source address in the transmitted frame.

TCTRI[1] is the Insert FCS Field Enable signal. When

TCTRI[1] is HIGH, the E-10 core computes a four-byte

FCS and appends it to the end of a transmitted frame.

When TCTRI[1] is LOW, the host must generate and

append the FCS ﬁeld to the frame.

TCTRI[2] is the Automatic Frame Padding Enable signal.

When TCTRI[2] is HIGH, the E-10 core examines the

data ﬁeld supplied by the host. If the data ﬁeld contains

less than 46 bytes (46 bytes is the minimum amount of

data required for a minimum frame length), the E-10 core

supplies enough bytes ﬁlled with zeroes to make a

46-byte data ﬁeld. If TCTRI[2] is LOW, the E-10 core

does not automatically append any bytes to the data ﬁeld.

TCTRI[3] is the SQE Test Enable signal. When TCTRI[3]

is HIGH, the E-10 core expects to receive a “heartbeat”

on the COLLINP and COLLINN signal inputs after each

frame is transmitted. The heartbeat is a 10-MHz burst

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and starts six to 16 bit times (0.6 µs to 1.6 µs) after the

last transition of the transmitted signal and lasts for a

duration of ﬁve to 15 bit times. If TCTRI[3] is LOW, the

E-10 core expects no such signalling. The SQE Test

Enable signal is not applicable to Twisted-Pair mode.

TDATAI[7:0] Transmit Data

Input

The data on this eight-bit transmit data bus is sampled on

the LOW-to-HIGH transition of CLK10I when TREADDP

is asserted. After TREADDP is asserted HIGH, the

external logic has up to 800 ns to place the next data

byte onto the TDATAI[7:0] bus.

TDONEP

Transmit Done

Output

The E-10 core puts a 100-ns positive pulse on the

TDONEP pin to indicate either the end of a transmission,

the frame was transmitted successfully, excessive

collisions are detected, or the signals TFINISHP or

TABORTP are asserted. When this signal is asserted, the

transmit status pins are valid. Section 2.7, “Transmitter

Status Signals,” deﬁnes the transmit status pins.

TFINISHP

Transmit Finish

Input

When TFINISHP is asserted HIGH during a transmission,

the current transmission attempt is completed, no retry is

attempted, and a TDONEP pulse generated even if the

transmission attempt is not successful.

TLASTP

Transmit Last Byte

Input

The host asserts TLASTP HIGH to indicate that

TDATAI[7:0] contains the last byte of data in the frame.

TREADDP

Transmitter Read Data Output

A HIGH pulse on this output pin indicates that the data

byte previously placed on the TDATAI[7:0] lines by the

host is going to be read into the E-10 core on the next

LOW-to-HIGH transition of CLK10I. After the data is read,

the host can remove the data from the TDATAI[7:0] pins.

The host should put the next data byte on the

TDATAI[7:0] pins within 800 ns.

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Signal Descriptions

February 1997 - Rev. A

TRNSMTP

TSTARTP

Transmitting

Output

A HIGH on TRNSMTP indicates to external logic for both

the AUI and TP modes that the MAC is in transmit mode

and is putting Manchester-encoded data on the E-10 pins

that drive the off-core transceivers.

Transmit Start

Output

The E-10 core asserts a 100-ns positive pulse on the

TSTARTP pin to indicate the start of a transmission (or

retransmission). The host should supply data on the

TDATAI[7:0] pins within 6.4 µs of the TSTARTP pulse.

External logic may use this signal to reset the data

pointer to the beginning of the transmit data buffer.

2.7 Transmitter Status Signals

The E-10 transmitter status signals may be used by the host to monitor

various conditions regarding the transmission of a data frame.

TSECOLP

TSIDEFP

Transmit Status Excessive Collisions

Output

This signal is asserted HIGH when the frame could not

be transmitted after 16 attempts. The transmission will

then be aborted with no further retry attempts.

Transmit Status Initially Deferred

Output

This signal is asserted HIGH when the ﬁrst transmission

attempt of a frame is deferred because of activity on the

network and the frame was transmitted without a

collision. The core keeps the TSIDEFP signal asserted

during any subsequent transmission attempt and does

not deassert the TSIDEFP signal until after the end of the

transmission.

TSLCOLP

Transmit Status Late Collision

Output

This signal is asserted HIGH when a collision is detected

more than 512 bits into the frame. The transmit engine

continues to retry. The time period corresponding to

512 bits is a “slot” time (51.2 µs), and is considered to be

the maximum time necessary to transmit data on an

Ethernet channel so that all nodes detect activity. If a late

collision (after 512 bit times) occurs, it indicates that the

Ethernet connection is out of speciﬁcation and corrective

action should be taken.

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When the E-10 core detects a collision less than 512 bits

into the frame, the TSECOLP, TSMCOLP, or TSOCOLP

signals are asserted HIGH, depending on the

circumstances surrounding the collision (see the

individual signal descriptions for more details).

TSMCOLP

TSNCLBP

Transmit Status Multiple Collisions

Output

This signal is asserted HIGH when more than one

transmission attempt resulted in a collision during the

transmission of the frame. This signal is also asserted

when the transmission is terminated due to the assertion

of TABORTP.

Transmit Status No Carrier Loopback

Output

In AUI mode, TSNCLBP is asserted HIGH when a

transmission results in a transmit carrier loopback or

transmit carrier dropout error. If the E-10 core does not

detect a signal within 512 bit times from the time it was

transmitted, the error condition exists. A transmit dropout

condition could result from a broken or missing coaxial

cable.

In Twisted-Pair mode TSNCLBP is asserted HIGH if a

frame is transmitted while the transceiver is in the link-fail

state. Link pulses are 100-ns in duration and are

transmitted every 16.384 ms in the absence of transmit

data. A link fail state could result from a broken or

missing receive wire pair.

TSOCOLP

TSSQEEP

Transmit Status One Collision

Output

This signal is asserted HIGH when the frame was

transmitted after exactly one collision. This signal is also

asserted when the transmission was terminated due to

the assertion of TABORTP.

Transmit Status SQE Error

Output

A HIGH on this output pin indicates a SQE test error.

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Signal Descriptions

February 1997 - Rev. A

2.8 General MAC Signals

The general MAC signals connect to the parallel interface and the control

system circuitry. The description of each signal follows.

COLLOUTP Transmit Collision

Output

COLLOUTP is asserted (HIGH) when a collision is

encountered during a transmission. COLLOUTP is valid

for AUI mode and Twisted-Pair half duplex mode.

COLLOUTP is not valid for Twisted-Pair full duplex mode.

In AUI mode, the collision signal coming from the external

Media Attachment Unit (MAU) at the collision input pins

causes the COLLOUTP signal to be asserted. In Twisted-

Pair mode, when simultaneous transmit and receive

activity takes place, the E-10 core asserts COLLOUTP.

The host must take the operational mode into account

when interpreting this signal.

DUPLEXP

Full Duplex Select

Input

When this input is asserted, the MAC is in full duplex

mode. Full duplex mode is applicable only in the Twisted-

Pair mode of operation.

In Twisted-Pair full duplex mode, collision detection is not

valid. The host must take the operating mode into

account when interpreting the collision output signal

(COLLOUTP).

LOOPBKP

Diagnostic Loopback Enable

Input

When LOOPBKP is HIGH, the E-10 core ENDEC is in

the diagnostic loopback mode and the transmitter output

is fed back to the receiver input inside the core. Loopback

mode allows testing the E-10 transmitter and receiver up

to but not including the off-core transceivers under

program control without the need of an external loopback

connector. This diagnostic loopback capability is

applicable to both the AUI and Twisted-Pair modes. It

does not represent the standard loopback function in

Twisted-Pair mode (as the core presents an internal

on-chip MAU for Twisted-Pair mode)

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NOADDRI[47:0]

Node Address

Input

This 48-bit node address bus is driven with the individual

address of the station. It is up to the host to provide the

appropriate levels on NOADDRI[47:0] to conﬁgure the

address.

SELIO

4-Wire and 8-Wire Mixed Signal Cell Select

Input

SELIO must be asserted for four-wire Twisted-Pair mode

and deasserted for eight-wire Twisted-Pair mode. When

SELIO is asserted, the core does not use the PREEP,

PREEN, or DATAN signals. For more information on the

four-wire and eight-wire modes, see Section 3.3,

“Twisted-Pair Interface” on page 3-14.

TP/AUI

Twisted-Pair/AUI Select

Input

When TP/AUI is deasserted (LOW), the MAC core is in

AUI mode. When the signal is asserted (HIGH), Twisted-

Pair mode is selected. Below are listed the principal

differences in the way the E-10 core operates in these

two modes:

Feature

TP Mode AUI Mode

SQE Test

No

Yes

No

Link Pulse Detection

Yes

Link Pulse Polarity Detection and

Correction

Link Integrity Pulses Generated

Yes

No

Collision Pair Pins

Yes

(COLLINP, COLLINN) are used

Cause of Loopback Transmit Carrier Link Fail No Carrier

Error Loopback

It makes no difference to the core if the AUI interface is

6-wire or 9-wire. The transceivers and external circuitry

used in either 6-wire or 9-wire AUI operation present the

same signals to the MAC core.

For more information on the AUI mode of operation, see

Section 3.4, “Attachment Unit Interface (AUI)” on

page 3-20. For more information on the twisted-pair mode

of operation, see Section 3.3, “Twisted-Pair Interface” on

page 3-14.

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Signal Descriptions

February 1997 - Rev. A

2.9 Timing and Test Signals

The timing and test signals connect to the parallel interface and the

control circuitry of the system. In multiple-core environments, only one

core may be the clock master. All other cores must be slaves. For clock

duty cycles and tolerances, see Section 4.2, “E-10 Clock Timing,” on

page 4-10. The description of each signal follows.

CLK10I

10-MHz Clock In

Input

The E-10 core ENDEC uses CLK10I for MAC and bus

interface timing. CLK10I should be driven by the CLK10O

output pin through a buffer external to the E-10 core.

CLK10O

CLK20I

10-MHz Clock Out

This 10-MHz output is derived from the 80-MHz input

signal, CLK80I.

Output

20-MHz Clock In

Input

The E-10 core uses CLK20I for timing and for the

Manchester encoder clocking. CLK20I should be driven

by the CLK20O output pin through a buffer external to the

E-10 core.

CLK20O

CLK80I

20-MHz Clock Out

This 20-MHz output is derived from the 80-MHz input

signal, CLK80I.

Output

80-MHz Clock In

Input

CLK80I is the master clock source provided to the E-10

core ENDEC. It is the only external timing signal used by

the E-10 core ENDEC. CLK80I may be provided as an

external oscillator or it may be provided with a PLL circuit

as part of some chip logic surrounding the E-10 core.

FASTESTN

GNDN

Fast Test

Input

FASTESTN is used for chip testing purposes only (fast

test) and must be left HIGH during normal operation.

Ground

Input

The GND signal must be asserted (LOW) during normal

core operation. It is used for testing the core.

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RESETN

Core Reset

Input

After power is applied to the chip, RESETN should be

asserted LOW for a minimum of 200 ns (at least 100 ns

after TEST1N goes HIGH) to force initialization.

TESTSEP

Scan Enable

Input

TESTSEP is the scan enable pin for testing the module

in the ENDEC. The ENDEC has a full-scan test chain

built into it.

TESTSIP

TESTSOP

TEST1N

Scan Input

Input

TESTSIP is the scan input pin for full scan testing.

Scan Output

TESTSOP is the scan output pin for full scan testing.

Output

Test 1

Input

TEST1N is for chip testing purposes only (fast test) and

must be left HIGH in normal operation.

TEST2N

Test 2

Input

TEST2N must be left HIGH in normal operation. It must

be asserted LOW for 100 ns to initialize the ENDEC core

logic. The CLK10O AND CLK20O outputs become

operational only after the TES2N signal is deasserted

(HIGH) during initialization RESETN is then asserted

(LOW) for an additional 100 ns to initialize the rest of the

ENDEC logic. In test mode, TEST2N is used for testing

the ENDEC core.

TMODE

VCC

Test Mode

Input

TMODE must be left deasserted (LOW) during normal

operation and asserted (HIGH) in test mode. TMODE is

used during scan testing.

Positive Voltage

Input

The VCC pin should be asserted (HIGH) during normal

operation. It is used for core testing.

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Signal Descriptions

February 1997 - Rev. A

Chapter 3

E-10 Functional

Description

This chapter provides a functional description of the E-10 core and

contains the following sections:

♦

Section 3.1, “Media Access Control (MAC)”

Section 3.2, “Encoder/Decoder (ENDEC)”

Section 3.3, “Twisted-Pair Interface”

Section 3.4, “Attachment Unit Interface (AUI)”

3.1 Media Access Control (MAC)

The MAC is the portion of the E-10 core that handles the Carrier Sense

Multiple Access with Collision Detection (CSMA/CD) protocol for trans-

mission and reception of frames. The MAC performs the following func-

tions:

♦

Frame Data Encapsulation and Decapsulation

Frame Transmission

Frame Reception

3.1.1 Frame Data Encapsulation and Decapsulation

The format of the frame generated by the ANSI/IEEE Ethernet 802.3

protocol consists of several ﬁelds, as explained in the following

subsections. Figure 3.1 shows the overall structure and order of

transmission of bits and octets of a frame.

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Figure 3.1 MAC Frame Format

7 Octets

1 Octet

Preamble

SFD

6 Octets

2 Octets

Destination Address

Source Address

Length/Type

1 Frame

Octets within a Frame are

Transmitted Top-to-Bottom

Data

Pad

Frame Check

Sequence

4 Octets

LSB

MSB

Bits within each Octet are

Transmitted Left-to-Right

3.1.1.1 Preamble Field

The preamble ﬁeld is a 7-octet (56-bit) alternating one-zero pattern

(starting with a one), which is Manchester-encoded before being

transmitted onto the media. The alternating one-zero pattern ensures

that there are no transitions between bits in the Manchester-encoded

signal, which results in a 5-MHz signal (see Figure 3.2). Because the

twisted-pair Ethernet cable attenuates higher frequencies, the 5-MHz

signal creates a perfect signal for acquisition by the digital Phase-Locked

Loop (PLL). Any pattern other than an alternating one-zero pattern would

create a higher-frequency signal and make acquisition more difﬁcult. In

addition, an alternating one-zero data pattern, when Manchester-

encoded, has data transitions at the same clock edge, which makes it

easier for the PLL to achieve lock.

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E-10 Functional Description

February 1997 - Rev. A

Figure 3.2 Alternate One-Zero Manchester Encoding

1 Bit

10-MHz Clock

Alternate Ones

and Zeroes Data

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Manchester-Encoded

Alternate Ones and

Zeroes Data (5 MHz)

3.1.1.2 Start Frame Delimiter (SFD) Field

The eight-bit start of frame delimiter ﬁeld contains the 10101011 bit

2

pattern. This bit pattern allows alignment of the data received in the rest

of the frame.

3.1.1.3 Address Fields

The frame has two 48-bit address ﬁelds. The ﬁrst ﬁeld contains the

destination address and speciﬁes the address(es) for which the frame is

intended. If the ﬁrst bit of the destination address is a zero, the address

is an individual address. A one in the ﬁrst bit indicates a multicast or

group address. The second address is the source address and should

contain the individual address of the station from which the message

originated.

3.1.1.4 Length/Type Field

The two-byte length ﬁeld indicates the number of data bytes in the data

ﬁeld. The MAC does not interpret the data in the length ﬁeld and does

not treat it any differently than the data ﬁeld.

3.1.1.5 Data and Pad Field

The data ﬁeld contains a sequence of fully transparent data bytes; that

is, the data bytes are not analyzed or interpreted in any way by the MAC.

The size of the data ﬁeld may be between zero and 1,500 bytes, but can

be extended up to 4,500 bytes or more, depending on the clock accuracy

of the transmitting and receiving stations.

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The function of the pad ﬁeld is to ensure minimum frame size. If the

supplied data ﬁeld contains less than 46 bytes of data, the MAC can add

a pad ﬁeld to make the sum of bytes in the data and pad ﬁeld equal to

46. Appended pad data consists of bytes ﬁlled with zeroes.

3.1.1.6 Frame Check Sequence (FCS) Field

The transmit and receive algorithm uses the standard 802.3 four-byte

frame check sequence (FCS) ﬁeld to ensure data integrity. The E-10 core

uses a linear feedback shift register to compute the value in the FCS

ﬁeld. The FCS is a function of the content of the source address,

destination address, length, data, and pad ﬁelds. The generating

polynomial shown in Equation 3.1 deﬁnes the encoding. The nine MSBs

of the FCS may be used by an external hashing table function to perform

multicast address ﬁltering.

Equation 3.1

FCS Encoding

G(x) = x³²+ x²⁶+ x²³+ x²²+ x¹⁶+ x¹²+ x¹¹+ x¹⁰+ x⁸+ x⁷+ x⁵

+ x⁴+ x³+ x²+ x + 1

3.1.2 Frame Transmission

Frame transmission is enabled with the TAVAILP signal. TAVAILP

indicates that at least one frame is ready to be transmitted. All

transmissions start by complying with the rules of deference; that is, they

monitor the physical medium for activity. If no activity exists, the transmit

cycle starts.

During the start of a transmission, the transmitter asserts a 100-ns

positive start of transmission pulse (TSTARTP). The start pulse resets

the transmit pointer to the beginning of the transmit buffer. When the

TREADDP signal is pulsed (HIGH), it indicates to the external control

logic that data is read on the LOW-to-HIGH transition of the CLK10I

input. If a collision is detected during a transmission, the collision

enforcement rules are followed, and the transmission is aborted. If the

signals TABORTP and TFINISHP are not asserted, and the frame was

not retried 15 times, backoff and deference rules are followed and the

frame transmission is retried.

The external control logic asserts the TLASTP signal to indicate that the

last byte of data to be transmitted is present at the TDATAI[7:0] pins.

When a frame is transmitted successfully, or when a serious error is

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E-10 Functional Description

February 1997 - Rev. A

detected during the transmission, the transmitter asserts the transmitter

done (TDONEP) pulse. The TDONEP pulse indicates to the external logic

that either the transmission is complete, or the TABORTP or TFINISHP

signals were asserted before the end of the transmission, or that the

transmitter exhausted its ability to transmit the frame successfully.

External logic has a minimum of 800 ns to deassert or assert TAVAILP

indicating whether or not a new frame is ready for transmission.

3.1.2.1 Carrier Deference Rules

Even when it has nothing to transmit, the transmit portion of the MAC

monitors the trafﬁc on the physical medium. When there is no trafﬁc (a

carrier is not detected by the MAC and the MAC is not transmitting) the

MAC starts a 9.6 µs interframe timer. The interframe timer is reset if the

MAC senses a carrier during the ﬁrst 5.6 µs of the interframe gap after

a reception. During the time from 5.6 µs to 9.6 µs, the interframe timer

is not reset, to ensure fair access to the medium.

If, at the end of the interframe gap, a frame is waiting to be transmitted,

transmission is started regardless of the presence of a carrier. If a carrier

is present, a collision occurs so that a node constantly transmitting is

forced to back off. If, at the end of the interframe gap, there is no frame

waiting to be transmitted, the MAC starts monitoring for a carrier again,

and resets the interframe timer as soon as it detects a carrier.

3.1.2.2 Interframe Spacing

The carrier deference method described above ensures that the E-10

provides an interframe gap of 9.6 µs. The interframe gap ensures fair

arbitration among all sources trying to transmit and prevents one

transmitter from dominating the transmission channel.

3.1.2.3 Collision Enforcement Rules

When a collision is detected during a frame transmission (for the definition

of a frame, see the subsection entitled “Frame Data Encapsulation and

Decapsulation” on page 3-1), the transmission is not terminated

immediately. The preamble and start of frame delimiter (SFD) are

transmitted unmodified regardless of the collision state. If a collision is

detected before the preamble and SFD have finished transmitting, a 32-bit

jam pattern of alternating ones and zeros is transmitted immediately after

the SFD and then the transmission ends. If the collision is detected after

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the preamble and SFD, while data is being transmitted, the data

transmitted changes to a jam pattern of alternating ones and zeros for

32 bits before the transmission is terminated.

3.1.2.4 Transmission Backoff Algorithm

When a transmission attempt has terminated due to a collision, the

transmission is retried until either it is successful or 15 retries (16

attempts total) have been terminated due to collisions. A controlled

randomization process called “truncated binary exponential backoff”

schedules the retransmission. At the end of enforcing a collision

(jamming), the transmit engine delays before attempting to retransmit the

frame. The delay is in 51.2 µs increments, or slot times. The number of

slot times to delay before the nth retransmission attempt is chosen as a

uniformly distributed random integer r in the range:

k

-1 < r < 2

, where

k = min (n, 10)

Note that min (n, 10) signiﬁes that the value is the minimum of n or 10,

whichever is less.

A 25-bit Linear Feedback Shift Register (LFSR) generates a pseudo-

random number. Because of potential synchronization problems between

multiple stations on the network using the same pseudo-random number

generator, the number is further randomized every transmission attempt

with the station’s individual address.

3.1.2.5 Source Address Insertion

The hardware can insert the source address during transmission from

the individual address input pins. In this mode, the host is responsible for

supplying the ﬁrst six bytes (destination address). The six address bytes

are transmitted from the host on the E-10 transmit data input pins

(TDATAI[7:0]). The next six bytes transmitted are read from the individual

address registers (source address). After these two addresses are sent,

the transmitter returns to the transmit data pins and continues

transmitting subsequent data bytes from there. The byte counter in the

transmit data buffer must not include the six source address bytes in this

mode, but must include the six destination address bytes. The transmitter

is in source address insertion mode when the TCTRI[0] pin is HIGH.

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E-10 Functional Description

February 1997 - Rev. A

3.1.2.6 Automatic Pad Insertion

During transmission, a pad ﬁeld can be inserted by the hardware. In this

mode enough bytes are added just before the FCS ﬁeld to increase the

total data ﬁeld length to the IEEE 802.3 minimum of 46 bytes. The data

inserted in the pad ﬁeld is all zeroes. The transmitter is in automatic pad

insertion mode when the TCTRI[2] pin is HIGH.

3.1.2.7 Frame Check Sequence (FCS) Insertion

During transmission the E-10 hardware can compute and transmit the

FCS ﬁeld automatically. In this mode, a 32-bit polynomial is computed

from the source address, destination address, length, data, and pad

ﬁelds and transmitted immediately following the data or pad ﬁeld. The

transmitter is in FCS insertion mode when the TCTRI[1] pin is HIGH.

If the host instead is going to supply the FCS ﬁeld and the E-10 core is

going to insert the source address, the host must ensure that the FCS

is computed based on the 48-bit source address being supplied to the

E-10 core on the NOADDRI[47:0] pins.

3.1.2.8 Transmit Status Indications

The six E-10 pins listed below indicate the status of Ethernet

transmission with regard to collisions and errors:

♦

Late Collision (TSLCOLP). The bit durations for transmit and receive

data are each 100 ns. When a collision onset is detected after the

allowed window of 512 bit times (51.2 µs), the E-10 core asserts the

late collision error bit (TSLCOLP) HIGH. A late collision is treated

just like a normal collision, following the collision enforcement rules,

and the transmission is retried.

♦

Excessive Collisions (TSECOLP). When the transmission engine has

attempted to transmit a frame 16 consecutive times, and all

attempted transmissions have terminated due to a collision, the E-10

core asserts the excessive collision error pin (TSECOLP) HIGH, and

no more transmit retries are performed.

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♦

Transmit Carrier Loopback Error (TSNCLBP). In AUI mode, when an

error is detected in the receive carrier signal that is required to be

fed back during the transmission of a frame, the E-10 core asserts

the transmit carrier loopback error pin (TSNCLBP) HIGH. Two

different conditions can cause the transmit carrier loopback error pin

to be asserted in AUI mode:

–

During transmission, no carrier is received during the ﬁrst 512 bit

times (51.2 µs) of the transmission.

–

During transmission, carrier was received but was interrupted

before transmission stopped.

The transmit carrier loopback error has no effect on the transmission/

retransmission process, but no SQE test is performed.

In Twisted-Pair mode, the E-10 core asserts the transmit carrier loopback

pin HIGH to indicate a link failure during the transmission of the frame.

A link failure can be caused by a twisted-pair transceiver failure or by a

broken twisted-pair cable. In the link fail state, the E-10 core does not

route the Manchester-encoded data to the transmitter pins, but it still

transmits link integrity pulses.

♦

SQE Error (TSSQEEP). The E-10 core asserts the signal quality

error pin (TSSQEEP) HIGH when the MAC detects all the following

conditions:

–

The E-10 core is in AUI mode

The E-10 core is in half-duplex mode

SQE testing is enabled (TCTRI[3] pin is HIGH)

The late collision status pin (TSLCOLP) is not HIGH

The excessive collisions status pin (TSECOLP) is not HIGH

The transmit carrier loopback error status pin (TSNCLBP) is not

HIGH

–

No SQE signal was received in the first 5.6 µs of the interframe gap

♦

One Collision (TSOCOLP). The E-10 core asserts the one collision

status pin (TSOCOLP) HIGH when the frame is transmitted after

exactly one collision. If more than one collision occurred before the

frame was transmitted, the TSMCOLP pin is asserted (HIGH) and

the TSOCOLP pin is deasserted (LOW). Assertion of the TSOCOLP

pin is not an error indication, but is intended only for information, and

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E-10 Functional Description

February 1997 - Rev. A

can be used to update network statistics counters. When the

transmission of a frame is terminated with the signal TABORTP, the

E-10 core asserts the TSOCOLP signal (together with TSMCOLP) to

indicate this fact to external logic. Section 2.6, “Transmitter Signals,”

contains a description of the TABORTP signal. TSOCOLP is valid

when the TDONE pin pulses.

♦

Multiple Collisions (TSMCOLP). The E-10 core asserts the multiple

collision status pin (TSMCOLP) HIGH when the frame is transmitted

after more than one collision. This pin is not an error indication, but

is intended only for information, and can be used to update network

statistical counters. When the transmission of a frame was

terminated with the signal TABORTP, the E-10 core asserts the

TSMCOLP signal (together with TSOCOLP) to indicate this fact to

external logic. TSMCOLP is valid when the TDONEP pin pulses.

3.1.3 Frame Reception

Frame reception is allowed after the receiver enable signal (RENABP) is

asserted. After the transceiver squelch circuitry detects a valid signal,

and the receiver PLL locks onto the incoming signal as indicated by

assertion of the RLOCKEDP signal, the receiver starts searching for a

valid start of frame delimiter. The PLL takes a minimum of six and a

maximum of eight bit times (600 to 800 ns) to achieve lock.

A valid start of frame delimiter is deﬁned as 0b10101011. When the start

of frame delimiter is detected, the receiver pulses the RSTARTP pin. A

pulse on the RSTARTP pin informs the external logic to make available

a new receive buffer, because received data will start arriving in 800 ns.

Every time a new byte of received data is available on the RDATAO[7:0]

bus, the E-10 receiver pulses the RBYTEP pin.

The ﬁrst 48 bits of the frame contain the destination address. The MAC

receiver portion of the E-10 core compares the destination address bits

with the data on the 48-bit node address bus (NOADDRI[47:0]), and

when the bits are equal, allows the continued reception of the frame.

When the receiver promiscuous mode pin (RPMENP) is asserted, any

individual destination address validates the frame, and allows the

reception process to continue. When the destination address is a

multicast address, including the broadcast address (the address contains

all ones), the receiver computes a nine-bit hash function from the

destination address, and leaves the decision to accept or reject the frame

to external logic.

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When an end-of-frame delimiter is detected, the receiver accepts the

frame and generates a 100-ns pulse on the RDONEP pin when all the

following conditions are true:

♦

At least one address ﬁlter passed

The frame was at least 64 bytes in length

The receiver is still enabled

When the end-of-frame delimiter does not generate an RDONEP pulse,

the receiver instead pulses the RCLEANP pin, which indicates to the

external logic that it must ignore the data received. It is then up to the

host logic to manage the receive buffer space properly (either give up the

buffer space so it can be used for other transmit or receive data or

allocate another buffer).

3.1.3.1 Address Filtering

Three address ﬁlter mechanisms are present in the receiver, two for

individual addresses, and one for multicast addresses. At least one of

these address ﬁlters must pass to accept the received frame. The

address ﬁlters are listed below:

♦

Individual Address Filter. The ﬁrst bit of an individual address is a

zero. The incoming destination address is compared with the data

from the individual address pins. When all 48 bits match and the

receiver is enabled (RENABP pin asserted HIGH), the address ﬁlter

passes.

♦

Individual Address Promiscuous Mode. When the external logic

asserts the individual address promiscuous mode enable pin

(RPMEN) HIGH and the destination address is an individual address,

the address ﬁlter always passes, and the incoming frame is received.

Multicast Address Filter. The ﬁrst bit of an multicast address is a one.

When the destination address bits that are received in the frame

contain a multicast address, the E-10 core uses its built-in FCS

generator to compute a nine-bit polynomial (the nine MSBs of the

32-bit FCS generator) from the incoming address. The value of this

polynomial can be used as an index into an external multicast ﬁlter

hash table. External logic can decide to either accept or reject the

incoming frame. The external logic asserts the RMCENP pin (HIGH)

to enable the multicast address ﬁlter. Figure 3.3 shows the general

3-10

E-10 Functional Description

February 1997 - Rev. A

host implementation of a multicast ﬁlter. Section 2.5, “Multicast Filter

Signals,” in Chapter 2, “Signal Descriptions,” explains the functions of

the individual signals shown in the ﬁgure.

When the destination address is all ones, it indicates a broadcast

address. When the E-10 core detects a broadcast address, it receives

the incoming frame.

Figure 3.3 Host Multicast Filter Implementation

RMCENP (HIGH to Enable E-10 Multicast Filter Logic)

E-10

Core

32-Bit LFSR

MINDEX8

MINDEX0

MINDEX8

Bit 32

Register

Bit 24

Multicast Filter

Hash Table

MSTARTP

MDONEP

MBITP

3.1.3.2 FCS Checking

During reception, the FCS value is checked against the value computed

by the receive CRC checker. If the two values do not match, the frame

is received and the E-10 core asserts the FCS error pin (RSFCSEP)

HIGH to indicate data corruption in the frame. The decision to accept or

reject the frame is left to external logic.

3.1.3.3 Frame Size Checking

Frame size checking is performed on every received frame. If a frame is

less then 64 bytes in length, the receiver cleanup pulse (RCLEANP)

discards the received data (collision fragment). IEEE 802.3 speciﬁes a

maximum frame size of 1,518 bytes, but the MAC does not do any

maximum length checking, and much larger frames (for instance 4,500

bytes) can be received, as long as care is taken not to exceed PLL

elasticity. The application is responsible for checking the maximum frame

size and reporting any errors.

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3.1.3.4 Start of Frame Delimiter Checking

The start of frame delimiter, a bit sequence of 0b10101011 that occurs

following the preamble, starts the reception of bytes.

3.1.3.5 Receive Status Indications

The ﬁve E-10 pins listed below indicate the status of Ethernet reception

with regard to collisions and errors.

♦

Frame Check Error (RSFCSEP). The E-10 core asserts the frame

check error pin (RSFCSEP) HIGH when bits of the incoming frame

do not generate a CRC identical to the one in the received FCS ﬁeld,

indicating data corruption has occurred in the received frame.

♦

Dribble Bit Error (RSDRBLEP). The E-10 core asserts the dribble bit

error pin (RSDRBLEP) HIGH at the end of a frame when less than

a complete byte has been received, indicating the reception of from

one to seven “dribble” bits. The E-10 core asserts the RSDRBLEP

pin HIGH independently of the frame check error bit. RSDRBLEP

can be ignored if the RSFCSEP pin is not set.

The reason RSDRBLEP can be ignored is that the FCS is updated

every eight bits. If there are less than eight dribble bits (from one to

seven bits) at the end of the frame and the current FCS is correct,

any extra dribble bits (less than eight) do not matter. However, if

there are eight or more dribble bits, the FCS will be updated and will

most likely be wrong due to the dribble bits. In this case, RSDRBEL

should not be ignored.

♦

Phase-Locked Loop Error (RSPLLEP). The E-10 core asserts the

phase-locked loop error pin (RSPLLEP) when, during reception of a

frame, the digital phase-locked data recovery circuit elasticity is

exhausted. The elasticity becomes exhausted due to drift between

the 10-MHz clock frequency of the device sending the data and the

ENDEC 10-MHz clock frequency. See the subsection entitled “PLL

Characteristics” on page 3-13 for an explanation of elasticity.

RSPLLEP is asserted when a frame is received with a transmit clock

error sufﬁciently larger than the IEEE 802.3 requirement of 0.01%

that the PLL elasticity is exhausted within a normal frame, or when

a frame length sufﬁciently larger than that speciﬁed in IEEE 802.3

has caused the elasticity to be exhausted even when the clock is

within tolerance.

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E-10 Functional Description

February 1997 - Rev. A

♦

Match Individual Address (RSMATIP). The E-10 core asserts the

match individual address pin (RSMATIP) HIGH when the destination

address matches the node address.

Match Multicast Address (RSMATMP). The E-10 core asserts the

match multicast address pin (RSMATMP) HIGH or deasserts it LOW

as a result of the decision of the external multicast ﬁlter logic to

accept or reject the multicast address.

3.2 Encoder/Decoder (ENDEC)

The ENDEC consists of the Manchester encoder, Manchester decoder,

and the digital phase-locked loop.

3.2.1 PLL Characteristics

The digital phase-locked loop used for data recovery has the following

characteristics:

♦

Sampling

–

Sampling Frequency: 160 MHz

Sampling Interval: 6.25 ns

With the above sampling parameters, each bit of 100 ns is sampled

16 times.

♦

Jitter Tolerance: ± 18.00 ns

This parameter indicates that the incoming data bits may have a jitter

up to ±18.00 ns and the digital PLL will still work acceptably.

Tracking speed

–

Initial (ﬁrst 4.8 µs): 0.39%

Steady-state (after 4.8 µs): 0.098%

When ﬁrst attempting to lock on to an oncoming data stream (during

the ﬁrst 4.8 µs), the PLL looks every 16 bits to see if a bit transition

is occurring in the center of the sampling window. Dividing the

sampling interval of 6.25 ns by the 16-bit interval (1600 ns) yields

0.0039 or 0.39%.

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February 1997 - Rev. A

After the ﬁrst 4.8 µs, the PLL maintains a window of 64 bits for

ﬁnding a transition. Dividing the sampling interval of 6.25 ns by the

64-bit interval (6400 ns) yields 0.00098 or 0.098%.

♦

Elasticity

–

Maximum clock drift time 600 ns (6 bit times)

Maximum clock error @ 1518 byte frame: 0.05%

Maximum clock error @ 4500 byte frame: 0.016%

Elasticity indicates the tolerance of the PLL to slightly different clock

rates between a transmitter and a receiver. The E-10 core allocates

a buffer of 13 bits to accommodate clock drift. The 13-bit buffer

allows a clock drift of six bits (600 ns) from center in either direction

during a frame transfer.

For a 1518-byte frame, consisting of six bytes of destination address,

six bytes of source address, two bytes of length, 1500 bytes of data,

and four bytes of FCS (6 + 6 + 2 + 1500 + 4 = 1518), the maximum

clock drift allowed is 0.05% (0.05% x 1518 bytes x 8 bits/byte = 6 bits).

For a 4500 byte frame, the maximum clock drift allowable during

frame transfer is 0.016% (0.016% x 4500 bytes x 8 bits/byte = 6 bits).

3.3 Twisted-Pair Interface

The E-10 core supports two twisted-pair conﬁgurations:

♦

Four-wire

Eight-wire

♦

3.3.1 4-Wire Twisted-Pair Interface

The four-wire E-10 twisted-pair interface is shown in Figure 3.4. The

four-wire interface implements CoreWare mixed signal transmitter and

receiver cores to prepare the E-10 core’s I/O signals for connection to the

network. An ASIC implementation of an Ethernet port using the E-10 core

and mixed signal I/O cores provides a simple interface to the network.

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E-10 Functional Description

February 1997 - Rev. A

A four-wire interface is usually best for multiport applications. The mixed

signal I/O cores reduce the number of ASIC device pins and external

passive components.

Figure 3.4 4-Wire Twisted-Pair Interface Using Mixed Signal Cores

ASIC

E-10 Core

DATAP

TX+

TX-

Drivers

10BASE-T

Magnetics and

Passive

Components

RJ-45

Connector

DATATP

DATAI

RX+

Receivers

DATATN

RX-

3.3.1.1 4-Wire Twisted-Pair Transmit Interface

With the four-wire twisted-pair interface, the E-10 core outputs a single

Manchester-encoded transmit signal, DATAP, to a mixed signal

differential driver core. The driver produces low common-mode noise

differential outputs, which provide the desired output swing to the

magnetics (transformer). The mixed signal driver reduces the generation

of high-frequency signal components, thereby minimizing external

ﬁltering requirements and reducing external component costs.

3.3.1.2 4-Wire Twisted-Pair Receive Interface

The four-wire receiver interface complies with the receiver speciﬁcations

of the IEEE 802.3 10BASE-T standard, including noise immunity,

propagation delays, jitter requirements, and received signal rejection

criteria (Smart Squelch).

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The four-wire twisted pair receive interface has three signals at the E-10

core interface: DATATP, DATATN, and DATAI. The three signals are inputs

to the E-10 core and come from a two-input differential mixed signal

receiver.

The receiver converts the two differential analog data signals from the

network to DATATP, DATATN, and DATAI, which are CMOS-level

single-ended digital outputs. The three signals switch in such a way that

the E-10 core can properly perform data detection, reverse polarity

detection, and smart squelch.

3.3.2 8-Wire Twisted-Pair Interface

The eight-wire E-10 twisted-pair interface is shown in Figure 3.5. This

interface uses data pre-emphasis on data transmitted from the core and

threshold detection circuitry on the data being received by the core.

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E-10 Functional Description

February 1997 - Rev. A

Figure 3.5 8-Wire Twisted-Pair Interface

ASIC

E-10 Core

DATAP

TX+

PRE+

PREEP

Drivers

PRE-

PREEN

10BASE-T

DATAN

TX-

Magnetics and

Passive

Components

RJ-45

Connector

RX+

REF

DATATP

Receivers

DATAI

REF

RX-

DATATN

3.3.2.1 8-Wire Twisted-Pair Transmit Interface

With the eight-wire twisted-pair interface, the core outputs four transmit

signals, the true and complemented (differential) Manchester-encoded

data (DATAP and DATAN) and those signals delayed by 50 ns (PREEP

and PREEN). These four signals are sent through four individual transmit

buffers and resistively combined (DATAP with PREEP and DATAN with

PREEN). The technique of resistively combining the signals is known as

digital pre-emphasis and provides the necessary electrical driving

capability and predistortion control for transmitting signals over a

maximum length twisted-pair cable, as speciﬁed by the IEEE 802.3

10BASE-T standard. Digital pre-emphasis compensates for the twisted-

pair cable, which acts like a low-pass ﬁlter and causes greater

attenuation to the 10-MHz (50-ns) pulses of the Manchester encoded

waveform than the 5-MHz (100-ns) pulses. When a data stream of all

ones or all zeroes is present, Manchester encoding causes a transition

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February 1997 - Rev. A

every bit time, which creates a 10-MHz bitstream. With a data stream of

alternate ones and zeroes, Manchester encoding causes a transition

every other bit time, which creates a 5-MHz bitstream. Figure 3.6 shows

how different data patterns are Manchester encoded.

The differential Manchester-encoded signal is passed to an external

transmit ﬁlter. The transmit function meets the propagation delays and

jitter speciﬁed by the standard.

Figure 3.6 Manchester Encoding

1 Bit

10-MHz Clock

1

0

All Ones

Data (10 MHz)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

All Zeroes

Data (10 MHz)

Alternate Ones and

Zeroes Data (5 MHz)

0

1

0

1

0

1

0

1

0

1

Random Data

3.3.2.2 8-Wire Twisted-Pair Receive Interface

The eight-wire receiver interface complies with the receiver speciﬁcations

of the IEEE 802.3 10BASE-T standard, including noise immunity,

propagation delays, jitter requirements, and received signal rejection

criteria (Smart Squelch).

With the eight-wire twisted-pair receive interface, there are three input

signals at the E-10 core interface: DATATP, DATATN, and DATAI. These

input signals are the outputs from three distinct differential receivers.

In a similar fashion to the four-wire interface, the three input signals

switch in such a way that the E-10 core can properly perform data

detection, reverse polarity detection, and smart squelch.

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E-10 Functional Description

February 1997 - Rev. A

Following is a functional description of the twisted-pair interface. It

includes these sections:

♦

Squelch

Link Test Function

Polarity Detection and Correction

3.3.3 Squelch

An intelligent (smart) receive squelch is implemented on the receiver

differential inputs to ensure that impulse noise on the receiver inputs is

not mistaken for a valid signal. The smart squelch logic uses a

combination of amplitude and timing measurements to determine the

validity of data on the twisted-pair inputs.

The squelch circuitry operation is illustrated in Figure 3.7. Squelching

determination starts when the input signal crosses the positive or

negative threshold (a). To continue a valid signal sequence, the signal

then has to cross the other threshold (b) within 150 ns. To complete the

valid signal process, the input signal has to cross the original threshold

(c) again within 150 ns. If the signal proves to be valid, the smart squelch

logic does not suppress the signal. However, if not all of the conditions

just outlined are met, the signal is suppressed.

Figure 3.7 Squelch Signal

< 150 ns

Positive

Threshold

(+ 585 mV)

a

c

b

Negative

Threshold

(- 585 mV)

< 150 ns

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

3.3.4 Link Test Function

The link test function is implemented as speciﬁed by the IEEE 802.3

10BASE-T standard. During periods of transmit pair inactivity, Link Test

pulses are periodically sent from any transmitting device over the twisted-

pair medium to allow constant monitoring of medium integrity. Link

pulses, which are 100 ns wide, are transmitted from the E-10 core every

16.384 ms in the absence of transmit data. The core expects to receive

a link pulse every 96 ms.

The absence of serial Link Integrity pulses on the receiver inputs causes

a Link Fail State to occur. In the Link Fail State, data transmission, data

reception, and the collision detection functions are disabled and remain

disabled until valid data or eight consecutive Link Test pulses appear on

the receiver inputs.

When the E-10 core identiﬁes the link as functional, the E-10 core

asserts the LPASSP pin HIGH to indicate that the link status is good.

3.3.5 Polarity Detection And Correction

The receive function includes the ability to invert the polarity of the

signals appearing at the receiver pair if the polarity of the received signal

is reversed, as in the case of a wiring error. This feature allows frames

received from a reversed twisted-pair interface to be corrected prior to

transfer to the E-10 core. The function uses link pulses to determine

polarity of the received signal. A reversed polarity condition is detected

when seven consecutive opposite-polarity receive link pulses are

detected without receipt of a link pulse of the expected polarity.

3.4 Attachment Unit Interface (AUI)

An AUI provides the link from a 10BASE-T network to a 10BASE-5,

10BASE-2, or 10BASE-F network. As shown in Figure 3.8, an AUI

provides the appropriate interface to a Medium Attachment Unit (MAU)

so that the MAU can interface to a variety of physical media.

3-20

E-10 Functional Description

February 1997 - Rev. A

Figure 3.8 10BASE-5 AUI Connection

MAU

AUI

ENDEC

Transceiver

DTE (PC)

AUIs provide transmit, receive, and collision control functions. The E-10

core supports two different Attachment Unit Interface (AUI) configurations:

♦

Six-wire

Nine-wire

3.4.1 6-Wire AUI Interface

The six-wire E-10 AUI interface shown in Figure 3.9 implements CoreWare

mixed signal transmitter and receiver cores to prepare the

E-10 core’s I/O signals for connection to the network. An ASIC

implementation of an Ethernet port using the E-10 core and mixed signal

cores, along with a few discrete components provide impedance matching,

isolation, filtering and electromagnetic interference (EMI) suppression.

Ethernet-10 (E-10) Core Technical Manual

3-21

February 1997 - Rev. A

Figure 3.9 AUI 6-Wire Interface

ASIC

E-10 Core

DATAP

AUI

DB-15

Connector

TX+

TX-

Data

Driver

1

9

2

10

3

11

RX+

DATATP

4

12

Magnetics and

Passive

Components

Data

Receiver

5

DATAI

13

6

14

DATATN

RX-

7

15

8

COLLINP

COLLINN

COLL+

COLL-

Collision

Receiver

Without the integrated mixed signal I/O cores, multiple-port interfaces

produce high common-mode coherent noise, which requires the use of

expensive ﬁltering to meet FCC requirements.

3.4.1.1 6-Wire AUI Transmit Interface

With the six-wire AUI interface, the E-10 core outputs a single

Manchester-encoded signal, DATAP, to a mixed signal differential driver

core. The driver produces low common-mode noise differential outputs.

Using controlled impedance voltage, the driver produces the desired

output swing to the magnetics (transformer).

3-22

E-10 Functional Description

February 1997 - Rev. A

Using mixed signal drivers reduces the generation of high-frequency signal

components, which propagate easily and cause interference. High-

frequency components must otherwise be eliminated with external filtering.

Using mixed signal drivers minimizes external filtering requirements and

thereby reduces the associated external component costs.

3.4.1.2 6-Wire AUI Receive Interface

The six-wire twisted pair receive interface provides a receiver for data

and a receiver for collision control.

The data receiver has three signals at the E-10 core interface: DATATP,

DATATN, and DATAI. The three signals are inputs to the E-10 core and

come from a two-input differential mixed signal receiver.

The data receiver converts the two differential analog data signals from

the network to DATATP, DATATN, and DATAI. The three signals switch in

such a way that the E-10 core can properly perform data detection,

reverse polarity detection, and smart squelch.

The collision receiver has two signals at the E-10 core interface:

COLLINP and COLLINN. These two signals are inputs to the core and

come from a two-input differential mixed signal receiver

3.4.2 9-Wire AUI Interface

The nine-wire E-10 AUI interface is shown in Figure 3.10.

Ethernet-10 (E-10) Core Technical Manual

3-23

February 1997 - Rev. A

Figure 3.10 AUI 9-Wire Interface

ASIC

AUI

DB-15

Connector

E-10 Core

DATAP

Data

Driver

1

9

DATAN

2

10

3

11

DATATP

Data

4

12

Magnetics and

Passive

Components

DATAI

5

Receiver

13

6

DATATN

14

7

15

8

COLLINP

Collision

Receiver

COLLINN

3.4.2.1 9-Wire AUI Transmit Interface

With the nine-wire AUI interface, the E-10 core outputs two transmit

signals, the true and complemented (differential) Manchester-encoded

data signals DATAP and DATAN. The transmit circuitry sends these

differential signals to the AUI cable through a transformer.

A transformer isolates the transmit pins from the transceiver cable,

achieving system isolation.

3-24

E-10 Functional Description

February 1997 - Rev. A

3.4.2.2 9-Wire AUI Receive Interface

The nine-wire twisted pair receive interface provides a receiver for data

and a receiver for collision control.

The data receiver has three signals at the E-10 core interface: DATATP,

DATATN, and DATAI.

The data receiver converts the two differential analog data signals from

the network to DATATP, DATATN, and DATAI. The three signals switch in

such a way that the E-10 core can properly perform data detection,

reverse polarity detection, and smart squelch.

The collision receiver has two signals at the E-10 core interface:

COLLINP and COLLINN.

3.4.3 Signal Quality Error (SQE) Function (Heartbeat)

The Signal Quality Error (SQE) diagnostic feature has been speciﬁed for

the MAU in the IEEE 802.3 standard. The feature is supported by the

E-10 core when it operates in the AUI mode with an external MAU

(see Figure 3.8).

The SQE test is a self-test feature supported in the MAU that is invoked

after the end of each transmission by the DTE, where the E-10 core is

located. When enabled, the SQE test consists of a 10-MHz burst sent

from the MAU over the collision pair and starts six to 16 bit times (0.6 µs

to 1.6 µs) after the last transition of the transmitted signal and lasts for

a duration of ﬁve to 15 bit times. This test is an indication to the E-10

core that the MAU has recognized the end of the transmission and the

MAU collision circuitry is intact and operational.

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

3-26

E-10 Functional Description

February 1997 - Rev. A

Chapter 4

Functional Timing

This chapter describes the Media Access Controller (MAC) and E-10

clock timing and contains the following sections:

♦

Section 4.1, “MAC Transmission and Reception Timing”

Section 4.2, “E-10 Clock Timing”

Section 4.3, “Multiple Core Clocking”

4.1 MAC Transmission and Reception Timing

This section explains MAC transmission and reception timing, and

Manchester encoder-decoder (ENDEC) timing.

4.1.1 MAC Transmission Timing

Figure 4.1 shows the MAC transmission timing. The transmission

process starts with external logic asserting TAVAILP to indicate that a

complete frame is ready to be transmitted (a). The transmitter starts

transmitting (the E-10 core asserts TRNSMTP HIGH) as soon as it is

ﬁnished deferring, and then waits an additional 9.6 µs for the interframe

gap (b). At this time, the E-10 core pulses the TSTARTP pin to indicate

that transmit data is needed within 6.4 µs on the transmit data bus

(TDATAI[7:0]). At this point, the E-10 core pulses the TREADDP pin

every 800 ns for every byte of transmit data read from the transmit data

bus. There are gaps in the stream of TREADDP pulses when the

transmitter does an automatic insertion of the source address, pad ﬁeld,

or frame check sequence. External logic asserts the TLASTP signal,

accompanied by the last byte of transmit data.

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

The E-10 core stops transmission after the optional autoinsertion of the

pad and FCS ﬁelds and after all data has been transmitted to the

network (c). As soon as all transmit status bits are valid, the E-10 core

pulses the TDONEP pin to indicate that transmission of the frame is

complete (d). The TAVAILP signal is not sampled again until a minimum

of 800 ns after the TDONEP pulse, to give external logic time to do buffer

housekeeping, and to determine whether or not another buffer is ready

to be transmitted.

Figure 4.1 Successful Transmission

a

b

c

d

TAVAILP

TRNSMTP

TSTARTP

TLASTP

TREADDP

TDATAI[7:0]

TDONEP

D3 D4

DL

D1 D2

TSXXXX

(Status)

Note:TSXXXX consists of the following Transmit Status signals:

TSECOLP, TSIDEFP, TSLCOLP, TSMCOLP, TSNCLBP, TSOCOLP, and TSSQEEP

4-2

Functional Timing

February 1997 - Rev. A

4.1.1.1 Transmission Aborted by a Collision

A collision can abort a transmission. The timing for this condition is

shown in Figure 4.2. The transmission starts normally as shown in (a)

and (b). The transmitter transmits the complete preamble and start of

frame delimiter while it latches any collision. As soon as the transmitter

detects the presence of a collision after the SFD is transmitted (c), it

stops requesting additional transmit data bytes, transmits four bytes of

alternating ones and zeros and then terminates the transmission without

asserting a TDONEP pulse (d). After the transmission is terminated, the

transmitter starts the backoff algorithm, and then, after deferring, starts

a frame retransmission.

Figure 4.2 Transmission Aborted by a Collision

a

b

c

d

TAVAILP

TRNSMTP

TSTARTP

TLASTP

TREADDP

TDATAI[7:0]

TDONEP

D1 D2

D3

TSXXXX

(Status)

Note:TSXXXX consists of the following Transmit Status signals:

TSECOLP, TSIDEFP, TSLCOLP, TSMCOLP, TSNCLBP, TSOCOLP, and TSSQEEP

4.1.1.2 Retransmission

The host asserts AVAILP to the E-10 core when the host has one or

more frames available to be transmitted. A transmission that was aborted

by a collision initiates a retransmission. After the backoff algorithm and

deferral, the E-10 core starts the retransmission. The E-10 core does not

sample the TAVAILP signal during a retransmission, but the rest of the

timing is identical to any normal transmission. The host asserts the

TLASTP signal to indicate to the core that the TDATA[7:0] signals from

the host contain the last byte of data in the frame.

Ethernet-10 (E-10) Core Technical Manual

4-3

February 1997 - Rev. A

4.1.1.3 Transmission Aborted by TABORTP

When external logic decides it wants to terminate a transmission (for

example, after a transmission data underrun), it can assert the signal

TABORTP instead of sending a new transmit data byte. The timing for

this condition is shown in Figure 4.3. The transmission starts normally as

shown in (a) and (b). The transmitter terminates the transmission when

it detects the assertion of TABORTP (c) after transmitting four bytes of

alternating ones and zeros (d). This operation is identical to a

transmission aborted by a collision.

Figure 4.3 Transmission Aborted by TABORTP

a

b

c

d

TAVAILP

TRNSMTP

TSTARTP

TABORTP

TREADDP

TDATAI[7:0]

TDONEP

D1 D2

XX

TSXXXX

(Status)

Note:TSXXXX consists of the following Transmit Status signals:

TSECOLP, TSIDEFP, TSLCOLP, TSMCOLP, TSNCLBP, TSOCOLP, and TSSQEEP

4.1.1.4 Transmission Terminated With TFINISHP

When the signal TFINISHP is asserted at the end of a transmission, the

MAC terminates the transmission with the assertion of TDONEP,

independent of the detection of a collision. The frame is not retried, even

if it normally would have been. Assertion of TFINISHP can prevent a

frame from being retried independent of the normal default conditions.

For example, the transmit status pin TSLCOLP can be connected to

TFINISHP to prevent frames with a late collision from being retried.

4-4

Functional Timing

February 1997 - Rev. A

4.1.2 MAC Reception Timing

MAC reception timing is shown in Figure 4.4. When the E-10 core

receives a frame from the network, the data recovery digital PLL locks

onto the transitions of the preamble. Phase-lock occurs within six to eight

bit times (three bits for intelligent squelch operation and the remainder

for the PLL to operate). When phase-lock occurs, the E-10 core asserts

the RLOCKEDP pin (a). The receiver then goes into receiving mode and

asserts RCVNGP (b) when the start of frame delimiter is detected (b).

The beginning of a reception is marked with an RSTARTP pulse, which

prepares the off-core logic for the arrival of new data. The off-core logic

has 800 ns to make a new receive buffer available before new data bytes

start arriving (indicated by RBYTEP pulses). Reception is stopped when

the end of frame delimiter is detected and the receive status pins

(RSxxxx) are valid. Section 2.4, “Receiver Status Signals,” lists the

individual receive status pins. The RDONEP pulse indicates to external

logic that the received frame is complete (c).

Figure 4.4 Successful Reception

a

b

c

RLOCKEDP

RCVNGP

RSTARTP

RBYTEP

D1 D2 D3

DL-1

DL

RDATAO[7:0]

RDONEP

RCLEANP

RSXXXX

(Status)

Note:RSXXXX consists of the following Transmit Status signals:

RSDRBLEP, RSFCSEP, RSMATIP, RSMATMP and RSPLLEP

Ethernet-10 (E-10) Core Technical Manual

4-5

February 1997 - Rev. A

4.1.2.1 Reception With No Individual Address Filter Match

Figure 4.5 shows the timing of the address ﬁlters during reception.

Packet reception begins at (a). When all address ﬁlters do not match

during a reception of a frame from the network (b), the receiver stops

transferring received data to the host. When reception stops, the receiver

terminates with the assertion of the RCLEANP pulse (c).

Figure 4.5 Reception With No Individual Address Filter Match

a

b

c

RCVNGP

RSTARTP

RBYTEP

D1 D2 D3 D4 D5

D6

RDATAO[7:0]

RDONEP

RCLEANP

RSXXXX

(Status)

Note:RSXXXX consists of the following Transmit Status signals:

RSDRBLEP, RSFCSEP, RSMATIP, RSMATMP and RSPLLEP

4-6

Functional Timing

February 1997 - Rev. A

4.1.2.2 Reception With External Multicast Filter Match

Figure 4.6 shows the external multicast filter match timing. Packet

reception begins at (a). When multicast is enabled, and a multicast frame

is received from the network, the receive engine calculates a nine-bit hash

function (MINDEXO[8:0]) from the 48-bit multicast destination address.

The receiver indicates to external logic to either accept or reject the

message with the MSTARTP pulse (b). External logic has until the end of

a minimum length frame (51.2 µs from the SFD) to make a decision.

When the external logic decides to accept the frame, it asserts the MBITP

signal and pulses the MDONEP input (c). The receiver now permanently

asserts the RSMATMP signal and accepts the rest of the frame, and when

the receiver is finished, it asserts the RDONEP pulse (d).

Figure 4.6 Reception With External Multicast Filter Match

a

b

c

d

RCVNGP

RSTARTP

RBYTEP

D1 D2 D3 D4 D5 D6 D7 D8

DL-1 DL

RDATAO[7:0]

MSTARTP

MINDEXO[8:0]

MDONEP

MBITP

RSMATMP

RDONEP

Ethernet-10 (E-10) Core Technical Manual

4-7

February 1997 - Rev. A

4.1.2.3 Reception With No External Multicast Filter Match

Figure 4.7 shows the no external multicast filter match timing. Packet

reception begins at (a). A pulse on MSTARTP (b) indicates to the external

logic that a new nine-bit hash function has been computed from the

destination address. When the external logic decides to reject the frame,

it deasserts the MBITP signal and pulses the MDONEP input to indicate

to the receiver that it has made the decision (c). The receiver now

deasserts the RSMATMP signal and rejects the rest of the frame. When

the receiver is finished, the E-10 core pulses the RCLEANP pin (d).

Figure 4.7 Reception With No External Multicast Filter Match

a

b

c

d

RCVNGP

RSTARTP

RBYTEP

D1 D2 D3 D4 D5 D6

D7

RDATAO[7:0]

MSTARTP

MINDEXO[8:0]

MDONEP

MBITP

RSMATMP

RCLEANP

4-8

Functional Timing

February 1997 - Rev. A

4.1.3 ENDEC Timing

Examples of ENDEC timing are shown in Figure 4.8 and Figure 4.9. The

bit times shown in the diagrams are 100 ns in duration.

Figure 4.8 Twisted Pair Serial Output Data

1

Idle

0

1

0

EOF (300 ns)

Idle

DATAP

DATAN

PREEP

PREEN

Externally

Combined

Signal

Figure 4.9 Twisted Pair Link Integrity Pulses

100-ns

Idle

Pulse

DATAP

DATAN

PREEP

PREEN

Externally

Combined

Signal

Ethernet-10 (E-10) Core Technical Manual

4-9

February 1997 - Rev. A

4.2 E-10 Clock Timing

This section explains the E-10 clock, receiver, and transmitter timing.

The input clock to the E-10 core is 80 MHz. The duty cycle should have

a nominal duty cycle of 50/50, with a worst-case duty cycle of 60/40

because both the LOW-to HIGH and the HIGH-to-LOW transitions of this

signal are used in the digital phase-locked loop that samples the input

data. The MAC timing logic divides the 80 MHz down to 20 MHz and

10 MHz. These derived frequencies are available on the E-10 output pins.

Noninverting buffers have to be put outside of the E-10 core. The outputs

of these buffers have to be routed back to the E-10 input pins as shown

in Figure 4.10. The E-10 core expects all input signals from the host to

be synchronous with its own 10-MHz clock rate. This requirement for

synchronism dictates that the external logic use the same synchronous

10-MHz clock driver that E-10 uses. If more than one E-10 core resides

on the same chip, only the clock drivers from a single E-10 core can drive

all clock inputs and the external logic.

Figure 4.10 E-10 Clock Buffers

E-10 Core

CLK80

from clock_driver

or PLL

CLK80

CLK20I

CLK10I

CLK20

CLK10

CLK20O

CLK10O

Because the transmit clock is derived from the 80 MHz input clock, the

maximum clock error has to comply with the IEEE 802.3 maximum error

of ± 0.01% or 100 ppm.

4-10

Functional Timing

February 1997 - Rev. A

4.3 Multiple Core Clocking

Multiple E-10 cores can be used in an ASIC. This section describes how

multiple E-10 core clocking can best be accomplished.

4.3.1 Core Clocks

The E-10 core uses three different clocks:

♦

80 MHz. This clock is used as the primary timing input, and is used

in several places, as follows:

–

Clocking the data recovery digital PLL

Clocking the Ethernet signal squelch circuits

Generating the lower frequency clocks (20 and 10 MHz)

♦

20 MHz. This clock is used for the Manchester encoding.

10 MHz. This main clock drives the MAC, ENDEC, and Transceiver

state machines.

The E-10 core does not contain any clock drivers. The designer should

add two clock buffers (see Figure 4.10) of sufﬁcient strength to drive all

E-10 cores in parallel. The 10- and 20-MHz clock buffers should be

driven by the 10- and 20-MHz output pins of only one of the E-10 cores.

4.3.2 80-MHz Clock

The 80-MHz clock can be generated by a Phase-Locked Loop (PLL),

which consists of a phase comparator, external loop ﬁlter, and voltage-

controlled oscillator (see Figure 4.11). The reference input can be a

10- or 20-MHz clock or can be driven by an on chip 10- or 20-MHz

crystal oscillator. Generating the 80-MHz clock on the chip reduces the

higher frequencies on the printed circuit board and should allow for

easier passing of the FCC emissions test.

Ethernet-10 (E-10) Core Technical Manual

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February 1997 - Rev. A

4.3.3 10- and 20-MHz Clocks

The 10- and 20-MHz inputs should be synchronized to the 80-MHz input

clock. The E-10 core generates 20- and 10-MHz clocks and makes these

three signals available on core output pins. The 20- and 10-MHz output

pins of only one of the E-10 cores should be used to drive all E-10 cores

on the chip. Most of the input signals of the E-10 core are synchronous

and should be clocked with the same 10-MHz clock as is used by the

cores. The 10- and 20-MHz clock buffers should be strong enough to

allow for a delay of no more than 9 ns from CLK80 input to the CLK10

and CLK20 inputs.

4.3.4 E-10 Testing

To allow testing of the E-10 cores, the three clocks used by the cores

should be multiplexed with three signals coming directly from the input

pins. The E-10 test vectors need direct control over the three test inputs

plus the multiplexer control input. The clock multiplexing scheme is

shown in Figure 4.11.

4-12

Functional Timing

February 1997 - Rev. A

Figure 4.11 Multiple-Core Clock Multiplexing

Test_CLK80

Clock

E-10

Multiplexers Buffers

Core #1

80-MHz

VCO

CLK80I

CLK20O

CLK20I

CLK10O

Not Connected

Test_CLK20

Test_CLK10

CLK10I

E-10

Core #2

Loop

Phase

FiLter

Compare

CLK80I

CLK20I

CLK10I

Clock Reference

10- or 20-MHz

Test_Enable

CLK20O

CLK10O

Not Connected

E-10

Core #n

10- or 20-MHz

External Clock

CLK80I

CLK20I

CLK10I

CLK20O

CLK10O

Clocks for

Synchronous

Interface

Ethernet-10 (E-10) Core Technical Manual

4-13

February 1997 - Rev. A

4-14

Functional Timing

February 1997 - Rev. A

Chapter 5

Speciﬁcations

This chapter provides speciﬁcations for the E-10 core, including the

AC timing as well as input and output loading, driver type, and power

consumption.

This chapter has three sections:

♦

Section 5.1, “Derivation of AC Timing and Loading”

Section 5.2, “AC Timing”

Section 5.3, “Pin Summary”

5.1 Derivation of AC Timing and Loading

Every customer that buys a core from LSI Logic for incorporation into an

ASIC also receives delay predictor software, which gives you an input

loading report so you can plan for buffer strengths that drive core inputs.

When you integrate the core into the rest of your logic and run other

simulation software, you get a ramptime violation report that indicates if

a core output is too heavily loaded. You can then adjust buffering, wire

length, and other parameters to eliminate the violation.

As a result, there are no speciﬁc numbers in this chapter for AC timing

and loading, because the numbers depend on the technology you use

and the design layout.

5.2 AC Timing

This section gives a list of the signals that must operate properly with

respect to the CLK10I and CLK20O signals. The relationship between

the signals is depicted in Figure 5.1 and Figure 5.2.

Ethernet-10 (E-10) Core Technical Manual

5-1

February 1997 - Rev. A

The numbers in Figure 5.1 and Figure 5.2 refer to the AC timing

parameters listed in the ﬁrst column of Table 5.1. The core has been

veriﬁed under worst-case process voltage and ambient temperature.

Table 5.1 E-10 Core AC Timing Parameters

Parameter

Description

TFINISHP setup to CLK10I

TFINISHP hold from CLK10I

TAVAILP setup to CLK10I

TAVAILP hold from CLK10I

TDATAI[7:0] setup to CLK10I

TDATAI[7:0] hold from CLK10I

TABORTP setup to CLK10I

TABORTP hold from CLK10I

TLASTP setup to CLK10I

TLASTP hold from CLK10I

RENABP setup to CLK10I

RENABP hold from CLK10I

MDONEP setup to CLK10I

MDONEP hold from CLK10I

MBITP setup to CLK10I

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

MBITP hold from CLK10I

TSTARTP delay from CLK10I

TDONEP delay from CLK10I

TREADDP delay from CLK10I

TRNSMTP delay from CLK10I

RSTARTP delay from CLK10I

5-2

Speciﬁcations

February 1997 - Rev. A

Table 5.1 (Cont.) E-10 Core AC Timing Parameters

Parameter

Description

RDONEP delay from CLK10I

RCLEANP delay from CLK10I

RBYTEP delay from CLK10I

RDATAO[7:0] delay from CLK10I

RCVNGP delay from CLK10I

RLOCKEDP delay from CLK10I

DATAP delay from CLK20O

DATAN delay from CLK20O

PREEP delay from CLK20O

PREEN delay from CLK20O

LPASSP delay from CLK10I

LPBADP delay from CLK10I

COLLOUTP delay from CLK10I

MSTARTP delay from CLK10I

MINDEXO[8:0] delay from CLK10I

RESETN pulse width

22.

23.

24.

25.

26.

27.

28.

29.

30.

31.

32.

33.

34.

35.

36.

37.

38.

39.

RESETN LOW before CLK10I rise

RESETN HIGH before CLK10I rise

Ethernet-10 (E-10) Core Technical Manual

5-3

February 1997 - Rev. A

Figure 5.1 E-10 Core Setup and Hold Timing Diagram

CLK10I

1, 3, 5, 7, 9, 11, 13, 15

2, 4, 6, 8, 10, 12, 14, 16

Valid

Inputs

17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 32, 33, 34, 35, 36

Valid

Outputs

CLK20O

Outputs

28, 29, 30, 31

Valid

Figure 5.2 E-10 Core Reset Timing Diagram

37

RESETN

38

39

CLK10O

5.3 Pin Summary

Table 5.2 summarizes the E-10 core input and output signals. The table

provides the signal names and types for both outputs and inputs.

5-4

Speciﬁcations

February 1997 - Rev. A

Table 5.2 E-10 Pin Summary

Mnemonic

Description

Type

Active

CLK80I

80-MHz Clock

Input

Output

Input

–

CLK10I

10-MHz Clock

CLK20I

20-MHz Clock

CLK10O

CLK20O

COLLINN

COLLINP

COLLOUTP

DATAI

10-MHz Clock

20-MHz Clock

Negative Collision Threshold

Positive Collision Threshold

Transmit Collision

Data Input from Network

Positive Data

Output HIGH

Input

–

DATAP

Output

Input

DATAN

Negative Data

DATATP

Positive Data Threshold

Negative Data Threshold

Drive Enable

DATATN

Input

DRIVEENN

DUPLEXP

FASTESTN

LCORPP

LFORCEP

LOOPBKP

LPASSP

LPBADP

MBITP

Output LOW

Full Duplex Select

Fast Test

Input

HIGH

LOW

HIGH

Link Correct Polarity

Force Link

Loopback Enable

Link Pass

Output HIGH

Link Polarity Bad

Multicast Hash Table Bit

Multicast Filter Done

Input

HIGH

MDONEP

(Sheet 1 of 3)

Ethernet-10 (E-10) Core Technical Manual

5-5

February 1997 - Rev. A

Table 5.2 (Cont.) E-10 Pin Summary

Mnemonic

Description

Type

Active

MINDEXO[8:0] Multicast Hash Function

Output

–

MSTARTP

Multicast Filter Start

Node Address

Output HIGH

NOAD-

Input

–

DRI[47:0]

PREEP

Positive Data Pre-Emphasis

Negative Data Pre-Emphasis

Received Byte

Output

–

PREEN

RBYTEP

Output HIGH

RCLEANP

RCVNGP

RDATAO[7:0]

RDONEP

RENABP

RESETN

RLOCKEDP

RMCENP

RPMENP

RSDRBLEP

RSFCSEP

Receiver Cleanup

Receiving

Received Data

Output

–

Receiver Done

Output HIGH

Receive Enable

Input

HIGH

LOW

Reset

Receiver Locked Output

Receive Multicast Enable

Receive Promiscuous Mode Enable

Receive Status Dribble Bits

Output HIGH

Input

HIGH

Output HIGH

Receive Status Frame Check Sequence

Error

RSMATIP

RSMATMP

RSPLLEP

RSTARTP

Receive Status Match Individual Address Output HIGH

Receive Status Match Multicast Address Output HIGH

Receive Status Phase-Locked Loop Error Output HIGH

Receiver Start Output HIGH

RSNOOPENP Receiver Lookback Enable

Input

HIGH

–

SELIO

4-Wire/8-Wire Mixed Signal Cell Select

(Sheet 2 of 3)

5-6

Speciﬁcations

February 1997 - Rev. A

Table 5.2 (Cont.) E-10 Pin Summary

Mnemonic

Description

Type

Active

TABORTP

TAVAILP

Transmit Abort

Input

HIGH

–

Transmitter Packet Available

Transmit Control

TCTRI[3:0]

TDATAI[7:0]

TDONEP

TESTSE

Transmit Data

–

Transmit Done

Output HIGH

Scan Enable

Input

Output

Input

HIGH

–

TESTSI

Scan Input

TESTSO

TEST1N

Scan Output

–

Fast Test

LOW

HIGH

–

TEST2N

Reset B

TFINISHP

TLASTP

Transmit Finish

Transmit Last Byte

Test Mode

TMODE

TP/AUI

Twisted-Pair/AUI Select

Transmitter Read Control

Transmitting

TREADDP

TRNSMTP

TSECOLP

TSIDEFP

TSLCOLP

TSMCOLP

TSNCLBP

TSOCOLP

TSSQEEP

TSTARTP

Output HIGH

Transmit Status Excessive Collisions

Transmit Status Initially Deferred

Transmit Status Late Collision

Transmit Status Multiple Collision

Transmit Status No Carrier Loopback

Transmit Status One Collision

Transmit Status SQE Error

Transmit Start

(Sheet 3 of 3)

Ethernet-10 (E-10) Core Technical Manual

5-7

February 1997 - Rev. A

5-8

Speciﬁcations

February 1997 - Rev. A

Appendix A

Glossary

Address Filtering (Individual, Multicast, Promiscuous) – Address

ﬁltering is the process the E-10 core performs to match a destination

address within a received frame with an address derived at the receiving

station. Three common types of address ﬁltering are:

♦

Individual—the ﬁrst bit of an individual address is a zero. The

incoming destination address is compared with the data from the

individual address pins. When all 48 bits match and the receiver is

enabled, the address ﬁlter passes.

♦

Multicast—the ﬁrst bit of an multicast address is a one. When the

destination address bits that are received in the frame contain a

multicast address, the E-10 core uses its built-in FCS generator to

compute a nine-bit polynomial (the nine MSBs of the 32-bit FCS

generator) from the incoming address. The value of this polynomial

can be used as an index into an external multicast ﬁlter hash table.

External logic can decide to either accept or reject the incoming

frame. The external logic enables the multicast address ﬁlter.

♦

Promiscuous—when the external logic asserts the individual address

promiscuous mode enable pin (RPMEN) HIGH and the destination

address is an individual address, the address ﬁlter always passes,

and the incoming frame is received.

Attachment Unit Interface (AUI) – The AUI is the interface between the

Medium Attachment Unit (MAU) and the data terminal equipment (DTE)

device or repeater. A typical AUI interface consists of a 15-pin “D” connector.

Backoff – In IEEE 802.3 networks, backoff occurs when two or more

nodes attempt a transmission and collide. The function of stopping

transmission, and waiting a speciﬁed random time before retrying the

transmission is considered backoff. In IEEE 802.3 networks a “truncated

binary exponential backoff” algorithm is employed.

Ethernet-10 (E-10) Core Technical Manual

A-1

February 1997 - Rev. A

Coaxial Cable – Coaxial cable is a transmission medium with a central

copper-wire conductor surrounded by concentric layers of plastic/polyvinyl

chloride, aluminum or aluminized mylar and a copper tube that acts as

an insulator (ground) and source of shielding from electromagnetic and

radio frequency interference (CMI/RFI). Two types of coaxial cable—

known as “thick” and “thin” for their respective diameters—are used in

Ethernet data transmissions.

Collision – When an Ethernet station is operating in the AUI mode, it

can sense a change in the energy level of the communication channel

and interpret the phenomenon as a collision. A collision is caused by two

stations attempting to transmit at the same time.

Collision Detection – Collision detection is the ability of a transmitting

node on an Ethernet LAN to sense a change in the energy level of the

channel and to interpret the phenomenon as a collision

CRC (Cyclic Redundancy Check) – CRC is a basic error-checking

mechanism for link-level data transmission; a characteristic link-level

feature of (typically) bit-oriented data communications protocols. The

data integrity of a received frame or packet is checked via a polynomial

algorithm based on the content of the frame and then matched with the

result that is performed by the sender and included in a (most often,

16-bit) ﬁeld appended to the frame.

CSMA/CD (Carrier Sense Multiple Access with Collision

Detection) – CSMA/CD is a LAN protocol access method where the

nodes are attached to a cable. When a node transmits data onto the

network and raises the carrier, the remaining nodes detect the carrier

(Carrier Sense) and “listen” for the information to detect if it is intended

for them. The nodes have network access (Multiple Access) and can

send if no other transmission is taking place. If two nodes attempt to

send simultaneously, a collision takes place (Collision Detection) and

both nodes must retry at random intervals.

Data Recovery – The data sent over an Ethernet LAN is Manchester-

encoded and must be recovered by the receiving station. In the E-10

core, a digital phase-locked loop recovers the data through a sampling

process and has the necessary elasticity to allow for the bit drift that

occurs over lengthy frame sizes.

A-2

Glossary

February 1997 - Rev. A

Dribble Bit – A dribble bit is a bit that is “extra” and occurs when, at the

end of a frame, less than a complete byte is received. It is possible to

have from one to seven dribble bits at the end of a frame if a complete

byte is not received.

Dropout Error – A dropout error occurs when the carrier on a

transmission channel stops due to a broken or missing cable.

Elasticity – Elasticity is a measure of the tolerance of the phase-locked

loop to the cumulative bit shift due to small differences in the free

running clock oscillator frequencies of the transmitting source and

receiving destination.

End-of-Frame Delimiter – An end-of-frame delimiter is a series of three

bits of ones at the end of a frame that are not Manchester-encoded; that is,

they are non-return-to-zero bits that do not contain a transition in the

middle of the bit time. The purpose of the end-of-frame delimiter is to

cause the PLL at the receiving station to lose lock so the host can be

notiﬁed that the frame has ended.

When a receiving node detects a bit that is not Manchester-encoded, it

considers the previous four bytes to be the FCS.

ENDEC – ENDEC is short for Encoder/Decoder and is a functional block

within network adapters that performs two basic functions. First, this

function encodes the data from the controller to be transmitted over the

network. Second, it decodes the data on the network to a form suitable

for the network controller chip. In the case of Ethernet, the ENDEC

converts NRZ controller data to Manchester data (and back again).

Ethernet Local Area Network (LAN) – An Ethernet LAN is a branching

broadcast communications system for carrying digital data packets

among locally distributed computing stations. Ethernet is a 10 Mbit/s

baseband, Local Area Network that has evolved into the IEEE 802.3

speciﬁcation and is deﬁned by a data-link protocol that speciﬁes how

data is placed on and retrieved from a common transmission medium.

Ethernet is used as the underlying transport vehicle by several upper

level protocols, including TCP/IP and Xerox Network System (XNS).

See IEEE 802.3.

Ethernet-10 (E-10) Core Technical Manual

A-3

February 1997 - Rev. A

Frame – An Ethernet frame contains the following eight ﬁelds:

♦

Preamble

Start-of-Frame Delimiter

Destination Address

Source Address

Length

Data

Pad (if necessary)

Frame Check Sequence

Frame Check Sequence (FCS) – The Ethernet transmit and receive

algorithm uses the standard IEEE 802.3 four-byte frame check sequence

(FCS) ﬁeld to ensure data integrity. During data transmission, the E-10

core uses a 32-bit linear feedback shift register (LFSR) to compute the

value that will be sent in the FCS ﬁeld. The FCS value is a function of

the content of the source address, destination address, length, data, and

pad ﬁelds. On data reception, the E-10 core preloads the LFSR with all

ones and updates this value with each byte received, including the

received FCS. If the ﬁnal value in the LFSR does not match a

predetermined value after all bytes including the FCS are received, the

E-10 core ﬂags an FCS error.

Heartbeat – In IEEE 802.3 networks, a heartbeat is a short burst of

collision signal that is transmitted from the MAU to the DTE after every

packet. See Signal Quality Error (SQE) Test.

Hub – The E-10 core operating in 10BASE-T mode uses a hub to

concentrate connections to multiple terminals. Hubs come in various

sizes, with 4-port, 8-port, and 12-port being the most common. The

number of ports indicates the number of terminals that can be connected

to the hub. Most hubs have built-in transceivers and network

management features. Hubs are mainly used in star topology LANs. The

E-10 core is speciﬁcally designed for multiple-core integration, especially

for “hub-on-a-chip” implementations.

A-4

Glossary

February 1997 - Rev. A

IEEE 802.3 – IEEE 802.3 is a standard set by the IEEE for CSMA/CD

network protocol, which is a Physical Layer deﬁnition including

speciﬁcations for cabling in addition to transmitting data and controlling

cable access. See Ethernet LAN.

Jam – In IEEE 802.3 networks, when a collision occurs the colliding

nodes ensure that the collision is seen by the entire network by

continuing to transmit for a minimum time during a collision. This

occurrence is known as jamming.

Jitter – Jitter is the slight movement of a transmission signal in time or

phase that can introduce errors and loss of synchronization in high-

speed synchronous communications.

LAN (Local Area Network) – A LAN is a communications system

linking computers together to form a network whose dimensions typically

are less than ﬁve kilometers. Transmissions within a Local Area Network

generally are digital, carrying data among stations at rates usually above

one megabit per second. A LAN is an assembly of computing resources

such as microcomputers (for example, PCs), printers, minicomputers and

mainframes linked by a common transmission medium, including coaxial

cable or twisted-pair wiring.

Link Failure – In the Twisted-Pair mode, a link failure can be caused by

a twisted-pair transceiver failure or by a broken twisted-pair receive

cable. A link failure occurs when there are eight consecutive missing link

integrity pulses.

Link Integrity Pulses – The E-10 core monitors Link Integrity pulses,

which may be sent on a regular basis from any other device on the

network when the channel is idle. The purpose of the pulses is to ensure

that the channel is functional even in the absence of active data. The

Link Integrity pulses should be positive-going pulses spaced

approximately 50 milliseconds apart.

Link Polarity Detection/Correction – Link Integrity pulses should be

positive-going pulses. If they are not, it is an indication that the wiring is

inverted. The E-10 core can optionally, under control of the host, invert

the data on the receive pair when it detects that eight consecutive Link

Integrity pulses have been received with inverted polarity.

Ethernet-10 (E-10) Core Technical Manual

A-5

February 1997 - Rev. A

Lock Time – Lock time is the amount of time it takes the receiver phase-

locked loop to achieve phase lock with an input signal, which may be

either data bits or preamble bits. It takes approximately six to eight bits

for the E-10 digital phase-locked loop circuit to achieve lock. Three bits

are required for the smart squelch operation and the remaining bits are

required for the PLL to operate.

Loopback – When the E-10 core is in loopback mode, the transmitter

output is fed back to the receiver input inside the chip. Loopback mode

allows testing of the E-10 transmitter and receiver up to but not including

the off-core transceivers under program control without the need of an

external loopback connector. Loopback is applicable to both the AUI and

Twisted-Pair modes.

Another loopback mode is known as “lookback.” When the E-10 core is

in lookback mode, all transmitted frames are routed back through the

receiver. Operation is similar to that of normal loopback described in the

previous paragraph except that the phase-locked loop is bypassed.

MAC (Media Access Control) – The data link sublayer that is

responsible for transferring data to and from the physical layer.

Manchester Encoding/Decoding – A Manchester-encoded bit contains

a transition (either HIGH-to-LOW or LOW-to-HIGH) in the center of the

bit time. Having a transition every bit time allows a phase-locked loop at

a receiving station to maintain lock and extract both data and clock from

the waveform.

With Manchester encoding, each bit is divided into two complementary

halves. A LOW-to-HIGH voltage transition in the middle of the bit period

designates a binary one, while a HIGH-to-LOW transition represents a

binary zero.

MAU (Media Attachment Unit) – An MAU is the physical and electrical

component that provides the means of attaching a terminal to a local

area network medium.

Multicast Hash Function – See address ﬁltering (multicast).

Packet – A packet is data sent in the data ﬁeld of an Ethernet frame.

A-6

Glossary

February 1997 - Rev. A

Phase-Locked Loop Circuit – A phase-locked loop circuit operates

from a local free-running oscillator and is able to achieve and maintain

phase and frequency with a signal received from a source that is

operating on a different free-running oscillator. The purpose of a phase-

locked loop is to provide a clock source that is synchronous with data

that is derived from a different clock source. Such a circuit is used

commonly in telecommunications systems where data is transmitted

without an accompanying clock.

Pre-Emphasis – The purpose of pre-emphasis is to increase the

amplitude of the higher frequencies in an output signal. Data pre-emphasis

guarantees that an Ethernet system operating Twisted-Pair mode can drive

signals properly at 10 Mbit/s on cable up to 100 meters long.

Router – A router is similar to a bridge but has the ability to connect

networks at the OSI network level, as shown in Figure A.1.

Figure A.1 Router OSI Interconnect Level

Application

Presentation

Session

Application

Presentation

Session

Transport

Network

Transport

Network

LLC Sublevel

MAC Sublevel

Data Link

Physical

Data Link

Physical

Router

Source: In-Stat

A router is an intelligent device that plans the most efﬁcient route for data

to move between networks. Routers generally have the ability to recover

lost data packets. The end user must address the router to send data

through it. Routers are slower in the transfer of data than bridges and

are more expensive to purchase. For this reason, routers are not used

to connect LANs (although it is possible) but are more commonly used

to connect LANs to wide area networks.

Ethernet-10 (E-10) Core Technical Manual

A-7

February 1997 - Rev. A

Runt Packet – In IEEE 802.3 networks, a runt packet is a special case of

a fragment packet where the length of the packet is less than 512 bit times.

Signal Quality Error (SQE) Test – The Signal Quality Error (SQE) test

is a self-test feature supported in the MAU that is invoked after the end

of each transmission by the station. When enabled, the SQE test

consists of a 10-MHz burst and starts six to sixteen bit times (0.6 µs to

1.6 µs) after the last transition of the transmitted signal and lasts for a

duration of ﬁve to 15 bit times. This test is an indication to the station

that the MAU has recognized the end of the transmission and the MAU

collision circuitry is intact and operational.

Slot Time – A slot time is 512 bit times (51.2 µs), and is the time it takes

to “ﬁll up” an Ethernet cable with data. In AUI mode, if the receive

circuitry of a station does not detect a carrier within one slot time from

the initiation of transmission (preamble start), it is an indication of trouble

on the cable.

Smart Receive Squelch – An intelligent (smart) receive squelch is

implemented on the receiver differential inputs to ensure that impulse

noise on the receive inputs is not mistaken for a valid signal. The smart

squelch logic uses a combination of amplitude and timing measurements

to determine the validity of data.

SQE Burst (Heartbeat) – See Signal Quality Error (SQE) Test.

Start of Frame Delimiter (SFD) – The eight-bit start of frame delimiter

ﬁeld follows the seven-octet preamble at the beginning of a frame and

contains the 10101011 bit pattern. This pattern allows synchronization

2

of the data received in the rest of the frame.

Tracking Speed – Tracking speed refers to the speed with which a PLL

responds to changes in the incoming signal. In the E-10 core, when ﬁrst

attempting to lock on to an oncoming data stream (during the ﬁrst 4.8

µs), the PLL looks every 16 bits (1.6 µs) to see if a bit transition is

occurring in the center of the sampling window. After the ﬁrst 4.8 µs, the

PLL maintains a window of 64 bits (6.4 µs) for ﬁnding a transition.

A-8

Glossary

February 1997 - Rev. A

Transceiver – A transceiver is a combined transmitter and receiver and

is an essential element of all LAN networks. When an Ethernet LAN

operates in the 10BASE-2 or 10BASE-5 mode, the transceivers are

generally located in the MAU and connect directly to the coaxial cable.

In the Twisted-Pair mode, the transceivers are generally located in the

data terminal equipment and connect directly to the twisted-pair cable.

Transmit Carrier Loopback – Transmit Carrier Loopback occurs in the

AUI mode. When a station transmits onto the wire, it should detect its

own activity on the line within 512 bit times (51.2 µs), which is the

maximum amount of time to “ﬁll the wire” under normal circumstances.

Transmit Carrier Loopback Error – Transmit Carrier Loopback Error

occurs when a station does not detect its own activity on the line within

512 bit times (51.2 µs).

Transmit Carrier Dropout Error – A transmit carrier dropout error

occurs when the carrier on a transmission channel stops due to a broken

or missing cable, or bad transceivers.

Twisted-Pair Transmission System – In 10BASE-T terminology, this

term refers to the twisted-pair wire link and its two attached MAUs.

Twisted-Pair Wire – Twisted-pair wire is a cable comprised of two 18 to

24 AWG (American Wire Gauge) solid copper strands twisted around

each other. The twisting provides a measure of protection from

electromagnetic and radio-frequency interference (EMI/RFI). Two types

are available: shielded and unshielded. The former is wrapped inside a

metallic sheath that provides protection from EMI/RFI. The latter, also

known as telephone wire, is covered with plastic or PVC, which provides

no protection from EMI/RFI.

10BASE-2 – 10BASE-2 is the IEEE 802.3 Physical Layer Standard for

thin wire Ethernet (sometimes called cheapernet). This standard uses

RG58 standard coaxial cable. 10BASE2 stands for: 10 = 10 Mbit/s data

rate, BASE = Baseband, 2 = 185 meter segment length.

10BASE-5 – 10BASE-5 is the IEEE 802.3 Physical Layer Standard for

thick cable Ethernet, utilizing thick double shielded coaxial cable.

10BASE-5 stands for: 10 = 10 Mbit/s data rate, BASE = Baseband,

5 = 500 meters segment length.

Ethernet-10 (E-10) Core Technical Manual

A-9

February 1997 - Rev. A

10BASE-F – 10BASE-F is the IEEE 802.3 Physical Layer Standard for

ﬁber-based Ethernet. 10BASE-F stands for; 10 = 10 Mbit/s data rate,

BASE = baseband, F= ﬁber.

10BASE-T – 10BASE-T is the IEEE 802.3 Physical Layer Standard for

the new twisted-pair Ethernet in a star topology. 10BASE-T stands for;

10 = 10 Mbit/s data rate, BASE = baseband, T = Twisted-pair over 100

meters nominal segment length.

A-10

Glossary

February 1997 - Rev. A

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LSI Logic Corporation

Corporate Headquarters

Tel: 408.433.8000

Fax: 408.433.8989

New Jersey

Edison

Denmark

LSI Logic Development

Centre

Korea

LSI Logic Corporation of

Korea Ltd

Seoul

♦ Tel: 908.549.4500

Fax: 908.549.4802

Ballerup

Tel: 45.44.86.55.55

Fax: 45.44.86.55.56

♦ Tel: 82.2.561.2921

NORTH AMERICA

New York

Fax: 82.2.554.9327

New York

California

Irvine

Tel: 716.223.8820

Fax: 716.223.8822

France

LSI Logic S.A.

Paris

Singapore

LSI Logic Pte Ltd

Singapore

Tel: 65.334.9061

Fax: 65.334.4749

♦ Tel: 714.553.5600

Fax: 714.474.8101

North Carolina

Raleigh

♦ Tel: 33.1.34.63.13.13

Fax: 33.1.34.63.13.19

San Diego

Tel: 619.635.1300

Fax: 619.635.1350

Tel: 919.783.8833

Fax: 919.783.8909

Germany

LSI Logic GmbH

Munich

Electronic Resources Ltd

Tel: 65.298.0888

Fax: 65.298.1111

Oregon

Silicon Valley

Sales Ofﬁce

Tel: 408.433.8000

Fax: 408.954.3353

Design Center

Beaverton

Tel: 503.645.0589

Fax: 503.645.6612

♦ Tel: 49.89.4.58.33.0

Fax: 49.89.4.58.33.108

Spain

LSI Logic S.A.

Madrid

Stuttgart

Tel: 49.711.13.96.90

Fax: 49.711.86.61.428

Texas

Austin

Tel: 512.388.7294

Fax: 512.388.4171

♦ Tel: 34.1.3672200

♦ Tel: 408.433. 8000

Fax: 34.1.3673151

Fax: 408.433.2820

Hong Kong

Sweden

Colorado

Boulder

AVT Industrial Ltd

Hong Kong

LSI Logic AB

Stockholm

Dallas

Tel: 303.447.3800

Fax: 303.541.0641

♦ Tel: 214.788.2966

Tel: 852.2428.0008

Fax: 852.2401.2105

♦ Tel: 46.8.444.15.00

Fax: 214.233.9234

Fax: 46.8.750.66.47

Florida

Houston

India

Switzerland

Boca Raton

Tel: 407.989.3236

Fax: 407.989.3237

Tel: 713.379.7800

Fax: 713.379.7818

LogiCAD India Private Ltd

Bangalore

Tel: 91.80.526.2500

Fax: 91.80.338.6591

LSI Logic Sulzer AG

Brugg/Biel

Tel: 41.32.536363

Fax: 41.32.536367

Washington

Georgia

Bellevue

Atlanta

Tel: 770.395.3808

Fax: 770.395.3811

Tel: 206.822.4384

Fax: 206.827.2884

Israel

LSI Logic

Ramat Hasharon

♦ Tel: 972.3.5.403741

Fax: 972.3.5.403747

Taiwan

LSI Logic Asia-Paciﬁc

Taipei

Canada

Ontario

♦ Tel: 886.2.718.7828

Illinois

Fax: 886.2.718.8869

Schaumburg

Ottawa

♦ Tel: 847.995.1600

♦ Tel: 613.592.1263

Netanya

Cheng Fong Technology

Corporation

Tel: 886.2.910.1180

Fax: 886.2.910.1175

Fax: 847.995.1622

Fax: 613.592.3253

♦ Tel: 972.9.657190

Fax: 972.9.657194

Kentucky

Toronto

Bowling Green

Tel: 502.793.0010

Fax: 502.793.0040

♦ Tel: 416.620.7400

Italy

LSI Logic S.P.A.

Milano

Fax: 416.620.5005

Lumax International

Corporation, Ltd

Quebec

Montreal

♦ Tel: 39.39.687371

Tel: 886.2.788.3656

Fax: 886.2.788.3568

Maryland

Fax: 39.39.6057867

Bethesda

♦ Tel: 514.694.2417

♦ Tel: 301.897.5800

Fax: 514.694.2699

Japan

Macro-Vision

Fax: 301.897.8389

LSI Logic K.K.

Tokyo

Technology Inc.

Tel: 886.2.698.3350

Fax: 886.2.698.3348

INTERNATIONAL

Massachusetts

Waltham

♦ Tel: 81.3.5463.7821

Australia

Fax: 81.3.5463.7820

♦ Tel: 617.890.0180

Reptechnic Pty Ltd

New South Wales

Tel: 612.9953.9844

Fax: 612.9953.9683

United Kingdom

LSI Logic Europe plc

Bracknell

Fax: 617.890.6158

Osaka

♦ Tel: 81.6.947.5281

Minnesota

Minneapolis

Fax: 81.6.947.5287

♦ Tel: 44.1344.426544

Fax: 44.1344.481039

♦ Tel: 612.921.8300

Fax: 612.921.8399

♦ Sales Ofﬁces with Design

Resource Centers

Printed in USA

Printed on

Recycled Paper

ISO 9000 Certified


型号：	ETHERNET-10
厂家：	ETC
描述：	Ethernet-10 Core technical manual 2/97 以太网- 10的核心技术手册2/97\n 以太网
文件：	总100页 (文件大小：452K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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