ETC5054FN [ETC]
u-Law CODEC ; U- Law编码解码器\n
| 型号： | ETC5054FN |
| 厂家： | 
ETC |
| 描述： | u-Law CODEC
|
| 文件： | 总18页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ETC5054
ETC5057
SERIAL INTERFACE CODEC/FILTER
COMPLETE CODEC AND FILTERING SYS-
TEM (DEVICE) INCLUDING:
– Transmithigh-pass and low-pass filtering.
– Receivelow-pass filter with sin x/x correction.
– ActiveRC noise filters
– µ-lawor A-lawcompatibleCOderandDECoder.
– Internalprecision voltage reference.
– Serial I/O interface.
– Internalauto-zero circuitry.
DIP16 (Plastic)
A-LAW 16 PINS (ETC5057FN, 20 PINS)
µ-LAW WITHOUT SIGNALING, 16 PINS
(ETC5054FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
CCITT SPECIFICATIONS
ORDERING NUMBERS:
ETC5057N
ETC5054N
5V OPERATION
±
LOW OPERATING POWER - TYPICALLY 60
mW
POWER-DOWN STANDBY MODE - TYPI-
CALLY 3 mW
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
TERFACES
SO16 (Wide)
MAXIMIZES LINE INTERFACE CARD CIR-
CUIT DENSITY
0 to 70°C OPERATION
ORDERING NUMBERS:
ETC5057D
ETC5054D
DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and µ–law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
PLCC20
ORDERING NUMBERS:
ETC5057FN
ETC5054FN
companded A-law or –law PCM format. The de-
µ
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or µ–law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
March 2000
1/18
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ETC5054 - ETC5057
PIN CONNECTIONS (Topview)
DIP and SO
PLCC
BLOCK DIAGRAM
2/18
ETC5054 - ETC5057
PIN DESCRIPTION
Pin
N
N
°
°
Type DIP PLCC
Name
Function
Description
*
and
SO (**)
VBB
S
1
1
Negative
Power Supply
VBB = – 5V ± 5 %.
GNDA
VFRO
GND
O
2
3
2
3
Analog Ground
All signals are referenced to this pin.
Analog Output of the Receive Filter
Receive Filter
Output
VCC
FSR
S
I
4
5
5
6
Positive Power
Supply
VCC = + 5 V ± 5 %.
Receive Frame
Sync Pulse
Enables BCLKR to shift PCM data into DR. FSR is an
8kHz pulse train. See figures 1, 2 and 3 for timing
details.
DR
I
I
6
7
7
8
Receive Data
Input
PCM data is shifted into DR following the FSR leading
edge.
BCLKR/CLKSEL
Shift-in Clock
Shifts data into DR after the FSR leading edge. May
vary from 64 kHz to 2.048 MHz. Alternatively, may be
a logic input which selects either 1.536 MHz/1.544
MHz or 2.048 MHz for master clock in synchronous
mode and BCLKX is used for both transmit and receive
directions (see table 1). This input has an internal pull-
up.
MCLKR/PDN
I
8
9
Receive Master Clock Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKX, but should be
synchronous with MCLKX for best performance. When
MCLKR is connected continuously low, MCLKX is
selected for all internal timing. When MCLKR is
connected continuously high, the device is powered
down.
MCLKX
BCLKX
DX
I
9
12 Transmit Master Clock Must be 1.536 MHz, 1.544 MHz or 2.048 MHz. May be
asynchronous with MCLKR.
10
11
12
14
15
16
Shift-out Clock
Shifts out the PCM data on DX. May vary from 64 kHz
to 2.048 MHz, but must be synchronous with MCLKX.
I
O
I
Transmit
Data Output
The TRI-STATE PCM data output which is enabled
by FSX.
FSX
Transmit Frame
Sync Pulse
Enables BCLKX to shift out the PCM data on DX. FSX is
an 8 kHz pulse train. See figures 1, 2 and 3 for timing
details.
TSX
GSX
O
O
I
13
14
15
16
17
18
19
Transmit Time Slot
Gain Set
Open drain output which pulses low during the encoder
time slot. Recommended to be grounded if not used.
Analog output of the transmit input amplifier. Used to
set gain externally.
VFXI–
VFXI+
Inverting Amplifier
Input
Inverting Input of the Transmit Input Amplifier.
I
20 Non-inverting Amplifier Non-inverting Input of theTransmit Input Amplifier.
Input
(*) I: Input, O: Output, S: Power Supply
(**) Pins 4,10,11 and 13 are not connected
TRI-STATE is a trademark of National Semiconductor Corp.
3/18
ETC5054 - ETC5057
TRI-STATE DX output is returned to a high im-
pedance state. With and FSR pulse, PCM data is
latched via the DR input on the negative edge of
BCLKX (or BCLKR if running). FSX and FSR must
FUNCTIONAL DESCRIPTION
POWER-UP
When power is first applied, power-on reset cir-
cuitry initializes the device and places it into
the power-down mode. All non-essential circuits
are deactivated and the DX and VFRO outputsare
put in high impedance states. To power-up the
device, a logical low level or clock must be ap-
plied to the MCLKR/PDN pin and FSX and/or FSR
pulses must be present. Thus, 2 power-down
control modes are available. The first is to pull the
MCLKR/PDN pin high ; the alternative is to hold
both FSX and FSR inputs continuously low. The
device will power-down approximately 2 ms after
the last FSX or FSR pulse. Power-up will occur on
the first FSX or FSR pulse. The TRI-STATE PCM
data output, DX, will remain in the high impedance
state until the secondFSX pulse.
be synchronouswith MCLKX/R
.
ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit
and receive clocks may be applied, MCLKX and
MCLKR must be 2.048 MHz for the ETC5057, or
1.536 MHz, 1.544 MHz for the ETC5054, and
need not be synchronous. For best transmission
performance, however, MCLKR should be syn-
chronous with MCLKX, which is easily achieved
by applying only static logic levels to the
MCLKR/PDN pin. This will automatically connect
MCLKX to all internal MCLKR functions (see pin
description). For 1.544 MHz operation, the device
automatically compensates for the 193rd clock
pulse each frame. FSX starts each encoding cycle
and must be synchronous with MCLKX and
BCLKX. FSR starts each decoding cycle and must
be synchronous with BCLKR. BCLKR must be a
clock, the logic levels shown in table 1 are not
valid in asynchronous mode. BCLKX and BCLKR
may operate from 64 kHz to 2.048 MHz.
SYNCHRONOUS OPERATION
For synchronous operation, the same master
clock and bit clock should be used for both the
transmit and receive directions. In this mode, a
clock must be applied to MCLKX and the
MCLKR/PDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up
the device and a high level powers down the de-
vice. In either case, MCLKX will be selected as
the master clock for both the transmit and receive
circuits. A bit clock must also be applied to BCLKX
and the BCLKR/CKSEL can be used to select the
proper internal divider for a master clock of 1.536
MHz, 1.544 MHz or 2.048 MHz. For 1.544 MHz
operation, the device automatically compensates
for the 193rd clock pulse each frame. With a fixed
level on the BCLKR/CLKSEL pin, BCLKX will be
selected as the bit clock for both the transmit and
receive directions. Table 1 indicates the frequen-
cies of operation which can be selected, depend-
ing on the state of BCLKR/CLKSEL. In this syn-
chronous mode, the bit clock, BCLKX, may be
from 64 kHz to 2.048 MHz, but must be synchro-
nous with MCLKX.
SHORT FRAME SYNC OPERATION
The device can utilize either a short frame sync
pulse or a long frame sync pulse. Upon power in-
itialization, the device assumes a short frame
mode. In this mode, both frame sync pulses, FSX
and FSR, must be one bit clock period long, with
timing relationships specified in figure 2. With FSX
high during a falling edge of BCLKX the next ris-
ing edge of BCLKX enables the DX TRI-STATE
output buffer, which will output the sign bit. The
following seven rising edges clock out the remain-
ing seven bits, and the next falling edge disables
the DX output.With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the
next falling edge of BCLKR latches in the sign bit.
The following seven falling edges latch in the
seven remaining bits. Both devices may utilize the
short frame sync pulse in synchronous or asyn-
chronous operatingmode.
Each FSX pulse begins the encoding cycle and
the PCM data from the previous encode cycle is
shifted out of the enabled DX output on the posi-
tive edge of BCLKX. After 8 bit clock periods, the
LONG FRAME SYNC OPERATION
Table 1: SelectionofMasterClockFrequencies.
To use the long frame mode, both the frame sync
pulses, FSX and FSR, must be three or more bit
clock periods long, with timing relationships speci-
fied in figure 3. Based on the transmit frame sync,
FSX, the device will sense whether short or long
frame sync pulses are being used. For 64 kHz op-
eration, the frame sync pulse must be kept low for
a minimum of 160 ns (see fig. 1). The DX TRI-
STATE output buffer is enabled with the rising
edge of FSX or the rising edge of BCLKX, which-
ever comes later, and the first bit clocked out is
the sign bit. The following seven BCLKX rising
Master Clock Frequency
Selected
BCLKR/CLKSEL
ETC5057
ETC5054
Clocked
0
2.048 MHz
1.536 MHz or
1.544 MHz
2.048 MHz
1.536 MHz or
1.544 MHz
1 (or open circuit)
2.048 MHz
1.536 MHz or
1.544 MHz
4/18
ETC5054 - ETC5057
edges clock out the remaining seven bits. The DX
output is disabled by the falling BCLKX edge fol-
lowing the eighth rising edge, or by FSX going
low, which-ever comes later. A rising edge on the
receive frame sync pulse, FSR, will cause the
PCM data at DR to be latched in on the next eight
falling edges of BCLKR (BCLKX in synchronous
mode). Both devices may utilize the long frame
sync pulse in synchronous or asynchronous
mode.
proximation encoding cycle begins. The 8-bit
code is then loaded into a buffer and shifted out
through DX at the next FSX pulse. The total en-
coding delay will be approximately 165 µs (due to
µ
the transmit filter) plus 125 s (due to encoding
delay), which totals 290µs. Any offset vol-tage
due to the filters or comparator is cancelled by
sign bit integration.
RECEIVE SECTION
The receive section consists of an expanding
DAC which drives a fifth order switched-capacitor
low pass filter clocked at 256 kHz. The decoder is
A-law (ETC5057) or µ–law (ETC5054) and the
5th order low pass filter corrects for the sin x/x at-
tenuation due to the 8 kHz sample and hold.
The filter is then followed by a 2nd order RC ac-
tive post-filter and power amplifier capable of driv-
ing a 600Ω load to a level of 7.2 dBm. The re-
ceive section is unity-gain. Upon the occurence of
FSR, the data at the DR input is clocked in on the
falling edge of the next eight BCLKR (BCLKX) pe-
riods. At the end of the decoder time slot, the de-
coding cycle begins, and 10µs later the decoder
DAC output is updated. The total decoder delay
TRANSMIT SECTION
The transmit section input is an operational ampli-
fier with provision for gain adjustment using two
external resistors, see figure 6. The low noise and
wide bandwidth allow gains in excess of 20 dB
across the audio passband to be realized. The op
amp drives a unitygain filter consisting of RD ac-
tive pre-filter, followed by an eighth order
switched-capacitor bandpass filter clocked at 256
kHz. The output of this filter directly drives the en-
coder sample-and-holdcircuit. The A/D is of com-
panding type according to A-law (ETC5057) or µ–
law (ETC5054) coding conventions. A precision
voltage reference is trimmed in manufacturing to
provide an input overload (tMAX) of nominally2.5V
peak (see table of transmission characteristics).
The FSX frame sync pulse controls the sampling
of the filter output, and then the successive-ap-
µ µ
10 s (decoder update) plus 110 s (filter
is
delay) plus 62.5µs (1/2 frame), which gives ap-
proximately 180µs. A mute circuitry is a active
during 10ms when power up.
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
Unit
V
VCC to GNDA
VBB to GNDA
7
– 7
VBB
V
VIN, VOUT
Voltage at any Analog Input or Output
Voltage at Any Digital Input or Output
Operating Temperature Range
VCC + 0.3 to VBB – 0.3
VCC + 0.3 to GNDA – 0.3
– 25 to + 125
– 65 to + 150
300
V
V
Toper
Tstg
C
C
C
°
°
°
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
ELECTRICAL OPERATING CHARACTERISTICS VCC = 5.0 V ± 5 %, VBB = – 5.0 V ± 5%GNDA = 0 V,
TA = 0 °C to 70 °C; Typical Characteristics Specified at VCC = 5.0 V, VBB = – 5.0 V, TA = 25 °C ; all signals
are referenced to GNDA.
Symbol
VIL
VIH
Parameter
Min.
Typ.
Max.
0.6
Unit
V
V
Input Low Voltage
Input High Voltage
2.2
VOL
Output Low Voltage
IL = 3.2mA
D X
TSX
0.4
0.4
V
V
IL = 3.2mA, Open Drain
VOH
Output High Voltage
IH = 3.2mA
D X
2.4
–10
–10
V
IIL
IIH
IOZ
Input Low Current (GNDA ≤ VIN ≤ VIL, all digital inputs)
Input High Current (VIH ≤ VIN ≤ VCC) except BCLKR/BCLKSEL
Output Current in HIGH Impedance State (TRI-STATE)
10
10
µA
µA
(GNDA ≤ VO ≤ VCC
)
DX
–10
10
µA
5/18
ETC5054 - ETC5057
ANALOG INTERFACE WITH TRANSMIT INPUT AMPLIFIER (all devices)
Symbol
Parameter
Min.
Typ.
Max.
Unit
IIXA
Input Leakage Current
(–2.5V ≤ V ≤ +2.5V)
VFXI+ or VFXI-
VFXI+ or VFXI-
– 200
200
nA
RIXA
Input Resistance
10
10
MΩ
(–2.5V
V
+2.5V)
≤
≤
ROXA
RLXA
CLXA
VOXA
AVXA
FUXA
Output Resistance (closed loop, unity gain)
Load Resistance
1
3
Ω
GSX
GSX
GSX
k
Ω
Load Capacitance
50
pF
V
Output Dynamic Range (RL 10K )
Voltage Gain (VFXI+ to GSX)
2.8
±
≥
Ω
5000
1
V/V
MHz
mV
V
Unity Gain Bandwidth
2
V
OSXA Offset Voltage
– 20
– 2.5
60
20
V
CMXA Common-mode Voltage
2.5
CMRRXA Common-mode Rejection Ratio
PSRRXA Power Supply Rejection Ratio
dB
dB
60
ANALOG INTERFACE WITH RECEIVE FILTER (all devices)
Symbol
RORF
RLRF
Parameter
Min.
600
Typ.
Max.
Unit
Ω
Output Resistance
VFRO
1
3
Load Resistance (VFRO = ±2.5V)
Ω
CLRF
Load Capacitance
500
200
pF
mV
VOSRO Output DC Offset Voltage
– 200
POWER DISSIPATION (all devices)
Symbol
ICC
IBB
ICC
IBB
Parameter
Min.
Typ.
0.5
Max.
1.5
Unit
mA
mA
mA
mA
0
Power-down Current
Power-down Current
Active Current
0
0.05
6.0
0.3
1
9.0
1
Active Current
6.0
9.0
6/18
ETC5054 - ETC5057
TIMING SPECIFICATIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
1/tPM
Frequency of master clocks
Depends on the device used and the BCLKR/CLKSEL Pin
MCLKX and MCLKR
1.536
1.544
2.048
MHz
MHz
MHz
tWMH
tWML
tRM
Width of Master Clock High
Width of Master Clock Low
MCLKX and MCLKR
160
160
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLKX and MCLKR
MCLKX and MCLKR
MCLKX and MCLKR
Rise Time of Master Clock
50
50
tFM
Fall Time of Master Clock
tPB
Period of Bit Clock
485
160
160
488
15.725
tWBH
tWBL
tRB
Width of Bit Clock High (VIH = 2.2V)
Width of Bit Clock Low (VIL = 0.6V)
Rise Time of Bit Clock (tPB = 488ns)
Fall Time of Bit Clock (tPB = 488ns)
50
50
tFB
tSBFM
Set-up time from BCLKX high to MCLKX falling edge.
(first bit clock after the leading edge of FSX)
100
0
tHBF
Holding Time from Bit Clock Low to the Frame Sync
(long frame only)
ns
tSFB
Set-up Time from Frame Sync to Bit Clock (long frame only)
80
ns
ns
tHBFI
Hold Time from 3rd Period of Bit Clock
Low to Frame Sync (long frame only)
FSX or FSR
100
tDZF
Delay time to valid data from FSX or BCLKX, whichever comes later
and delay time from FSX to data output disabled.
(CL = 0pF to 150pF)
20
0
165
ns
ns
tDBD
Delay time from BCLKX high to data valid.
(load = 150pF plus 2 LSTTL loads)
180
165
tDZC
tSDB
tHBD
tHOLD
Delay time from BCLKX low to data output disabled.
Set-up time from DR valid to BCLKR/X low.
Hold time from BCLKR/X low to DR invalid.
50
50
50
0
ns
ns
ns
ns
Holding Time from Bit Clock High to Frame Sync
(short frame only)
tSF
tHF
Set-up Time from FSX/R to BCLKX/R Low
(short frame sync pulse) - Note 1
80
ns
ns
Hold Time from BCLKX/R Low to FSX/R Low
(short frame sync pulse) - Note 1
100
tXDP
tWFL
Delay Time to TSXlow (load = 150pF plus 2 LSTTL loads)
140
ns
ns
Minimum Width of the Frame Sync Pulse (low level)
64kbit/s operating mode)
160
Note 1: For short frame sync timing FSX and FSR must go high while their respective bit clocks are high.
Figure 1: 64kbits/sTIMING DIAGRAM (see next page for complete timing).
FSx
FSR
7/18
ETC5054 - ETC5057
Figure 2: Short Frame Sync Timing
8/18
ETC5054 - ETC5057
Figure 3: Long Frame Sync Timing
9/18
ETC5054 - ETC5057
TRANSMISSION CHARACTERISTICS
TA = 0 to 70°C, VCC = +5V ±5%, VBB = –5V ±5%, GNDA = 0V, f = 1.0KHz, VIN = 0dBm0 transmit input
amplifier connected for unity-gain non-inverting (unless otherwise specified).
AMPLITUDE RESPONSE
Symbol
Parameter
Min.
Typ.
Max.
Unit
Absolute levels - nominal 0 dBm0 level is 4 dBm (600 Ω)
0 dBm0
1.2276
Vrms
tMAX
Max Overload Level
3.14 dBm0 (A LAW)
3.17 dBm0 (U LAW)
2.492
2.501
VPK
VPK
GXA
GXR
Transmit Gain, Absolute (TA = 25 °C, VCC = 5 V, VBB = – 5 V)
Input at GSX = 0 dBm0 at 1020 Hz
– 0.15
0.15
dB
Transmit Gain, Relative to GXA
f = 16 Hz
– 40
– 30
– 26
– 0.2
– 0.1
0.15
0.05
0
f = 50 Hz
f = 60 Hz
f = 180 Hz
– 2.8
– 1.8
– 0.15
– 0.35
– 0.7
f = 200 Hz
dB
f = 300 Hz - 3000 Hz
f = 3300 Hz
f = 3400 Hz
f = 4000 Hz
– 14
– 32
f = 4600 Hz and up, Measure Response from 0Hz to 4000 Hz
GXAT
GXAV
GXRL
Absolute Transmit Gain Variation with Temperature
TA = 0 to +70 C
– 0.1
0.1
dB
dB
°
Absolute Transmit Gain Variation with Supply Voltage
(VCC = 5 V ± 5 %, VBB = – 5 V ± 5 %)
– 0.05
0.05
Transmit Gain Variations with Level
Sinusoidal Test Method Reference Level = – 10 dBm0
VFXI+ = – 40 dBm0 to + 3 dBm0
VFXI+ = – 50 dBm0 to – 40 dBm0
VFXI+ = – 55 dBm0 to – 50 dBm0
– 0.2
– 0.4
– 1.2
0.2
0.4
1.2
dB
dB
dB
GRA
GRR
Receive Gain, Absolute (TA = 25°C, VCC = 5V, VBB = –5V)
Input = Digital Code Sequence for 0dBm0 Signal at 1020Hz
– 0.15
0.15
dB
Receive Gain, Relative to GRA
f = 0Hz to 3000Hz
f = 3300Hz
f = 3400Hz
f = 4000Hz
– 0.35
– 0.35
– 0.7
0.20
0.05
0
dB
dB
dB
dB
– 14
GRAT
GRAV
GRRL
Absolute Transmit Gain Variation with Temperature
A
T = 0 to +70 C
– 0.1
0.1
dB
dB
°
Absolute Receive Gain Variation with Supply Voltage
(VCC = 5 V ± 5 %, VBB = – 5 V ± 5 %)
– 0.05
0.05
Receive Gain Variations with Level
Sinusoidal Test Method; Reference input PCM code
corresponds to an ideally encoded – 10 dBm0 signal
PCM level = – 40 dBm0 to + 3 dBm0
– 0.2
– 0.4
– 1.2
0.2
0.4
1.2
dB
dB
dB
PCM level = – 50 dBm0 to – 40 dBm0
PCM level = – 55 dBm0 to – 50 dBm0
VRO
Receive Output Drive Level (R = 600 )
– 2.5
2.5
V
Ω
L
10/18
ETC5054 - ETC5057
TRANSMISSION (continued)
ENVELOPEDELAY DISTORTION WITH FREQUENCY
Symbol
DXA
Parameter
Min.
Typ.
Max.
Unit
Transmit Delay, Absolute (f = 1600Hz)
290
315
s
µ
DXR
Transmit Delay, Relative to DXA
f = 500Hz - 600Hz
195
120
50
20
55
80
130
220
145
75
40
75
105
155
f = 600Hz - 800Hz
f = 800Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz
µs
DRA
DRR
Receive Delay, Absolute (f = 1600Hz)
180
200
s
s
µ
µ
Receive Delay, Relative to DRA
f = 500Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz
– 40
– 30
– 25
– 20
70
100
145
90
125
175
NOISE
Symbol
NXP
Parameter
Min.
Typ.
Max.
Unit
Transmit Noise, P Message Weighted (A LAW, VFXI + = 0 V)
1)
– 74
– 69 dBm0p
NRP
Receive Noise, P Message Weighted
(A LAW, PCM code equals positive zero)
Transmit Noise, C Message Weighted µ LAW (VFXI + = 0 V)
– 82
12
– 79 dBm0p
NXC
NRC
15
11
dBmC0
dBrnC0
Receive Noise, C Message Weighted
(µ LAW, PCM Code Equals Alternating Positive and Negative Zero)
8
NRS
Noise, Single Frequency
f = 0 kHz to 100 kHz, Loop around Measurement,
VFXI + = 0 Vrms
– 53
dBm0
dBp
PPSRX Positive Power Supply Rejection, Transmit (note 2)
VCC = 5.0 VDC + 100 mVrms, f = 0 kHz-50 kHz
40
40
NPSRX Negative Power Supply Rejection, Transmit (note 2)
VBB = – 5.0 VDC + 100 mVrms,
f = 0 kHz-50 kHz
dBp
PPSRR Positive Power Supply Rejection, Receive
(PCM code equals positive zero, VCC = 5.0 VDC + 100mVrms)
f = 0Hz to 4000Hz
40
40
36
dBp
dB
dB
f = 4KHz to 25KHz
f = 25KHz to 50KHz
NPSRR Negative Power Supply Rejection, Receive
(PCM code equals positive zero, VBB = 5.0 VDC + 100mVrms)
f = 0Hz to 4000Hz
40
40
36
dBp
dB
dB
f = 4KHz to 25KHz
f = 25KHz to 50KHz
11/18
ETC5054 - ETC5057
TRANSMISSION CHARACTERISTICS (continued)
NOISE (continued)
Symbol
Parameter
Min.
Typ.
Max.
Unit
SOS
Spurius out-of-band Signals at theChannel Output
Loop around measurement, 0dBm0, 300Hz - 3400Hz input applied
to DR, measure individual image signals at DX
4600Hz - 7600Hz
– 32
– 40
– 32
dB
dB
dB
7600Hz - 8400Hz
8400Hz - 100,000Hz
DISTORTION
Symbol
Parameter
Min.
Typ.
Max.
Unit
STDX
or
STDR
Signal to Total Distortion (sinusoidal test method)
Transmit or Receive Half-channel
Level = 3.0dBm0
33
36
29
30
14
15
Level = 0dBm0 to –30dBm0
Level = –40dBm0
XMT
R CV
XMT
RCV
dBp
Level = –55dBm0
SFDX
SFDR
IMD
Single Frequency Distortion, Transmit (T = 25 C)
–46
–46
dB
dB
°
A
Single Frequency Distortion, Receive (T = 25 C)
°
A
Intermodulation Distortion
Loop Around Measurement, VFXI+ = –4dBm0 to –21dBm0, two
–41
dB
Frequencies in the Range 300Hz - 3400Hz
CROSSTALK
Symbol
Parameter
Min.
Typ.
– 90
– 90
Max.
– 75
– 70
Unit
dB
CTX-R
Transmit to Receive Crosstalk, 0 dBm0 Transmit Level
f = 300Hz to 3400Hz, DR = Steady PCM Mode
CTR-X
Receive to Transmit Crosstalk, 0 dBm0 Receive Level
f = 300Hz to 3400Hz, (note 2)
dB
Notes:
1) Measured by extrapolation from distortion test results.
2) PPSRX, NPSRX, CTR-X is measured with a –50dBm0 activating signal applied at VFXI+.
ENCODING FORMAT AT DX OUTPUT
A-Law (including even bit inversion)
Law
µ
V
V
V
IN (at GSX) = +Full-scale
IN (at GSX) = 0V
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IN (at GSX) = – Full-scale
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
12/18
ETC5054 - ETC5057
N2 − 1
APPLICATION INFORMATION
POWER SUPPLIES
Z1 . Z 2
√
2
=
R3
N
While the pins at the ETC505X family are well
protected against electrical misuse, it is recom-
mended that the standard CMOS practice be fol-
lowed, ensuring that ground is connected to the
device before any-other connections are made. In
applications where the printed circuit board may
be plugged into a ”hot” socket with power and
clocks already present, an extra long ground pin
in the connector should be used.
N2 −
1
R3 = Z1
2
−
+
1
N
2NS
RECEIVE GAIN ADJUSTMENT
For applications where
CODEC/filter receive output must drive a 600Ω
load, but a peak swing lower then 2.5V is re-
a
ETC505X family
±
All ground connections to each device should
meet at a common point as close as possible to
the GNDA pin. This minimizes the interaction of
ground return currents flowing through a common
quired, the receive gain can be easily adjusted by
inserting a matched T-pad or π –pad at the out-
put. Table II lists the required resistor values for
600Ω terminations. As these are generally non-
standard values, the equations can be used to
compute the attenuationof the closest pratical set
of resistors. It may be necessary to use unequal
values for the R1 or R4 arms of the attenuatorsto
achieve a precise attenuation. Generally it is tol-
erable to allow a small deviation of the input im-
pedance from nominal while still maintaining a
good return loss. For example a 30dB return loss
against 600Ω is obtained if the output impedance
µ
bus impedance. 0.1 F supply decoupling capaci-
tors should be connected from this common
ground point to VCC and VBB as close to the de-
vice as possible.
For best performance, the ground point of each
CODEC/FILTER on a card should be connected
to a common card ground in star formation, rather
than via a ground bus. This common ground point
should be decoupled to VCC and VBB with 10µF
capacitors.
Ω
Ω
of the attenuator is in the range 282 to 319
(assuming a perfect transformer).
Figure 4: T-PAD Attenuator
Table 2 : AttenuatorTables For
Z1 = Z2 = 300 Ω (all values in Ω).
dB
R1
R2
R3
R4
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
1.7
3.5
26k
13k
8.7k
6.5k
5.2k
4.4k
3.7k
3.3k
2.9k
2.6k
1.3k
850
650
494
402
380
284
244
211
184
161
142
125
110
98
3.5
6.9
52k
26k
N2 + 1
N
5.2
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
17.4k
13k
R1 = Z1
−2 √Z1 . Z 2
N2
1
N2
6.9
8.5
−
−
1
10.5k
8.7k
7.5k
6.5k
5.8k
5.2k
2.6k
1.8k
1.3k
1.1k
900
785
698
630
527
535
500
473
450
430
413
386
366
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
N
N2 − 1
=
√
2
R2 2 Z1.Z
POWERIN
√
Where: N =
3
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17k
1.5k
POWEROUT
4
5
84
Z1
Z2
√
and: S =
6
100
115
129
143
156
168
180
190
200
210
218
233
246
7
8
√
.
Also : Z = ZSC ZOC
9
10
11
12
13
14
15
16
18
20
Where ZSC = impedancewith shortcircuit termi-
nation and ZOC = impedancewith opencircuit ter-
mination.
Figure 5: Π-PAD Attenuator
77
61
13/18
ETC5054 - ETC5057
Figure 6: Typical SynchronousApplication.
14/18
ETC5054 - ETC5057
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
A1
B
C
D
E
e
2.35
0.1
2.65 0.093
0.3 0.004
0.104
0.012
0.020
0.013
0.413
0.299
0.33
0.23
10.1
7.4
0.51 0.013
0.32 0.009
10.5 0.398
7.6
0.291
1.27
0.050
H
h
10
0.25
0.4
10.65 0.394
0.75 0.010
1.27 0.016
0.419
0.030
0.050
L
SO16 Wide
K
0° (min.)8° (max.)
L
h x 45
A
B
e
K
A1
C
H
D
9
8
16
E
1
15/18
ETC5054 - ETC5057
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
a1
B
b
0.51
0.77
0.020
1.65 0.030
0.065
0.787
0.5
0.020
0.010
b1
D
E
e
0.25
20
8.5
0.335
0.100
0.700
2.54
17.78
e3
F
7.1
5.1
0.280
0.201
I
L
3.3
0.130
DIP16
Z
1.27
0.050
16/18
ETC5054 - ETC5057
mm
inch
OUTLINE AND
MECHANICAL DATA
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A
B
9.78
8.89
4.2
10.03 0.385
9.04 0.350
4.57 0.165
0.395
0.356
0.180
D
d1
d2
E
2.54
0.56
0.100
0.022
7.37
8.38 0.290
0.330
0.004
e
1.27
0.38
0.050
0.015
F
G
0.101
M
M1
1.27
1.14
0.050
0.045
PLCC20
B
M
M1
3
2
1
20 19
18
4
5
6
7
8
M
M1
F
e
17
16
15
14
E
9
10 11 12
13
d2
A
d1
D
G (Seating Plane Coplanarity)
PLCC20ME
17/18
ETC5054 - ETC5057
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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18/18
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