ESDA6V1-4F [ETC]

QUAD TRANSIL ARRAY FOR ESD PROTECTION ; QUAD TRANSIL阵列，用于ESD保护\n


型号：	ESDA6V1-4F
厂家：	ETC
描述：	QUAD TRANSIL ARRAY FOR ESD PROTECTION QUAD TRANSIL阵列，用于ESD保护\n
文件：	总6页 (文件大小：46K)
中文：	中文翻译
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ESDA6V1-4F1

QUAD TRANSIL™ ARRAY

FOR ESD PROTECTION

A.S.D.™

APPLICATIONS

Where transient overvoltage protection in ESD

sensitive equipment is required, such as :

3 2 1

■

Computers

Printers

Communication systems

GSM handsets and accessories

Other telephone sets

Set top boxes

GND

DESCRIPTION

Flip Chip

The ESDA6V1-4F1 is a 4-bit wide monolithic

suppressor designed to protect against ESD

components which are connected to data and

transmission lines.

(Bump side)

FUNCTIONAL DIAGRAM

It clamps the voltage just above the logic level

supply for positive transients, and to a diode

forward voltage drop below ground for negative

transients.

FEATURES

■

4 Unirectional transil functions

Breakdown voltage: V_BR= 6.1Vmin

Low leakage current < 10 µA

Very low PCB space consuming

BENEFITS

■

> ± 15kV ESD Protection

High integration

Suitable for high density boards

ESD RESPONSE TO IEC61000-4-2

(air discharge 16kV, positive surge)

COMPLIES WITH THE FOLLOWING STAN-

DARDS:

- IEC61000-4-2: Level 4

15 kV (air discharge)

8 kV

(contact discharge)

- MIL STD 883E-Method 3015-6: class3

(Human body model)

July 2002 - Ed: 2A

1/6

ESDA6V1-4F1

ABSOLUTE MAXIMUM RATINGS (T_amb= 25°C)

Symbol

Test conditions

Value

Unit

V_PP

ESD discharge - MIL STD 883E - Method 3015-6

IEC61000-4-2 air discharge

±25

±15

± 8

IEC61000-4-2 contact discharge

P_PP

T_j

Peak pulse power (8/20µs)

150

°C

Junction temperature

T_stg

T_L

Storage temperature range

-55 to +150

260

Lead solder temperature (10 seconds duration)

Operating temperature range

T_op

-40 to +85

ELECTRICAL CHARACTERISTICS (T_amb= 25°C)

Symbol

V_RM

V_BR

V_CL

I_RM

I_PP

Parameter

Stand-off voltage

Breakdown voltage

Clamping voltage

VCLVBR VRM

Leakage current

IRM

Peak pulse current

αT

Voltage temperature coefficient

Capacitance per line

Dynamic impedance

Forward voltage drop

Slope = 1/Rd

IPP

V_F

V_BR

I_R

I_RM@ V_RM

typ.

min.

max.

max

Type

note 1 note 2 0V bias

µA

mΩ

10^-4/°C

ESDA6V1- 4F1

6.1

7.2

350

250

Note 1: Square pulse I

= 15A, tp = 2.5µs

= αT * (T

Note 2: ∆V

- 25) * V (25°C)

amb BR

2/6

ESDA6V1-4F1

Fig. 1: Peak power dissipation versus initial junc-

tion temperature

Fig. 2: Peak pulse power versus exponential pulse

duration (Tj initial = 25°C)

Ppp[Tj initial]/Ppp[Tj initial=25°C]

Ppp(W)

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

1000

100

Tj initial(°C)

tp(µs)

0.1

0.0

100

125

150

175

100

Fig. 3: Clamping voltage versus peak pulse current

(Tj initial = 25°C). Rectangular waveform t_P= 2.5µs.

Fig. 4: Capacitance versus reverse applied voltage

(typical values).

C(pF)

Ipp(A)

250

50.0

F=1MHz

Vosc=30mV

tp = 2.5µs

225

200

175

150

125

10.0

1.0

100

Vcl(V)

VR(V)

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Fig. 5: Relative variation of leakage current versus

junction temperature (typical values).

IR[Tj] / IR[Tj=25°C]

1.8

1.6

1.4

1.2

Tj(°C)

1.0

100

125

150

3/6

ESDA6V1-4F1

CALCULATION OF THE CLAMPING VOLTAGE

USE OF THE DYNAMIC RESISTANCE

The ESDA6V1-4F1 has been designed to clamp fast spikes like ESD. Generally the PCB designers need

to calculate easily the clamping voltage V . This is why we give the dynamic resistance in addition to the

classical parameters.

The voltage across the protection cell can be calculated with the following formula:

V_CL= V_BR+ R_dI_PP

Where I

is the peak current through the ESDA cell.

DYNAMIC RESISTANCE MEASUREMENT

The short duration of the ESD has led us to prefer a more adapted test wave, as below defined, to the

classical 8/20 µs and 10/1000 µs surges

IPP

2µs

2.5 µs

2.5 µs duration measurement wave

As the value of the dynamic resistance remains stable for a surge duration lower than 20µs, the 2.5µs

rectangular surge is well adapted. In addition both rise and fall times are optimised to avoid any parasitic

phenomenon during the measurement of Rd.

ESD PROTECTION WITH ESDA6V1-4F1

With the focus of lowering the operation levels, the problem of malfunction caused by the environment is

critical. Electrostatic discharge (ESD) is a major cause of failure in electronic system.

Transient Voltage Suppressors are an ideal choice for ESD protection and have proven capable in

suppressing ESD events. They are capable of clamping the incoming transient to a low enough level such

that damage to the protected semiconductor is prevented. Surface mount TVS arrays offer the best choice

for minimal lead inductance. They serve as parallel protection elements, connected between the signal line

to ground. As the transient rises above the operating voltage of the device, the TVS array becomes a low

impedance path diverting the transient current to ground.

4/6

ESDA6V1-4F1

The ESDA6V1-4F1 array is the ideal product for use as board level protection of ESD sensitive

semiconductor components.

The Flip Chip package makes the ESDA6V1-4F1 device some of the smallest ESD protection devices

available. It also allows design flexibility in the design of “crowded” boards where the space saving is at a

premium. This enables to shorten the routing and can contribute to improved ESD performance.

LAYOUT RECOMMENDATIONS

500µm

Copper Pad

Cu - Ni (2-6µm) - Au (0.2µm max)

= 250µm (300µm max)

Ø =320µm max (stencil aperture)

Solder paste

Stencil Design

Ø =340µm min (for 300µm pad

Non Solder mask opening

thickness of 150µm

Circuit board layout is a critical design step in the suppression of ESD induced transients. The following

guidelines are recommended :

■

The ESDA6V1-4F1 should be placed as close as possible to the input terminals or connectors.

Minimise the path length between the ESD suppressor and the protected device

Minimise all conductive loops, including power and ground loops

The ESD transient return path to ground should be kept as short as possible.

Use ground planes whenever possible.

5/6

ESDA6V1-4F1

PACKAGE MECHANICAL DATA

Flip Chip (all dimensions in µm)

500

MARKING

Die size: (1570 ± 50) x (1070 ± 50)

Die height (including bumps): 650 ± 40

Bump diameter: 315 ± 50

Pitch: 500 ± 50

1570

MARKING

Type

ESDA6V1-4F1

Marking

Delivery mode

Tape & reel

Order Code

Base qty

5000

ESDA6V1-4F1

Note: For PCB design, assembly recommendations and packing information please refer to Application

note AN1235. (“Flip-Chip: Package Description and recommendations for use”)

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of

use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by

implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied.

STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-

proval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

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http://www.st.com

6/6

ESDA6V1-4F [ETC]

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