ES52110 [ETC]

8-bit D/A Converter; 8位D / A转换器
ES52110
型号: ES52110
厂家: ETC    ETC
描述:

8-bit D/A Converter
8位D / A转换器

转换器
文件: 总15页 (文件大小:206K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Features  
DESCRIPTION  
ES52110 contains two & two 8-bit  
multiplying D/A converter in a single chip.This  
monolithic construction offers excellent DAC-  
to DAC matching and trzcking. The ES 52110  
consists of two R-2R resistor-ladder networks,  
two tracking span resistors, two data latches,  
one input buffer, and control logic circuit, Both  
On-Chip Latches for Both DACs.  
+5V to +12V Operation .  
DACs Matched to 1%.  
Four Quadrant Multiplication.  
TTL/CMOS Compatibel from 5V to 12V.  
Full Temperature Operation.  
8-bit Endpoint Linearity(+1/2 LSB)  
Microprocessor Compatible.  
DACs  
offer  
excellent  
four  
quadrant  
multiplication characteristics with a separated  
reference input and feedback resistor for each  
DAC.  
Applications  
Disk Drives  
Digital Gain/Attenuation Control  
Digitally-Controlled Filter Parameters  
19999/12/27 01:37 PM  
1
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
PIN Assignment  
AGND  
1
2
3
4
5
6
7
8
9
20 OUT B  
19 RFBB  
OUT A  
RFBA  
18 VREF  
B
VREF  
A
17 VDD  
DGND  
16 WR  
DACA/DACB  
(MSB)DB7  
DB6  
ES52099  
(YOP VOEW)  
15 CS  
14 DB0(LSB)  
13 DB 1  
12 DR2  
11 DB3  
DB5  
DB4 10  
Pin Description  
Pin NUMBER.  
1
NAME  
AGND  
TYPE  
DESCRIPTION  
The currcnt from the digital input are  
switched between the DAC OUTPUT and  
AGND thus maintaining fixed currcnt in  
cach ladder leg. Independent of switch statc.  
Analog data is restored from D/A conveter  
which the digital data is transferred ino ether  
of the two DAC.  
2
OUT A  
OUT B  
O
O
20  
3
19  
RFB  
A
Internal feedback resistor  
RFB A  
4
18  
VREF  
RREF  
A
B
The refercnce voltage for the R-2R ladder  
structure DAC.  
5
6
DGND  
DAC A/D ACB  
I
Both DAC latchcs sharc a common s-bit  
input port. The control input DAC A/D ACB  
selects which DAC can accept data from the  
input port.  
7-14  
15  
DB7-DB0  
CS  
I
I
Data bus is TTL./CMOS com -patible. Data  
is transferred into the either of two latches of  
DAC. DB0 is the least significant bit  
Input CS and WR control the operating  
mode of the selectod DAC. When CS and  
WR are both ow. The sclected DAC is in the  
Write mode. The input dath latches of the  
sclectod DAC are transparcnt and its analog  
output responds to activity on DB0-DB7  
Power  
17  
VDD  
19999/12/27 01:37 PM  
2
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
FUNCTION DESCRIPTION :  
Function Mode  
The selected DAC latch retains the data which is present on DB0-DB7 just  
prior to CS or WR assuming a high state.Both analog outputs remain at the  
values corresponding to the data in their respective latches.  
MODE SELECT TABLE  
DAC A/D ACB  
CS  
L
L
H
X
WR  
L
L
X
H
DACA  
WRITE  
HOLD  
HOLD  
HOLD  
DACB  
HOLD  
WRITE  
HOLD  
HOLD  
L
H
X
X
L=Low State H=High State X=Don't Care  
Circuit Description  
D/A Converter  
The ES 52110 contains two identical 8-bit multiplying D/A converters,  
DAC A and DAC B. Each DAC consists of a highly stable R-2R ladder and  
eight N-channel current steering switches. Asimplified D/A circuit for DAC  
A is shown in Figure 1. An inverted R-2R ladder structure is used, that is,  
binary weighted currents are switched between the DAC ouptut and AGND  
thus maintaining fixed currents in each ladder leg independent of switch  
state. There is normally closed switch in series with the internal feedback  
resistor (RFB). This switch improves linearity performance over temperature  
and power supply rejection; however , when the circuit is not powered up,  
the switch assumes and open state.  
19999/12/27 01:37 PM  
3
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Equivalent Circuit  
Figure 2 shows an approximate equivalent circuit for one of the ES 52110's D/A  
converters, in this case DAC A. A simpilar equivalent circuit can be drawn for DAC B.  
Note that AGND is common for both DAC A and DAC B. The current source ILKG is  
composed of surface and junction leakages , as with most semiconductor devices,  
apporximately doubles every 10. The resistor Ro as shown in Figure 2, is the  
equivalent output resistance of the device which varies with 11kΩ. COUT is the  
capacitance due to the N-channel switches and varies from about 50Pf to 120pF ,  
depending upon the digital input. g(VREFA,N) is the Thevenin equivalent voltage  
generator, due to the reference input voltage VREFA and transfer function of the R-2R  
ladder.  
19999/12/27 01:37 PM  
4
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
VDD to AGND  
Min  
O
Type  
Max  
+15  
Unit  
V
VDD to AGND  
O
O
+15  
VDD+0.3  
VDD+0.3  
VDD  
V
V
AGND to DGND  
Digital Input Vdtage to DGND  
VPIN2, VPIN20 to AGND  
VREF, VREFB to AGND  
VRFBA, VRFBB to AGND  
Operating Temperature Range  
Junction Temperature  
Storage Temperature  
Lead Temperature  
-0.3  
-0.3  
-25  
-25  
-55  
V
V
+20  
V
+20  
V
+125  
+150  
+150  
+300  
-65  
Notes:  
1.Do not aplly voltage higher than VDD or less than GND potential on any terminal except  
VREF  
.
2.The digital control inputs are Zener-Protected; however, permanent damage may occur  
on unprotected units from high-energy electrostatic fields. Keep units in conductive  
form at all times until ready for use.  
3.Do not insert this device into powered sockets; remove power before insertion or  
removal.  
4.Use proper antistatic handing proced ures.  
5.Stressed above those listed under"Abslute Maximum Ratings"may cause permanent  
damage to the device.  
19999/12/27 01:37 PM  
5
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Application Information  
The most common application of this DAC is voltage output operation. Unipolar  
output operation provides a 0 to 10 volt output swing when connected, as shown in  
Figure 4. The maximum output voltage polarity is the inverse of the input reference  
voltage, since the op amp inverts the input currents. The transfer equation for unipolar  
operation is V OUT=-VIN D/256, where Dis the decimal value of the data bit inputs DB0  
THRU DB7 and V IN is the reference input voltage. The transfer equation highlights  
another popular applicaton of CMOS DAC's , The output voltage is the product of the  
reference voltage and the digital input code. The reference input voltage can be any value  
in the range of ±VCC volts for both DC or AC signals. The circuit in Figure 4 performs  
tow-quadrant multiplication. Table 1 provides example analog outputs for the given  
digital input codes.  
For biploar output operation connect the ES 52110 as shown in Figure 5. This circuit  
configuration provides an offset current, derived from the reference to enable the output  
op amp to swing in both polarities. The digital input coding becomes offset binary . Table  
2 provides some example analog outputs for various digital nputs (D). The transfer  
equation for bipolar operation is VOUT = VIN×(D/128-1),where Dis the decimal value of  
the data bit inputs DB0 thru DB7. This circuit provides full four-quadrant multiplication  
able to accept both polarities on all input as well as the circuit output.  
19999/12/27 01:37 PM  
6
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
DACLATCH CONTENTS ANALOG OUTPUT  
DACLATCH CONTENTS ANALOG OUTPUT  
MSB LSB  
11111111  
1000001  
10000000  
01111111  
00000001  
00000000  
(DAC A or DACB)  
-VIN(255/256)  
-VIN(129/256)  
-VIN(128/256) = -VIN /2  
-VIN(127/256)  
MSB LSB  
111111111  
10000001  
10000000  
01111111  
00000001  
00000000  
(DAC A or DACB)  
+VIN(127/128)  
+VIN(1 /128)  
0
+VIN(1 /128)  
+VIN(127 /128)  
+VIN(128 /128)  
-VIN(1/ 256)  
-VIN(0/ 256) = 0  
Table 1. Unipolar Binary Code Table.  
Table 1. Unipolar Binary Code Table.  
NOTE: 1 LSB = (2 E-8)(VIN) = (1/256)(VIN)  
NOTE: 1 LSB = (2 E-7)(VIN) = (1/128)(VIN)  
19999/12/27 01:37 PM  
7
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
ELECTRICAL CHARACTERISTICS  
Operating Conditions:  
VDD = +5V±5%;VREFA = VREFB = +10V;IOUT A = IOUTB = 0V; TA = Full Temp. Range  
specified under Absolute Maximum Rating, unless otherwise noted.  
Static Accuracy  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
Resolution  
N
8
Bits  
Relative Accuracy  
(Note 2)  
Differential Nonlineraity  
(Note 3)  
Full-Scale Gain Error  
(Note 4)  
INL  
± 1/2 LSB  
± 1/2 LSB  
± 1/2 LSB  
INL  
GFSE  
8
TA = +25℃  
TA = Full Temp. Range  
Input Resistance  
(VREFA, VREFB)  
(Note 6)  
RIN  
15  
kΩ  
Input Resistance Match  
(VREFA/VREFB)  
± 0.1 ±1  
%
ΔRIN/RIN  
Digital Inputs  
(Note 9)  
Parameter  
Symbol  
VINH  
Conditions  
Min Typ Max Units  
Digital Input High  
(Note 8)  
Digital Input Low  
(Note 8)  
2.4  
V
VINL  
VIN  
0.8  
V
Input Current  
(Note 7)  
±0.01 ±1  
TA = +25℃  
TA = Full Temp. Range  
µA  
±10  
Input Capacitance  
(Note 10)  
CIN  
DB0-DB7  
WR, CS, DAV, A/DACB  
10  
15  
pF  
19999/12/27 01:37 PM  
8
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Switching Characteristics  
(Note 10,11)  
Parameter  
Symbol  
Conditions  
Min Typ Max Units  
Chip Select to  
Write Set-Up To,e  
Chip Select to  
tCS  
tCH  
tAS  
100  
ns  
ns  
ns  
ns  
ns  
ns  
10  
Write Hold time  
Chip Select to  
100  
100  
10  
Write Hold time  
Data Select to  
tDS  
Write Set-Up time  
Data Select to  
tDH  
Write Hold time  
Write Pulse Width  
TWR  
90  
Power Supply  
Parameter  
Symbol  
IDD  
Conditions  
Min Typ Max Units  
Supply Current  
All Digital Input = VDE or VNL  
1
mA  
All Digital Input = 0V or VDD  
TA = +25℃  
0.5  
1.0  
mA  
TA = Full Temp. Range  
19999/12/27 01:37 PM  
9
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
AC Performance Characteristic  
Parameter  
Symbol  
Conditions  
TA = +25℃  
Min Typ Max Units  
DC Supply Rejection Ratio  
(Δgain/ΔVDD)  
(Note 13)  
0.02  
0.04 %/%  
PSRR  
ts  
TA = Full Temp. Range  
Current Settling Time  
(Notes 10, 15, 16, 20)  
TA = Full Temp. Range  
350  
ns  
100  
Digital Charge Injection  
(Note 17)  
Q
nVs  
pF  
TA = +25℃  
COUTA DAC Latches Loaded  
COUTA With 0000 0000  
25  
25  
Ouptput Capactiance  
COUTA DAC Latches Loaded  
COUTA With 0000 0000  
60  
60  
pF  
FTA VREFA to IaxA :  
TA = +25℃  
TA = Full Temp. Range  
FTA VREFA to IaxA :  
TA = +25℃  
TA = Full Temp. Range  
CCIBA VREFA to IOUTB :  
VREFA = +20VP-P  
-70  
-65  
dB  
AC Feedthrough  
-70  
-65  
dB  
dB  
dB  
Channel-to-Channel  
Isolation  
(Note 19)  
-80  
-80  
Sinewave @ f = 10kHz  
VREFB = 0V;TA = 25℃  
CCIBA VREFA to IOUTB :  
VREFA = +20VP-P  
Sinewave @ f = 10kHz  
VREFB = 0V;TA = 25℃  
For Code Transition from  
Digital Crosstalk  
Q
0000 0000 to 1111 1111  
TA = +25℃  
30  
nVs  
dB  
Harmonic Distortion  
THD VDD = 6V @f = 1kHz  
-85  
TA = +25℃  
19999/12/27 01:37 PM  
10  
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Operating Conditions :  
VDD = +12V±5% ;VREFA = VREFB = +10V;IOUTA = IOUTB = 0V;TA =  
Full Temp. Range specified under Absolute Maximum Rating, unless  
otherwise noted.  
Static Accuracy  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Resolution  
Relative Accuracy  
(Note 2)  
N
INL  
8
Bits  
LSB  
± 1/2  
Differential Nonlineraity  
(Note 3)  
Full-Scale Gain Error  
(Note 4)  
DNL  
GFSE  
± 1  
LSB  
LSB  
±0.5  
±0.1  
±2  
±3  
TA = +25  
TA = Full Temp. Range  
Gain Tmperaturceoefficient  
(Δgain/Δtempertme)  
(Note 4)  
Output Leakage Curent  
IATA(Pin 2)IOUT(Pin 2)  
(Note 4)  
TCGFSE  
±0.0035  
%℃  
±0.5  
±5  
±200  
TA = +25℃  
TA = Full Temp.Range  
ILKG  
nA  
Input Resistance  
(VREFA, VREFB)  
(Note 6)  
Input Resistance Match  
(VREFA, VREFB)  
RIN  
8
15  
±1  
kΩ  
±0.1  
%
ΔRIN/RIN  
Digital Inputs  
(Note 9)  
Parameter  
Symbol  
VINH  
Conditions  
Min  
3.4  
Typ  
Max  
Unit  
V
Digital Input High  
(Note 8)  
Digital Input Low  
(Note 8)  
Input Current  
(Note 7)  
VINL  
IIN  
1.5  
V
±0.01  
±1  
±10  
TA = +25℃  
TA = Full Temp.Range  
DB0-DB7  
WR,CS,DAV A/DACB  
µA  
Input Capacitance  
(Note 10)  
CIN  
10  
15  
pF  
19999/12/27 01:37 PM  
11  
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Switchin g C harac teris tucs  
(Note 10, 11)  
Parameter  
Symbol  
Conditions  
Min Typ Max Unit  
Chip Select to  
TCS  
60  
10  
60  
10  
70  
10  
60  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Write Set-Up Time  
Chip Select to  
TCH  
TAS  
TAH  
TDS  
TDH  
TWR  
Write Hold Time  
DAC Select to  
Write Set-Up Time  
DAC Select to  
Write Hold Time  
Data Select to  
Write Set-Up Time  
Data Select to  
Write Hold Time  
Write Pulse Width  
Power Supply  
Parameter  
Symbol  
Conditions  
Min Typ Max Unit  
All Digital Input = VINH or VINL  
TA = +25℃  
6
6.5  
mA  
mA  
TA = Full Temp. Range  
Supply Current  
IDD  
All Digital Input = 0V or VDD  
TA = +25℃  
0.5  
1.0  
TA = Full Temp. Range  
19999/12/27 01:37 PM  
12  
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
Parameter  
DC Supply Rejection Ratio  
(Δgain /ΔVDD)  
Symbol  
PSRR  
ts  
Conditions  
TA = +25℃  
TA = Full Temp. Range  
TA = Full Temp. Range  
TA = +25℃  
Min  
Typ  
Max  
0.01  
0.02  
Unit  
%/%  
ns  
(Note 13)  
Current Settling Time  
(Note 10,15,16,20)  
Digital Charge Injection  
(Note 17)  
250  
Q
160  
nVs  
pF  
COUT  
A
DAC Latches Loaded  
25  
25  
Ouptput Capactiance  
COUTA With 0000 0000  
C
C
OUTA DAC Latches Loaded  
OUTA With 0000 0000  
60  
60  
pF  
FTA  
VREFA to IaxA :  
TA = +25℃  
-70  
-65  
AC Feedthrough  
dB  
TA = Full Temp. Range  
FTB  
VREFA to IaxA :  
TA = +25℃  
-70  
-65  
dB  
dB  
TA = Full Temp. Range  
CCIBA VREFA to IOUTB :  
REFA = +20VP-P  
Channel-to-Channel  
Isolation  
V
-80  
Sinewave @ f = 10kHz  
(Note 19)  
VREFB = 0V;TA = 25℃  
CCIAB VREFA to IOUTB :  
REFA = +20VP-P  
Sinewave @ f = 10kHz  
REFB = 0V;TA = 25℃  
V
-80  
dB  
V
For Code Transition from  
0000 0000 to 1111 1111  
TA = +25℃  
VDD = 6V @f = 1kHz  
TA = +25℃  
Digital Crosstalk  
Harmonic Distortion  
Notes:  
Q
50  
nVs  
dB  
THD  
-85  
1.Specifications apply to both DAC A and DAC B.  
2.This is an endpoint linearity specification.  
3.All grades guaranteed to be monotonic over the full operating the full operating temp. range.  
4.Measured using internal RFBA and RFBB. Both DAC latches loaded with 1111 1111.  
5.DAC loaded with 0000 0000.  
6.Input resistance TC = 300 ppm/.  
7.VIN = 0V or VDD.  
8.For all data bits DB0-DB7, WR, CS, DAC A/DACB.  
9.Logic inputs are MOS gates. Typical input current(+25)is less than lnA.  
10.Guaranteed and not tested.  
11.See timing diagram.  
12.These characteristics are for design guidance only and not subject to test.  
13.ΔVDD = ±5%.  
14.From digital input to 90% of final analog-output current.  
15.VREFA = VREFB = +10V;LOUTA, IOUTB load = 100Ω, CEXT = 13Pf.  
16.WR, CS = 0V, DB0-DB7 = 0V to VDD or VDD to 0V.  
19999/12/27 01:37 PM  
13  
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
17.For code transition 0000 0000 to 1111 1111.  
18.VREFA, VREFB = 20VP-P sinewave @ f = 10kHz.  
19.Both DAC latches loaded with 1111 1111.  
20.Extrapolated:ts(1/2LSB) = TPD + 6.2τ, whereτ = the measured first time constant of the  
fimal RC decay.  
WRITE CYCLE TIMING DIAGRAM  
Notes:  
1.All input signal rise and fall times measured from 10% to 90% are tr = tf = 20ns.  
2.Timing measurement reference level is(VIH + VIL)/2.  
19999/12/27 01:37 PM  
14  
ITRI  
ES52110  
ERSO  
8-bit D/A Converter  
19999/12/27 01:37 PM  
15  

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