EN29LV160JT70TI
更新时间:2024-09-18 02:26:05
品牌:ETC
描述:16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only
EN29LV160JT70TI 概述
16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only 16兆位( 2048K ×8位/ 1024K ×16位)闪存引导扇区快闪记忆体, CMOS 3.0伏只
EN29LV160JT70TI 数据手册
通过下载EN29LV160JT70TI数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载EN29LV160J
EN29LV160J ******PRELIMINARY DRAFT******
16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory
Boot Sector Flash Memory, CMOS 3.0 Volt-only
FEATURES
• 3.0V, single power supply operation
- Minimizes system level power requirements
• High performance program/erase speed
- Byte program time: 8µs typical
- Sector erase time: 200ms typical
- Chip erase time: 3.5s typical
• Manufactured on 0.28 µm process technology
• High performance
• JEDEC Standard program and erase
- Access times as fast as 70 ns
commands
• JEDEC standard
bits feature
polling and toggle
DATA
• Low power consumption (typical values at 5
MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 µA typical standby current (standard access
time to active mode)
• Single Sector and Chip Erase
• Sector Unprotect Mode
• Embedded Erase and Program Algorithms
• Erase Suspend / Resume modes:
Read and program another Sector during
Erase Suspend Mode
• Flexible Sector Architecture:
- One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
thirty-one 64 Kbyte sectors (byte mode)
- One 8 Kword, two 4 Kword, one 16 Kword
and thirty-one 32 Kword sectors (word mode)
- Supports full chip erase
- Individual sector erase supported
- Sector protection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
• 0.28 µm double-metal double-poly
triple-well CMOS Flash Technology
• Low Vcc write inhibit < 2.5V
• >100K program/erase endurance cycle
• 48-pin TSOP (Type 1)
• Commercial Temperature Range
Additionally, temporary Sector Group
Unprotect allows code changes in previously
locked sectors.
GENERAL DESCRIPTION
The EN29LV160J is a 16-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 2,097,152 bytes or 1,048,576 words. Any byte can be programmed typically in 10µs.
The EN29LV160J features 3.0V voltage read and write operation, with access times as fast as 55ns
to eliminate the need for WAIT states in high-performance microprocessor systems.
The EN29LV160J has separate Output Enable (
), Chip Enable (
), and Write Enable (WE)
CE
OE
controls, which eliminate bus contention issues. This device is designed to allow either single Sector
or full chip erase operation, where each Sector can be individually protected against program/erase
operations or temporarily unprotected to erase or program. The device can sustain a minimum of
100K program/erase cycles on each Sector.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
1
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
1
48
A16
2
47
BYTE#
3
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Vss
4
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Vcc
5
6
7
A8
8
A19
NC
9
Standard
TSOP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RESET#
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
Vss
NC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
CE#
A1
A0
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
A0-A19
Function
20 Addresses
EN29LV160
DQ0-DQ14
15 Data Inputs/Outputs
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Chip Enable
DQ15 / A-1
DQ0 – DQ15
(A-1)
A0 – A19
CE#
OE#
Output Enable
Hardware Reset Pin
Ready/Busy Output
Write Enable
Supply Voltage
(2.7-3.6V)
RESET#
RY/BY#
WE#
Reset
CE
OE
Vcc
RY/BY
WE
Byte
Vss
NC
BYTE#
Ground
Not Connected to anything
Byte/Word Mode
Table 2. Sector Address Tables (EN29LV160J)
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
2
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte mode (x8) Word Mode (x16)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
62/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
000000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–
00000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
SA10
SA11
SA12
SA13
SA14
SA15
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
50000–57FFF
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
0AFFFF
0B0000–
0BFFFF
0C0000–
0CFFFF
0D0000–
0DFFFF
0E0000–
0EFFFF
0F0000–
0FFFFF
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
SA26
SA27
SA28
SA29
SA30
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
1AFFFF
1B0000–
1BFFFF
1C0000–
1CFFFF
1D0000–
1DFFFF
1E0000–
1EFFFF
SA31
SA32
1
1
1
1
1
1
1
1
1
1
0
1
X
0
X
0
32/16
8/4
1F0000–1F7FFF
1F8000–1F9FFF
1FA000–
F8000–FBFFF
FC000–FCFFF
SA33
SA34
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
8/4
FD000–FDFFF
FE000–FFFFF
1FBFFF
1FC000–
1FFFFF
X
16/8
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
3
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 3. Sector Address Tables (EN29LV160J)
Address Range (in hexadecimal)
Sector Size
(Kbytes/
Kwords)
Sector A19 A18 A17 A16 A15 A14 A13 A12
Byte mode (x8) Word Mode (x16)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
X
0
1
16/8
8/4
8/4
000000–003FFF
004000–005FFF
006000–007FFF
008000–00FFFF
010000–01FFFF
020000–02FFFF
030000–03FFFF
040000–04FFFF
050000–05FFFF
060000–06FFFF
070000–07FFFF
080000–08FFFF
090000–09FFFF
0A0000–
00000–01FFF
02000–02FFF
03000–03FFF
04000–07FFF
08000–0FFFF
10000–17FFF
18000–1FFFF
20000–27FFF
28000–2FFFF
30000–37FFF
38000–3FFFF
40000–47FFF
48000–4FFFF
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
32/16
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
X
X
X
X
X
X
X
X
X
SA13
SA14
SA15
SA16
SA17
SA18
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
50000–57FFF
0AFFFF
0B0000–
0BFFFF
0C0000–
0CFFFF
0D0000–
0DFFFF
0E0000–
64/32
64/32
64/32
64/32
64/32
58000–5FFFF
60000–67FFF
68000–6FFFF
70000–77FFF
78000–7FFFF
0EFFFF
0F0000–
0FFFFF
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
64/32
100000–10FFFF
110000–11FFFF
120000–12FFFF
130000–13FFFF
140000–14FFFF
150000–15FFFF
160000–16FFFF
170000–17FFFF
180000–18FFFF
190000–19FFFF
1A0000–
80000–87FFF
88000–8FFFF
90000–97FFF
98000–9FFFF
A0000–A7FFF
A8000–AFFFF
B0000–B7FFF
B8000–BFFFF
C0000–C7FFF
C8000–CFFFF
SA29
SA30
SA31
SA32
SA33
SA34
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
D0000–D7FFF
D8000–DFFFF
E0000–E7FFF
E8000–EFFFF
F0000–F7FFF
F8000–FFFFF
1AFFFF
1B0000–
1BFFFF
1C0000–
1CFFFF
1D0000–
1DFFFF
1E0000–
64/32
64/32
64/32
64/32
64/32
1EFFFF
1F0000–
1FFFFF
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
4
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
5
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
PRODUCT SELECTOR GUIDE
Product Number
EN29LV160J
Regulated Voltage Range: Vcc=3.0 – 3.6 V
Full Voltage Range: Vcc=2.7 – 3.6 V
-70
-
-
Speed Option
-90
Max Access Time, ns (tacc
Max CE# Access, ns (tce)
Max OE# Access, ns (toe)
)
70
70
30
90
90
35
BLOCK DIAGRAM
RY/BY
Vcc
Vss
DQ0-DQ15 (A-1)
Block Protect Switches
Erase Voltage Generator
Input/Output Buffers
State
Control
WE
Program Voltage
Generator
Command
Register
STB
Chip Enable
Output Enable
Logic
Data Latch
CE
OE
Y-Decoder
Y-Gating
STB
Vcc Detector
A0-A18
Timer
X-Decoder
Cell Matrix
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
6
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
TABLE 3. OPERATING MODES
16M FLASH USER MODE TABLE
DQ8-DQ15
WE
#
A0-
A18
Byte#
= VIH
DOUT
DIN
Byte#
= VIL
High-Z
High-Z
Operation
CE#
OE#
Reset#
DQ0-DQ7
Read
Write
L
L
L
H
H
L
H
H
AIN
AIN
DOUT
DIN
Vcc ± 0.3V
H
L
Vcc ± 0.3V
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary
X
X
H
X
X
X
H
X
X
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
High-Z High-Z
H
H
L
X
Sector Unprotect
X
X
X
VID
AIN
DIN
DIN
X
Notes:
L=logic low= VIL, H=Logic High= VIH, VID =11 ± 0.5V, X=Don’t Care (either L or H, but not floating!),
DIN=Data In, DOUT=Data Out, AIN=Address In
TABLE 4. DEVICE IDENTIFICTION (Autoselect Codes)
16M FLASH MANUFACTURER/DEVICE ID TABLE
Description
Mode
A19 A11 A92 A8 A7 A6 A5 A1 A0
DQ8
to
DQ15
DQ7 to
DQ0
CE
L
OE WE
to
to
to
A12 A10
A2
Manufacturer ID:
Eon
Device ID
(top boot
block)
Device ID
(bottom boot
block)
L
H
X
X
X
X
VID
VID
H1
X
X
X
L
L
X
L
L
L
X
04H
Word
L
L
L
L
L
L
L
L
H
H
H
H
22h
X
C4H
22C4H
49H
X
H
Byte
Word
Byte
22h
X
X
X
X
VID
VID
X
X
X
X
L
L
X
X
L
H
L
2249H
01h
(Protected)
00h
(Unprotected)
X
X
Sector Protection
Verification
L
L
H
SA
H
Note:
1. If a manufacturing ID is read with A8=L, the chip will output a configuration code 7Fh. A further Manufacturing ID must be
read with A8=H.
2. A9 = VID is for HV A9 Autoselect mode only. A9 must be ≤ Vcc (CMOS logic level) for Command Autoselect Mode.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
7
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
USER MODE DEFINITIONS
Word / Byte Configuration
The signal set on the BYTE# Pin controls whether the device data I/O pins DQ15-DQ0 operate in the
byte or word configuration. When the Byte# Pin is set at logic ‘1’, then the device is in word
configuration, DQ15-DQ0 are active and are controlled by CE# and OE#.
On the other hand, if the Byte# Pin is set at logic ‘0’, then the device is in byte configuration, and only
data I/O pins DQ0-DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8-DQ14
are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
Standby Mode
The EN29LV160J has a CMOS-compatible standby mode, which reduces the current to < 1µA
(typical). It is placed in CMOS-compatible standby when the
pin is at VCC ± 0.5. RESET# and
CE
BYTE# pin must also be at CMOS input levels. The device also has a TTL-compatible standby mode,
which reduces the maximum VCC current to < 1mA. It is placed in TTL-compatible standby when the
pin is at VIH. When in standby modes, the outputs are in a high-impedance state independent of
CE
the
input.
OE
Read Mode
The device is automatically set to reading array data after device power-up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The
system can read array data using the standard read timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status data. After completing a programming operation in
the Erase Suspend mode, the system may once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more additional information.
The system must issue the reset command to re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset Command” additional details.
Output Disable Mode
When the
or
pin is at a logic high level (VIH), the output from the EN29LV160J is disabled.
OE
CE
The output pins are placed in a high impedance state.
Auto Select Identification Mode
The autoselect mode provides manufacturer and device identification, and sector protection
verification, through identifier codes output on DQ15–DQ0. This mode is primarily intended for
programming equipment to automatically match a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode requires VID (10.5 V to 11.5 V) on
address pin A9. Address pins A6, A1, and A0 must be as shown in Autoselect Codes table. In
addition, when verifying sector protection, the sector address must appear on the appropriate highest
order address bits. Refer to the corresponding Sector Address Tables. The Command Definitions
table shows the remaining address bits that are don’t-care. When all necessary bits have been set as
required, the programming equipment may then read the corresponding identifier code on DQ15–
DQ0.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
8
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
To access the autoselect codes in-system; the host system can issue the autoselect command via
the command register, as shown in the Command Definitions table. This method does not require
VID. See “Command Definitions” for details on using the autoselect mode.
Write Mode
Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two
unlock write cycles, followed by the program set-up command. The program address and data are written
next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides internally generated program pulses and verifies
the programmed cell margin. The Command Definitions in Table 5 show the address and data
requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, the device then returns to reading array data and
addresses are no longer latched. The system can determine the status of the program operation by using
DQ7 or DQ6. See “Write Operation Status” for information on these status bits.
Any commands written to the device during the Embedded Program Algorithm are ignored.
Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt the operation and set DQ5 to “1”, or cause the
Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show
that the data is still “0”. Only erase operations can convert a “0” to a “1”.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously
protected sectors.
There are two methods to enabling this hardware protection circuitry. The first one requires
only that the RESET# pin be at V and then standard microprocessor timings can be used to enable
ID
or disable this feature. See Flowchart 7a and 7b for the algorithm and Figure 12 for the timings.
When doing Sector Unprotect, all the other sectors should be protected first.
The second method is meant for programming equipment. This method requires V be
ID
applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is
described in a separate document called EN29LV160J Supplement, which can be obtained by
contacting a representative of Eon Silicon Devices, Inc.
Temporary Sector Unprotect
Start
This feature allows temporary unprotection of previously protected
sector groups to change data while in-system. The Sector Unprotect
mode is activated by setting the RESET# pin to VID. During this mode,
formerly protected sectors can be programmed or erased by simply
selecting the sector addresses. Once is removed from the RESET#
pin, all the previously protected sectors are protected again. See
accompanying figure and timing diagrams for more details.
Reset#=VID (note 1)
Perform Erase or Program
Operations
Reset#=VIH
Notes:
1. All protected sectors unprotected.
2. Previously protected sectors protected
again.
COMMON FLASH MEMORY
INTERFACE
Temporary Sector
Unprotect Completed (note 2)
(CFI)
The
common
flash
interface
(CFI)
allows specific vendor-specified software
algorithms to be used for entire families of
specification outlines device and host systems
software interrogation handshake, which
devices.
Software support can then be
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
9
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
device-independent, JEDEC ID-independent,
and forward- and backward-compatible for the
specified flash device families. Flash vendirs
can standardize their existing interfaces for
long-term compatibility.
The system can read CFI information at the
addresses given in Tables 5-8. In word mode,
the upper address bits (A7–MSB) must be all
zeros. To terminate reading CFI data, the
system must write the reset command.
This device enters the CFI Query mode when
the system writes the CFI Query command,
98h, to address 55h in word mode (or address
AAh in byte mode), any time the device is
ready to read array data.
The system can also write the CFI query
command when the device is in the autoselect
mode. The device enters the CFI query mode
and the system can read CFI data at the
addresses given in Tables 5–8. The system
must write the reset command to return the
device to the autoselect mode.
Table 5. CFI Query Identification String
Adresses
Adresses
(Word Mode) (Byte Mode)
Data
Description
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
20h
22h
24h
26h
28h
2Ah
2Ch
2Eh
30h
32h
34h
0051h
0052h Query Unique ASCII string “QRY”
0059h
0002h
Primary OEM Command Set
0000h
0040h
Address for Primary Extended Table
0000h
0000h
Alternate OEM Command set (00h = none exists)
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists
0000h
Table 6. System Interface String
Addresses
Addresses
(Word Mode) (Byte Mode)
Data
Description
1Bh
36h
0027h Vcc Min (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
0036h Vcc Max (write/erase)
D7-D4: volt, D3 –D0: 100 millivolt
1Ch
38h
1Dh
1Eh
1Fh
3Ah
3Ch
3Eh
0000h Vpp Min. voltage (00h = no Vpp pin present)
0000h Vpp Max. voltage (00h = no Vpp pin present)
0004h
Typical timeout per single byte/word write 2^N µs
20h
40h
0000h
Typical timeout for Min, size buffer write 2^N µs (00h = not
supported)
21h
22h
23h
24h
25h
26h
42h
44h
46h
48h
4Ah
4Ch
000Ah Typical timeout per individual block erase 2^N ms
0000h Typical timeout for full chip erase 2^N ms (00h = not supported)
0005h Max. timeout for byte/word write 2^N times typical
0000h Max. timeout for buffer write 2^N times typical
0004h Max. timeout per individual block erase 2^N times typical
0000h Max timeout for full chip erase 2^N times typical (00h = not
supported)
Table 7. Device Geometry Definition
Addresses
Addresses
(Word mode)
(Byte Mode)
Data
Description
27h
4Eh
0015h
Device Size = 2^N byte
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
10
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
38h
39h
3Ah
3Bh
3Ch
50h
52h
54h
56h
58h
5Ah
5Ch
5Eh
60h
62h
64h
66h
68h
6Ah
6Ch
6Eh
70h
72h
74h
76h
78h
0002h
0000h
0000h
0000h
0004h
0000h
0000h
0040h
0000h
0001h
0000h
0020h
0000h
0000h
0000h
0080h
0000h
001Eh
0000h
0000h
0001h
Flash Device Interface description (refer to CFI publication 100)
Max. number of byte in multi-byte write = 2^N
(00h = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information
(refer to the CFI specification of CFI publication 100)
Erase Block Region 2 Information
Erase Block Region 3 Information
Erase Block Region 4 Information
Table 8. Primary Vendor-specific Extended Query
Adresses
Addresses
(Word Mode)
(Byte Mode)
Data
Description
Query-unique ASCII string “PRI”
40h
41h
42h
43h
44h
80h
82h
84h
86h
88h
0050h
0052h
0049h
0031h
0030h
Major version number, ASCII
Minor version number, ASCII
Address Sensitive Unlock
0 = Required, 1 = Not Required
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
Sector Protect
45h
46h
47h
48h
8Ah
8Ch
8Eh
90h
0000h
0002h
0001h
0001h
0 = Not Supported, X = Number of sectors in per group
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
Sector Protect/Unprotect scheme
01 = 29F040 mode, 02 = 29F016 mode,
03 = 29F400 mode, 04 = 29LV800A mode
Simultaneous Operation
00 = Not Supported, 01 = Supported
Burst Mode Type
00 = Not Supported, 01 = Supported
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
49h
92h
0004h
4Ah
4Bh
4Ch
94h
96h
98h
0000h
0000h
0000h
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
11
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Hardware Data protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low VCC Write Inhibit
When Vcc is less than VLKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than VLKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
VLKO
.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on
,
or
do not initiate a write cycle.
W E
OE CE
Logical Inhibit
Write cycles are inhibited by holding any one of
= VIL,
= VIH, or
= VIH. To initiate a write
W E
OE
CE
cycle,
and
must be a logical zero while
is a logical one. If
,
, a nd
a re a ll
OE
CE
W E
OE
CE W E
lo g ic a l ze ro (no t re c o m m e nd e d usa g e ), it will b e c o nsid e re d a re a d .
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with
W E
= V ,
= V and
= V , the device will not accept commands on the rising edge of
OE
IH
CE
.
WE
IL
IL
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
12
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
COMMAND DEFINITIONS
The operations of the EN29LV160J are selected by one or more commands written into the
command register to perform Read/Reset Memory, Read ID, Read Sector Protection, Program,
Sector Erase, Chip Erase, Erase Suspend and Erase Resume. Commands are made up of data
sequences written at specific addresses via the command register. The sequences for the
specified operation are defined in the Command Definitions table (Table 5). Incorrect addresses,
incorrect data values or improper sequences will reset the device to Read Mode.
Table 5. EN29LV160J Command Definitions
Bus Cycles
1st
2nd
Write Cycle
3rd
Write Cycle
4th
5th
6th
Command
Sequence
Write Cycle
Write Cycle
Write Cycle
Write Cycle
Add
Data Add
Data Add
Data Add
Data
Add
Data Add
Data
Read
Reset
1
1
RA
xxx
RD
F0
Manufacturer
ID
Word
Byte
555
AAA
2AA
555
555
90
000/ 7F/
4
AA
55
55
100
1C
AAA
001/
101
7F/
22DA
Word
Byte
555
AAA
555
AAA
555
AAA
2AA
555
2AA
555
90
AAA
Device ID
Top Boot
4
AA
002/ 7F/
102 DA
001/ 7F/
Word
Byte
555
90
AAA
Device ID
Bottom Boot
101
225B
4
4
AA
AA
55
002/ 7F/
555
102
(SA) XX00
X02
(SA) 00
5B
2AA
Word
Byte
555
90
AAA
Sector Protect
Verify
XX01
55
55
555
X04
01
Word
Byte
Word
Byte
555
AAA
555
AAA
XXX A0
XXX 90
2AA
555
2AA
555
PA
555
A0
Program
Unlock Bypass
4
3
AA
AA
PA
PD
AAA
555
AAA
55
20
Unlock Bypass Program
Unlock Bypass Reset
2
2
PD
XXX 00
Word
555
AAA
555
AAA
2AA
555
2AA
555
555
80
555
AAA
555
AAA
2AA
555
2AA
555
555
10
Chip Erase
6
6
AA
55
AA
AA
55
55
Byte
Word
Byte
AAA
AAA
555
Sector Erase
AA
55
80
SA
30
AAA
Erase Suspend
Erase Resume
1
1
xxx
xxx
B0
30
Address and Data values indicated in hex
RA = Read Address: address of the memory location to be read. This is a read cycle.
RD = Read Data: data read from location RA during Read operation. This is a read cycle.
PA = Program Address: address of the memory location to be programmed. X = Don’t-Care
PD = Program Data: data to be programmed at location PA
SA = Sector Address: address of the Sector to be erased or verified. Address bits A18-A12 uniquely select any Sector.
Reading Array Data
The device is automatically set to reading array data after power up. No commands are required to
retrieve data. The device is also ready to read array data after completing an Embedded Program or
Embedded Erase algorithm.
Following an Erase Suspend command, Erase Suspend mode is entered. The system can read array data
using the standard read timings, with the only difference in that if it reads at an address within erase
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
13
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
suspended sectors, the device outputs status data. After completing a programming operation in the Erase
Suspend mode, the system may once again read array data with the same exception.
The Reset command must be issued to re-enable the device for reading array data if DQ5 goes high, or while
in the autoselect mode. See next section for details on Reset.
Reset Command
Writing the reset command to the device resets the device to reading array data. Address bits are don’t-
care for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the device to reading array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete. The reset command may be written between the
sequence cycles in a program command sequence before programming begins. This resets the device to
reading array data (also applies to programming in Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the operation is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must be written to return to reading array data (also
applies to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation, writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system to access the manufacturer and devices
codes, and determine whether or not a sector is protected. The Command Definitions table shows the
address and data requirements. This is an alternative to the method that requires VID on address bit A9
and is intended for PROM programmers.
Two unlock cycles followed by the autoselect command initiate the autoselect command sequence.
Autoselect mode is then entered and the system may read at addresses shown in Table 4 any number of
times, without needing another command sequence.
The system must write the reset command to exit the autoselect mode and return to reading array data.
Word / Byte Programming Command
The device may be programmed by byte or by word, depending on the state of the Byte# Pin.
Programming the EN29LV160J is performed by using a four bus-cycle operation (two unlock write
cycles followed by the Program Setup command and Program Data Write cycle). When the program
command is executed, no additional CPU controls or timings are necessary. An internal timer
terminates the program operation automatically. Address is latched on the falling edge of
or
CE
, whichever is last; data is latched on the rising edge of
or
W E
, whichever is first.
W E
CE
Programming status may be checked by sampling data on DQ7 (
polling) or on DQ6 (toggle
DATA
bit). ). When the program operation is successfully completed, the device returns to read mode and
the user can read the data programmed to the device at that address. Note that data can not be
programmed from a 0 to a 1. Only an erase operation can change a data from 0 to 1. When
programming time limit is exceeded, DQ5 will produce a logical “1” and a Reset command can return
the device to Read mode.
Unlock Bypass
To speed up programming operation, the Unlock Bypass Command may be used. Once this feature
is activated, the shorter two cycle Unlock Bypass Program command can be used instead of the
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
14
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
normal four cycle Program Command to program the device. This mode is exited after issuing the
Unlock Bypass Reset Command. The device powers up with this feature disabled.
Chip Erase Command
Chip erase is a six-bus-cycle operation. The chip erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
chip erase command, which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required
to provide any controls or timings during these operations. The Command Definitions table shows the
address and data requirements for the chip erase command sequence.
Any commands written to the chip during the Embedded Chip Erase algorithm are ignored.
The system can determine the status of the erase operation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete,
the device returns to reading array data and addresses are no longer latched.
Flowchart 4 illustrates the algorithm for the erase operation. See the Erase/Program Operations tables in
“AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing
waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
un-lock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by
the address of the sector to be erased, and the sector erase command. The Command Definitions table
shows the address and data requirements for the sector erase command sequence.
Once the sector erase operation has begun, only the Erase Suspend command is valid. All other
commands are ignored.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, or
DQ2. Refer to “Write Operation Status” for information on these status bits. Flowchart 4 illustrates the
algorithm for the erase operation. Refer to the Erase/Program Operations tables in the “AC
Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing
waveforms.
Erase Suspend / Resume Command
The Erase Suspend command allows the system to interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for erasure. This command is valid only during the
sector erase operation. The Erase Suspend command is ignored if written during the chip erase operation
or Embedded Program algorithm. Addresses are don’t-cares when writing the Erase Suspend command.
When the Erase Suspend command is written during a sector erase operation, the device requires a
maximum of 20 µs to suspend the erase operation.
After the erase operation has been suspended, the system can read array data from or program data to
any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.)
Normal read and write timings and command definitions apply. Reading at any address within erase-
suspended sectors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2
together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status”
for information on these status bits.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
15
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
After an erase-suspended program operation is complete, the system can once again read array data
within non-suspended sectors. The system can determine the status of the program operation using the
DQ7 or DQ6 status bits, just as in the standard program operation. See “Write Operation Status” for more
information. The Autoselect command is not supported during Erase Suspend Mode.
The system must write the Erase Resume command (address bits are don’t-care) to exit the erase
suspend mode and continue the sector erase operation. Further writes of the Resume command are
ignored. Another Erase Suspend command can be written after the device has resumed erasing.
WRITE OPERATION STATUS
DQ7
DATA Polling
The EN29LV160J provides
embedded operations. The
Polling on DQ7 to indicate to the host system the status of the
Polling feature is active during the Byte Programming, Sector
DATA
DATA
Erase, Chip Erase, Erase Suspend. (See Table 6)
When the Byte Programming is in progress, an attempt to read the device will produce the
complement of the data last written to DQ7. Upon the completion of the Byte Programming, an
attempt to read the device will produce the true data last written to DQ7. For the Byte Programming,
polling is valid after the rising edge of the fourth
or
pulse in the four-cycle sequence.
CE
DATA
WE
When the embedded Erase is in progress, an attempt to read the device will produce a “0” at the
DQ7 output. Upon the completion of the embedded Erase, the device will produce the “1” at the DQ7
output during the read. For Chip Erase, the
polling is valid after the rising edge of the sixth
DATA
pulse in the six-cycle sequence. For Sector Erase, polling is valid after the last
DATA
or
W E
CE
rising edge of the sector erase
or
pulse.
C E
W E
Polling must be performed at any address within a sector that is being programmed or erased
DATA
and not a protected sector. Otherwise,
polling may give an inaccurate result if the address
DATA
used is in a protected sector.
Just prior to the completion of the embedded operations, DQ7 may change asynchronously when the
output enable ( ) is low. This means that the device is driving status information on DQ7 at one
OE
instant of time and valid data at the next instant of time. Depending on when the system samples the
DQ7 output, it may read the status of valid data. Even if the device has completed the embedded
operations and DQ7 has a valid data, the data output on DQ0-DQ6 may be still invalid. The valid
data on DQ0-DQ7 will be read on the subsequent read attempts.
The flowchart for
Polling (DQ7) is shown on Flowchart 5. The
Polling (DQ7) timing
DATA
DATA
diagram is shown in Figure 8.
RY/BY: Ready/Busy
The RY/BY is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY status is valid after the rising edge of the final WE pulse in the
command sequence. Since RY/BY is an open-drain output, several RY/BY pins can be tied together
in parallel with a pull-up resistor to Vcc.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
16
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
In the output is low, signifying Busy, the device is actively erasing or programming. This includes
programming in the Erase Suspend mode. If the output is high, signifying the Ready, the device is
ready to read array data (including during the Erase Suspend mode), or is in the standby mode.
DQ6
Toggle Bit I
The EN29LV160J provides a “Toggle Bit” on DQ6 to indicate to the host system the status of the
embedded programming and erase operations. (See Table 6)
During an embedded Program or Erase operation, successive attempts to read data from the device
at any address (by toggling
or
) will result in DQ6 toggling between “zero” and “one”. Once
CE
OE
the embedded Program or Erase operation is complete, DQ6 will stop toggling and valid data will be
read on the next successive attempts. During Byte Programming, the Toggle Bit is valid after the
rising edge of the fourth
pulse in the four-cycle sequence. For Chip Erase, the Toggle Bit is valid
WE
after the rising edge of the sixth-cycle sequence. For Sector Erase, the Toggle Bit is valid after the
last rising edge of the Sector Erase pulse.
W E
In Byte Programming, if the sector being written to is protected, DQ6 will toggles for about 2 µs, then
stop toggling without the data in the sector having changed. In Sector Erase or Chip Erase, if all
selected blocks are protected, DQ6 will toggle for about 100 µs. The chip will then return to the read
mode without changing data in all protected blocks.
Toggling either
or
will cause DQ6 to toggle.
OE
CE
The flowchart for the Toggle Bit (DQ6) is shown in Flowchart 6. The Toggle Bit timing diagram is
shown in Figure 9.
DQ5 Exceeded Timing Limits
DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1.” This is a failure condition that indicates the program or erase
cycle was not successfully completed. Since it is possible that DQ5 can become a 1 when the device has
successfully completed its operation and has returned to read mode, the user must check again to see if
the DQ6 is toggling after detecting a “1” on DQ5.
The DQ5 failure condition may appear if the system tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue the reset command to return the device to reading
array data.
DQ3 Sector Erase Timer
After writing a sector erase command sequence, the output on DQ3 can be used to determine whether or
not an erase operation has begun. (The sector erase timer does not apply to the chip erase command.)
When sector erase starts, DQ3 switches from “0” to “1.” This device does not support multiple sector
erase command sequences so it is not very meaningful since it immediately shows as a “1” after the first
30h command. Future devices may support this feature.
DQ2 Erase Toggle Bit II
The “Toggle Bit” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle
Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when
the system reads at addresses within those sectors that have been selected for erasure. (The system may
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
17
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 5 to compare outputs for DQ2 and
DQ6.
Flowchart 6 shows the toggle bit algorithm, and the section “DQ2: Toggle Bit” explains the algorithm. See
also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing
diagram. The DQ2 vs. DQ6 figure shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Flowchart 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling.
Typically, a system would note and store the value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not
toggling, the device has completed the program or erase operation. The system can read array data on
DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped
toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully
completed the program or erase operation. If it is still toggling, the device did not complete the operation
successfully, and the system must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read
cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Flowchart 6).
Write Operation Status
RY/BY
Operation
DQ7
DQ6
DQ5
DQ3
DQ2
#
0
0
1
Embedded Program
Algorithm
No
toggle
DQ7#
Toggle
Toggle
0
0
0
N/A
1
Standard
Mode
Embedded Erase Algorithm
0
1
Toggle
Reading within Erase
Suspended Sector
No
Toggle
N/A
Toggle
Erase
Suspend
Mode
Reading within Non-Erase
Suspended Sector
Data
Data
Data
0
Data
N/A
Data
N/A
1
0
Erase-Suspend Program
DQ7#
Toggle
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
18
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 6. Status Register Bits
DQ
Name
Logic Level
Definition
Erase Complete or
erase Sector in Erase
suspend
‘1’
‘0’
Erase On-Going
DATA
POLLING
7
Program Complete or
data of non-erase Sector
during Erase Suspend
DQ7
DQ7
‘-1-0-1-0-1-0-1-’
DQ6
Program On-Going
Erase or Program On-going
Read during Erase Suspend
TOGGLE
BIT
6
Erase Complete
‘-1-1-1-1-1-1-1-‘
‘1’
‘0’
‘1’
‘0’
Program or Erase Error
Program or Erase On-going
Erase operation start
5
3
ERROR BIT
ERASE
TIME BIT
Erase timeout period on-going
Chip Erase, Erase or Erase
suspend on currently
addressed
Sector. (When DQ5=1, Erase
Error due to currently
addressed Sector. Program
during Erase Suspend on-
going at current address
TOGGLE
BIT
2
‘-1-0-1-0-1-0-1-’
DQ2
Erase Suspend read on
non Erase Suspend Sector
Notes:
DQ7
Polling: indicates the P/E C status check during Program or Erase, and on completion before checking bits
DATA
DQ5 for Program or Erase Success.
DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.
Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.
DQ5 Error Bit: set to “1” if failure in programming or erase
DQ3 Sector Erase Command Timeout Bit: Operation has started. Only possible command is Erase suspend (ES).
DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
19
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
EMBEDDED ALGORITHMS
Flowchart 1. Embedded Program
START
Write Program
Command Sequence
(shown below)
Data Poll Device
Verify Data?
Last
Increment
Address
No
Address?
Yes
Programming Done
Flowchart 2. Embedded Program Command Sequence
See the Command Definitions section for more information.
555H / AAH
2AAH / 55H
555H / A0H
PROGRAM ADDRESS / PROGRAM DATA
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
20
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Flowchart 3. Embedded Erase
START
Write Erase
Command Sequence
Data Poll from
System or Toggle Bit
successfully
completed
Data =FFh?
No
Yes
Erase Done
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
21
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Flowchart 4. Embedded Erase Command Sequence
See the Command Definitions section for more information.
Chip Erase
555H/AAH
Sector Erase
555H/AAH
2AAH/55H
555H/80H
2AAH/55H
555H/80H
555H/AAH
2AAH/55H
555H/10H
555H/AAH
2AAH/55H
Sector Address/30H
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
22
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Flowchart 5. DATA Polling
Algorithm
Start
Read Data
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read Data (1)
Notes:
Yes
(1) This second read is necessary in case the
first read was done at the exact instant when
the status data was in transition.
DQ7 = Data?
No
Fail
Pass
Start
Flowchart 6. Toggle Bit Algorithm
Read Data twice
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
Read Data twice (2)
Notes:
No
(1) This second set of reads is necessary in case
the first set of reads was done at the exact
instant when the status data was in transition.
DQ6 = Toggle?
Yes
Fail
Pass
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
23
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Flowchart 7a. In-System Sector Protect Flowchart
START
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle =
60h?
Temporary Sector
Unprotect Mode
Yes
Set up sector
address
Sector Protect: Write 60h
to sector addr with
A6 = 0, A1 = 1, A0 = 0
Wait 150 µs
Verify Sector Protect:
Write 40h to sector
address with
A6 = 0, A1 = 1, A0 = 0
Increment
PLSCNT
Reset
PLSCNT = 1
Wait 0.4 µs
Read from sector
address with
A6 = 0, A1 = 1, A0
No
No
Data = 01h?
Yes
PLSCNT = 25?
Yes
Device failed
Yes
Protect another
sector?
No
Remove VID
from RESET#
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
24
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Flowchart 7b. In-System Sector Unprotect Flowchart
START
PLSCNT = 1
Protect all sectors:
The indicated
portion of the sector
RESET# = VID
protect algorithm
must be performed
Wait 1 µS
for all unprotected
sectors prior to
issuing the first
No
sector unprotect
address (see
Diagram 7a.)
Temporary Sector
Unprotect Mode
First Write
Cycle = 60h?
Yes
No
All sectors
protected?
Yes
Set up first sector
address
Sector Unprotect: Write 60H to
sector address with A6 = 1,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector Unprotect:
Write 40h to sector address
with A6 = 1, A1 = 1, A0 =0
Increment
PLSCNT
Wait 0.4 µS
Read from sector address with
A6 = 1, A1 = 1, A0 = 0
No
No
PLSCCNT =
1000?
Set up next sector
Data = 00h?
address
Yes
Yes
Sector
Unprotect
Algorithm
No
Last sector
verified?
Device failed
Yes
Remove VID from
RESET#
Write reset
command
Sector Unprotect
complete
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
25
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 7. DC Characteristics
(Ta = 0°C to 70°C or - 40°C to 85°C; VCC = 2.7-3.6V)
Symbol
Parameter
Test Conditions
Min
Max
Unit
Typ
Input Leakage Current
Output Leakage Current
Supply Current (read) TTL
±5
±5
16
18
20
µA
µA
I
0V≤ V ≤ Vcc
IN
LI
I
0V≤ V ≤ Vcc
OUT
LO
8
6
7
mA
mA
mA
CE# = V ; OE# = V
;
IH
IL
(read) CMOS Byte
I
CC1
f = 5MHz
(read) CMOS Word
CE# = V ,
IH
BYTE# = RESET# =
Vcc ± 0.3V
(Note 1)
CE# = BYTE# =
RESET# = Vcc ± 0.3V
(Note 1)
Supply Current (Standby - TTL)
0.4
1.0
5.0
mA
I
I
CC2
CC3
(Standby - CMOS)
1
µA
Byte program, Sector or
Chip Erase in progress
25
50
mA
Supply Current (Program or Erase)
Input Low Voltage
-0.5
0.8
V
V
V
V
V
IL
0.7 x
Vcc
Vcc ±
0.3
Input High Voltage
V
IH
Output Low Voltage
0.45
V
I
= 4.0 mA
= -2.0 mA
OL
OL
0.85 x
Vcc
Vcc -
0.4V
Output High Voltage TTL
I
OH
OH
V
OH
Output High Voltage CMOS
V
I
= -100 µA,
A9 Voltage (Electronic Signature)
A9 Current (Electronic Signature)
10.5
2.3
11.5
100
V
V
ID
A9 = VID
µA
I
ID
Supply voltage (Erase and
Program lock-out)
V
LKO
2.5
V
Notes
1. BYTE# pin can also be GND ± 0.3V. BYTE# and RESET# pin input buffers are always enabled so that
they draw power if not at full CMOS supply voltages.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
26
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Test Conditions
3.3 V
2.7 kΩ
Device Under Test
CL
6.2 kΩ
Note: Diodes are IN3064 or equivalent
Test Specifications
Test Conditions
Output Load
-55
-70
-90
Unit
1 TTL Gate
Output Load Capacitance, CL
Input Rise and Fall times
Input Pulse Levels
30
100
20
100
20
pF
ns
V
5
0.0-0.3
0.45-2.4
0.45-2.4
Input timing measurement
reference levels
Output timing measurement
reference levels
0.8, 0.7 x 0.8, 0.7 x
Vcc Vcc
0.8, 0.7 x 0.8, 0.7 x
Vcc Vcc
1.5
1.5
V
V
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
27
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
AC CHARACTERISTICS
Hardware Reset (Reset#)
Speed options
-70 -90
Unit
Parameter
Test
Setup
Description
Std
Reset# Pin Low to Read or Write
Embedded Algorithms
Reset# Pin Low to Read or Write
Non Embedded Algorithms
tREADY
Max
Max
20
µs
tREADY
500
nS
tRP
tRH
Reset# Pulse Width
Min
Min
500
50
nS
nS
Reset# High Time Before Read
Reset# Timings
RY/BY#
0 V
CE#
OE#
tRH
RESET#
tRP
tREADY
Reset Timings NOT During Automatic Algorithms
RY/BY#
tREADY
CE#
OE#
RESET#
tRP
tRH
Reset Timings During Automatic Algorithms
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
28
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
AC CHARACTERISTICS
Word / Byte Configuration (Byte#)
Speed
Unit
Std
Parameter
Description
-70
0
-90
0
-120
0
tBCS
Byte# to CE# switching setup time
CE# to Byte# switching hold time
RY/BY# to Byte# switching hold time
Min
Min
Min
ns
ns
ns
tCBH
0
0
0
0
0
0
tRBH
CE
OE
Byte
tCBH
tBCS
Byte timings for Read Operations
CE
WE
Byte
tRBH
tBCS
RY/BY
Byte timings for Write Operations
Note: Switching BYTE# pin not allowed during embedded operations
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
29
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 8. AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbols
Speed Options
Test
Description
Setup
JEDEC
Standard
-70
-90
Unit
Min
70
90
ns
Read Cycle Time
tAVAV
tRC
Max
70
90
ns
Address to Output Delay
tAVQV
tACC
= VIL
CE
= VIL
OE
Max
Max
Max
Max
Min
70
30
20
20
0
90
35
20
20
0
ns
ns
ns
ns
ns
Chip Enable To Output Delay
Output Enable to Output Delay
Chip Enable to Output High Z
tELQV
tGLQV
tEHQZ
tGHQZ
tAXQX
tCE
tOE
tDF
tDF
tOH
OE = VIL
Output Enable to Output High Z
Output Hold Time from
Addresses,
whichever occurs first
or ,
CE OE
Notes:
For - 50
Vcc = 3.0V ± 5%
Output Load : 1 TTL gate and 30pF
Input Rise and Fall Times: 5ns
Input Rise Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level, Input and Output: 1.5 V
For all others:
Vcc = 2.7V – 3.6V
Output Load: 1 TTL gate and 100 pF
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.45 V to .8 x Vcc
Timing Measurement Reference Level, Input and Output: 0.8 V and .7 x Vcc
tRC
Addresses Stable
Addresses
CE#
tACC
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
Output Valid
Outputs
Reset#
RY/BY#
0V
Figure 5. AC Waveforms for READ Operations
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
30
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 9. AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter
Symbols
Speed Options
Description
JEDEC
Standard
-70
-90
Unit
Min
Min
Min
Min
Min
70
90
ns
tAVAV
tWC
Write Cycle Time
0
45
30
0
0
45
45
0
ns
ns
ns
ns
tAVWL
tWLAX
tDVWH
tWHDX
tAS
tAH
Address Setup Time
Address Hold Time
Data Setup Time
tDS
tDH
tOES
Data Hold Time
Min
MIn
Min
0
0
0
0
ns
ns
ns
Output Enable Setup Time
Read
Output Enable
Toggle and
tOEH
Hold Time
10
10
Polling
DATA
Read Recovery Time before
Min
0
0
ns
tGHWL
tGHWL
Write (
High to
Low)
W E
OE
CE
Min
Min
Min
Min
0
0
0
0
ns
ns
ns
ns
tELWL
tWHEH
tWLWH
tWHDL
tCS
tCH
tWP
tWPH
SetupTime
Hold Time
CE
35
20
45
20
Write Pulse Width
Write Pulse Width High
Programming Operation
(Word AND Byte Mode)
Typ
7
7
µs
tWHWH1 tWHWH1
Max
Typ
Max
Typ
Max
Min
200
0.3
5
200
0.3
5
µs
s
tWHWH2 tWHWH2
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time
s
3
3
s
tWHWH3 tWHWH3
35
50
35
50
s
µs
tVCS
Min
500
500
ns
tVIDR
Rise Time to V
ID
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
31
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 10. AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter
Symbols
Speed Options
Description
JEDEC
Standard
-70
-90
Unit
Min
Min
Min
Min
Min
Min
70
90
ns
Write Cycle Time
tAVAV
tWC
0
45
30
0
0
45
45
0
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Data Setup Time
tAVEL
tELAX
tDVEH
tEHDX
tAS
tAH
tDS
tDH
tOES
Data Hold Time
0
0
Output Enable Setup Time
0
0
0
ns
ns
Output Enable Read
tOEH
Hold Time
Toggle and
Data Polling
10
Min
10
10
Read Recovery Time before
0
0
ns
tGHEL
tWLEL
tEHWH tWH
tGHEL
Write ( High to Low)
OE
CE
Min
Min
Min
Min
Typ
0
0
0
0
ns
ns
ns
ns
µs
tWS
SetupTime
Hold Time
W E
W E
35
20
7
45
20
7
tELEH
tEHEL
tCP
Write Pulse Width
Write Pulse Width High
tCPH
tWHWH1 tWHWH1
Programming Operation
(Byte AND word mode)
Max
Typ
Max
Typ
Max
Min
Min
200
0.3
5
200
0.3
5
µs
s
tWHWH2 tWHWH2
Sector Erase Operation
Chip Erase Operation
Vcc Setup Time
s
3
3
s
tWHWH3 tWHWH3
35
50
500
35
50
500
s
µs
ns
tVCS
tVIDR
Rise Time to V
ID
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
32
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Table 11. ERASE AND PROGRAMMING PERFORMANCE
Limits
Max
Parameter
Comments
Typ
Unit
Sector Erase Time
Chip Erase Time
0.2
8
sec
Excludes 00H programming prior
to erasure
3.5
7
35
sec
µs
Byte Programming Time
Word Programming Time
300
300
7
µs
Excludes system level overhead
Byte
8.2
4.1
24.5
12.2
Chip Programming
sec
Time
Word
Minimum 100K cycles
(preliminary)
Erase/Program Endurance
100K
cycles
Table 12. LATCH UP CHARACTERISTICS
Parameter Description
Min
Max
Input voltage with respect to Vss on all pins except I/O pins
-1.0 V
12.0 V
(including A9, Reset and
)
OE
Input voltage with respect to Vss on all I/O Pins
-1.0 V
Vcc + 1.0 V
100 mA
Vcc Current
-100 mA
Note : These are latch up characteristics and the device should never be put under
these conditions. Refer to Absolute Maximum ratings for the actual operating limits.
Table 14. 32-PIN TSOP PIN CAPACITANCE @ 25°C, 1.0MHz
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
C
IN
V
IN
Input Capacitance
6
7.5
pF
C
V
= 0
OUT
OUT
Output Capacitance
8.5
7.5
12
9
pF
pF
C
V
= 0
IN2
IN
Control Pin Capacitance
Table 15. DATA RETENTION
Parameter Description
Test Conditions
Min
Unit
150°C
10
Years
Years
Minimum Pattern Data Retention Time
125°C
20
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
33
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
AC CHARACTERISTICS
Figure 6. AC Waveforms for Chip/Sector Erase Operations Timings
Erase Command Sequence (last 2 cycles)
Read Status Data (last two cycles)
tWC
tAS
tAH
Addresses
CE#
0x2AA
SA
VA
VA
0x555 for chip
erase
tGHWL
tCH
OE#
tWP
WE#
tCS
tWPH
tWHWH2 or tWHWH3
Data
0x55
0x30
Status
DOUT
tDS
tDH
tBUSY
tRB
RY/BY#
VCC
tVCS
Notes:
1. SA=Sector Address (for sector erase), VA=Valid Address for reading status, Dout=true data at read address.
2. Vcc shown only to illustrate tvcs measurement references. It cannot occur as shown during a valid command
sequence.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
34
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Figure 7. Program Operation Timings
Program Command Sequence (last 2 cycles)
Program Command Sequence (last 2 cycles)
tWC
tAS
tAH
Addresses
CE#
0x555
PA
PA
PA
tGHWL
tWP
OE#
tCH
WE#
tWPH
tCS
tWHWH1
Data
OxA0
PD
Status
DOUT
tDS
tRB
tBUSY
tDH
RY/BY#
VCC
tVCS
Notes:
1. PA=Program Address, PD=Program Data, DOUT is the true data at the program address.
2. VCC shown in order to illustrate tVCS measurement references. It cannot occur as shown during a valid
command sequence.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
35
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Figure 8. AC Waveforms for /DATA Polling During Embedded Algorithm
Operations
tRC
VA
Addresses
CE#
VA
tACC
VA
tCH
tCE
tOE
OE#
tOEH
tDF
WE#
tOH
Comple-
ment
True
Complement
Status Data
Valid Data
Valid Data
DQ[7]
Status
Data
True
DQ[6:0]
tBUSY
RY/BY#
Notes:
1. VA=Valid Address for reading Data# Polling status data
2. This diagram shows the first status cycle after the command sequence, the last status read cycle and the array data read cycle.
Figure 9. AC Waveforms for Toggle Bit During Embedded Algorithm
Operations
tRC
Addresses
CE#
VA
VA
VA
VA
tACC
tCE
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
Valid Status
Valid Data
Valid Status
(first read)
Valid Status
DQ6, DQ2
RY/BY#
tBUSY
(second read)
(stops toggling)
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
36
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Figure 10. Alternate CE# Controlled Write Operation Timings
PA for Program
SA for Sector Erase
0x555 for Chip Erase
0x555 for Program
0x2AA for Erase
Addresses
VA
tWC
tAS
tAH
WE#
OE#
CE#
Data
tWH
tGHEL
tCP
tCPH
tCWHWH1 / tCWHWH2 / tCWHWH3
tWS
tBUSY
tDS
tDH
Status
DOUT
PD for Program
0x30 for Sector Erase
0x10 for Chip Erase
0xA0 for Program
0x55 for Erase
RY/BY#
tRH
Reset#
Notes:
PA = address of the memory location to be programmed.
PD = data to be programmed at byte address.
VA = Valid Address for reading program or erase status
Dout = array data read at VA
Shown above are the last two cycles of the program or erase command sequence and the last status read
cycle
Reset# shown to illustrate tRH measurement references. It cannot occur as shown during a valid command
sequence.
Figure 11. DQ2 vs. DQ6
Enter
Embedded
Erase
Enter Erase
Suspend
Program
Erase
Suspend
Erase
Resume
WE#
Erase
Enter
Suspend
Read
Enter
Suspend
Program
Erase
Suspend
Read
Erase
Complete
Erase
DQ6
DQ2
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
37
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Temporary Sector Unprotect
Speed Option
-70 -90
Unit
Parameter
Description
Std
tVIDR
tRSP
VID Rise and Fall Time
Min
Min
500
4
Ns
RESET# Setup Time for Temporary
Sector Unprotect
µs
Figure 13. Temporary Sector Unprotect Timing Diagram
VID
RESET#
0 or 3 V
0 or 3 V
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
38
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Figure 12. Sector Protect/Unprotect Timing Diagram
VID
Vcc
RESET#
0V
0V
tVIDR
tVIDR
SA,
A6,A1,A0
Valid
Valid
Valid
Data
60h
60h
40h
Status
Sector Protect/Unprotect
Verify
CE#
>0.4µS
WE#
>1µS
Sector Protect: 150 uS
Sector Unprotect: 15 mS
OE#
Notes:
Use standard microprocessor timings for this device for read and write cycles.
For Sector Protect, use A6=0, A1=1, A0=0. For Sector Unprotect, use A6=1, A1=1, A0=0.
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
39
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
FIGURE 12. TSOP
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
40
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
41
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
ABSOLUTE MAXIMUM RATINGS
Parameter
Value
Unit
Storage Temperature
-65 to +125
°C
Plastic Packages
-65 to +125
-55 to +125
°C
°C
Ambient Temperature
With Power Applied
Output Short Circuit Current1
200
MA
V
A9, OE#, Reset# 2
-0.5 to +11.5
Voltage with
Respect to Ground
All other pins 3
Vcc
-0.5 to Vcc+0.5
-0.5 to 4.0
V
V
Notes:
1.
2.
No more than one output shorted at a time. Duration of the short circuit should not be greater than one second.
Minimum DC input voltage on A9, OE#, RESET# pins is –0.5V. During voltage transitions, A9, OE#, RESET# pins may
undershoot Vss to –1.0V for periods of up to 50ns and to –2.0V for periods of up to 20ns. See figure below. Maximum DC
input voltage on A9, OE#, and RESET# is 11.5V which may overshoot to 12.5V for periods up to 20ns.
3.
4.
Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, inputs may undershoot Vss to –1.0V for periods
of up to 50ns and to –2.0 V for periods of up to 20ns. See figure below. Maximum DC voltage on output and I/O pins is Vcc
+
0.5 V. During voltage transitions, outputs may overshoot to Vcc + 1.5 V for periods up to 20ns. See figure below.
Stresses above the values so mentioned above may cause permanent damage to the device. These values are for a stress
rating only and do not imply that the device should be operated at conditions up to or above these values. Exposure of the
device to the maximum rating values for extended periods of time may adversely affect the device reliability.
RECOMMENDED OPERATING RANGES1
Parameter
Value
Unit
Ambient Operating Temperature
Commercial Devices
0 to 70
°C
Industrial Devices
-40 to 85
Regulated Voltage
Range: 3.0-3.6V
Operating Supply Voltage
Vcc
V
Full Voltage Range: 2.7 to
3.6V
1.
Recommended Operating Ranges define those limits between which the functionality of the device is guaranteed.
Vcc
+1.5V
Maximum Negative Overshoot
Maximum Positive Overshoot
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
42
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Waveform
Waveform
ORDERING INFORMATION
EN29LV160J
T
45
T
I
P
PACKAGING CONTENT
(Blank) = Conventional
P = Pb Free
TEMPERATURE RANGE
(Blank) = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
PACKAGE
T = 48-pin TSOP
S = Small Outline Package
SPEED
70 = 70ns
90 = 90ns
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
BASE PART NUMBER
EN = EON Silicon Devices
29LV = FLASH, 3V Read Program Erase
160J = 16 Megabit (2M x 8 / 1M x 16)
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
43
Rev 0.3 Release Date: 2002/01/30
EN29LV160J
Revisions List
0.1 (2001.07.03):
Preliminary version
0.2 (2001.07.05):
“block” changed to “sector”
LACTHUP >= 200mA line removed from first page
Chip erase and Sector Erase command descriptions modified.
DQ7,DQ5,DQ3 status polling descriptions modified.
Table 12 Latchup characteristics modified
Changed P/E endurance to 100K everywhere
Changed Absolute Maximum Ratings
Unlock Bypass stuff added
0.3 (2001.08.23):
On Table 7. DC Characteristics, changed:
“Vcc=2.7-3.6V +/- 10%” to “Vcc=2.7-3.6V”
VOH(TTL) Min “2.4” changed to “0.85 x Vcc”
Table 8: input/output levels changed in notes.
0.4 (2002.01.30):
Updated Device ID
Updated Device ID
Updated Operating Supply Voltage
Updated Ordering Information
4800 Great America Parkway, Suite 202
Santa Clara, CA 95054
Tel: 408-235-8680
Fax: 408-235-8685
44
Rev 0.3 Release Date: 2002/01/30
EN29LV160JT70TI 相关器件
型号 | 制造商 | 描述 | 价格 | 文档 |
EN29LV160JT70TIP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT70TP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90S | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90SI | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90SIP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90SP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90T | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90TI | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90TIP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 | |
EN29LV160JT90TP | ETC | 16 Megabit (2048K x 8-bit / 1024K x 16-bit) Flash Memory Boot Sector Flash Memory, CMOS 3.0 Volt-only | 获取价格 |
EN29LV160JT70TI 相关文章
- 2024-09-20
- 5
- 2024-09-20
- 8
- 2024-09-20
- 8
- 2024-09-20
- 6