EM641FT8FS-45S [ETC]
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM; 512K X16位低功耗和低电压全CMOS静态RAM
| 型号： | EM641FT8FS-45S |
| 厂家： | 
ETC |
| 描述： | 512K x16 bit Low Power and Low Voltage Full CMOS Static RAM |
| 文件： | 总11页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EM681FV16AU Series
Low Power, 512Kx16 SRAM
Document Title
512K x16 bit Low Power and Low Voltage Full CMOS Static RAM
Revision History2.1
Revision No.
History
Draft Date
Remark
0.0
Initial Draft
Oct. 26, 2006
Preliminary
Production code change from
EM681FV16U-45LL to
EM681FV16U-45LF
0.1
0.2
0.1 Revision
0.2 Revision
Jan. 18, 2007
April. 10, 2007
Production code change from
EM681FV16U-45LF to
EM681FV16AU-45LF
0.3
0.4
0.3 Revision
0.4 Revision
Product code table update
Fix typo error
June 15, 2007
Nov. 12, 2007
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea Zip Code : 690-719
Tel : +82-64-740-1712 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
The attached data sheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM681FV16AU Series
Low Power, 512Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
• Process Technology : 0.15µm Full CMOS
• Organization : 512K x 16 bit
• Power Supply Voltage : 2.7V ~ 3.6V
• Low Data Retention Voltage : 1.5V (Min.)
• Three state output and TTL Compatible
• Package Type : 44-TSOP2
The EM681FV16AU is fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The fami-
lies also supports low data retention voltage for battery
back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range Speed
PKG Type
Standby
(ISB1, Typ.)
Operating
(ICC1.Max)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
Industrial (-40 ~ 85oC)
EM681FV16AU-45LF
EM681FV16AU-55LF
EM681FV16AU-70LF
2.7V~3.6V
2.7V~3.6V
2.7V~3.6V
45ns
55ns
70ns
2 µA
2 µA
2 µA
4mA
4mA
4mA
44-TSOP2
44-TSOP2
44-TSOP2
PIN DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
VCC
VSS
Memory Array
2048 x 4096
Data
Cont
I/O0 ~ I/O7
I/O Circuit
Data
Cont
I/O8 ~ I/O15
Column Select
A11 A12 A13 A14 A15 A16
A
17 A18
44-TSOP2 : Top view
WE
OE
UB
LB
Control Logic
CS
Name
Function
Name
Function
CS
Chip select inputs
Vcc Power Supply
OE
Output Enable input
Write Enable input
Vss Ground
WE
UB Upper Byte (I/O8~15)
A0~A18 Address Inputs
LB Lower Byte (I/O0~7
NC No Connected
)
I/O0~I/O15 Data Inputs/outputs
2
EM681FV16AU Series
Low Power, 512Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Voltage on Any Pin Relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Symbol
Minimum
-0.2 to 4.0V
-0.2 to 4.0V
1.0
Unit
V
V , V
IN
OUT
V
V
CC
P
W
D
o
Operating Temperature
T
-40 to 85
A
C
* Stresses greater than those listed above “Absolute Maximum Ratings” may cause permanent damage to the device. Functional oper-
ation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
I/O
I/O
Mode
Power
0-7
8-15
H
X
L
L
L
L
L
L
L
X
X
H
L
X
X
H
H
H
H
L
X
H
X
L
X
H
X
H
L
High-Z
High-Z
High-Z
Data Out
High-Z
High-Z
High-Z
High-Z
High-Z
Deselected
Deselected
Stand by
Stand by
Active
Active
Active
Active
Active
Active
Active
Output Disabled
Lower Byte Read
L
H
L
Data Out Upper Byte Read
L
L
Data Out Data Out
Word Read
Lower Byte Write
Upper Byte Write
Word Write
X
X
X
L
H
L
Data In
High-Z
Data In
High-Z
Data In
Data In
L
H
L
L
L
Note: X means don’t care. (Must be low or high state)
3
EM681FV16AU Series
Low Power, 512Kx16 SRAM
1)
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply voltage
Ground
Symbol
Min
Typ
3.3
Max
3.6
0
Unit
V
V
2.7
0
CC
V
0
-
V
SS
2)
V
Input high voltage
Input low voltage
2.2
V
V
V
+ 0.2
IH
CC
3)
V
-
0.6
-0.2
IL
1. TA= -40 to 85oC, otherwise specified
2. Overshoot: VCC +2.0 V in case of pulse width < 20ns
3. Undershoot: -2.0 V in case of pulse width < 20ns
4. Overshoot and undershoot are sampled, not 100% tested.
1)
o
CAPACITANCE (f =1MHz, T =25 C)
A
Item
Input capacitance
Symbol
Test Condition
Min
Max
Unit
C
V =0V
-
8
pF
pF
IN
IO
IN
Input/Ouput capacitance
C
V =0V
-
10
IO
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ Max
Unit
ILI
VIN=VSS to VCC
Input leakage current
-1
-
-
-
1
1
2
uA
uA
CS=VIH or OE=VIH or WE=VIL or LB=UB=VIH
VIO=VSS to VCC
ILO
ICC
Output leakage current
Operating power supply
-1
-
IIO=0mA, CS=VIL, WE=VIH, VIN=VIH or VIL
mA
Cycle time=1µs, 100% duty, IIO=0mA,
ICC1
CS<0.2V, LB<0.2V or/and UB<0.2V,
-
-
-
-
4
mA
mA
V
IN<0.2V or VIN>VCC-0.2V
Average operating current
Cycle time = Min, IIO=0mA, 100% duty,
CS=VIL, LB=VIL or/and UB=VIL ,
VIN=VIL or VIH
45ns
55ns
70ns
45
35
25
ICC2
VOL
VOH
ISB
IOL = 2.1mA
Output low voltage
Output high voltage
Standby Current (TTL)
-
2.2
-
-
-
-
0.4
-
V
V
IOH = -1.0mA
CS=VIH, Other inputs=VIH or VIL
CS>VCC-0.2V
0.5
mA
Other inputs=0 ~ VCC
ISB1
Standby Current (CMOS)
LF
-
2
15
uA
o
(Typ. condition : VCC=3.3V @ 25 C)
o
(Max. condition : VCC=3.6V @ 85 C)
4
EM681FV16AU Series
Low Power, 512Kx16 SRAM
3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
VTM
2)
R1
Input Pulse Level : 0.4 to 2.4V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
1)
Output Load (See right) : CL = 100pF + 1 TTL (70nsec)
2)
R2
1)
1)
CL
CL = 30pF + 1 TTL (45ns/55ns)
1. Including scope and Jig capacitance
2. R =3070 ohm,
R =3150 ohm
2
1
3. V =2.8V
TM
4. CL = 5pF + 1 TTL (measurement with t , t , t
, t
, t
)
LZ HZ OLZ OHZ WHZ
o
o
READ CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
55ns
70ns
Symbol
Parameter
Unit
Min
Max
Min
Max
Min
Max
Read cycle time
tRC
tAA
45
-
55
-
70
-
ns
ns
ns
ns
ns
ns
Address access time
-
-
-
45
45
30
45
-
-
-
-
55
55
35
55
-
-
-
-
70
70
35
70
-
Chip select to output
tco
Output enable to valid output
UB, LB access time
tOE
tBA
Chip select to low-Z output
tLZ
5
5
5
tBLZ
tOLZ
tHZ
UB, LB enable to low-Z output
Output enable to low-Z output
5
5
-
-
5
5
-
-
5
5
-
-
ns
ns
ns
ns
ns
ns
Chip disable to high-Z output
0
20
20
20
-
0
20
20
20
-
0
25
25
25
-
tBHZ
tOHZ
tOH
0
0
0
UB, LB disable to how-Z output
Output disable to high-Z output
0
0
0
Output hold from address change
10
10
10
o
o
WRITE CYCLE (V =2.7 to 3.6V, Gnd = 0V, T = -40 C to +85 C)
cc
A
45ns
55ns
70ns
Unit
Symbol
Parameter
Write cycle time
Min
Max
Min
Max
Min
Max
tWC
tCW
tAs
45
-
55
-
70
-
ns
ns
ns
ns
Chip select to end of write
Address setup time
45
0
-
-
-
45
0
-
-
-
60
0
-
-
-
Address valid to end of write
tAW
tBW
tWP
tWR
tWHZ
tDW
tDH
45
45
60
UB, LB valid to end of write
Write pulse width
45
45
0
-
-
45
45
0
-
-
60
55
0
-
-
ns
ns
ns
ns
ns
ns
ns
Write recovery time
-
-
-
Write to ouput high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
0
20
0
20
0
25
25
0
30
0
30
0
-
-
-
-
-
tOW
5
5
5
5
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1). (Address Controlled, CS=OE=V , UB or/and LB=V
)
IL
IL
t
RC
Address
Data Out
t
AA
t
OH
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = V )
IH
t
RC
Address
t
AA
t
OH
t
CO
CS
t
HZ
t
t
BA
UB,LB
t
t
BHZ
OHZ
OE
OE
t
OLZ
High-Z
Data Out
Data Valid
t
t
BLZ
WHZ
t
LZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
6
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
t
WC
Address
CS
t
(2)
t
(4)
CW
WR
t
AW
t
BW
UB,LB
WE
t
(1)
WP
t
DH
t
(3)
t
AS
DW
High-Z
High-Z
Data in
Data Valid
t
WHZ
t
OW
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
t
WC
Address
tAS(3)
t
(2)
t
(4)
CW
WR
CS
t
AW
t
BW
UB,LB
t
(1)
WP
WE
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
7
EM681FV16AU Series
Low Power, 512Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
t
WC
Address
CS
t
(2)
t
(4)
CW
WR
t
AW
t
BW
UB,LB
WE
t
(3)
t
(1)
AS
WP
t
DH
t
DW
Data in
Data Valid
High-Z
High-Z
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end or write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EM681FV16AU Series
Low Power, 512Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
VCC for Data Retention
Symbol
VDR
Test Condition
Min
Typ
Max
Unit
ISB1 Test Condition
(Chip Disabled) 1)
1.5
-
3.6
V
VCC=1.5V, ISB1 Test Condition
(Chip Disabled) 1)
IDR
Data Retention Current
-
-
uA
ns
4
tSDR
tRDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
-
-
-
-
See data retention wave form
tRC
NOTES
1. See the I
measurement condition of data sheet page 4.
SB1
DATA RETENTION WAVE FORM
t
t
RDR
Data Retention Mode
SDR
V
cc
2.7V
2.2V
V
DR
CS > Vcc-0.2V
CS
GND
9
EM681FV16AU Series
Low Power, 512Kx16 SRAM
PACKAGE DIMENSION
44 - TSOP2 (0.8mm pin pitch)
10
EM681FV16AU Series
Low Power, 512Kx16 SRAM
SRAM PART CODING SYSTEM
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
2. Product Type
3. Density
11. Power
10. Speed
4. Function
9. Package
8. Generation
7. Organization
5. Technology
6. Operating Voltage
1. Memory Component
7. Organization
EM --------------------- Memory
8 ---------------------- x8 bit
16 ---------------------- x16 bit
2. Product Type
6 ------------------------ SRAM
8. Generation
Blank ----------------- 1st generation
A ----------------------- 2nd generation
B ----------------------- 3rd generation
C ----------------------- 4th generation
D ----------------------- 5th generation
E ----------------------- 6th generation
F ----------------------- 7th generation
G ---------------------- 8th generation
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
4. Function
0 ----------------------- Dual CS
1 ----------------------- Single CS
9. Package
2 ----------------------- Multiplexed
Blank ---------------- KGD, 48&36FpBGA
S ---------------------- 32 sTSOP1
T ---------------------- 32 TSOP1
U ---------------------- 44 TSOP2
V ---------------------- 32 SOP
3 ------------- Single CS / LBB, UBB(tBA=tOE)
4 ------------- Single CS / LBB, UBB(tBA=tCO)
5 ------------- Dual CS / LBB, UBB(tBA=tOE)
6 ------------- Dual CS / LBB, UBB(tBA=tCO)
5. Technology
10. Speed
F ------------------------- Full CMOS
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 ---------------------- 100ns
12 ---------------------- 120ns
6. Operating Voltage
T ------------------------- 5.0V
V ------------------------- 3.3V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free & Green)
L ---------------------- Low Power
S ---------------------- Standard Power
11
相关型号：
©2020 ICPDF网 联系我们和版权申明