DSP56858EVMUM_D [ETC]
DSP56858 Evaluation Module User＇s Manual ; DSP56858评估模块用户手册\n
| 型号： | DSP56858EVMUM_D |
| 厂家： | 
ETC |
| 描述： | DSP56858 Evaluation Module User＇s Manual
|
| 文件： | 总60页 (文件大小：815K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Order this document by
DSP56858EVMUM/D
Rev. 2.0, 10/07/2002
DSP56858 Evaluation Module
User’s Manual
© Motorola, Inc., 2002. All rights reserved.
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Table of Contents
Preface
Chapter 1
Introduction
1.1
1.2
1.3
DSP56858EVM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
DSP56858EVM Configuration Jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
DSP56858EVM Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2
Technical Summary
2.1
2.2
2.2.1
2.2.2
2.3
2.4
2.5
2.6
2.7
DSP56858 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Program and Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
SRAM Bank 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
SRAM Bank 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
SPI Serial EEPROM/Data FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
RS-232 Serial Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Debug LEDs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Debug Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
JTAG Connector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Parallel JTAG Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
2.8
2.8.1
2.8.2
2.9
2.10 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
2.11 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
2.12 Stereo Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
2.12.1
2.12.2
Analog Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
2.13 Daughter Card Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
2.13.1
2.13.2
Memory Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . . 2-18
Peripheral Daughter Card Expansion Connector . . . . . . . . . . . . . . . . . . . . . 2-19
2.14 USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
2.15 Host Interface Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2.16 Test Points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
MOTOROLA
Table of Contents
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Appendix A
DSP56858EVM Schematics
Appendix B
DSP56858EVM Bill of Material
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List of Figures
1-1
1-2
1-3
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
Block Diagram of the DSP56858EVM. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
DSP56858EVM Jumper Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Connecting the DSP56858EVM Cables . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Schematic Diagram of the External CS0 Memory Interface . . . . . . . . . . 2-3
Schematic Diagram of the External CS1/CS2 Memory Interface . . . . . . 2-4
SPI EEPROM Memory Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Schematic Diagram of the RS-232 Interface . . . . . . . . . . . . . . . . . . . . . . 2-6
Schematic Diagram of the Clock Interface. . . . . . . . . . . . . . . . . . . . . . . . 2-7
Schematic Diagram of the Debug LED Interface. . . . . . . . . . . . . . . . . . . 2-9
Block Diagram of the Parallel JTAG Interface. . . . . . . . . . . . . . . . . . . . 2-11
Schematic Diagram of the User Interrupt Interface . . . . . . . . . . . . . . . . 2-12
Schematic Diagram of the RESET Interface . . . . . . . . . . . . . . . . . . . . . 2-13
Schematic Diagram of the Power Supply . . . . . . . . . . . . . . . . . . . . . . . . 2-14
CODEC Analog Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
CS4218 Stereo Audio Codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Diagram of the USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
MOTOROLA
List of Figures
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iv
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List of Tables
1-1
DSP56858EVM Default Jumper Options. . . . . . . . . . . . . . . . . . . . . . . . . 1-3
SPI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
RS-232 Serial Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Operating Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
JTAG Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Parallel JTAG Interface Disable Jumper Selection. . . . . . . . . . . . . . . . . 2-10
Parallel JTAG Interface Connector Description. . . . . . . . . . . . . . . . . . . 2-11
Codec Sample Rate Selector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
ESSI Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
GPIO Port Connector Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Memory Daughter Card Connector Description. . . . . . . . . . . . . . . . . . . 2-18
Peripheral Daughter Card Connector Description . . . . . . . . . . . . . . . . . 2-19
Host Interface Connector Description. . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
MOTOROLA
List of Tables
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vi
DSP56858EVM User’s Manual
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Preface
This reference manual describes in detail the hardware on the DSP56858 Evaluation
Module.
Audience
This document is intended for application developers who are creating software for
devices using the Motorola DSP56858 part.
Organization
This manual is organized into two chapters and two appendixes.
• Chapter 1, Introduction - provides an overview of the EVM and its features.
• Chapter 2, Technical Summary - describes in detail the DSP56858 hardware.
• Appendix A, DSP56858EVM Schematics - contains the schematics of the
DSP56858EVM.
• Appendix B, DSP56858EVM Bill of Material - provides a list of the materials used on
the DSP56858EVM board.
Suggested Reading
More documentation on the DSP56858 and the DSP56858EVM kit may be found at URL:
http://www.mot.com/SPS/DSP/documentation/index.html
MOTOROLA
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Notation Conventions
This manual uses the following notational conventions:
Term or Value
Symbol
Examples
Exceptions
Active High Signals
(Logic One)
No special symbol
attached to the signal
name
A0
CLKO
Active Low Signals
(Logic Zero)
Noted with an
overbar in text and in
most figures
WE
OE
In schematic drawings,
Active Low Signals may be
noted by a backslash: /WE
Hexadecimal Values
Decimal Values
Begin with a “$” sym-
bol
$0FF0
$80
No special symbol
attached to the
number
10
34
Binary Values
Numbers
Begin with the letter
“b” attached to the
number
b1010
b0011
Considered positive
unless specifically
noted as a negative
value
5
-10
Voltage is often shown as
positive: +3.3V
Blue Text
Bold
Linkable on-line
...refer to Chapter 7,
License
Reference sources,
paths, emphasis
...see:
http://www.mot.com/S
PS/DSP...
Definitions, Acronyms, and Abbreviations
Definitions, acronyms and abbreviations for terms used in this document are defined
below for reference..
Codec
COder/DECoder; a part used to convert analog signals to digital (coder)
and digital signals to analog (decoder)
DIP
Dual Inline Package
DSP
Digital Signal Processor or Digital Signal Processing
Electrically Erasable Programmable Read-Only Memory
EEPROM
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EOnCE
Enhanced On-Chip Emulation; a debug bus and port created by Motorola
to enable a designer to create a low-cost hardware interface for a
professional quality debug environment
ESSI
EVM
GPIO
Enhanced Synchronous Serial Interface; a communications port on
Motorola’s family of DSPs
Evaluation Module; a hardware platform which allows a customer to
evaluate the silicon and develop his application.
General Purpose Input and Output port on Motorola’s family of DSPs;
does not share pin functionallity with any other peripheral on the chip
and can only be set as an input, output or level-sensitive interrupt input
HI
Host Interface; a communications port on Motorola’s family of DSPs
Integrated Circuit
IC
JTAG
LED
LQFP
MPIO
Joint Test Action Group; a bus protocol/interface used for test and debug
Light Emitting Diode
Low Profile Quad Flat Pack package
Multi Purpose Input and Output port on Motorola’s family of DSPs;
shares package pins with other peripherals on the chip and can function
as a GPIO
PCB
PLL
RAM
ROM
SCI
Printed Circuit Board
Phase Locked Loop
Random Access Memory
Read Only Memory
Serial Communications Interface; a communications port on Motorola’s
family of DSPs
SPI
Serial Peripheral Interface; a communications port on Motorola’s family
of DSPs
SRAM
SSI
Static Random Access Memory
Synchronous Serial Interface; a communications port on Motorola’s
family of DSPs
MOTOROLA
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THD
USB
WS
Total Harmonic Distortion
Universal Serial Bus
Wait State
References
The following sources were referenced to produce this manual:
[1] DSP56800E Reference Manual, DSP56800ERM/D
[2] DSP5685x 16-Bit Digital Signal Processor User’s Manual,
DSP5685xUM/AD
[3] DSP56858 16-Bit Digital Signal Processor Technical Data, DSP56858/D
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Chapter 1
Introduction
The DSP56858EVM is used to demonstrate the abilities of the DSP56858 and to provide a
hardware tool allowing the development of applications that use the DSP56858.
The DSP56858EVM is an evaluation module board that includes a DSP56858 part, 16-bit
stereo codec, USB 1.1/2.0 interface, external memory and a daughter card expansion
interface. The daughter card expansion connectors are for signal monitoring and user
feature expandability.
The DSP56858EVM is designed for the following purposes:
• Allowing new users to become familiar with the features of the 56800E
architecture. The tools and examples provided with the DSP56858EVM facilitate
evaluation of the feature set and the benefits of the family.
• Serving as a platform for real-time software development. The tool suite enables
the user to develop and simulate routines, download the software to on-chip or
on-board RAM, run it, and debug it using a debugger via the JTAG/Enhanced
OnCE (EOnCE) port. The breakpoint features of the EOnCE port enable the user
to easily specify complex break conditions and to execute user-developed software
at full speed until the break conditions are satisfied. The ability to examine and
modify all user-accessible registers, memory and peripherals through the EOnCE
port greatly facilitates the task of the developer.
• Serving as a platform for hardware development. The hardware platform enables
the user to connect external hardware peripherals. The on-board peripherals can be
disabled, providing the user with the ability to reassign any and all of the DSP's
peripherals. The EOnCE port's unobtrusive design means that all memory on the
board and on the DSP chip is available to the user.
1.1 DSP56858EVM Architecture
The DSP56858EVM facilitates the evaluation of various features present in the DSP56858
part. The DSP56858EVM can be used to develop real-time software and hardware
products based on the DSP56858. The DSP56858EVM provides the features necessary
MOTOROLA
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for a user to write and debug software, demonstrate the functionality of that software and
interface with the customer’s application-specific device(s). The DSP56858EVM is
flexible enough to allow a user to fully exploit the DSP56858’s features to optimize the
performance of his product, as shown in Figure 1-1.
DSP56858
RESET
LOGIC
SPI Data FLASH
1M-bit
SPI
RESET
IRQ Interface
IRQ
RS-232
Interface
MODE
LOGIC
DSub
9-Pin
MODE
SCI0
CS0
Address,
Data &
Control
(Program Memory)
128Kx16-bit SRAM
Peripheral
Daughter Card
Connector
CS1/CS2
(Data Memory)
128Kx16-bit SRAM
ESSI1
SCI1
Memory
Daughter Card
Connector
Stereo Line In
USB Interface
(CS3)
USB
Con
Stereo 16-bit
Codec
ESSI0
Stereo Line Out
Headphone Jack
Amp
JTAG
Connector
JTAG/EOnCE
GPIO
HI
Debug LEDs
Parallel
JTAG
Interface
DSub
25-Pin
Host Interface
Connector
4.00MHz
Crystal
Power Supply
+1.8V, +3.3V & +5.0V
+1.8V, +3.3V
& GND
XTAL/EXTAL
Figure 1-1. Block Diagram of the DSP56858EVM
1.2 DSP56858EVM Configuration Jumpers
Ten jumper groups, (JG1-JG11), shown in Figure 1-2, are used to configure various
features on the DSP56858EVM board. Table 1-1 describes the default jumper group
settings.
1-2
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DSP56858EVM Configuration Jumpers
4
2
8
7
2
1
JG8
JG10
JG11
JG1
JG9
1 3
JG5
5
1
6
2
P1
3
TB1
P2
JG2
JG6
J5
S1
JG5
JG9
JTAG
2
4
1
3
RESET
JG1
JG7
3
JG8
DSP56858EVM
RE10519B REV
J3
JG11
JG10
J2
1
U2
S2
IRQA
U1
U3
HEADPHONE
P6
S3
JG2
IRQB
J1
JG4
JG3
JG7
JG4
JG3
U7
1
9
2
J4
S4
1
JG6
S4
P4
P5
LEDS
U6
LINE
IN
LINE
OUT
10
3
1
Figure 1-2. DSP56858EVM Jumper Reference
Table 1-1. DSP56858EVM Default Jumper Options
Jumper
Group
Jumpers
Connections
Comment
JG1
JG2
JG3
JG4
JG5
JG6
Enable on-board Word selectable SRAM via CS0 (U2)
Enable on-board Byte selectable SRAM via CS1/CS2 (U3)
Use on-board EXTAL crystal input for DSP oscillator
Use on-board XTAL crystal input for DSP oscillator
Enable on-board Parallel JTAG Host/Target Interface
Enable ESSI0 Port for CODEC data
1–2
1-2, 3-4
2–3
1–2
NC
1-2, 3-4, 5-6, 7-8,
9-10
JG7
JG8
Enable GPIO for CODEC control
Enable SCI0 Port to RS-232 transceiver
Enable RS-232 output
1-2, 3-4, 5-6
1–2, 3-4
JG9
NC
1–2, 3–4, 5–6 & 7–8
1-2
JG10
JG11
Enable SPI Port to Serial EEPROM/Data FLASH
Enable USB interface via CS3
MOTOROLA
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1.3 DSP56858EVM Connections
An interconnection diagram is shown in Figure 1-3 for connecting the PC and the external
+12.0V DC/AC power supply or external +5.0V DC lab power supply to the
DSP56858EVM board.
Parallel Extension
Cable
DSP56858EVM
PC-compatible
Computer
P1
Connect cable
to Parallel/Printer port
P2 TB1
+5.0V
Lab
Supply
External
+12.0V
Power
with 2.1mm,
receptacle
connector
Figure 1-3. Connecting the DSP56858EVM Cables
Perform the following steps to connect the DSP56858EVM cables:
1. Connect the parallel extension cable to the Parallel port of the host computer.
2. Connect the other end of the parallel extension cable to P1, shown in Figure 1-3,
on the DSP56858EVM board. This provides the connection which allows the host
computer to control the board.
3. Make sure that the external +12.0V DC 1.2A switching power supply or the
external +5.0V DC 1A lab power supply is not plugged into a +120V AC power
source.
4. Connect the 2.1mm output power plug from the external switching power supply
into P2, shown in Figure 1-3, on the DSP56858EVM board. Optionally, attach an
external +5.0V DC lab power supply via the 2-pin terminal block, TB1.
5. Apply power to the external power supply. The green Power-On LED, LED7, will
illuminate when power is correctly applied.
1-4
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Chapter 2
Technical Summary
The DSP56858EVM is designed as a versatile Digital Signal Processor, (DSP),
development card for developing real-time software and hardware products to support a
new generation of applications in digital and wireless messaging, digital answering
machines, feature phones, modems, and digital cameras. The power of the 16-bit
DSP56858 DSP, combined with the on-board 128K × 16-bit external program/data static
RAM (SRAM), 128K × 16-bit external data/program SRAM, RS-232 interface, Stereo
16-bit codec interface, USB 2.0 interface, Daughter Card Expansion interface and parallel
JTAG interface, makes the DSP56858EVM ideal for developing and implementing many
audio and voice algorithms, as well as for learning the architecture and instruction set of
the DSP56858 processor.
The main features of the DSP56858EVM, with board and schematic reference designators
include:
• DSP56858 16-bit +1.8V/+3.3V Digital Signal Processor operating at 120MHz [U1]
• External fast static RAM (FSRAM) memory, configured as:
— 128K×16-bit of memory [U2] with one wait state at 120MHz via CS0
— 128K×16-bit of memory [U3] with one wait state at 120MHz via CS1/CS2
• 1M-bit Serial EEPROM/Data FLASH [U4]
• 4.00MHz crystal oscillator for DSP frequency generation [Y1]
• Optional external oscillator frequency input connectors [JG3 and JG4]
• Joint Test Action Group (JTAG) port interface connector for an external debug
Host Target Interface [J3]
• On-board Parallel JTAG Host Target Interface, with a connector for a PC printer
port cable [P1]
• RS-232 interface for easy connection to a host processor [U5 and P3]
• 16-bit stereo codec interface [U6, JG6, JG7, P4 and P5]
• Stereo headphone interface [U8 and P6]
• Codec sample rate selector [S5]
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• USB interface [U15and J5]
• Peripheral Daughter Card Expansion Connector, to allow the user to connect his
own SCI, ISSI, SPI or GPIO-compatible peripheral to the DSP [J2]
• Memory Daughter Card Expansion Connector, to allow the user to connect his own
memory or memory device to the DSP [J1]
• Host Interface Connector, for high-speed bus data transfer [J4]
• On-board power regulation from an external +12V DC-supplied power input [P2]
• On-board power regulation from an optional +5V DC-supplied power input [TB1]
• Light Emitting Diode (LED) power indicator [LED7]
• Six on-board real-time user debugging LEDs [LED1-6]
• Boot MODE selector [S4]
• Manual RESET push-button [S1]
• Manual interrupt push-button for IRQA [S2]
• Manual interrupt push-button for IRQB [S3]
2.1 DSP56858
The DSP56858EVM uses a Motorola DSP56858FV120 part, designated as U1 on the
board and in the schematics. This part will operate at a maximum speed of 120MHz. A full
description of the DSP56858, including functionality and user information, is provided in
these documents:
• DSP56858 Technical Data, (DSP56858/D): Provides features list and
specifications, including signal descriptions, DC power requirements, AC timing
requirements and available packaging
• DSP5685x User’s Manual, (DSP5685xUM/AD): Provides an overview description
of the DSP and detailed information about the on-chip components, including the
memory and I/O maps, peripheral functionality, and control/status register
descriptions for each subsystem
• DSP56800E Reference Manual, (DSP56800ERM/D): Provides a detailed
description of the core processor, including internal status and control registers and
a detailed description of the family instruction set
Refer to these documents for detailed information about chip functionality and operation.
They can be found on this URL:
http://www.motorola.com/semiconductors
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Program and Data Memory
2.2 Program and Data Memory
The DSP56858EVM contains two 128Kx16-bit Fast Static RAM banks. SRAM bank 0 is
controlled by CS0 and SRAM bank 1 is controlled by CS1 and CS2.
2.2.1 SRAM Bank 0
SRAM bank 0, which is controlled by CS0, uses a 128K×16-bit Fast Static RAM (GSI
GS72116, labelled U2) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-1. CS0 can be configured to use this memory bank as 16-bit program
memory, data memory, or both. Additionally, CS0 can be configured to assign this
memory’s size and starting address to any modulo address space.
This memory bank will operate with one wait state access while the DSP56858 is running
at 120MHz and can be disabled by removing the jumper at JG1.
GS72116
DSP56858
A0-A16
A0-A16
D0-D15
RD
DQ0-DQ15
OE
WR
WE
CS0
+3.3V
JG1
Jumper Pin 1-2:
Enable SRAM
Jumper Removed:
Disable SRAM
CE
Figure 2-1. Schematic Diagram of the External CS0 Memory Interface
2.2.2 SRAM Bank 1
SRAM bank 1, which is controlled by CS1 and CS2, uses a 128K×16-bit Fast Static RAM
(GSI GS72116, labelled U3) for external memory expansion; see the FSRAM schematic
diagram in Figure 2-2. Using CS1 and CS2, this memory bank can be configured as byte
(8-bit) or word (16-bit) accessable program memory, data memory, or both. Additionally,
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CS1 and CS2 can be configured to assign this memory’s size and starting address to any
modulo address space.
This memory bank will operate with one wait state access while the DSP56858 is running
at 120MHz and can be disabled by removing the jumpers at JG2.
GS72116
DSP56858
A0-A16
A0-A16
D0-D15
RD
DQ0-DQ15
OE
WR
WE
JG2
1
3
2
4
CS1
CS2
LB
HB
CE
Jumper Pin 1-2:
Enable SRAM Low Byte
Jumper Pin 3-4:
Enable SRAM High Byte
Figure 2-2. Schematic Diagram of the External CS1/CS2 Memory Interface
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SPI Serial EEPROM/Data FLASH Memory
2.3 SPI Serial EEPROM/Data FLASH Memory
A 1M-bit +3.3V SPI serial EEPROM/Data FLASH Memory, Atmel AT45DB011B-SC, is
provided on the DSP56858EVM, reference Figure 2-3. This memory connects directly to
the SPI Port through a header on the DSP56858. It can be used to load program code and
data into the DSP56858’s internal or external memory spaces. Jumper block JG10 is
provided to allow the user to disconnect the on-board SPI EEPROM/Data FLASH from
the SPI port and allow him to connect his own SPI port peripheral. The header details are
shown in Table 2-1.
Data FLASH Enable
(SPI Port Connector)
Serial EEPROM /
DSP56858
MOSI/SRFS
MISO/SRCK
Data FLASH
SDI
SDO
SCLK/STCK
SCK
CS
SS/STFS/PC3
JG10
Figure 2-3. SPI EEPROM Memory Block Diagram
.
Table 2-1. SPI Port Connector Description
JG10
Pin #
Signal
Pin #
Signal
1
3
5
7
SS/PF3
MISO/PF0
MOSI/PF1
SCK/PF2
2
4
6
8
CS
SDO
SDI
SCK
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2.4 RS-232 Serial Communications
The DSP56858EVM provides an RS-232 interface by the use of an RS-232 level
converter, (Maxim MAX3245EEAI, designated as U5). Refer to the RS-232 schematic
diagram in Figure 2-4. The RS-232 level converter transitions the SCI UART’s +3.3V
signal levels to RS-232-compatible signal levels and connects to the host’s serial port via
connector P3. Flow control is not provided, but could be implemented using uncommitted
GPIO signals. The pinout of connector P3 is listed in Table 2-2. The RS-232 level
converter/transceiver can be disabled by placing a jumper at JG9.
RS-232
Level Converter
DSP56858
Interface
P3
1
6
2
TXD0
RXD0
T1in
T1out
R1in
7
3
8
R1out
4
9
5
+3.3V
x
FORCEOFF
Jumper Removed:
JG9
Enable RS-232
1
2
Jumper Pin 1-2:
Disable RS-232
Figure 2-4. Schematic Diagram of the RS-232 Interface
.
Table 2-2. RS-232 Serial Connector Description
P3
Pin #
Signal
Pin #
Signal
1
2
3
4
5
Jumper to 6 & 4
TXD0
6
7
8
9
Jumper to 1 & 4
Jumper to 8
Jumper to 7
N/C
RXD0
Jumper to 1 & 6
GND
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Operating Mode
2.5 Clock Source
The DSP56858EVM uses a 4.00MHz crystal, Y1, connected to its external crystal inputs,
EXTAL and XTAL. To achieve its 120MHz maximum operating frequency, the
DSP56858 uses its internal PLL to multiply the input frequency by 30. An external
oscillator source can be connected to the DSP by using the oscillator bypass connectors,
JG3 and JG4; see Figure 2-5. If the input frequency is above 4MHz, then the EXTAL
input should be jumpered to ground by adding a jumper between JG4 pins 1 and 2. The
input frequency would then be injected on JG3’s pin 2. If the DSP needs to be
synchronized to the codec’s sample frequency, then the DSP’s input frequency should be
jumpered using the 12.2280MHz codec frequency. If the input frequency is below 4MHz,
then the input frequency can be injected on JG4’s pin 2.
EXTERNAL
OSCILLATOR
HEADERS
DSP56858
JG4
3
2
1
EXTAL
+1.65V
4.00MHz
JG3
1
2
3
XTAL
12.2880MHz
Figure 2-5. Schematic Diagram of the Clock Interface
2.6 Operating Mode
The DSP56858EVM provides a boot-up MODE selection switch, S4. This switch is used
to select the operating mode of the DSP as it exits RESET. Refer to the DSP56858 User’s
Manual for a complete description of the chip’s operating modes. Table 2-3 shows the
two operation modes available on the DSP56858.
Table 2-3. Operating Mode Selection
Operating Mode
S4 (ON)
Comment
0
1
2
3
1–2, 3-4 & 5-6
3-4 & 5-6
1-2 & 5-6
5-6
Bootstrap from External byte-wide memory
Bootstrap from SPI
Normal Expanded mode
Development Expanded mode
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Table 2-3. Operating Mode Selection
Operating Mode
S4 (ON)
Comment
4
5
1-2 & 3-4
3-4
Host Interface Port Single Strobe mode
Host Interface Port Dual Strobe mode
2.7 Debug LEDs
Six on-board Light-Emitting Diodes, (LEDs), are provided to allow real-time debugging
for user programs. These LEDs will allow the programmer to monitor program execution
without having to stop the program during debugging; refer to Figure 2-6.
Table 2-4describes the control of each LED.
Table 2-4. LED Control
Controlled by
User LED
LED1
Port
Signal
PD0
PD1
PD2
PD3
PD4
PD5
Port D
Port D
Port D
Port D
Port D
Port D
LED2
LED3
LED4
LED5
LED6
Setting PD0, PD1, PD2, PD3, PD4 or PD5 to a Logic One value will turn on the
associated LED.
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Debug Support
DSP56858
INVERTING BUFFER
+3.3V
RED LED
YELLOW LED
GREEN LED
RED LED
PD0
PD1
PD2
PD3
YELLOW LED
GREEN LED
PD4
PD5
Figure 2-6. Schematic Diagram of the Debug LED Interface
2.8 Debug Support
The DSP56858EVM provides an on-board Parallel JTAG Host Target Interface and a
JTAG interface connector for external Target Interface support. Two interface connectors
are provided to support each of these debugging approaches. These two connectors are
designated the JTAG connector and the Host Parallel Interface Connector.
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2.8.1 JTAG Connector
The JTAG connector on the DSP56858EVM allows the connection of an external Host
Target Interface for downloading programs and working with the DSP56858’s registers.
This connector is used to communicate with an external Host Target Interface which
passes information and data back and forth with a host processor running a debugger
program. Table 2-5 shows the pin-out for this connector.
Table 2-5. JTAG Connector Description
J3
Pin #
Signal
Pin #
Signal
1
3
TDI
TDO
TCK
2
4
GND
GND
GND
KEY
TMS
NC
5
6
7
NC
8
9
RESET
+3.3V
DE
10
12
14
11
13
TRST
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG5. Reference
Table 2-6 for this jumper’s selection options.
Table 2-6. Parallel JTAG Interface Disable Jumper Selection
JG5
Comment
No jumpers
On-board Parallel JTAG Interface Enabled
Disable on-board Parallel JTAG Interface
1–2
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Debug Support
2.8.2 Parallel JTAG Interface Connector
The Parallel JTAG Interface Connector, P1, allows the DSP56858 to communicate with a
Parallel Printer Port on a Windows PC; reference Figure 2-7. Using this connector, the
user can download programs and work with the DSP56858’s registers. Table 2-7 shows
the pin-out for this connector. When using the parallel JTAG interface, the jumper at JG5
should be removed, as shown in Table 2-6.
Parallel JTAG Interface
IN OUT
DB-25 Connector
DSP56858
TDI
TDO
TDI
OUT
IN
IN
TDO
P_TRST
TMS
OUT
TRST
IN OUT
IN OUT
TMS
TCK
TCK
P_RESET
P_DE
IN
IN
OUT
OUT
RESET
DE
+3.3V
EN
JG5
Jumper Removed:
Enable JTAG I/F
1
2
Jumper Pin 1-2:
Disable JTAG I/F
Figure 2-7. Block Diagram of the Parallel JTAG Interface
Table 2-7. Parallel JTAG Interface Connector Description
P1
Pin #
Signal
Pin #
Signal
1
2
3
4
5
6
7
NC
14
15
16
17
18
19
20
NC
PORT_IDENT
NC
PORT_RESET
PORT_TMS
PORT_TCK
PORT_TDI
PORT_TRST
PORT_DE
NC
GND
GND
GND
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Table 2-7. Parallel JTAG Interface Connector Description
P1
Pin #
Signal
Pin #
Signal
8
PORT_IDENT
PORT_VCC
NC
21
22
23
24
25
GND
GND
GND
GND
GND
9
10
11
12
13
PORT_TDO
NC
PORT_CONNECT
2.9 External Interrupts
Two on-board push-button switches are provided for external interrupt generation, as
shown in Figure 2-8. S1 allows the user to generate a hardware interrupt for signal line
IRQA. S2 allows the user to generate a hardware interrupt for signal line IRQB. These two
switches allow the user to generate interrupts for his user-specific programs.
+3.3V
DSP56858
10K
S2
IRQA
0.1µF
+3.3V
10K
S3
IRQB
0.1µF
Figure 2-8. Schematic Diagram of the User Interrupt Interface
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Reset
2.10 Reset
Logic is provided on the DSP56858 to generate an internal Power-On RESET. The
DSP56858EVM provides reset logic to support the RESET signals from the JTAG
connector, the Parallel JTAG Interface and the user RESET push-button; refer to
Figure 2-9.
JTAG_RESET
RESET
RESET
PUSHBUTTON
MANUAL RESET
TRST
JTAG_TAP_RESET
Figure 2-9. Schematic Diagram of the RESET Interface
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2.11 Power Supply
The main power input, +12.0V DC/AC, to the DSP56858EVM is through a 2.1mm coax
power jack. An optional +5.0V DC power supply input is available through a 2-pin
terminal block, TB1. A +12.0V DC 1.2A power supply is provided with the
DSP56858EVM; however, less than 500mA is required by the EVM. The remaining
current is available for user daughter card applications when connected to the daughter
card interface. The power regulation on the DSP56858EVM provides +5.0V DC voltage
regulation for the codec’s analog circuits and to the additonal voltage regulation logic on
the EVM. The additonal voltage regulation logic provides +1.8V DC voltage regulation
for the DSP’s core and +3.3V DC voltage regulation for the DSP’s I/O, memory, parallel
JTAG interface and supporting logic; refer to Figure 2-10. Power applied to the
DSP56858EVM is indicated with a Power-On LED, referenced as LED7.
P2
Power
Condition
+5.0V DC
Analog
+5.0V
Regulator
CODEC
+12.0V DC
TB1
+3.3V DC
+3.3V
Regulator
DSP56858
+5.0V DC
GND
DSP56858EVM
PARTS
DSP56858
CORE
+1.8V DC
+1.8V
Regulator
Figure 2-10. Schematic Diagram of the Power Supply
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Stereo Codec
2.12 Stereo Codec
A 16-bit audio-quality stereo codec, Crystal Semiconductor CS4218, is connected to the
DSP56858’s ESSI port to support audio, voice and signal analysis applications. The codec
is clocked with a 12.288MHz oscillator. This allows the codec to operate between a
sample frequency of 8KHz and 48KHz. The sample rate can be manually set by setting the
appropriate switch positions on DIP switch S5. The sample rate selections possible using
this three-position dip switch are detailed in Table 2-8. The codec supports +3.3V digital
levels, eliminating the need for voltage level translation circuitry. Additionally, a set of
zero ohm resistors are provided on the EVM to allow a user to disconnect the on-board
codec from the ESSI port and allow him to connect his own codec to the ESSI port; see
Figure 2-12. The on-board codec has analog signal conditioning logic, allowing direct
connection to its line-level input and line-level output signals through two 1/8” stereo
jacks; reference Figure 2-11.
Table 2-8. Codec Sample Rate Selector
SW 5
SW 5
SW 5
Position 3 Position 2 Position 3
Sample Rate
(MF6)
(MF7)
(MF8)
ON
ON
ON
ON
ON
OFF
ON
48.00KHz
32.00KHz
24.00KHz
19.20KHz
16.00KHz
12.00KHz
9.60KHz
ON
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
OFF
ON
OFF
ON
OFF
OFF
OFF
8.00KHz
2.12.1 Analog Input/Output
The DSP56858EVM uses jacks for line-level stereo input, line-level stereo output and
stereo headphone output. A National Semiconductor LM4880 provides the drive required
for the use of headphones. This device offers a THD, which is superior by a factor of two
to the CS4218’s on-chip headphone drive circuitry. The basic Analog codec connections
are shown in Figure 2-11.
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CS4218
P4
P5
P6
RIN1
LIN1
LOUTL
LOUTR
Line-Level
Input
Line-Level
Output
A
A
LM4880
Headphone
Output
A
Figure 2-11. CODEC Analog Connections
2.12.2 Digital Interface
The serial interface of the codec transfers digital audio data and control data into and out
of the device. The ESSI port consists of independent transmitter and receiver sections and
is used for serial communication with the codec.
On the DSP side, the Serial Transmit Data pin, STD0, is an output when data is being
transmitted to the codec. The Serial Receive Data pin, SRD0, is an input when data is
being received from the codec. These two pins are connected to the codec’s Serial Data
Input, SDIN, and Serial Data Output, SDOUT, pins.
The DSP’s Transmit Serial Clock pin, SCK0, provides the serial bit rate clock for the ESSI
interface. It is connected to the CODEC’s Serial Port Clock pin, SCLK. Data is
transmitted on the rising edge of SCLK and is received on the falling edge of SCLK.
The DSP’s GPIO PORT C Bit 4 pin, PC4, is programmed to control the codec’s Active
Low Reset signal, RESET.
The Serial Transmit Frame Sync pin, SC02, is programmed to control the codec’s Frame
Sync signal, FSYNC. This signal is sampled by SCLK, with a rising edge indicating a new
frame is about to start. The FSYNC frequency is always the system’s sample rate. It may
be an input to the codec, or it may be an output from the codec in data mode.
The basic codec digital connections are shown in Figure 2-12, Table 2-9 and Table 2-10.
The codec’s MODE is set by the three MODE selection resistors, R42-R44. In the factory
default setting of MODE 4, the codec is set to be the master of the ESSI bus with its data
word set at 32 bits per frame; i.e., 16 bits Left channel and 16 bits Right channel. The
sample rate is selected on the Sample Rate Selector switch S5; see Table 2-8 for selection
options. Codec control information is sent over a separate serial port using: PC3 as the
Control Chip Select signal, CCS; PE2 as the Control Data Input signal, CDIN; and PE3 as
the Control Clock signal, CCLK.
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Stereo Codec
CODEC Enable Logic
DSP56858
STD0
CS4218
SDIN
JG6
2
4
1
3
SRD0
SDOUT
6
8
SCLK
5
7
SCK0
SC02
FSYNC
10
PC4
9
RESET
JG7
PC3
CCS
2
1
CDIN
CCLK
PE2
PE3
4
6
3
5
Figure 2-12. CS4218 Stereo Audio Codec
.
Table 2-9. ESSI Port Connector Description
JG6
Pin #
DSP Signal
Pin #
Codec Signal
1
3
5
7
9
STD0
SRD0
SCK0
SC02
PC4
2
4
SDIN
SDOUT
SCLK
6
8
FSYNC
RESET
10
.
Table 2-10. GPIO Port Connector Description
JG7
Pin #
DSP Signal
Pin #
Codec Signal
1
3
5
PC3
PE2
PE3
2
4
6
CCS
CDIN
CCLK
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2.13 Daughter Card Connectors
The EVM board contains two daughter card expansion connectors. One connector, J1,
contains the DSP’s external memory bus signals. The other connector, J2, contains the
DSP’s peripheral port signals.
2.13.1 Memory Daughter Card Expansion Connector
The DSP’s external memory bus signals are connected to the Memory Daughter Card
Expansion connector, J1. Table 2-11 shows the port signal-to-pin assignments.
Table 2-11. Memory Daughter Card Connector Description
J1
Pin #
Signal
Pin #
Signal
1
A10
A9
2
A11
CS1
A15
A14
A19
A13
A12
D8
3
4
5
A8
6
7
A7
8
9
A20
WR
D0
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
D1
D2
D9
GND
D3
GND
D10
D11
D12
D13
A17
D14
D15
RD
D4
D5
D6
A18
D7
CS0
A0
A1
A6
A16
GND
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Daughter Card Connectors
J1
Pin #
Signal
Pin #
Signal
41
43
45
47
49
51
A2
A3
42
44
46
48
50
A5
A4
CS3
+3.3V
GND
+5.0V
CS2
+3.3V
GND
2.13.2 Peripheral Daughter Card Expansion Connector
The DSP’s peripheral port signals are connected to the Peripheral Daughter Card
Expansion connector, J2. Table 2-12 shows the port signal-to-pin assignments.
Table 2-12. Peripheral Daughter Card Connector Description
J2
Pin #
Signal
Pin #
Signal
1
CS0/PA0
CLKO
2
CS1/PA1
CS2/PA2
TIO1/PG1
RSTOUT
TIO3/PG3
NC
3
4
5
TIO0/PG0
CS3/PA3
TIO2/PG2
NC
6
7
8
9
10
12
14
16
18
20
22
24
26
28
30
11
13
15
17
19
21
23
25
27
29
GND
GND
SRD0/PC1
SC01/PC4
SCK/PF2
GND
SRD1/PD1
SC11/PD4
SCK1/PD2
GND
MOSI/PF1
MISO/PF0
GND
SC10/PD3
SC12/PD5
GND
SS/PF3
STD1/PD0
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Table 2-12. Peripheral Daughter Card Connector Description (Continued)
J2
Pin #
Signal
Pin #
Signal
31
33
35
37
39
41
43
45
47
49
51
SC00/PC3
SC02/PC5
RESET
GND
32
34
36
38
40
42
44
46
48
50
MODA/PH0
MODB/PH1
MODC/PH2
GND
STD0/PC0
SCK0/PC2
IRQB
RXD1/PE2
TXD1/PE3
RXD0/PE0
TXD0/PE1
+3.3V
IRQA
+3.3V
GND
GND
+5.0V
2.14 USB
A USB version 2.0 interface controller, NetChip NET2270, is connected to the
DSP56858’s external address/data bus via CS3. The NET2270 is clocked with a
30.00MHz crystal. This allows the NET2270 interface controller to support the USB Full
Speed (12 Mb/sec USB version 1.1) along with the USB High Speed (480 Mb/sec USB
version 2.0) bus transfer rates. The NET2270 provides a USB Tranceiver, Serial Interface
Engine, USB Protocol Controller, Endpoint FIFOs, Local Bus Interface and Configuration
Registers. Refer to the USB diagram in Figure 2-13. The USB Interface’s use of CS3 can
be disabled by removing the jumper at JG11.
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USB
USB Interface
DSP56858
D0-D15
LD0-LD15
LA0-LA4
IOR
J5
A0-A4
RD
DM
DP
2
3
WR
IOW
IRQ
USB
B-TYPE
IRQA
JG11
2
1
CS3
CS
Jumper Pin 1-2:
Enable USB
Jumper Removed:
Disable USB
Figure 2-13. Diagram of the USB Interface
MOTOROLA
Technical Summary
2-21
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2.15 Host Interface Connector
The DSP56858EVM board contains a Host Interface connector. The HI connector, J4,
provides the signals present on the DSP56858’s HI port. Table 2-13 shows the HI
connectors signal-to-pin assignments.
Table 2-13. Host Interface Connector Description
J4
Pin #
Signal
Pin #
Signal
1
3
HD0
HD2
2
HD1
HD3
4
5
HD4
6
HD5
7
HD6
8
HD7
9
HA0
10
12
14
16
18
20
HA1
11
13
15
17
19
HA2
HRW
HCS
HACK
GND
GND
HDS
HREQ
+3.3V
+3.3V
2.16 Test Points
The DSP56858EVM board has a total of seven test points. Three digital GND test points
are located in corners of the board. The +5.0VA and AGND test points are located in the
analog corner of the board. The +1.8V and +3.3V test points are located in the power
supply section of the board.
2-22
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Appendix A
DSP56858EVM Schematics
MOTOROLA
DSP56858EVM Schematics
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A-1
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A-2
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MOTOROLA
DSP56858EVM Schematics
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A-3
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A-4
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MOTOROLA
DSP56858EVM Schematics
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A-5
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A-6
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+
+
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A-7
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1
2
A-8
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MOTOROLA
DSP56858EVM Schematics
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A-9
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1
A-10
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3
4
3
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A-11
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1
1
1
1
A-12
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Appendix B
DSP56858EVM Bill of Material
Qty
Description
Ref. Designators
Vendor Part #
Integrated Circuits
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
DSP56858
U1
Motorola, DSP56858FV120
GSI, GS72116ATP-7
GS72116
U2, U3
AT45DB011
MAX3245
U4
Atmel, AT45DB011B-SC
U5
Maxim, MAX3245EEAI
CS4218
U6
Crystal Semiconductor, CS4218-KQ
Epson, SG-531P-12.288MC
National Semiconductor, LM4880M
ON Semiconductor, MC74LCX244ADW
Fairchild, 74AC00SC
12.288MHz OSC
LM4880
U7
U8
74LCX244
U9
74AC00
U10
74AC04
U11
ON Semiconductor, MC74AC04AD
ON Semiconductor, MC33269DT-5
ON Semiconductor, MC33269DT-3.3
ON Semiconductor, MC33269DT-ADJ
NetChip, NET2270
+5.0V Voltage Regulator
+3.3V Voltage Regulator
+1.8V Voltage Regulator
NET2270
U12
U13
U14
U15
U20
DS1818
Dallas Semiconductor, DS1818
Resistors
12
5
270 Ω
5.1K Ω
51 Ω
R1 - R5, R75 - R80, R83
R6, R10, R13, R14, R16
R7, R9
SMEC, RC73L2A270OHMJT
SMEC, RC73L2A5.1KOHMJT
SMEC, RC73L2A51OHMJT
SMEC, RC73L2A10MOHMJT
SMEC, RC73L2A47KOHMJT
2
1
10M Ω
47K Ω
R8
4
R11, R12, R15, R88
MOTOROLA
DSP56858EVM Bill of Material
B-1
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Qty
Description
5.62K Ω, 1%
Ref. Designators
Vendor Part #
4
R19, R20, R23, R25
SMEC, RC73L2A5.62KOHMFT
SMEC, RC73L2A10KOHMJT
29
10K Ω
R21, R22, R24, R26, R29-R31,
R34-R36, R38, R53-R60,
R64-R67, R71-R73, R90-R92
2
13
4
39.2K Ω, 1%
1K Ω
R27, R28
SMEC, RC73L2A39.2KOHMFT
SMEC, RC73L2A1KOHMJT
SMEC, RC73L2A20.0KOHMFT
SMEC, RC73JP2A
R32, R33, R45-R52, R61-R63
20.0K Ω, 1%
0 Ω
R37, R39-R41
R42, R43
R44
2
0
0 Ω
SMEC, RC73JP2A
0
10K Ω
R68
SMEC, RC73L2A10KOHMJT
SMEC, RC73L2A470KOHMJT
SMEC, RC73L2A243OHMFT
SMEC, RC73L2A107OHMFT
SMEC, RC73L2A35.7OHMFT
SMEC, RC73L2A1.5KOHMJT
SMEC, RC73L2A1MOHMJT
SMEC, RC73L2A9.09KOHMFT
3
470K Ω
243 Ω, 1%
107 Ω, 1%
35.7 Ω, 1%
1.5K Ω
R69, R70, R74
R81
1
1
R82
2
R84, R85
R86
1
1
1M Ω
R87
1
9.09K Ω, 1%
R89
Inductors
L1 - L4
4
5
1.0mH FERRITE BEAD
FERRITE BEAD
Panasonic, EXC-ELSA35V
TOKO, FLSM2520-1R0J
L5 - L9
LEDs
2
2
3
Red LED
LED1, LED4
LED2, LED5
LED3, LED6, LED7
Diode
Hewlett-Packard, HSMS-C650
Hewlett-Packard, HSMY-C650
Hewlett-Packard, HSMG-C650
Yellow LED
Green LED
1
1
S2B-FM401
D1
Vishay, DL4001DICT
DIODES, DF02S
+50V 1A BRIDGE RECT
D2
B-2
DSP56858EVM User’s Manual
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Qty
Description
Ref. Designators
Vendor Part #
Capacitors
2
2
9
2
3
8
0.33µF
C1, C6
C2, C4
SMEC, MCCE334K3NR-T1
SMEC, MCCE471J2NO-T1
SMEC, MCCE105K3NR-T1
SMEC, MCCE222K2NR-T1
SMEC, MCCE474K3NR-T1
ELMA, RV2-16V470M-R
470pF
1.0µF, +25V DC
0.0022µF
C3, C5, C14, C16, C18-C22
C7, C8
0.47µF
C9-C11
47µF, +16V DC
C12, C15, C17, C55, C57, C59,
C63, C69
25
0.1µF
C13, C23-C25, C27, C29, C31,
C33, C35, C37, C39, C41, C43,
C44, C46-C48, C50, C52, C54,
C56, C58, C67, C68, C72
SMEC, MCCE104K2NR-T1
18
0.01µF
C26, C28, C30, C32, C34, C36,
C38, C40, C42, C45, C49, C51,
C60, C64-C66, C70, C71
SMEC, MCCE103K2NR-T1
1
2
470µF, +16V DC
C53
ELMA, RV-16V471MH10R
SMEC, MCCE150J2NO-T1
15pF
C61, C62
Jumpers
4
2
2
1
1
1
1 × 2, 2mm Header
JG1, JG5, JG9, JG11
SAMTEC, TMM-102-02-S-S
SAMTEC, TMM-102-02-S-D
SAMTEC, TMM-103-02-S-S
SAMTEC, TMM-105-02-S-D
SAMTEC, TMM-103-02-S-D
SAMTEC, TMM-104-02-S-D
2 x 2, 2mm Header
3 × 1, 2mm Header
5 x 2, 2mm Header
3 x 2, 2mm Header
4 × 2, 2mm Header
JG2, JG8
JG3, JG4
JG6
JG7
JG10
Test Points
4
1
1
1
Black Test Point
Red Test Point
White Test Point
Yellow Test Point
TP1, TP3, TP6, TP7
Keystone, 5001
Keystone, 5000
Keystone, 5002
Keystone, 5004
TP2
TP4
TP5
MOTOROLA
DSP56858EVM Bill of Material
B-3
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Crystals
1
1
4.00MHz Crystal
30.00MHz Crystal
Y1
Y2
CTS, ATS04ASM-T
Epson, MA-306 30.000M-C2
Connectors
1
1
DB25M Connector
P1
P2
AMPHENOL, 617-C025P-AJ121
Switchcraft, RAPC-722
2.1mm coax
Power Connector
1
3
2
1
1
1
1
DE9S Connector
1/8” Stereo Jack
51-Pin HD Connector
7 x 2 Bergstick
P3
P4 - P6
J1, J2
AMPHENOL, 617-C009S-AJ120
Switchcraft, 35RAPC4BHN2
BERG, 91930-21151
J3
SAMTEC, TSW-107-07-S-D
SAMTEC, TSW-110-07-S-D-RT
Mill-Max, 897-30-004-90-000000
On-Shore Technology, ED500/2DS
10 x 2 RT Bergstick
Type B USB
J4
J5
2-Pin Terminal Block
TB1
Switches
S1 - S3
S4, S5
Transistors
Q1
3
2
SPST Pushbutton
3-Position DIP SW
Panasonic, EVQ-PAD05R
CTS, 209-3LPST
1
2N2222A
ZETEX, FMMT2222ACT
Miscellaneous
SH1 - SH20
RF1 - RF4
20
4
2mm Shunt
Rubber Feet
Samtec, 2SN-BK-G
3M, SJ5018BLKC
B-4
DSP56858EVM User’s Manual
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Index
ESSI ix
EVM ix
C
Clock Source 2-7
Codec viii
Connectors
F
FSRAM 2-3
G
Host Interface 2-22
D
GPIO ix
Daughter Card Connectors 2-18
Daughter Card Expansion interface 2-1
Debugging 2-8
H
DIP viii
DSP viii
DSP56858EVM
HI viii, ix
Host Parallel Interface Connector 2-9
Host Target Interface 2-9
+12.0V DC power supply 2-14
1 M-bit Serial EEPROM/Data FLASH 2-1
128Kx16-bit of memory 2-1
16-bit +1.8V/+3.3V Digital Signal Processor 2-1
16-bit stereo codec interface 2-1
4.00MHz crystal oscillator 2-1
Codec sample rate selector 2-1
connecting to the PC 1-4
default jumper options 1-3
Development Card 2-1
external oscillator frequency input 2-1
FSRAM 2-1
I
IC ix
J
JTAG ix, 1-1, 2-1
connector 2-10
Jumper Group
JG1 1-3
JG10 1-3
JG11 1-3
JG2 1-3
JG3 1-3
JG4 1-3
GPIO compatible peripheral 2-2
Host Interface Connector 2-2
interconnection diagram 1-4
ISSI compatible peripheral 2-2
JTAG port interface 2-1
JG5 1-3
JG6 1-3
jumper settings 1-3
JG7 1-3
JG8 1-3
JG9 1-3
Memory Daughter Caard Expansion Connector 2-2
On-board power regulation 2-2
Parallel JTAG Host Target Interface 2-1
power connection cable connection 1-4
real-time debugging 2-8
Jumper Options 1-3
jumper settings 1-3
RS-232 interface 2-1
L
SCI compatible peripheral 2-2
SPI compatible peripheral 2-2
test points 2-22
LED ix
LQFP ix
USB interface 2-2
M
E
MPIO ix
EEPROM viii
EOnCE ix
MOTOROLA
Index
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1
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O
Operating Mode 2-7
P
PCB ix
PLL ix
power supply, external 1-4
R
RAM ix
ROM ix
RS-232
interface 2-1, 2-6
level converter 2-6
schematic diagram 2-6
RS-232 Serial Communications 2-6
S
SCI ix
SPI ix
SRAM ix
external data 2-1
external program 2-1
SSI ix
stereo 16-bit codec interface 2-1
Stereo headphone interface 2-1
T
THD x
U
USB x, 2-20
schematic diagram 2-20
W
WS x
2
DSP56858EVM User’s Manual
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