DSP56100FM_技术文档

Freescale Semiconductor, Inc.

DSP56100

16-BIT

DIGITAL SIGNAL PROCESSOR

FAMILY MANUAL

Motorola, Inc.

Semiconductor Products Sector

DSP Division

6501 William Cannon Drive, West

Austin, Texas 78735-8598

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Order this document by DSP56100FM/AD

Motorola reserves the right to make changes without further notice to any products herein to im-

prove reliability, function or design. Motorola does not assume any liability arising out of the appli-

cation or use of any product or circuit described herein; neither does it convey any license under its

patent rights nor the rights of others. Motorola products are not authorized for use as components

in life support devices or systems intended for surgical implant into the body or intended to support

or sustain life. Buyer agrees to notify Motorola of any such intended end use whereupon Motorola

shall determine availability and suitability of its product or products for the use intended. Motorola

and M are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Employment Oppor-

tunity /Afﬁrmative Action Employer.

OnCEä is a trade mark of Motorola, Inc.

ã Motorola Inc., 1994

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 1

DSP56100 FAMILY INTRODUCTION

MOTOROLA

DSP56100 FAMILY INTRODUCTION

1 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

1.1

1.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3

DSP56100 FAMILY FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4

1 - 2

DSP56100 FAMILY INTRODUCTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

1.1

INTRODUCTION

The DSP56100 Family Manual (see Figure 1-1) provides a description of the components

that are common to all DSP56100 family processors and includes a detailed description

of the basic DSP56100 family instruction set. The DSP56156 User’s Manual and

DSP56166 User’s Manual provide a brief overview of the core processor and a detailed

descriptions of the memory and peripherals that are chip specific.

16-bit

Products

DSP56156

DSP56166

DSP561xx

DSP56100

Family Manuals

• architecture

• instructions

Family Manual

DSP56156

DSP56166

DSP561xx

Device Manuals

• peripherals

• memories

User’s Manual

# DSP56156UM/AD

# DSP56166UM/AD

# DSP561xxUM/AD

DSP56156

Technical Data

DSP56166

Technical Data

DSP561xx

Technical Data

Specifications

• electrical

• mechanical

# DSP56156/D

# DSP56166/D

# DSP561xx/D

Figure 1-1 DSP56100 Family Product Literature

A DSP561xx User’s Manual and a DSP561xx Technical Data Sheet will be available for

any future DSP56100 family member.

MOTOROLA

DSP56100 FAMILY INTRODUCTION

1 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 FAMILY FEATURES

1.2

DSP56100 FAMILY FEATURES

The DSP56100 family consists of programmable CMOS 16-bit Digital Signal Processor

core composed of a 16-bit arithmetic DATA ALU (DALU), Address Generation Unit

(AGU), Program Controller Unit (PCU), and their associated DSP instruction set.

Table 1-1 gives a description of the DSP Core features.

Table 1-1 DSP Core Feature List

• Up to 30 Million Instructions per Second (MIPS) at 60 MHz.– 33.3 ns instruction cycle

• Single-cycle 16 x 16-bit parallel multiply-accumulate

• 2 x 40-bit accumulators with extension byte

• Fractional and integer arithmetic with support for multiprecision arithmetic

• Highly parallel instruction set with unique DSP addressing modes

• Nested hardware DO loops including infinite loops

• Two instruction LMS adaptive filter loop

• Fast auto-return interrupts

• Three external interrupt request pins

• Three 16-bit internal data buses and three 16-bit internal address buses

• Programmable access time on the external bus

• On-chip peripheral registers memory mapped in data memory space

• Off-chip peripheral space with programmable access time memory mapped in data memory space

• Low power wait and stop modes

• On-Chip Emulation (OnCE) for unobtrusive, processor speed independent debugging

• Operating frequency down to DC

• Single power supply

• Low power (HCMOS)

The block diagram of the core processor used in the DSP56100 family is shown in Figure

1-2.

1- 4

DSP56100 FAMILY INTRODUCTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 FAMILY FEATURES

XAB1

XAB2

PAB

EXTERNAL

ADDRESS

BUS

ADDRESS

GENERATION

UNIT

SWITCH

ON-CHIP

PERIPHERALS

HOST, SSI0, SSI,

TIMER, PI/O,

DATA

RAM

BOOTSTRAP

ROM

PROGRAM

RAM

BUS

CONTROL

8

CODEC, ETC.

XDB

INTERNAL DATA

BUS SWITCH

AND BIT

MANIPULATION

UNIT

DATA

EXTERNAL

DATA BUS

SWITCH

PDB

GDB

EXTAL

SXFC

CLKO

PROGRAM CONTROL UNIT

CLOCK

AND PLL

PROGRAM

DECODE

PROGRAM

INTERRUPT

CONTROLLER

DATA ALU

ADDRESS

GENERATOR

16x16+40 - 40-BIT MAC

CONTROLLER

TWO 40-BIT ACCUMULATORS

OnCE

4

16 BITS

MODx/IRQx

RESET

HOST INTERFACE

NOT PART OF THE

CORE

Figure 1-2 DSP56100 Family Core CPU Block Diagram

The amount and type of on-chip memory varies from chip to chip within the family and so

is not discussed here. However, the architecture allows up to 64K words each (128k total)

of program memory and data memory to be addressed.

The peripherals and options that can be incorporated on-chip include:

• A Byte-wide Host Port

• Synchronous Serial Ports

• General Purpose I/O Pins

• Timer With External Access

• ∑∆ Codec

• On-chip Oscillator

• Interrupt Request Pins

Other peripherals will be designed for new DSP56100 Family members.

MOTOROLA

DSP56100 FAMILY INTRODUCTION

1 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 FAMILY FEATURES

1- 6

DSP56100 FAMILY INTRODUCTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 2

CPU ARCHITECTURE OVERVIEW

MOTOROLA

CPU ARCHITECTURE OVERVIEW

2 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

2.1

2.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

DSP56100 BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Data Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Address Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3

Internal Bus Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Bit Manipulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Data ALU (DALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

Address Generation Unit (AGU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4

X Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Bootstrap Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6

Program Control Unit (PCU) and System Stack (SS) . . . . . . . . . . . . . 2-6

External Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

2.2.10

2.2.11

2 - 2

CPU ARCHITECTURE OVERVIEW

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

2.1

INTRODUCTION

The heart of the DSP56100 architecture is a 16-bit multiple-bus processor designed spe-

cifically for real-time digital signal processing (DSP). The overall architecture is presented

and detailed block diagrams of the Data ALU and Address ALU architecture are de-

scribed.

2.2

DSP56100 BLOCK DIAGRAM

The major components of the CPU are:

• Data Buses

• Address Buses

• Data ALU

• Address ALU

• Program Control and System Stack

An overall block diagram of the CPU architecture is shown in Figure 2-1.

2.2.1 Data Buses

Data movement on the chip occurs over three bidirectional 16-bit buses: the X Data Bus

(XDB), the Program Data Bus (PDB), and the Global Data Bus (GDB). Data transfer be-

tween the Data ALU and the X Data Memory occurs over the XDB when one memory ac-

cess is performed, over the XDB and the GDB when two simultaneous memory reads are

performed. All other data transfers occur over the GDB. Instruction word pre-fetches take

place in parallel over the PDB. The bus structure supports general register to register, reg-

ister to memory, memory to register, and memory to memory data movement and can

transfer up to three 16-bit words in the same instruction cycle. Transfers between buses

are accomplished through the Internal Bus Switch.

As a general rule, when reading any 8-bit register, the unused bits in the most significant

byte are zero filled and any unused or reserved bits are read as zero.

2.2.2 Address Buses

Addresses are specified for internal X Data Memory on two unidirectional 16-bit buses, X

Address Bus One (XAB1) and X Address Bus Two (XAB2). Program memory addresses

are specified on the bidirectional Program Address Bus (PAB).

When external memory spaces have to be addressed, a single 16-bit unidirectional ad-

dress bus driven by a three input multiplexer can select: XAB1, XAB2, or the PAB. One

instruction cycle is needed for each external memory access. There is no speed penalty

if only one external memory space is accessed in an instruction and if no wait states are

MOTOROLA

CPU ARCHITECTURE OVERVIEW

2 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 BLOCK DIAGRAM

inserted in the external bus cycle. If two or three external memory spaces are accessed

in a single instruction, there will be a one or two instruction cycle execution delay, respec-

tively, or more if wait states are inserted on the external bus. A bus arbitrator controls ex-

ternal accesses, making it transparent to the user.

2.2.3 Internal Bus Switch

Transfers between buses are accomplished in the Internal Bus Switch. The internal bus

switch is similar to a switch matrix and can connect any two internal buses without adding

any pipeline delays.

2.2.4 Bit Manipulation Unit

The bit manipulation unit performs bit manipulation and bit field manipulation on memory

words and register data. It is capable of testing and/or changing a user selected set of bits

within a byte.

2.2.5 Data ALU (DALU)

The Data ALU performs all of the arithmetic and logical operations on data operands. The

Data ALU consists of four 16-bit input registers, two 32-bit accumulator registers, two 8-

bit accumulator extension registers, an accumulator shifter, an output shifter, one data

bus shifter/limiter, and a parallel single cycle non-pipelined Multiply-Accumulator (MAC)

unit. Data ALU registers may be read or written by the XDB and GDB as 16-bit operands.

The Data ALU is capable of multiplication, multiply-accumulate with positive or negative

accumulation, addition, subtraction, shifting, and logical operations in one instruction cy-

cle. Data ALU arithmetic operations generally use fractional 2’s complement arithmetic.

Some signed/unsigned and integer operations are also possible. Data ALU source oper-

ands may be 16, 32 or 40 bits and may originate from input registers and/or accumulators.

ALU results are always stored in one of the accumulators. The upper 16-bits of an accu-

mulator can be used as a multiplier input. Arithmetic operations always have a 40-bit re-

sult and logical operations are performed on 16-bit operands yielding 16-bit results in one

of the two accumulators. Refer to Section 3 for a detailed description of the Data ALU ar-

chitecture.

2.2.6 Address Generation Unit (AGU)

The AGU performs all address storage and effective address calculations necessary to

address data operands in memory. This unit operates in parallel with other chip resources

to minimize address generation overhead. The AGU can implement three types of arith-

metic: linear, modulo, and reverse carry. The Address ALU contains four Address Regis-

ters (R0-R3), four Offset Registers (N0-N3), and four Modifier Registers (M0-M3). The

2 - 4

CPU ARCHITECTURE OVERVIEW

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 BLOCK DIAGRAM

GDB

16

15

0

15

0

MR CCR

SR

PC

OMR

m0

m1

m2

n0

n1

n2

r0

r1

r2

15

31

15

0

ALU

LA

LC

m3

n3

r3

0

6

0

SP

ADDRESS GENERATION UNIT

SSH

SSL

control bus

OnCE

PROGRAM

CONTROL

UNIT

15

INT. DATA BUS SWITCH

AND BIT MANIPULATION

16

XAB1

XAB2

PAB

ON-CHIP

I/O

PERIPHERALS

ON-CHIP

I/O

PERIPHERALS

XDB

PDB

GDB

ON-CHIP

MEMORY

ON-CHIP

MEMORY

DATA

ALU

SHIFTER/LIMITER

COND. GEN.

X1 X0 Y1 Y0 A2 A1 A0

B2 B1 B0

8

MR

8

16 x 16 → 40 BIT

16

MAC ALU

16

Figure 2-1 Architecture of the 16-Bit DSP CPU

Address Registers are 16-bit registers which may contain address or data. Each Address

Register may be output to the PAB and XAB1. R3 may be accessed for output to XAB2

MOTOROLA

CPU ARCHITECTURE OVERVIEW

2 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 BLOCK DIAGRAM

when R0, R1, or R2 are output to XAB1. The modifier and offset registers are 16-bit reg-

isters which are normally used to control updating of the address registers. Offset regis-

ters can also be used as 16-bit data general purpose registers.

AGU registers may be read or written by the GDB as 16-bit operands. The AGU can gen-

two 16-bit addresses every instruction cycle: one for either the XAB1 or PAB and

erate

ALU can directly address 65536 locations on the XAB and 65536 lo-

one for XAB2. The

cations on the XAB2 bus - a total capability of 131,072 16-bit data words. Refer to Section

4 for a detailed description of the AGU architecture.

2.2.7 X Data Memory

The On-Chip X Data Memory addresses are received from the XAB1 and XAB2 and data

transfers occur on the XDB and GDB. Two reads or one write can be performed during

one instruction cycle on the internal data memory. The on-chip peripherals occupy the top

64 locations in the X data memory space (X:$FFC0-X:$FFFF). X memory may be expand-

ed off-chip for a total of 65,536 addressable locations.

2.2.8 Program Memory

The On-Chip Program Memory addresses are received from the program control logic

(usually the program counter) or from the address ALU on the PAB. The first 64 locations

of the program memory are reserved for interrupt vectors. The program memory may be

expanded off-chip for a total of 65,536 addressable locations.

2.2.9 Bootstrap Memory

A program bootstrap ROM is only read by the program controller while in the bootstrap

mode, during which, the on-chip program RAM is defined as write-only.

2.2.10 Program Control Unit (PCU) and System Stack (SS)

The Program Control Unit performs instruction prefetch, instruction decoding, hardware

loop control and exception processing. It contains six, 16-bit directly addressable regis-

ters. They are the:

1. Program Counter (PC),

2. Loop Address (LA),

3. Loop Count (LC),

4. Status Register (SR),

5. Operating Mode Register (OMR),

6. Stack Pointer (SP).

2 - 6

CPU ARCHITECTURE OVERVIEW

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 BLOCK DIAGRAM

The System Stack is a separate internal RAM 15 locations “deep” which stores the PC

and the SR for subroutine calls and long interrupts. The stack will also store the LC and

the LA in addition to the PC and SR registers for program looping.

2.2.11 External Bus Interface

A common address bus is used to access external Data Memory, Program Memory, or

I/O devices when required. Separate select lines control access to the memory spaces.

MOTOROLA

CPU ARCHITECTURE OVERVIEW

2 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 BLOCK DIAGRAM

2 - 8

CPU ARCHITECTURE OVERVIEW

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 3

DATA ALU

MOTOROLA

DATA ALU

3 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

3.1

3.1.1

3.1.2

3.1.3

3.1.3.1

3.1.3.2

3.1.3.3

3.1.3.4

3.1.4

3.1.5

3.1.6

3.1.6.1

3.1.6.2

3.2

3.2.1

3.2.2

3.2.3

3.2.4

OVERVIEW AND ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3

Data ALU Input Registers (X1, X0, Y1, Y0) . . . . . . . . . . . . . . . . . . . . 3-4

Data ALU Accumulator Registers (A2, A1, A0, B2, B1, B0) . . . . . . . . 3-4

Multiply-Accumulator (MAC) and Logic Unit . . . . . . . . . . . . . . . . . . . . 3-6

Multiply-Accumulator (MAC) Array and Logic unit . . . . . . . . . . . . . . . 3-7

ZB Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7

Multiplier Control Recoder (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Extension Adder (EXA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Accumulator Shifter (AS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8

Output Shifter (OS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Data Shifter/Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9

THE DATA ALU ARITHMETIC AND ROUNDING . . . . . . . . . . . . . . . 3-10

Data Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10

Fractional Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11

Integer Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12

Multiprecision Arithmetic Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14

Rounding Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Convergent Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15

Two’s Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18

3.2.5

3.2.5.1

3.2.5.2

3 - 2

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

3.1

OVERVIEW AND ARCHITECTURE

This Section describes the structure and the operation of the Data ALU registers and

hardware in addition to describing the data representation, rounding, and saturation

arithmetic used within the Data ALU.

The major components of the Data ALU are

•

Data ALU Input Registers

Data ALU Accumulator Registers

A parallel single cycle non-pipelined Multiply-Accumulator (MAC) Unit

An Accumulator Shifter (AS)

An Output Shifter (OS)

A Data Shifter/Limiter (S/L)

A block diagram of the Data ALU architecture is shown in Figure 3-1 and a functional

block diagram is shown in Figure 3-2.

GD(0:15)

XD(0:15)

S/L

SB(0:15)

L

CONDITION

GENERATOR

DXB2(0:15)

DXB1(0:15)

NON

MULTIPLY

CONTROL

LSP(0:15)

MSP(0:15)

EXT(0:7)

X1 X0

Y1 Y0

A2 A1

A0

B2 B1

B0

8

MR

EXA

(0:7)

8

MULTIPLY -

ACCUMULATOR

AND LOGIC

MSA(0:15)

LSA(0:15)

15

MUX

16

Figure 3-1 Data ALU Architecture Block Diagram

MOTOROLA

DATA ALU

3 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

3.1.1 Data ALU Input Registers (X1, X0, Y1, Y0)

X1, X0, Y1, and Y0 are 16-bit latches which serve as input registers for the data ALU.

Each register may be read or written by the XDB as well as the GDB. X0, X1, Y0, and Y1

may be read over the XDB. They may be treated as four independent 16-bit registers or

as two 32-bit registers called X and Y which are developed by concatenating X1:X0 and

Y1:Y0 respectively (where X1 and Y1 are the most significant words and X0 and Y0 are

the least significant words in X and Y respectively).

These Data ALU input registers are used as source operands for most data ALU opera-

tions and allow new operands to be loaded for the next instruction while the register con-

tents are used by the current instruction.

3.1.2 Data ALU Accumulator Registers (A2, A1, A0, B2, B1, B0)

A1, A0, B1 and B0 are 16-bit latches which serve as data ALU accumulator registers. A2

and B2 are 8-bit latches which serve as accumulator extension registers. Each register

may be read or written by the XDB as a word operand. A1 and B1 may be read or written

by the GDB. When A2 or B2 is read, the register contents occupy the low-order portion

(bits 7-0) of the word; the high-order portion (bits 16-8) is sign-extended. When A2 or B2

is written, the register receives the low-order portion of the word; the high-order portion is

not used.

The accumulator registers are treated as two 40-bit registers A (A2:A1:A0) and B

(B2:B1:B0) for data ALU operations. These accumulator registers receive the

EXT:MSP:LSP portion of the Multiply-Accumulator unit output and supply a source accu-

mulator of the same form. Most data ALU operations specify the 40-bit accumulator reg-

isters as source and/or destination operands

The accumulator registers are treated as two 40-bit registers A (A2:A1:A0) and B

operations. These accumulator registers receive the

(B2:B1:B0) for data ALU

output and supply a source accu-

EXT:MSP:LSP portion of the Multiply-Accumulator unit

mulator of the same form. Most data ALU operations specify the 40-bit accumulator reg-

isters as source and/or destination operands.

When one accumulator is used as a multiplier input, only the upper portion (A1 or B1)

can be specified. This upper portion can also be directly used as an address register for

fast effective address computation.

Automatic sign extension of the 40-bit accumulators is provided when the A or B register

is written with a smaller size operand. This can occur when writing A or B from the X data

bus or with the results of certain data ALU operations (such as Tcc or TFR). If a word

operand is to be written to an accumulator register (A or B), the MSP portion of the accu-

3 - 4

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

16 bits

G Data Bus

X Data Bus

Saturate

<<1;pass;>>1

16 bits

Saturate

Shifter/Limiter

A2 A1

B2 B1

A0

B0

X1

Y1

X0

Y0

16 bits

MAC UNIT

<<4;<<1;pass;>>1;>>4;>>16

Accumulator Shifter

&

40 bits

LOGIC UNIT

40 bits

Figure 3-2 Data ALU Functional Block Diagram

mulator is written with the word operand, the LSP portion is zeroed and the EXT portion

is sign-extended from MSP. No sign extension is performed if an individual 16-bit register

(A1, A0, B1, or B0) is written.

The extension registers A2 and B2 offer protection against 32-bit overflow. When the

result of an accumulation crosses the MSB of MSP (bit 15 of A1 or B1), the extension bit

of the status register (E bit) is set. Up to 255 overflows or underflows are possible using

this extension byte, after which the sign is lost beyond the MSB of the EXT register, set-

ting the overflow bit (V bit) in the status register.

It is also possible to saturate the accumulator on a 32-bit value automatically after every

accumulation. This is done by setting the saturation bit in the Operating Mode Register

(OMR). The highest dynamic range of the machine is limited to 32 bits then, and the lim-

iting bit (L bit) in the status register is set by the saturation.

MOTOROLA

DATA ALU

3 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

The detection of the overflow logic is also used to saturate an accumulator out of the

while reading A or B accumulators over the XDB or transferring

shifter/limiter register

of A or B is not affected in that case (except

them to any data ALU register. The content

when the same accumulator is specified as source and destination); only the value trans-

ferred over the XDB is limited to a full-scale positive or negative 16-bit value ($7FFF or

$8000), respectively. This overflow protection is performed after the contents of the

accumulator have been shifted according to the scaling mode defined in the status regis-

ter. When limiting occurs, the L bit flag in the status register is set and latched. Note that

only when an entire 40 bit accumulator register (A or B) is specified as the source for a

parallel data move over the XDB will shifting and limiting be performed. Shifting and lim-

iting are not performed when A0, A1, A2, B0, B1, or B2 are individually specified.

3.1.3 Multiply-Accumulator (MAC) and Logic Unit

The MAC and logic unit is the main arithmetic processing unit of the DSP and performs

all of the calculations on data operands. The MAC unit accepts up to three input oper-

ands and outputs one 40-bit result of the form Extension:Most Significant Product: Least

Significant Product (EXT:MSP:LSP). The operation of the MAC unit occurs indepen-

dently and in parallel with XDB, GDB, and PDB activity. The Data ALU registers provide

pipelining for both data ALU inputs and outputs. Latches are provided on the MAC unit

input to permit writing an input register which is the source for a Data ALU operation in

the same instruction. All ALU operations occur in one instruction cycle. The inputs of the

multiplier can come from the X and Y registers (X1, X0, Y1, Y0) as well as from the MSP

of each accumulator (A1, B1). The multiplier executes 16 x 16-bit parallel signed/

unsigned fractional and signed integer multiplies.

For fractional arithmetic, the 31-bit product is added to the 40-bit contents of either the A

or B accumulator. The 40-bit sum is stored back in the same accumulator. This multiply/

accumulate is a single cycle operation (no pipeline). Integer operations always generate

a 16-bit result located in the accumulator MSP portion (A1 or B1). Full precision integer

operations are possible using an ASR instruction after any fractional MPY or MAC.

If a multiply without accumulation is specified in the instruction, the MAC clears the accu-

mulator and then adds the contents to the product. The results of all arithmetic instruc-

tions are valid (sign extended and zero filled) 40-bit operands in the form EXT:MSP:LSP,

A2:A1:A0, or B2:B1:B0 (except during integer operations). When a 40-bit result is to be

stored as a 16-bit operand, the LSP can simply be truncated or it can be rounded into the

MSP. The rounding performed is either convergent rounding (Round to the nearest

even) or twos-complement rounding. The type of rounding is specified by the rounding

bit in the status register. The bit in the accumulator which is rounded is specified by the

scaling mode bits in the status register.

3 - 6

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

The major components of the MAC unit are

• Multiply-Accumulator Array

• ZB Multiplexer

• Multiplier Control Recoder

• Extension Adder

• Logic unit

3.1.3.1

Multiply-Accumulator (MAC) Array and Logic unit

The multiply-accumulator array is a 16 X 16-bit asynchronous, parallel multiply-accumu-

lator with 40-bit accumulation. The MAC array is based on the modified Booth’s algo-

rithm. The MAC array is used in all arithmetic operations. The array performs signed and

unsigned arithmetic with a fractional data representation and signed arithmetic with an

integer data representation. The MAC array also performs rounding if specified in the

DSP instruction. The type of rounding is specified by the scaling mode bits and the

rounding bit in the status register.

Three input operands are received on six internal data buses AS2, AS1, AS0, EB, ZB,

and MB. The AS2:AS1:AS0 data bus is the 40-bit source accumulator bus and repre-

sents the EXT:MSP:LSP portion of the source accumulator. The AS2:AS1:AS0 bus is

the output of the accumulator shifter. The ZB data bus is a 16-bit input operand used in

most data ALU operations and represents the multiplicand in multiplication operations.

The MB data bus is a 16-bit input operand which represents the multiplier in multiplica-

tion operations. The ZB and MB buses are concatenated (ZB:MB) to form a 32-bit input

bus for long word operands. The EB bus is concatenated with the ZB and MB buses

(EB:ZB:MB) to form a 40-bit input bus for addition or subtraction of the two full accumula-

tors.

The logic unit in the MAC array performs the logical operations AND, OR, EOR, and

NOT on data ALU registers. The logic unit is 16 bits wide and operates on data in the

MSP portion of the accumulator. The LSP and EXT portions of the accumulator are not

affected.

3.1.3.2

ZB Multiplexer

The ZB Multiplexer sign extends, by one bit, the data coming into the MAC over the ZB

bus. This sign bit can be cleared by the ZB Multiplexer to obtain an unsigned format for

these operands. The ZB Multiplexer may also invert data coming into the MAC as

required.

MOTOROLA

DATA ALU

3 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

3.1.3.3

Multiplier Control Recoder (REC)

The multiplier control recoder directs the operation of the MAC array and performs multi-

plier operand recoding for the modified Booth’s algorithm multiplication. The MB bus is

the input to the multiplier control recoder. Data-independent multiplier control line gener-

ation is performed in the REC for most non-multiplication instructions. For example, the

multiplier control output for a data ALU addition would be a multiplication by +1 opera-

tion. For other data ALU operations, the multiplier control recoder generates control line

constants that do not correspond to a valid multiplier control word. The least significant

recoder outputs a zero control word and the most significant recoder provides all the

functions in these cases.

3.1.3.4

Extension Adder (EXA)

EXA is an 8-bit adder which serves as an extension accumulator for the MAC array. The

primary source operand is the AS2 internal data bus from the accumulator shifter. For

multiply-accumulate operations, the second source operand is an update constant gen-

erated from the carry and overflow outputs of the MAC array. For 40-bit additions or sub-

tractions, the EB internal data bus is used as the second source operand. This allows the

two accumulators to be added and subtracted from each other. The extension adder out-

put is the EXT portion of the MAC unit output and is the sum of the source operands.

3.1.4 Accumulator Shifter (AS)

The accumulator shifter is an asynchronous parallel shifter with a 40-bit input and a 40-

bit output. The source accumulator shifting operations are:

1. No Shift (Unmodified)

2. 1-Bit Left Shift (Arithmetic) ASL

3. 1-Bit Right Shift (Arithmetic) ASR

4. 4-Bit Right Shift (Arithmetic) ASR4

5. 4-Bit Left Shift (Arithmetic) ASL4

6. 16-Bit Right Shift (Arithmetic) ASR16

7. Force to zero

The shifter also performs a 15-bit arithmetic shift to the right during integer multiply-accu-

mulate (IMAC) instructions. The shifter is implemented immediately before MAC accu-

mulator input. The accumulator shifter output can be inverted or forced to zero and

linkages are provided to shift into and out of the condition code carry (C) bit. The accu-

mulator shifter outputs to the AS2, AS1, and AS0 buses in the internal ALU.

3 - 8

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OVERVIEW AND ARCHITECTURE

3.1.5 Output Shifter (OS)

The Output shifter is an asynchronous parallel shifter with 40-bit input and a 40-bit out-

put. This shifter operates a 15-bit left shift on the result of the integer operations IMPY/

IMAC before storing the shifters result into an accumulator. The shifted result is then

available in the A1 or B1 MSP for other arithmetic or logical operations.

3.1.6 Data Shifter/Limiter

The data shifter/limiter provides special post processing on data ALU accumulator regis-

ters when they are read out to the XDB or to other registers. It consists of a shifter fol-

lowed by a limiting circuit.

3.1.6.1

Scaling

The data shifter is capable of shifting data one bit to the left or right as well as passing

the data unshifted. It has a 16-bit output and a limiting output indicator. The data shifter is

controlled by the scaling mode bits in the status register. These mode bits permit

dynamic scaling of fixed point data using the same program code which permits block

floating point algorithms to be implemented in a regular fashion. FFT routines would typ-

ically use this feature to selectively scale each butterfly pass.

3.1.6.2

Limiting

Saturation arithmetic is provided to selectively limit overflow when reading a data ALU

accumulator register. Limiting is performed on the data shifter output. If the contents of

the selected source accumulator can be represented in the destination operand size

without overflow, the data limiter is disabled and the operand is not modified. If the con-

tents of the selected source accumulator cannot be represented without overflow in the

destination operand size, the data limiter will substitute a “limited” data value having

maximum magnitude and the same sign as the source accumulator. The value of the

accumulator is not changed. The limited data values are shown in Table 3-1

Table 3-1 Saturation by the Shifter/limiter

E bit

MSB of A2/B2

Output of the limiter

unchanged

$7FFF

0

1

x

0

1

$8000

The E bit is the extension bit of the status register (SR) which is defined Section 5.3.6.

Note that during the TFR2 instruction, the limiting is performed on 32 bits when the accu-

mulator is written to a register.

MOTOROLA

DATA ALU

3 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

3.2

THE DATA ALU ARITHMETIC AND ROUNDING

The DSP56100 family supports the two’s-complement representation of binary numbers.

In this format, the sign bit is the MSB of the binary word, which is set to zero for positive

numbers and set to one for negative numbers. Unsigned numbers are only supported by

instructions dedicated to multiple precision.

3.2.1 Data Representation

Three modes of format adjustments are supported by the 16-bit DSP:

1. Two’s complement fractional. In this format, the N bit operand is represented

using the 1.[N-1] format (1 signed bit, N-1 fractional bits). Such a format can

-[N-1]

represent numbers between -1 and +1-2

2. Unsigned fractional. Unsigned binary numbers may be thought of as positive

only. The unsigned numbers have nearly twice the magnitude of a signed number

of the same length. An unsigned fraction, D, is a number whose magnitude

satisfies the inequality:

0.0 ≤ D < 2.0

Examples of unsigned fractional numbers are 0.25, 1.25, and 1.999. The binary

word is interpreted as having a binary point after the most significant bit (MSB).

[N-1]

-

The most positive number is $FFFF or {1.0 + (1 - 2

N=16 bits). The smallest positive number is zero ($0000).

)} = 1.99996948 (for

3. Two’s complement integer. This format is used by two instructions, the integer

multiply and multiply-accumulate (IMPY/IMAC). Using this format, the N-bit

operand is represented using the N.0 format (N integer bits). Such a format can

-[N-1]

[N-1]

represent numbers between -2

and [2

-1].

The operand is written to the most significant accumulator register (A1 or B1) and its

most significant bit is automatically sign extended through the accumulator extension

register to maintain alignments of the binary point when a word operand is written to A or

B. The least significant accumulator register is automatically cleared. See Figure 3-3 for

more details on bit weighting and operand alignments

3 - 10

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

.

0

-15

-2

2

16-bit word operand

X0,X1,Y0,Y1,A1,B1

-15 -16

2

-31

-2

2

32-bit long word

operand

-16

-31

8

0

-15

2

-2

2

40-bit word operand

A,B

Fractional 2’s Complement Representation

15 14

2

0

-2

2

16-bit word operand

X0,X1,Y0,Y1,A1,B1

15

0

-2

16-bit word result

in A1,B1

unused

Integer 2’s Complement Representation

Figure 3-3

Bit Weighting and Alignments for Operands in

Fractional and Integer Representation

3.2.2 Fractional Arithmetic

Figure 3-4 shows the Multiply-Accumulation implementation for fractional arithmetic. The

multiplication of two 16-bit signed fractional operands gives a 32-bit signed fractional

intermediate result with the LSB always set to zero. This intermediate result is added to

one of the 40-bit accumulators. If rounding is specified in the MPY or MAC instruction

(MACR or MPYR), the intermediate result will be rounded to 16 bits before being stored

back to the destination accumulator

MOTOROLA

DATA ALU

3 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

.

Input Operand 1

Input Operand 2

Signed Fractional

Input Operands

s

16 bits

Signed

Intermediate

Multiplier Result

s s

0

31 bits

Signed Fractional

Mac Output

EXP

MSP

LSP

40 bits

Figure 3-4 Fractional Arithmetic

3.2.3 Integer Arithmetic

Figure 3-5 shows the Multiply and Multiply-Accumulate operations for integer arithmetic

and Figure 3-6 describes the implementation of the Integer Multiply-Accumulate. The

multiplication/multiply-accumulate of two 16-bit signed integer operands (IMPY/IMAC)

gives a 16-bit signed integer result in the MSP (A1 or B1). EXT (A2 or B2) is sign

extended and the LSP (A0 or B0) is unchanged. Since A0 and B0 remain unchanged by

integer arithmetic instructions, these two registers can be used as two additional data

ALU registers when using IMAC, IMPY, INC24, DEC24, CLR24, SWAP, and EXT

instructions. Full precision 40-bit integer operations are possible using a fractional MPY

or a series of MACs followed by an ASR instruction.

CAUTION

Overflow control and rounding are not performed during inte-

ger multiplication and integer multiply-accumulate.

Integer arithmetic is optimized for new address generation using the multiplier. For

example, when an address register Rn has to be updated to Rn + x0*y0 before fetching

new data from memory, the following sequence of code can be used:

move

imac

move

Rn,a

x0,y0,a

x:(a1),b

;a=Rn

;a1=Rn+x0*y0

;b1=X:<Rn+x0*y0>

3 - 12

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

Input Operand 1

Input Operand 2

Signed Integer

Input Operands

s

16 bits

Signed

Intermediate

Multiplier Result

0

31 bits

S Ext.

EXP

Signed Integer

Output

unchanged

MSP

16 bits

Figure 3-5 Integer Arithmetic (IMPY/IMAC)

16.0

S. ext.

16.

0

Multiply

>>15

Accumulator Shifter

=

31.1

39.1

Accumulate

=

39.1

<<15

Output Shifter

Figure 3-6 IMAC Implementation

MOTOROLA

DATA ALU

3 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

3.2.4 Multiprecision Arithmetic Support

A set of data ALU operations is provided in order to facilitate multi-precision multiplica-

tions. When these instructions are used, the multiplier accepts some combinations of

signed twos-complement format and unsigned format. These instructions are:

1. MPY/MAC su: multiplication and multiply-accumulate with signed times

unsigned operands

2. MPY/MAC uu: multiplication and multiply-accumulate with unsigned times

unsigned operands

3. DMACss:

4. DMACsu:

5. DMACuu:

multiplication with signed times signed operands and 16-bit

arithmetic right shift of the accumulator before accumulation

multiplication with signed times unsigned operands and 16-bit

arithmetic right shift of the accumulator before accumulation

multiplication with unsigned times unsigned operands and 16-

bit arithmetic right shift of the accumulator before accumulation

Figure 3-7 shows how the DMAC instruction is implemented inside the Data ALU and

Figure 3-8 illustrates the use of these instructions in the case of a double precision multi-

plication. The signed x signed operation is used to multiply or multiply-accumulate the

two upper, signed, portions of two signed double precision numbers. The unsigned x

signed operation is used to multiply or multiply-accumulate the upper, signed, portion of

one double precision number with the lower, unsigned, portion of the other double preci-

sion number. The unsigned x unsigned operation is used to multiply or multiply-accumu-

late the lower, unsigned, portion of one double precision number with the lower,

unsigned, portion of the other double precision number.

3 - 14

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

1.15

9.31

Multiply

>>16

Accumulator Shifter

=

1.31

25.15

+

Accumulate

=

9.31

Figure 3-7 DMAC Implementation

3.2.5

Rounding Modes

The DSP56100 family implements two types of rounding: convergent rounding and two’s

complement rounding. The type of rounding is selected by the OMR rounding bit (R bit).

3.2.5.1

Convergent Rounding

This is the default rounding mode. Convergent rounding is also called round-to-nearest

even number. It prevents the introduction of a bias normally produced by rounding down

if the number is odd (LSB=1) and rounding up if the number is even (LSB=0). Figure 3-9

shows the four possible cases for rounding a number in the A1 or B1 register. If the Least

Significant Portion (LSP) of a number is less than half ($<8000) of the bit to be rounded

(LSB), the number is rounded down and if the LSP of the number is greater than half of

the LSB (>$8000) the number is rounded up. If the LSP is exactly equal to half of the

LSB ($8000) and the LSB of the MSP is odd, the number is rounded up whereas if the

LSB of the MSP is even, the number is rounded down i.e., truncated. This technique

eliminates the bias in truncation rounding.

Block diagrams of the rounding implementations for the cases of no scaling, scaling

down and scaling up are shown in Figure 3-9, Figure 3-10, and Figure 3-11, respectively.

Scaling modes require that the zero detect hardware and LSB Even gate have one of

three forms since the LSB moves with the scaling mode.

MOTOROLA

DATA ALU

3 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

32 bits

XH

X1

XL

X0

X

YH

Y1

YL

Y0

=

Unsigned X Unsigned

mpyuu

move

x0,y0,a

a0,b0

XL x YL

Signed X Unsigned

+

dmacsu

x1,y0,a

XH x YL

YH x XL

macsu

move

dmacss

y1,x0,a

a0,b1

x1,y1,a

+

Signed X Signed

XH x YH

S Ext

B1

A2

A1

A0

B0

64 bits

Figure 3-8 Double Precision Multiplication

3 - 16

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

CASE I: A0<0.5 (<$8000), then round down (add zero and A1)

Before Rounding

After Rounding

A1

XX..X XX...XX0100 0000...0000

A2

A1

A0

A2

A0

XX..X XX...XX0100 011XXX...XX

39 31 15

0

39

31

15

0

CASE II: A0>0.5 (>$8000), then round up (add 1 to A1)

Before Rounding

After Rounding

A2

XX..X XX...XX0100 1110XX...XX

39 31 15

A1

A0

A2

A1

A0

XX..X XX...XX0101 0000...0000

39 31 15

0

CASE III: A0=0.5 (=$8000) and LSB of A1=0 (even), then round down (add zero to A1)

Before Rounding

After Rounding

A2

A1

A0

A2

A1

A0

XX..X XX...XX0100 1000...0000

39 31 15

XX..X XX...XX0100 0000...0000

39 31 15

0

CASE IV: A0=0.5 (=$8000) and LSB of A1=1(odd), then round up (add 1 to A1)

Before Rounding

After Rounding

A2

A1

A0

A2

A1

A0

XX..X XX...XX0101 1000...0000

39 31 15

XX..X XX...XX0110 0000...0000

0

39

31

15

0

Figure 3-9 Convergent Rounding

MOTOROLA

DATA ALU

3 - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

.

Accumulator

XXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

00000000 0000000000000000 1000000000000000

Add Rounding

Constant

Zero

Detect

LSB even

0

Force LSP to zero

Figure 3-10 Convergent Rounding Implementation – No Scaling

Accumulator

XXXXXXXX XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX

00000000 00000000000000 10000000000000000

Add Rounding

Constant

Zero

Detect

LSB even

0

Force LSP to zero

Figure 3-11 Convergent Rounding Implementation – Scale Down

Two’s Complement Rounding

3.2.5.2

When twos-complement rounding is selected by setting the rounding bit in the OMR, one

is added to the bit to the right of the rounding point (bit 15 of A0 when no-scaling; bit 0 of

A1 when scaling down; bit 14 of A0 when scaling up) before the bit truncation during a

rounding operation. Figure 3-12 shows the two possible cases.

3 - 18

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

CASE I: A0 < 0.5 (<$8000), then round down

Before Rounding

After Rounding

A2

A1

A0

A2

A1

A0

XX..X XX...XX0100 011XXX...XX

39 31 15

XX..X XX...XX0100 0000...0000

0

39

31

15

0

CASE II: A0 0.5 ( $8000), then round up

Before Rounding

After Rounding

A2

XX..X XX...XX0100 1110XX...XX

39 31 15

A1

A0

A2

A1

A0

XX..X XX...XX0101 0000...0000

39 31 15

0

Figure 3-12 Two’s Complement Rounding (No-scaling)

Once the rounding bit has been programmed in the OMR, there is a delay of one instruc-

tion cycle before the new rounding mode becomes active.

MOTOROLA

DATA ALU

3 - 19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

THE DATA ALU ARITHMETIC AND ROUNDING

3 - 20

DATA ALU

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 4

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

ADDRESS REGISTER FILE (Rn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

OFFSET REGISTER FILE (Nn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3

MODIFIER REGISTER FILE (Mn) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4

TEMPORARY ADDRESS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . 4-4

AGU STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5

PC RELATIVE ADDRESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

SECONDARY OFFSET ADDER UNIT . . . . . . . . . . . . . . . . . . . . . . . . 4-6

MODULO ARITHMETIC UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6

ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7

ADDRESS MODIFIER TYPES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12

4 - 2

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

4.1

INTRODUCTION

The major components of the AGU are:

• Address Register Files

• Offset Register Files

• Modifier Register Files

• Address Arithmetic Unit Containing:

– Temporary Address Register

– Local Status Register

– PC Relative Addressing Unit

– Secondary Offset Adder Unit

– Modulo Arithmetic Unit

– Address Output Multiplexer

A block diagram of the AGU is shown in Figure 4-1.

4.2

ADDRESS REGISTER FILE (Rn)

The Address Register File consists of four, sixteen-bit registers. The file contains the ad-

dress registers R0-R3 which usually contain addresses used as pointers to memory. Each

register may be read or written by the Global Data Bus. High speed access to the XAB1

and XAB2 buses is required to allow maximum access time for the internal and external

X Data Memory and Program Memory. Each address register may be used as an input to

the modulo arithmetic unit for a register update calculation. Each register may be written

by the Global Data Bus or by the output of the modulo arithmetic unit.

R2, R3 and Temp may be used as inputs to a separate offset adder for an independent

register update calculation. This special update calculation occurs during parallel, dual

reads (using R3) and during offset by absolute immediate offsets (using R2+$xx).

CAUTION

Due to pipelining, if an address register (M, N, or R) is changed

with a MOVE instruction, the new contents will not be available for

use as a pointer until the second following instruction.

4.3

OFFSET REGISTER FILE (Nn)

The Offset Register File consists of four, sixteen-bit registers. The file contains the offset

registers N0-N3 and usually contains offset values used to update address pointers. Each

offset register may be read or written by the Global Data Bus. Each offset register is read

when the same number address register is read and used as an input to the modulo arith-

metic unit.

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MODIFIER REGISTER FILE (Mn)

GDB(0:15)

PDB(0:15)

UB(0:15)

temp

Modifier

Register

File

Offset

Register

Address Register

File

m0

r0

n0

n1

n2

n3

ctrl

Address

Arithmetic

Unit

m1

m2

m3

r1

r2

r3

n3 only

NB(0:15)

MB(0:15)

RB(0:15)

XAB2(0:15)

XAB1(0:15) PAB(0:15)

Figure 4-1 AGU Block Diagram

4.4

MODIFIER REGISTER FILE (Mn)

The Modifier Register File consists of four, 16-bit registers. The file contains the modifier

registers M0-M3 and usually specifies the type of arithmetic used to modify an address

register during address register update calculations. Each modifier register may be read

or written by the Global Data Bus. Each modifier register is read when the same number

address register is read and used as an input to the modulo arithmetic unit. Each modifier

register is preset to $FFFF during a processor reset.

4.5

TEMPORARY ADDRESS REGISTER

The temporary address register, Temp, is a 16-bit register which provides for:

4 - 4

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

AGU STATUS REGISTER

1. temporary storage for an absolute address loaded from the Program Data Bus,

2. the immediate data loaded from the Global Data Bus,

3. Address Register Indirect with Immediate Displacement addressing mode,

4. the contents of A1 or B1 registers used by the Accumulator Register Indirect

Addressing mode, or

5. the output of the modulo arithmetic unit.

The modulo arithmetic unit output is loaded into the Temp register during the pre-update

cycle of the indexed by offset addressing mode, of the pre-decrement addressing mode,

and during the LEA instruction. In each of these addressing modes, an address register

is accessed, updated by the modulo arithmetic unit, and stored in Temp in one instruction

cycle. In the following cycle, the content of Temp is used to address the X memory. For

all absolute addressing modes, the address of the operand is written into Temp and then

used to address X: or P: memory.

4.6

AGU STATUS REGISTER

The 3-bit local status register in the AGU, which cannot be accessed by the user, will be

updated after every register update; i.e., only those addressing modes that update the ad-

dress register regardless of memory access type.

Updating of the local status register is as follows:

sr_v ← set if the modulo circuit performed a wrap, clear otherwise.

sr_z ← set if the result of the address update is zero, clear otherwise.

sr_n ← set if the result of the address update is negative, clear otherwise.

The CHKAAU instruction will copy the AGU status register to SR as follows:

V

Z

N

← sr_v

← sr_z

← sr_n

During double parallel reads, only the update of the address register used for the first par-

allel read (not r3) will affect the local status register.

Note: Only the V, Z, N bits of SR will be changed.

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PC RELATIVE ADDRESSING UNIT

4.7

PC RELATIVE ADDRESSING UNIT

The PC Relative Addressing Unit performs the PC relative address computation with sign

extension done on the program address offset. The result is gated onto the Program Ad-

dress Bus by a control signal from the program controller.

4.8

SECONDARY OFFSET ADDER UNIT

The Secondary Offset Adder Unit is used for an address update calculation during double

data memory read instructions, or for the addition of address register and immediate dis-

placement.

4.9

MODULO ARITHMETIC UNIT

The Modulo Arithmetic Unit contains one 16-bit full adder (called the offset adder) which

may add one, subtract one, or add the contents of the respective signed offset register N

to the contents of the selected address register. A second full adder (called the modulo

adder) adds the summed result of the first full adder to a modulo value M or minus M,

where M is stored in the respective modifier register. A third full adder (called the reverse

carry adder) adds the constant one, minus one, the offset N (stored in the respective offset

register) to the selected address register with the carry propagating in the reverse direc-

tion, from the most significant bit to the least. The offset adder and the reverse carry adder

are in parallel and share common inputs. Test logic determines which of the three

summed outputs of the full adders is output to the address register file or temporary reg-

ister.

The modulo arithmetic unit can update one address register, Rn, during one instruction

cycle. It is capable of performing linear, reverse carry, and modulo arithmetic. The con-

tents of the selected modifier register specifies the type of arithmetic required in an ad-

dress register update calculation. The modifier value is decoded in the modulo arithmetic

unit and affects the unit’s operation. The modulo arithmetic unit’s operation is data-depen-

dent and requires execution cycle decoding of the selected modifier register contents.

Note that for dual reads, there is no modulo capability for an R3 update, linear arithmetic

will be used.

The output of the offset adder gives the result of linear arithmetic (e.g. Rn+1; Rn+N) and

is selected as the modulo arithmetic unit’s output for linear arithmetic addressing modifi-

ers. The reverse carry adder performs the required operation for reverse carry arithmetic

and its output is selected as the modulo arithmetic unit’s output for reverse carry address-

ing modifiers. Reverse carry arithmetic is useful for 2^kpoint FFT addressing. For modulo

arithmetic, the modulo arithmetic unit will perform the function (Rn+N) modulo M where N

can be one, minus one, or the contents of the offset register Nn. If the modulo operation

4 - 6

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

requires wraparound for modulo arithmetic, the summed output of the modulo adder will

give the correct updated address register value; otherwise, if wraparound is not neces-

sary, the output of the offset adder gives the correct result.

The test logic will determine which output address to select. If the contents of the respec-

tive modifier register, M, specify linear or reverse carry arithmetic, the output of the mod-

ulo arithmetic unit will be the output of the offset adder or reverse carry adder,

respectively. If M specifies a modulo value (modulo arithmetic) the output of the modulo

arithmetic unit will be based on the results or both the offset and modulo adders.

The modulo arithmetic unit is also used in a special way during execution of the NORM

instruction. For the NORM instruction, the modulo arithmetic unit computes three values:

Rn, Rn-1 and Rn+1. Depending on the result of the Data ALU operation, one of the three

is selected for the register update. (See the NORM instruction in Appendix A)

4.10 ADDRESSING MODES

The DSP56100 family instruction set contains a full set of operand addressing modes. All

address calculations are performed in the Address Generation Unit to minimize execution

time and loop overhead.

Addressing modes specify whether the operand(s) is in a register or memory and provide

the specific address of the operand(s). An effective address in an instruction will specify

an addressing mode, and for some addressing modes, the effective address will further

specify an address register. In addition, address register indirect modes require additional

address modifier information which is not encoded in the instruction. The address modifier

information is specified in the selected address modifier register(s). All memory referenc-

es require one address modifier and the dual X memory reference requires one or two ad-

dress modifiers. The definition of certain instructions implies the use of specific registers

and the addressing modes used.

Address register indirect modes require an offset and a modifier register for use in ad-

dress calculations. These registers are implied by the address register specified in an ef-

fective address in the instruction word. Each offset register Nn and each modifier register,

Mn, is assigned to an address register, Rn, having the same register number, n, forming

a triplet. Thus the assigned triplets are M0;N0;R0, M1;N1;R1, M2;N2;R2, and M3;N3;R3.

The address register Rn is used as the address register, the offset register, Nn, is used

to specify an optional offset and the modifier register Mn is used to specify an addressing

mode modifier.

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

The addressing modes are grouped into three categories: register direct, address register

indirect, and special. These addressing modes are described below and summarized in

Table 4-1.

4.10.1

Register Direct Modes

These effective addressing modes specify that the operand is in one (or more) of the 10

Data ALU registers, 12 address registers or 7 control registers.

4.10.1.1 Data or Control Register Direct

The operand is in one, two, or three Data ALU register(s) as specified in a portion of the

data bus movement field in the instruction. This addressing mode is also used to specify

a control register operand for special instructions. This reference is classified as a register

reference.

4.10.1.2 Address Register Direct

The operand is in one of the 12 address registers (Rn, Mn, and Nn) specified by an effec-

tive address in the instruction. This reference is classified as a register reference.

CAUTION

Due to pipelining, if an address register (Mn, Nn, or Rn) is changed with a

MOVE instruction, the new contents will not be available for use as a pointer

until the second following instruction.

4.10.2

Address Register Indirect Modes

The effective address in the instruction specifies the address register Rn and the address

calculation to be performed. These addressing modes specify that the operand(s) is in

memory and provide the specific address of the operand(s). When an address register is

used to point to a memory location, the addressing mode is called address register indi-

rect. The term indirect is used because the operand is not the address register itself, but

the contents of the memory location pointed to by the address register. A portion of the

data bus movement field in the instruction specifies the memory reference to be per-

formed. The type of address arithmetic used is specified by the address modifier register,

Mn.

4.10.2.1 No Update (Rn)

The address of the operand is in the address register Rn. The contents of the Rn register

are unchanged. The Mn and Nn registers are ignored. This reference is classified as a

memory reference.

4 - 8

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

4.10.2.2 Postincrement by 1 (Rn)+

The address of the operand is in the address register Rn. After the operand address is

used, it is incremented by 1 and stored in the same address register. The type of arith-

metic used to increment Rn is determined by Mn. The Nn register is ignored. This refer-

ence is classified as a memory reference.

4.10.2.3 Postdecrement by 1 (Rn)-

The address of the operand is in the address register Rn. After the operand address is

used, it is decremented by 1 and stored in the same address register. The type of arith-

metic used to increment Rn is determined by Mn. The Nn register is ignored. This refer-

ence is classified as a memory reference.

4.10.2.4 Postincrement by Offset Nn (Rn)+Nn

The address of the operand is in the address register Rn. After the unsigned operand ad-

dress is used, the contents of the Nn register are added to Rn and stored in the same ad-

dress register. The content of Nn is treated as a 2’s complement number and can there-

fore be interpreted as signed or unsigned. The contents of the Nn register are unchanged.

The type of arithmetic used to increment Rn is determined by Mn. This reference is clas-

sified as a memory reference.

4.10.2.5 Indexed by Offset Nn (Rn+Nn)

The address of the operand is the sum of the contents of the address register Rn and the

contents of the address offset register Nn. This addition occurs before the operand can

be accessed and therefore requires an extra instruction cycle. The content of Nn is treated

as a 2’s complement number and can therefore be interpreted as signed or unsigned. The

contents of the Rn and Nn registers are unchanged. The type of arithmetic used to add

Nn to Rn is determined by Mn. This reference is classified as a memory reference.

4.10.2.6 Predecrement by 1 -(Rn)

The address of the operand is the contents of the address register Rn decremented by 1.

Before the operand address is used, it is decremented (subtracted) by 1 and stored in the

same address register. The type of arithmetic used to increment Rn is determined by Mn.

The Nn register is ignored. This reference is classified as a memory reference.

4.10.3

PC Relative Modes

In the PC relative addressing modes used in the BRA and DO instructions, the address

of the operand is obtained by adding a displacement, represented in two’s complement

format, to the value of the program counter (PC). The PC always points to the address of

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

the next instruction, so PC relative addressing with zero displacement will produce the ad-

dress of the next sequential instruction in program memory.

4.10.3.1 Long Displacement PC Relative

This addressing mode requires one word of instruction extension. The address of the op-

erand is the sum of the contents of the PC and the extension word. This reference is clas-

sified as a register reference.

4.10.3.2 Short Displacement PC Relative

The short displacement occupies 8 bits in the instruction operation word. The displace-

ment is first sign extended to 16 bits and then added to the PC to obtain the address of

the operand. This reference is classified as both a register reference and a memory ref-

erence.

4.10.3.3 Address Register PC Relative

The address of the operand is the sum of the contents of the address register Rn and the

PC. The Mn and Nn registers are ignored. This reference is classified as a register refer-

ence.

4.10.4

Special Address Modes

The special address modes do not use an address register in specifying an effective ad-

dress. These modes specify the operand or the address of the operand in a field of the

instruction or they implicitly reference an operand.

4.10.4.1 Upper Word of Accumulator

This addressing mode uses the contents of either A1 or B1 to address an operand in

memory. No update is performed. It is available for single parallel memory moves. This

reference is classified as an X memory reference.

4.10.4.2 Immediate Data

This addressing mode requires one word of instruction extension. The immediate data is

a word operand in the extension word of the instruction. This reference is classified as a

program reference.

4 - 10

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

4.10.4.3 Immediate Short Data

The 8-bit operand is in the instruction operation word. The 8-bit operand is used for the

ANDI, DO, ORI, and REP instructions in addition to the immediate move to register in-

struction. This reference is classified as a program reference.

4.10.4.4 Absolute Address

This addressing mode requires one word of instruction extension. The address of the op-

erand is in the extension word. This reference is classified as both a memory reference

and a program reference.

4.10.4.5 Absolute Short Address

For the Absolute Short addressing mode the address of the operand occupies 5 bits in the

instruction operation word and is zero extended. This reference is classified as both a

memory reference and a program reference.

4.10.4.6 Short Jump Address

The operand occupies 8 bits in the instruction operation word. The address is zero extend-

ed to 16 bits and is unsigned. This reference is classified as a program memory reference.

4.10.4.7 I/O Short Address

For the I/O short addressing mode the address of the operand occupies 5 bits in the in-

struction operation word and is one’s extended. I/O short is used with the bit manipulation

and move peripheral data instructions. This reference is classified as an X memory refer-

ence.

4.10.4.8 Implicit Reference

Some instructions make implicit reference to the program counter (PC), system stack

(SSH, SSL), loop address register (LA), loop counter (LC), or status register (SR). The

registers implied and their use are defined by the individual instruction descriptions (see

Appendix A). This reference is classified as both a register reference and a program ref-

erence.

4.10.4.9 Indexed by Short Displacement

This addressing mode uses one extension word which contains the 8-bit short index and

precedes the opcode word. The index requires an extra instruction cycle and always in-

dexes address register R2. This addressing mode is available for MOVEM and MOVEC

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESS MODIFIER TYPES

instructions as well as single parallel memory moves. This reference is classified as an X

memory reference.

4.10.5

Addressing Modes Summary

Table 4-2 contains a summary of the addressing modes discussed in the previous para-

graphs.

4.11 ADDRESS MODIFIER TYPES

The DSP56100 family Address Generation Unit supports linear, modulo, and bit-reversed

address arithmetic for all address register indirect modes. Address modifiers determine

the type of arithmetic used to update addresses. Address modifiers allow the creation of

data structures in memory for FIFOs (queues), delay lines, circular buffers, stacks, and

bit-reversed FFT buffers. Data is manipulated by updating address registers (pointers)

rather than moving large blocks of data. The contents of the address modifier register, Mn,

defines the type of address arithmetic to be performed for addressing mode calculations,

and for the case of modulo arithmetic, the contents of Mn also specifies the modulus. All

address register indirect modes may be used with any address modifier type. Each ad-

dress register Rn has its own modifier register Mn associated with it.

4.11.1

Linear Modifier

The address modification is performed using normal 16-bit (modulo 65,536) two’s com-

plement linear arithmetic. A 16-bit offset Nn, or immediate data (+1, -1, or a displacement

value) may be used in the address calculations. The range of values may be considered

as signed (Nn from -32,768 to +32,767) or unsigned (Nn from 0 to +65,536). There is no

arithmetic differences between these two data representations. Addresses are normally

considered unsigned, data is normally considered signed.

4.11.2

Reverse Carry Modifier

The address modification is performed by propagating the carry in the reverse direction,

i.e., from the MSB to the LSB. This is equivalent to bit-reversing the contents of Rn and

the offset value Nn, adding normally, and then bit-reversing the result. If the (Rn)+Nn ad-

dressing mode is used with this address modifier, and Nn contains the value 2^k-1(a power

of two), then postincrementing by Nn is equivalent to bit-reversing the k LSBs of Rn, in-

crementing Rn by 1, and bit-reversing the k LSBs of Rn again. This address modification

is useful for 2^kpoint FFT addressing. The range of values for Nn is 0 to +32,767. This al-

lows bit-reversed addressing for FFTs up to 65,536 points.

4 - 12

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESS MODIFIER TYPES

As an example, consider a 1024 point FFT with real data stored in one section of data

RAM and imaginary data stored in another section of data RAM. Then Nn would contain

the value 512 and postincrementing by +N would generate the address sequence 0, 512,

256, 768, 128, 640, … This is the scrambled FFT data order for sequential frequency

points from 0 to 2π. For proper operation the reverse carry modifier restricts the base ad-

dress of the bit reversed data buffer to an integer multiple of 2^k, such as 1024, 2048, 3072,

etc. The use of addressing modes other than postincrement by Nn is possible but may not

provide a useful result.

4.11.3

Modulo Modifier

The address modification is performed modulo M, where M is permitted to range from 2

to +32,768. Modulo M arithmetic causes the address register value to remain within an

address range of size M defined by a lower and upper address boundary. The value M-1

is stored in the modifier register Mn, thus allowing a modulo size range from 2 to 32,768.

The lower boundary (base address) value must have zeroes in the k LSBs, where 2^k> M,

and therefore must be a multiple of 2^k. The upper boundary is the lower boundary plus the

modulo size minus one (base address plus M-1).

For example, to create a circular buffer of 24 stages, M is chosen as 24 and the lower ad-

dress boundary must have its 5 LSBs equal to zero (2^k> 24, thus k > 5). The Mn register

is loaded with the value 23 (M-1). The lower boundary may be chosen as 0, 32, 64, 96,

128, 160, etc. The upper boundary of the buffer is then the lower boundary plus 23.

The address pointer is not required to start at the lower address boundary and may begin

anywhere within the defined modulo address range. In fact, the initial location of Rn de-

termines the lower and upper boundaries. The upper and lower boundaries are not explic-

itly needed. If the address register pointer increments past the upper boundary of the buff-

er (base address plus M-1) it will wrap around to the base address. If the address decre-

ments past the lower boundary (base address) it will wrap around to the base address

plus M-1.

If an offset Nn is used in the address calculations, the 16-bit value Nn must be less than

proper modulo addressing. This is because a single modulo wrap around

or equal to M for

M, the result is data dependent and unpredictable except

is detected. If Nn is greater than

for the special case where Nn=L*(2^k), a multiple of the block size, 2^k, where L is a positive

integer. Note that the offset Nn must be a positive two’s complement integer. For this case

the pointer Rn will be incremented using linear arithmetic to the same relative address L

blocks forward in memory. For the normal case where Nn is less than or equal to M, the

modulo arithmetic unit will automatically wrap the address pointer around by the required

amount. This type of address modification is useful in creating circular buffers for FIFOs

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESS MODIFIER TYPES

Table 4-1 DSP56100 Family Addressing Modes

Operand Reference

Uses Mn

Modifier

Addressing Mode

Register Direct

S

C

D

A

P

X XX

Data or Control Register

Address Register Rn

Address Modifier Register MnNo

Address Offset Register Nn

No

X

No

Address Register Indirect

No Update

No

Yes*

Yes

Yes*

Yes

X

Postincrement by 1

Postdecrement by 1

Postincrement by Offset Nn

Indexed by Offset Nn

Predecrement by 1

X

PC Relative

Long Displacement

Short Displacement

Address Register

No

X

Special

Upper word of accumulator

Immediate Data

Immediate Short Data

Absolute Address

Absolute Short Address

Short Jump Address

I/O Short Address

No

X

Implicit

X

Indexed by short displacement

Where:

S = System Stack Reference

P = Program Memory Reference

C =Program Controller Register Reference

X = X Memory Reference

D = Data ALU Register Reference

XX = Double X Memory Read

A = Address ALU Register Reference

*note: M3 is not used for updating R3 in the second read in the X memory

4 - 14

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESS MODIFIER TYPES

(queues), delay lines, and sample buffers up to 32,768 words long. It is also used for dec-

imation, interpolation, and waveform generation. The special case of (Rn)+Nn with

Nn=L*(2^k) is useful for performing the same algorithm on multiple buffers, for example im-

plementing a bank of parallel filters. The range of values for Nn is -32,768 to +32,767 al-

though all values are not useful when modulo addressing as described above.

4.11.4

Wrap-Around Modulo Modifier

The address modification is performed modulo M, where M may be any power of 2 in the

range from 2¹to 2¹⁵. Modulo M arithmetic causes the address register value to remain

within an address range of size M defined by a lower and upper address boundary. The

lower boundary (base address) value must have zeroes in the k LSBs, where 2^k= M, and

therefore must be a multiple of 2^k. The upper boundary is the lower boundary plus the

modulo size minus one (base address plus M-1).

For example, to create a circular buffer of 32 stages, M is chosen as 32 and the lower ad-

dress boundary must have its 5 LSBs equal to zero (2^k= 32, thus k = 5). The Mn register

is loaded with the value $001F. The lower boundary may be chosen as 0, 32, 64, 96, 128,

160, etc. The upper boundary of the buffer is then the lower boundary plus 31.

The address pointer is not required to start at the lower address boundary and may begin

anywhere within the defined modulo address range (between the lower and upper bound-

aries). If the address register pointer increments past the upper boundary of the buffer

(base address plus M-1) it will wrap around to the base address. If the address decre-

ments past the lower boundary (base address) it will wrap around to the base address

plus M-1. If an offset Nn is used in the address calculations, the 16-bit value Nn is required

to be less than or equal to M for proper modulo addressing since multiple wrap around is

not supported. The range of values for Nn is -32,768 to +32,767.

This type of address modification is useful for decimation, interpolation, and waveform

generation since the multiple wrap-around capability may be used for argument reduction.

MOTOROLA

ADDRESS GENERATION UNIT (AGU)

4 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESS MODIFIER TYPES

4.11.5

Address Modifier Type Encoding Summary

Table 4-2 contains a summary of the address modifier types discussed in the previous

paragraphs.

Table 4-2 Addressing Mode Modifier Summary

16-bit Modifier Reg. (M0-M3)

MMMMMMMMMMMMMMMM

Address Calculation Arithmetic

0000000000000000

0000000000000001

0000000000000010

.

Reverse Carry (Bit Reversed)

Modulo 2

Modulo 3

.

0111111111111110

0111111111111111

Modulo 32767

Modulo 32768

1000000000000000

.

Reserved

1111111111111110

1111111111111111

Reserved

Linear (Modulo 65536)

where MMMMMMMMMMMMMMMM = 16-bit Modifier Reg. Contents

4 - 16

ADDRESS GENERATION UNIT (AGU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 5

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

5.1

5.2

5.3

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

PROGRAM COUNTER (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3

STATUS REGISTER (SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Carry (Bit 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Overflow (Bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Zero (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Negative (Bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4

Unnormalized (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5

Extension (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Limit (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Sticky Bit (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6

Interrupt Masks (Bits 8,9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Scaling Mode (Bits 10,11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7

Reserved Status (Bits 12,13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

ForeVer Flag (Bit 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

Loop Flag (Bit 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

LOOP COUNTER (LC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

LOOP ADDRESS REGISTER (LA) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8

SYSTEM STACK (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

STACK POINTER (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9

Stack Pointer (Bits 0,1,2,3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Stack Error Flag - SE (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10

Underflow Flag - UF (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11

Unimplemented Stack Pointer Register bits . . . . . . . . . . . . . . . . . . . . 5-12

OPERATING MODE REGISTER (OMR) . . . . . . . . . . . . . . . . . . . . . . 5-12

Operating Mode Bits (Bits 0,1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-13

Bus Arbitration Mode Bit (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Saturation Bit (Bit 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-14

Rounding Bit (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Stop Delay Bit (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Clock Out Disable Bit (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15

Reserved Operating Mode Register Bits (Bits 3 and 8-15) . . . . . . . . . 5-15

5.3.1

5.3.2

5.3.3

5.3.4

5.3.5

5.3.6

5.3.7

5.3.8

5.3.9

5.3.10

5.3.11

5.3.12

5.3.13

5.4

5.5

5.6

5.7

5.7.1

5.7.2

5.7.3

5.7.4

5.8

5.8.1

5.8.2

5.8.3

5.8.4

5.8.5

5.8.6

5.8.7

5 - 2

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

5.1

INTRODUCTION

The PCU performs program address generation (instruction prefetch), instruction decod-

ing, hardware DO-loop control, and exception processing. The programmer views the

PCU as consisting of six registers and a hardware system stack (SS) as shown on Fig-

ure 5-1. In addition to the standard program flow-control resources, such as a program

counter (PC), complete status register (SR), and SS, the PCU features registers (loop

address LA and loop counter LC) dedicated to supporting the hardware DO loop instruc-

tion.

16 bit

MR CCR

16 bit

OMR

PC

16 bit

LA

16 bit

LC

6 bit

SP

SSH

SSL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16 bit

Figure 5-1 Program Control Unit Block Diagram

5.2

PROGRAM COUNTER (PC)

This 16-bit register contains the address of the next location to be fetched from Program

Memory Space. The PC may point to instructions, data operands or addresses of oper-

ands. References to this register are always inherent and are implied by most instruc-

tions. This special purpose address register is stacked when program looping is initiated,

when a branch or a jump to subroutine is performed, and when interrupts occur except

for fast interrupts (refer to Section 7.3.4.1).

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STATUS REGISTER (SR)

5.3

STATUS REGISTER (SR)

The status register is a 16-bit register consisting of an 8-bit Mode register (MR) and an 8-

bit Condition Code register (CCR). The MR register is the high-order 8 bits of the status

register; the CCR register is the low-order 8 bits.

The MR bits are only affected by processor reset, exception processing, the DO,

ENDDO, RTI, and SWI instructions and by instructions which directly reference the MR

register (e.g., ANDI, ORI). During processor reset, the interrupt mask bits of the

mode register will be set, the scaling mode bits, loop flag, sticky bit, and the for-

ever flag will be cleared. The CCR is a special purpose control register which defines

the current user state of the processor at any given time. The CCR bits are affected by

data ALU operations, one address ALU operation (CHKAAU), bit field manipulation

instructions, parallel move operations, and by instructions which directly reference the

CCR register. The CCR bits are not affected by data transfers over XDB except if data

limiting occurs when reading the A or B accumulators. During processor reset, all CCR

bits are cleared. The standard definition of the CCR bits is given below. Refer to Appen-

dix A, Section A.3 for the complete CCR bit computation rules. The SR register is

stacked when program looping is initialized when a jump or branch to subroutine (JSR,

BSR) is performed, and when interrupts occur, except for fast interrupts (refer to Section

7.3.4.1). The status register format is shown in Figure 5-2 and is described below.

5.3.1 Carry (Bit 0)

The carry (C) bit is set if a carry is generated out of the most significant bit of the result

for an addition. Also set if a borrow is generated in a subtraction. The carry or borrow is

generated out of bit 39 of the result. The carry bit is also modified by bit manipulation,

rotate, and shift instructions. Otherwise, this bit is cleared. This bit is cleared on hard-

ware reset.

5.3.2 Overflow (Bit 1)

The overflow (V) bit is set if an arithmetic overflow occurs in the result. This indicates that

the result is not representable in the accumulator register and the accumulator register

has overflowed. Otherwise, this bit is cleared.

5.3.3 Zero (Bit 2)

The zero (Z) bit is set if the result equals zero. Otherwise, this bit is cleared.

5.3.4 Negative (Bit 3)

The negative (N) bit is set if the most significant bit 39 of the result is set. Otherwise, this

bit is cleared.

5 - 4

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STATUS REGISTER (SR)

MR

CCR

15 14 13 12 11 10

9

8

7

6

L

5

4

3

2

Z

1

0

LF FV

*

S1 S0 I1 I0

S

E

U

N

V

C

Carry

Overflow

Zero

Negative

Unnormalized

Extension

Limit

Sticky Bit

Interrupt Mask

Scaling Mode

Reserved

ForeVer Flag

Loop Flag

Figure 5-2 Status Register Format

5.3.5 Unnormalized (Bit 4)

The unnormalized (U) bit is set if the two most significant bits of the MSP portion of the

result are the same. Cleared otherwise. The MSP portion is defined by the scaling mode

and the U bit is computed as follows;

S1 S0 Scaling Mode

U Bit Computation

0

1

0

1

0

No scaling

Scale down

Scale up

U = (Bit 31 xor Bit 30)

U = (Bit 32 xor Bit 31)

U = (Bit 30 xor Bit 29)

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STATUS REGISTER (SR)

The result of calculating the U bit in this fashion is that the definition of a positive normal-

ized number, p, is 0.5 < p < 1.0 and the definition of a negative normalized number, n, is

-1.0 < n < -0.5.

5.3.6 Extension (Bit 5)

The extension (E) bit is cleared if all the bits of the integer portion of the 40-bit result are

all the same; that is, the bit patterns 00…00 or 11…11. Set otherwise. The integer por-

tion is defined by the scaling mode and the E bit is computed as follows:

S1 S0 Scaling Mode

Integer portion

0

1

0

1

0

No scaling

Scale down

Scale up

Bits 39,38,…,32,31

Bits 39,38,…,33,32

Bits 39,38,…,31,30

If E is cleared, then the low-order fraction portion contains all the significant bits - the

high order integer portion is just sign extension. In this case, the accumulator extension

register can be ignored. If E is set, it indicates that the extension accumulator is in use.

5.3.7 Limit (Bit 6)

The limit (L) bit is set if the overflow bit V is set or if the data shifter/limiters perform a lim-

iting operation. The limit bit is also set by the saturation of the 32-bit result when the sat-

uration bit of the operating mode register is set. Not affected otherwise. The L bit is

cleared only by a processor reset or an instruction which specifically clears it. This allows

the L bit to be used as a latching overflow bit. Note that L is affected by data movement

operations which read the A or B accumulator registers onto the XDB or GDB.

5.3.8 Sticky Bit (Bit 7)

The Sticky (S) bit is set only on moves of the form F, X:<> (move from accumulator to

data memory) under the following conditions:

if no scaling

set_S=bit 30 XOR bit 29

if scaling down

set_S=bit 31 XOR bit 30

if scaling up

set_S=bit 29 XOR bit 28

This test is performed on two bits of the source accumulator.

5 - 6

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STATUS REGISTER (SR)

This bit is a sticky bit in the sense that once set, it can only be reset by a MOVE to the

status register SR or an ANDI #xx,SR. This bit is especially useful for attaining maximum

accuracy on input data of a block floating point FFT (see Application note APR4/D,

Implementation of Fast Fourier Transforms on Motorola’s Digital Signal Processors).

5.3.9 Interrupt Masks (Bits 8,9)

The interrupt mask bits I1 and I0 reflect the current priority level of the processor and

indicate the interrupt priority level (IPL) needed for an interrupt source to interrupt the

processor. The current priority level of the processor may be changed under software

control. The interrupt mask bits are set during processor reset.

I1

I0

Exceptions Accepted

Exceptions masked

0

1

0

1

0

1

IPL 0,1,2,3

IPL 1,2,3

IPL 2,3

None

IPL 0

IPL 0,1

IPL 0,1,2

IPL 3

5.3.10 Scaling Mode (Bits 10,11)

The scaling mode bits S1 and S0 specify the scaling to be performed in the Data ALU

shifter/limiter and the rounding position in the Data ALU multiply-accumulator (MAC).

The scaling modes are shown below.

S1 S0 Rounding bit

Scaling Mode

0

1

0

1

0

1

15

16

14

—

No Scaling

Scaling Down

Scaling up

Reserved

The shifter/limiter scaling mode affects data read from the A or B accumulator registers

out to the XDB. Different scaling modes may be used with the same program code to

allow dynamic scaling. This allows block floating point arithmetic to be performed. The

scaling mode also affects the MAC rounding position to maintain proper rounding when

different portions of the accumulator registers are read out to the XDB. This provides

consistent rounding in block floating point arithmetic. The scaling mode bits are cleared

at the start of a long interrupt service routine. The scaling mode bits are also cleared dur-

ing a processor reset.

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LOOP COUNTER (LC)

5.3.11 Reserved Status (Bits 12,13)

These bits are reserved for future expansion and will read as zero during DSP read oper-

ations. They should be written with zero for future compatibility.

5.3.12 ForeVer Flag (Bit 14)

The ForeVer flag (FV) bit is set when a DO FOREVER program loop is in progress and

enables the detection of the end of a program loop. The FV flag, like the loop flag is

restored when terminating a DO FOREVER program loop. Stacking and restoring the FV

flag when initiating and exiting a DO FOREVER program loop, respectively, allows the

nesting of program loops. The FV flag is cleared at the start of a long interrupt service

routine. The FV flag is also cleared during a processor reset.

5.3.13 Loop Flag (Bit 15)

The loop flag (LF) bit is set when a program loop is in progress and enables the detection

of the end of a program loop. LF and FV are the only status register bits which are

restored when terminating a program loop. Stacking and restoring the loop flag when ini-

tiating and exiting a program loop, respectively, allow the nesting of program loops. The

loop flag is cleared at the start of a long interrupt service routine. The loop flag is also

cleared during a processor reset.

5.4

LOOP COUNTER (LC)

The loop counter is a special 16-bit counter used to specify the number of times to repeat

a hardware program loop. This register is stacked by a DO instruction and unstacked by

end of loop processing or by execution of a BRKcc or an ENDDO instruction. When the

end of a hardware program loop is reached, the contents of the loop counter register are

tested for one. If the loop counter is one, the program loop is terminated and the LC reg-

ister is loaded with the previous LC contents stored on the stack. If the loop counter is

not one, it is decremented by one and the program loop is repeated. The loop counter

may be read under program control. This allows the number of times a loop has been

executed to be determined during execution. Note that if LC=0 during execution of the

DO instruction, the loop will not be executed and the program will continue with the

instruction immediately after the loop end of expression. LC is also used in the REP

instruction.

5.5

LOOP ADDRESS REGISTER (LA)

The loop address register indicates the location of the last instruction word in a program

loop. This register is stacked by a DO instruction and unstacked by end of loop process-

ing or by execution of an ENDDO instruction. When the instruction word at the address

5 - 8

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SYSTEM STACK (SS)

contained in this register is fetched, the content of LC is checked. If it is not one, the LC

is decremented, and the next instruction is taken from the address at the top of the sys-

tem stack; otherwise the PC is incremented, the loop flag is restored (pulled from stack),

the stack is purged, the LA and LC registers are pulled from the stack and restored, and

instruction execution continues normally. The LA register is a read/write register written

into by a DO instruction and is read by the system stack for stacking the register. The LA

register can be directly accessed by some instructions.

5.6

SYSTEM STACK (SS)

The system stack is a separate internal RAM, 15 locations “deep”, and divided into two

banks: High (SSH) and Low (SSL) each 16 bits wide. SSH stores the PC or LA contents;

SSL stores the LC or SR contents.

The PC and SR registers are pushed on the stack for subroutine calls and long inter-

rupts. These registers are pulled from the stack for subroutine returns using the RTS

instruction and for interrupt returns that use the RTI instruction. The system stack is also

used for storing the address of the beginning instruction of a hardware program loop as

well as the SR, LA, and LC register contents just prior to the start of the loop. This allows

nesting of DO loops.

Up to 15 long interrupts, 7 DO loops, or 15 JSRs or combinations of these can be accom-

modated by the Stack. Care must be taken when approaching the stack limit. When the

Stack limit is exceeded the data to be stacked will be lost and a non-maskable Stack

Error interrupt will occur. The stack error interrupt occurs after the stack limits have been

exceeded.

5.7

STACK POINTER (SP)

The stack pointer register (SP) is a 6-bit register that indicates the location of the top of

the system stack and the status of the stack (underflow, empty, full, and overflow condi-

tions). The stack pointer is referenced implicitly by some instructions (DO, REP, JSR,

RTI, etc.) or directly by the MOVEC instruction. The stack pointer register format is

shown in Figure 5-3 and is described below. Note that the stack pointer register is imple-

mented as a 6-bit counter which addresses (selects) a fifteen location stack with its four

least significant bits. The possible stack values are shown in Figure 5-4 and are

described below.

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STACK POINTER (SP)

5

4

3

2

1

0

UF SE P3 P2 P1 P0

Stack Pointer

Stack Error Flag

Underflow Flag

Figure 5-3 SP Register Format

Table 5-1 Stack Pointer Values

UF SE P3 P2 P1 P0

CAUSE

1

0

1

0

1

0

1

0

1

0

← Stack Underflow condition after double pull.

← Stack Underflow condition.

← Stack Empty (reset). Pull causes underflow.

← stack location 1.

1

0

1

0

1

0

1

0

1

0

1

0

1

← Stack location 14.

← Stack location 15 (stack full). Push causes overflow.

← Stack overflow condition.

← Stack Overflow condition after double push.

5.7.1 Stack Pointer (Bits 0,1,2,3)

The stack pointer (SP) points to the last used place on the stack. Immediately after hard-

ware reset these bits are cleared (SP=0), indicating that the stack is empty.

Data is pushed onto the stack by incrementing SP by one then writing the item at stack

location SP. An item is pulled off the stack by copying it from location SP and then decre-

menting SP by one.

5.7.2 Stack Error Flag - SE (Bit 4)

The Stack Error flag (SE) indicates that a stack error has occurred and the transition of

SE from 0 to 1 causes the priority level 3 stack error exception (see Chapter 14).

5 - 10

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STACK POINTER (SP)

When the stack is completely full, the Stack pointer reads 001111, and any operation

that pushes data to the stack will cause a stack error exception to occur and the stack

register will read 010000 (or 010001 if an implied double push occurs).

Any implied pull operation with SP=0 will cause a Stack Error exception (See chapter

14), and the SP will read all ones (or 111110 if an implied double pull occurs). As shown

in Figure 5-4, the SE bit is set.

Note: When SP=0 (stack empty), instructions which read stack without SP post-decre-

ment and instructions which write stack without SP pre-increment do not cause a

stack error exception. i.e. DO SSL, xxxx; REP SSL; MOVEC or MOVEP when SSL

is specified as a source or destination.

5.7.3 Underflow Flag - UF (Bit 5)

The Underflow flag (UF) is set when a stack underflow occurs. See Figure 5-4.

When the user explicitly writes the SP register with the UF set and the SE cleared, and

follows this operation with an implicit stack operation that increments/decrements the

stack pointer, the Underflow flag will be cleared by the implicit operation. As long as the

SE was not set. If the Stack Error was set, the Underflow flag will not change state (the

“sticky” effect). In this way, when a stack error does occur, the reason for the error,

underflow or overflow, is preserved. Some examples are given below as illustrations:

Example 1:

move

#$20,sp

anything,ssh

sp,x:out

; set underflow flag, clear stack error flag

; implicit SP increment

; read SP, it should be $01

In this example, the implicit SP increment cleared the Underflow flag because the Stack

Error flag was cleared.

Example 2:

move

#$30,sp

anything,ssh

sp,x:out

; set underflow flag, set stack error flag

; implicit SP increment

; read SP, it should be $31

In this example, the implicit SP increment did not clear the UF because SE was set.

Example 3:

move

#$2F,sp

anything,ssh

sp,x:out

; set underflow flag, clear stack error flag

; implicit SP increment

; read SP, it should be $10

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OPERATING MODE REGISTER (OMR)

In this example, the implicit SP increment produced a stack overflow error, setting Stack

Error and clearing the Underflow flag (to show an overflow error).

While the Stack Error flag is set, implicit SP increments/decrements will not affect the

Underflow or Stack Error flags in any way (this is the “sticky” effect) even if decrementing

when the 4 LSBs of SP are’0’ or incrementing when the 4 LSBs of SP are’1’.

Example 4:

move

#$10,sp

ssh,destin.

sp,x:out

; clear underflow flag, set stack error flag

; implicit SP decrement

; read SP, it should be $1F

In this example, the implicit SP decrement did not set the Underflow flag to denote

underflow because the Stack Error flag was set.

Example 5:

move

#$3F,sp

anything,ssh

sp,x:out

; set underflow flag, set stack error flag

; implicit SP increment

; read SP, it should be $30

In this example, the implicit SP increment did not clear the Underflow flag to denote over-

flow because the Stack Error flag was set.

5.7.4 Unimplemented Stack Pointer Register bits

Any unimplemented stack pointer register bits are reserved for future expansion and will

read as zero during DSP read operations.

5.8

OPERATING MODE REGISTER (OMR)

The operating mode register (OMR) is a 16-bit register which defines the current chip

operating mode of the processor. The OMR bits are only affected by processor reset and

by instructions which directly reference the OMR.

During processor reset the chip operating mode bits will be loaded from the external

Mode Select pins. The operating mode register format is shown in Figure 5-4 and is

described below.

Note: When a bit of the OMR is changed by an instruction, a delay of one instruction cycle

is necessary before the new mode comes into effect.

5 - 12

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OPERATING MODE REGISTER (OMR)

OMR

15 14 13 12 11 10

9

*

8

7

6

5

4

3

2

1

0

*

* CD SD R SA * MC MB MA

Operating Mode

Bus Arbitration Mode

Reserved

Saturation

Rounding

Stop Delay

Clockout Disable

Reserved

Figure 5-4 Operating Mode Register Format

5.8.1 Operating Mode Bits (Bits 0,1)

The chip operating mode bits MB and MA indicate the bus expansion mode of the DSP

when an external bus extension exists. These bits are loaded from the external Mode

Select pins MODB and MODA respectively on processor reset. After the DSP leaves the

RESET state, MB and MA may be changed under program control. The Operating

Modes are shown below:

MB MA Chip Operating Mode

Comments

0

Special Bootstrap 1

Bootstrap from an external byte-wide memory

located at P:$C000.

0

1

0

1

Special Bootstrap 2

Normal Expanded

Bootstrap from the Host port or SSI0

Internal PRAM enabled; External reset at P:$E0000

Int. program memory disabled; Ext. reset at P:$000.

Development Expanded

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OPERATING MODE REGISTER (OMR)

5.8.2 Bus Arbitration Mode Bit (Bit 2)

The bus operating mode bit MC indicates the bus arbitration mode of the DSP when an

external bus extension exists. This bit is loaded from the external Mode Select pin

MODC on processor reset. After the DSP leaves the RESET state, MC may be changed

under program control. The Bus Operating Modes are shown below and more details are

given in Section 7 and Section 15.

MC

Bus Arbitration Mode

0

1

Slave

Master

5.8.3 Saturation Bit (Bit 4)

The Saturation bit (SA), when set, selects automatic saturation on 32 bits for the results

going to the accumulator. This saturation is done by a special saturation circuit inside the

MAC unit. The purpose of this bit is to provide a saturation mode for 16-bit algorithms

which do not recognize or cannot take advantage of the extension accumulator.

The saturation logic operates by checking three bits of the 40-bit result: two bits of the

extension byte (exp[7] and exp[0]) and one bit on the MSP (msp[15]). The result

obtained in the accumulator when SA =1 is shown in Table 5-2:

Table 5-2 Actions of the Saturation Mode (SA=1)

exp[7] exp[0] msp[15]

result in accumulator

0

1

0

1

0

1

unchanged

$00 7FFF FFFF

1

0

1

0

1

0

1

$FF 8000 0000

unchanged

This bit is cleared by processor reset.

The scaling bits are ignored by this saturation logic and the two saturation constants

$007FFFFFFF and $FF80000000 are not affected by the scaling mode. In the same

way, the rounding of the saturation constant (during MPYR, MACR, RND) is independent

of the scaling mode: $007FFFFFFF is rounded to $007FFF0000 and $FF80000000 to

$FF80000000.

5 - 14

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OPERATING MODE REGISTER (OMR)

CAUTION

The saturation mode is ALWAYS disabled during the execution of the fol-

lowing instructions: DMACsu, DMACuu, MACsu, MACuu, MPYsu, MPYuu,

and ASL4. The instruction ASL4 A (or B) can be followed by a MOVE A,A

(or B,B) for proper operation when the saturation mode is turned on. How-

ever, the “V” bit of the status register will never be set by the saturation of

the accumulator during the MOVE A,A (or B,B). Only the “L” bit will then be

set. If the “V” bit needs to be tested by the program, ASL4 has to be substi-

tuted by a repetition of four ASLs.

5.8.4 Rounding Bit (Bit 5)

The Rounding bit (R)selects between convergent rounding and twos-complement round-

ing. When set, two’s-complement rounding (always round up) is used.

This bit is cleared by processor reset.

5.8.5 Stop Delay Bit (Bit 6)

The Stop Delay bit (SD) is used to select the delay that the DSP needs to exit the STOP

mode. Refer to Section 7.5 for more details.

This bit is cleared by processor reset.

5.8.6 Clock Out Disable Bit (Bit 7)

When the Clock out Disable bit (CD) is cleared in the OMR, a clock out signal comes out

of the

CLKO pin. Setting the CD bit will disable the signal coming out of the CLKO pin

one instruction cycle after the bit has been set. This bit can be set by the user program

when radiation sensitive applications do not need the clock out signal.

This bit is cleared by processor reset.

5.8.7 Reserved Operating Mode Register Bits (Bits 3 and 8-15)

These operating mode register bits are reserved. They will read as zero during DSP read

operations and should be written as zero to ensure future compatibility.

MOTOROLA

PROGRAM CONTROL UNIT (PCU)

5 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OPERATING MODE REGISTER (OMR)

5 - 16

PROGRAM CONTROL UNIT (PCU)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 6

INSTRUCTION SET AND EXECUTION

Fetch

F1 F2

F3

F3e F4 F5

F6

D3e D4 D5

E3 E3e E4

…

Decode

Execute

Instruction

Cycle:

D1 D2 D3

E1 E2

1

2

3

4

5

6

7

…

MOTOROLA

INSTRUCTION SET AND EXECUTION

6 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

6.1

6.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4

Bit Field Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Loop Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5

Move Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

INSTRUCTION FORMATS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6

INSTRUCTION EXECUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Instruction Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7

Memory Access Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.3

6.4

6.4.1

6.4.2

6 - 2

INSTRUCTION SET AND EXECUTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

6.1

INTRODUCTION

As indicated by the programming model in Chapter 5, the DSP architecture can be

viewed as three functional units operating in parallel (Data ALU, AGU and PCU). The

goal of the instruction set is to keep each of these units busy each instruction cycle. This

achieves maximum speed and minimum use of program memory.

This section introduces the DSP instruction set and instruction format. The complete

range of instruction capabilities combined with the flexible addressing modes provide a

very powerful assembly language for digital signal processing algorithms. The instruction

set has also been designed to allow efficient coding for future high-level DSP language

compilers. Execution time is enhanced by the hardware looping capabilities.

6.2

INSTRUCTION GROUPS

The instruction set is divided into the following groups:

• Arithmetic

• Logical

• Bit Field Manipulation

• Loop

• Move

• Program Control

Each instruction group is described in the following sections. Detailed information on

each instruction is given in Appendix A.

6.2.1 Arithmetic Instructions

The arithmetic instructions perform all of the arithmetic operations within the Data ALU.

They may affect all of the condition code register bits. Arithmetic instructions are register-

based (register direct addressing modes used for operands) so that the Data ALU opera-

tion indicated by the instruction does not use the XDB or the GDB. Optional data trans-

fers may be specified with most arithmetic instructions. This allows for parallel data

movement over the XDB and over the GDB during a Data ALU operation. This allows

new data to be prefetched for use in following instructions and results calculated by pre-

vious instructions to be stored. These instructions execute in one instruction cycle. The

following are the arithmetic instructions.

ABS

ADC

ADD

ASL

ASL4

ASR

Absolute Value

Add Long with Carry

Add

Arithmetic Shift Left

4 Bit Arithmetic Shift Left*

Arithmetic Shift Right

MOTOROLA

INSTRUCTION SET AND EXECUTION

6 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INSTRUCTION GROUPS

ASR4

ASR16

CLR

4 Bit Arithmetic Shift Right*

16 Bit Arithmetic Shift Right*

Clear an Accumulator

CLR24

CMP

Clear 24 MSBs of an Accumulator

Compare

CMPM

DEC

Compare Magnitude

Decrement Accumulator

DEC24

DIV

Decrement upper word of Accumulator

Divide Iteration*

DMAC

EXT

IMAC

IMPY

INC

Double (Multi) precision oriented MAC*

Sign Extend Accumulator from bit 31*

Integer Multiply-Accumulate*

Integer Multiply*

Increment Accumulator

INC24

MAC

MACR

MPY

Increment 24 MSBs of Accumulator

Signed Multiply-Accumulate

Signed Multiply-Accumulate and Round

Signed Multiply

MPYR

Signed Multiply and Round

MPY(su,uu) Mixed mode Multiply*

MAC(su,uu) Mixed mode Multiply-Accumulate*

NEG

NEGC

NORM

RND

SBC

Negate

Negate with Borrow*

Normalize*

Round

Subtract Long with Carry

Subtract

SUB

SUBL

SWAP

Tcc

Shift Left and Subtract

Swap MSP and LSP of an Accumulator*

Transfer Conditionally*

TFR

TFR2

TST

Transfer Data ALU Register (Accumulator as destination)

Transfer Accumulator (32 bit Data Alu register as destination)*

Test an accumulator

TST2

ZERO

Test an ALU data register*

Zero Extend Accumulator from bit 31*

*These instructions do not allow parallel data moves.

6.2.2 Logical Instructions

The logical instructions perform all of the logical operations within the Data ALU. They

may affect all of the condition code register bits. Logical instructions are register-based

as are the arithmetic instructions above. Optional data transfers may be specified with

most logical instructions. This allows for parallel data movement over the XDB and over

the GDB during a Data ALU operation. This allows new data to be prefetched for use in

following instructions and results calculated in previous instructions to be stored. With

the exceptions of ANDI or ORI the destination of all logical instructions is A1 or B1.

6 - 4

INSTRUCTION SET AND EXECUTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INSTRUCTION GROUPS

These instructions execute in one instruction cycle. The following are the logical instruc-

tions.

AND

ANDI

EOR

LSL

Logical AND

AND Immediate Program Controller Register*

Logical Exclusive OR

Logical Shift Left

LSR

NOT

OR

ORI

ROL

ROR

Logical Shift Right

Logical Complement

Logical Inclusive OR

OR Immediate Program Controller Register*

Rotate Left

Rotate Right

*These instructions do not allow parallel data moves.

6.2.3 Bit Field Manipulation Instructions

This group tests the state of any set of bits within a byte in a memory location or a regis-

ter and then sets, clears, or inverts bits in this byte. Bit fields which can be tested include

the upper byte and the lower byte in a 16 bit value. The carry bit of the condition code

register will contain the result of the bit test for each instruction. These instructions are

read-modify-write type operations and require two instruction cycles. The following are

the bit field manipulation instructions.

BFTSTL

BFTSTH

BFCLR

BFSET

BFCHG

Bit Field Test Low

Bit Field Test High

Bit Field Test and Clear

Bit Field Test and Set

Bit Field Test and Change

6.2.4 Loop Instructions

The loop instructions control hardware looping by initiating a program loop and setting up

looping parameters, or by “cleaning” up the system stack when terminating a loop. Initial-

ization includes saving registers used by a program loop (LA and LC) on the system

stack so that program loops can be nested. The address of the first instruction in a pro-

gram loop is also saved to allow no-overhead looping. The end address of the DO loop is

specified as PC relative. The following are the loop instructions.

DO

Start Hardware Loop

DO FOREVER Hardware Loop for ever

ENDDO

BRKcc

Disable Current Loop and Unstack Parameters

Conditional Exit from Hardware Loop

MOTOROLA

INSTRUCTION SET AND EXECUTION

6 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INSTRUCTION FORMATS

6.2.5 Move Instructions

The move instructions perform data movement over the XDB and over the GDB. Move

instructions do not affect the condition code register except the limit bit L if limiting is per-

formed when reading a Data ALU accumulator register. AGU instructions are also

included among the following move instructions. These instructions do not allow optional

data transfers. In addition to the following move instructions, there are parallel moves

which can be used simultaneously with many of the other instructions.

LEA

Load Effective Address

MOVE

Move Data with or without register transfer – TFR(3)

Move Control Register

Move Immediate Short

Move Program Memory

Move Peripheral Data

MOVE(C)

MOVE(I)

MOVE(M)

MOVE(P)

MOVE(S)

Move Absolute Short

6.2.6 Program Control Instructions

The program control instructions include branches, jumps, conditional branches and

jumps and other instructions which affect the PC and system stack. Program control

instructions may affect the condition code register bits as specified in the instruction.

The following are the program control instructions.

Bcc

Branch Conditionally

BSR

BRA

Branch to Subroutine (PC relative)

Branch

BScc

DEBUG

DEBUGcc

Jcc

Branch to Subroutine Conditionally

Enter Debug Mode

Enter Debug Mode Conditionally

Jump Conditionally

JMP

Jump

JSR

Jump to Subroutine

JScc

NOP

REP

REPcc

RESET

RTI

Jump to Subroutine Conditionally

No Operation

Repeat Next Instruction

Repeat Next Instruction Conditionally

Reset Peripheral Devices

Return from Interrupt

RTS

STOP

SWI

Return from Subroutine

Stop Processing (low power stand-by)

Software Interrupt

WAIT

Wait for Interrupt (low power stand-by)

6.3

INSTRUCTION FORMATS

Instructions are one or two words in length. The instruction and its length are specified by

the first word of the instruction. The next word may contain information about the instruc-

tion itself or about an operand for the instruction. The assembly language source code

6 - 6

INSTRUCTION SET AND EXECUTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INSTRUCTION EXECUTION

for a typical one word instruction is shown below. The source code is organized into four

columns.

Opcode

Operands

X Bus Data

G Bus Data

MAC

X0,Y0,A

X:(R0)+,X0

X:(R3)+,Y0

The Opcode column indicates the Data ALU, AGU, or PCU operation to be performed.

The Operands column specifies the operands to be used by the opcode. The X Bus Data

and G Bus Data columns specify optional data transfers over the X Bus and the address-

ing modes to be used. The Opcode column must always be included in the source code.

The DSP offers parallel processing using the Data ALU, AGU and PCU. For the instruc-

tion word above, the DSP will perform the designated ALU operation (Data ALU), up to

two data transfers specified with address register updates (AGU), and will also decode

the next instruction and fetch an instruction from program memory (PCU) all in one

instruction cycle. When an instruction is more than one word in length, an additional

instruction execution cycle is required. Most instructions involving the Data ALU are reg-

ister-based (all operands are in Data ALU registers) and allow the programmer to keep

each parallel processing unit busy. An instruction which is memory-oriented (such as a

bit field manipulation instruction) or that causes a control flow change (such as a branch/

jump) prevents the use of parallel processing resources during its execution.

6.4

INSTRUCTION EXECUTION

Instruction execution is pipelined to allow most instructions to execute at a rate of one

instruction every clock cycle. However, certain instructions will require additional time to

execute. These include instructions which are longer than one word, instructions which

use an addressing mode that requires more than one cycle, instructions which make use

of the global data bus more than once, and instructions which cause a control flow

change. In the latter case a cycle is needed to clear the pipeline.

6.4.1 Instruction Processing

Pipelining allows the fetch-decode-execute operations of an instruction to occur during

the fetch-decode-execute operations of other instructions. While an instruction is exe-

cuted, the next instruction to be executed is decoded, and the instruction to follow the

instruction being decoded is fetched from program memory. If an instruction is two words

in length, the additional word will be fetched before the next instruction is fetched. The

illustration below demonstrates pipelining; F1, D1 and E1 refer to the fetch, decode and

execute operations, respectively, of the first instruction. Note, the third instruction con-

tains an instruction extension word and takes two cycles to execute.

MOTOROLA

INSTRUCTION SET AND EXECUTION

6 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INSTRUCTION EXECUTION

F1 F2

F3

F3e F4 F5

F6

D3e D4 D5

E3 E3e E4

…

D1 D2 D3

E1 E2

Instruction

Cycle:

1

2

3

4

5

6

7

…

Figure 6-1 Instruction Pipelining

Each instruction requires a minimum of 12 clock phases to be fetched, decoded, and

executed. A new instruction may be started after four phases. Two word instructions

require a minimum of 16 phases to execute and a new instruction may start after eight

phases.

6.4.2 Memory Access Processing

One or more of the DSP memory sources (X data memory and program memory) may

be accessed during the execution of an instruction. Each of these memory sources may

be internal or external to the DSP. These address buses (XA1, XA2, and PAB) and three

data buses (XD, program data, and Global Data) are available for internal memory

accesses during one instruction cycle but only one address bus and one data bus are

available for external memory accesses (when an external bus is available). If all mem-

ory sources are internal to the DSP, one or more of the two memory sources may be

accessed in one instruction cycle (i.e., program memory access or program memory

access plus an X memory reference). However, when one or more of the memories are

external to the DSP, memory references may require additional instruction cycles. With

internal program memory and one internal data memory, memory references will not

require any additional instruction cycles (i.e. X memory references will take one instruc-

tion cycle). When program memory is external and the data memory is internal, no addi-

tional instruction cycles are required for all types of operand references. If the data

memory is also external, an additional cycle is necessary when the external data mem-

ory is accessed (i.e., when X memory references are specified). If each memory source

is external to the DSP, one additional cycle is required when one data memory is

accessed i.e., when a X memory reference is specified).

6 - 8

INSTRUCTION SET AND EXECUTION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 7

PROCESSING STATES

STOP

NORMAL

WAIT

RESET

EXCEPTION

MOTOROLA

PROCESSING STATES

7 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

7.1

7.2

7.2.1

7.2.2

7.2.2.1

7.2.2.2

7.2.2.3

7.2.2.4

7.2.2.5

7.2.2.6

7.2.2.7

7.3

7.3.1

7.3.2

7.3.3

7.3.4

7.3.4.1

7.3.4.2

7.3.4.3

7.3.5

7.3.5.1

7.3.5.2

7.3.5.3

7.3.6

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

NORMAL PROCESSING STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Instruction Pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-3

Summary of Pipeline Related Restrictions . . . . . . . . . . . . . . . . . . . . . 7-8

DO Instruction Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8

Restrictions Near the End of DO Loops . . . . . . . . . . . . . . . . . . . . . . . 7-8

ENDDO Instruction Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

RTI and RTS Instruction Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

SP and SSH/SSL Register Manipulation Restrictions . . . . . . . . . . . . 7-9

Rn, Nn, and Mn Register Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . 7-9

Fast Interrupt Routine Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10

EXCEPTION PROCESSING (INTERRUPT PROCESSING) . . . . . . . 7-10

Interrupt Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

Interrupt Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-12

Interrupt Instruction Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

Interrupt Instruction Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13

Fast Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14

Long Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15

Case of the REP Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16

Hardware Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17

Software Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20

Stack Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22

Interrupt Priority Levels (IPL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23

Exception Priorities within an IPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

RESET STATE PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-24

WAIT STATE PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-25

STOP STATE PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-28

7.3.6.1

7.3.6.2

7.4

7.5

7.6

7 - 2

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

7.1

INTRODUCTION

The DSP56100 family is always in one of five processing states: normal, exception,

reset, wait, and stop. These states are described in the following paragraphs.

7.2

NORMAL PROCESSING STATE

The normal processing state is associated with instruction execution. Details on normal

processing of the individual instructions can be found in Appendix A. Instructions are

executed using a three stage pipeline which is described in the following paragraphs.

7.2.1 Instruction Pipeline

The 16-bit DSP instruction execution is performed in a three level pipeline allowing most

instructions to execute at a rate of one instruction every instruction cycle. However, cer-

tain instructions will require additional time to execute. These include instructions which

are longer than one word, instructions which use an addressing mode that requires more

than one cycle, and instructions which cause a control flow change. In the latter case a

cycle is needed to clear the pipeline.

Instruction pipelining allows overlapping the execution of instructions such that the fetch-

decode-execute operations of a given instruction occurs concurrently with the fetch-

decode-execute operations of other instructions. Specifically, while an instruction is exe-

cuted, the next instruction to be executed is decoded, and the instruction to follow the

instruction being decoded is fetched from program memory. Only one word is fetched

per cycle so that if an instruction is two words in length, the additional word will be

fetched before the next instruction is fetched. Figure 7-1 demonstrates pipelining. F1,

D1, and E1 refer to the fetch, decode, and execute operations, respectively, of the first

instruction. The third instruction contains an instruction extension word and takes two

instruction cycles to execute. Although it takes three instruction cycles for the pipeline to

fill and the first instruction to execute, an instruction usually executes on each instruction

cycle thereafter.

Summarizing; each instruction requires a minimum of 3 instruction cycles (12 clock

phases) to be fetched, decoded, and executed. This means that there is a delay of three

instruction cycles on power up to fill the pipe. A new instruction may be started immedi-

ately following the previous instruction. Two word instructions require a minimum of four

instruction cycles to execute (three cycles for the first instruction word to move through

the pipe and execute and one more for the second word to execute) and a new instruc-

tion may start after the second cycle of the preceding instruction.

MOTOROLA

PROCESSING STATES

7 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

Instruction

Cycle

1

2

3

4

5

6

7

. . .

Fetch

Decode

Execute

F1

F2

D1

F3

D2

E1

F3e

D3

E2

F4

D3e

E3

F5

D4

E3e

F6 . . .

D5 . . .

E4 . . .

Figure 7-1 Instruction Pipelining

The pipeline is normally transparent to the user. However, it will affect program execution

in some situations. These situations are instruction sequence dependent and are best

described by case studies. Most of these restricted sequences occur because (1) all

addresses are formed during instruction decode or (2) contention for an internal resource

such as the status register (SR) occurs. If the execution of an instruction depends on the

relative location of the instruction in a sequence of instructions, there is a pipeline effect.

To test for a suspected pipeline effect, compare between the execution of the suspect

instruction (1) when it directly follows the previous instruction and (2) when four NOPs

are inserted between the two. If there is a difference, it is due to a pipeline effect. The 16-

bit DSP assembler is designed to flag instruction sequences with potential pipeline

effects so that the user can decide if the operation will be as expected.

Case 1: The following two examples show similar code sequences, the first with no pipe-

line effect and the second with a pipeline effect.

1) No pipeline effect:

ORI

Jcc

#xx,CCR

xxxx

;Changes CCR at the end of execution time slot

;Reads condition codes in SR in its execution time slot

The Jcc will test the bits modified by the ORI without any pipeline effect in the code seg-

ment above.

2) Instruction which started execution during decode:

ORI

#03,OMR

x:$100,a

;Sets MA, MB bits at execution time slot

MOVE

;Reads internal RAM instead of external RAM

There is a pipeline effect in example 2 because the address of the move is formed at its

decode time before the ORI changes the MA and MB bits (which change the memory

map) in the ORI’s execution time slot. The following code produces the expected results

of reading the external RAM:

ORI

NOP

MOVE

#03,OMR ;Sets MA, MB bits at execution time slot

;Delays the MOVE so it will read the updated OMR

x:$100,a ;Reads external RAM

Case 2: One of the more common sequences where pipeline effects are apparent is:

7 - 4

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

.

MOVE

#xxxx,Rn ;Move a number into register Rn (n=0-7).

MOVE

X:(Rn),A

;Use the new contents of Rn to address memory.

.

In this case, before the first MOVE instruction has written Rn during its execution cycle,

the second MOVE has accessed the old Rn and therefore will use the old contents of Rn.

This is because the address for indirect moves is formed during the decode cycle. This

overlapping instruction execution in the pipeline causes the pipeline effect. One instruc-

tion cycle should be allowed after a register has been written by a MOVE instruction

before the new contents are available for use by another MOVE instruction. The proper

instruction sequence is:

.

MOVE X0,Rn

;Move a number into register Rn.

NOP

;Execute any instruction or instruction sequence not using Rn

.

MOVE X:(Rn),A

;Use the new contents of Rn.

Case 3: A situation related to Case 2 can be seen in the boot ROM program. At the end

of the bootstrap operation, the OMR is changed to Mode #2 and then the program that

was loaded is executed. This process is accomplished in the last three instructions which

are shown below:

_BOOTEND

MOVEC

#2,OMR

; Set the operating mode to 2

; (and trigger an exit from

; bootstrap mode).

ANDI

#$0,CCR ; Clear SR as if RESET and

; introduce delay needed for

; Op. Mode change.

JMP

<$0

; Start fetching from PRAM, P:$0000

The JMP instruction generates its jump address during its decode cycle. If the JMP

instruction followed the MOVEC, the MOVEC instruction would not have changed the

OMR before the JMP instruction formed the fetch address. As a result, the jump would

fetch the instruction at P:$0000 of the bootstrap ROM (MOVE #$FFC0,R2). The OMR

would then change due to the MOVEC instruction and the next instruction would be the

second instruction of the downloaded code at P:$0001 of the internal RAM. However, the

ANDI instruction allows the OMR to be changed before the JMP instruction uses it and

the JMP fetches P:$0000 of the internal RAM as intended.

Case 4: An interrupt has two additional control cycles which are executed in the interrupt

controller concurrently with the fetch, decode, and execute cycles (see Section 7.3

MOTOROLA

PROCESSING STATES

7 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

“Exception Processing” and Figure 7-2). During these two control cycles, the interrupt is

arbitrated by comparing the interrupt mask level with the interrupt priority level (IPL) of

the interrupt and either allowing or disallowing the interrupt. Therefore, if the interrupt

mask is changed after an interrupt is arbitrated and accepted as pending but before the

interrupt is executed, the interrupt will be executed regardless of what the mask was

changed to. The following examples show that the old interrupt mask is in effect for

up to four additional instruction cycles after the interrupt mask is changed. Note

that all instructions shown in the examples here are one word instructions; however, one

two-word instruction can replace two one-word instructions except where noted.

Program flow with no interrupts after interrupts are disabled:

.

ORI

#03,MR

;disable interrupts

INST 1

INST 2

INST 3

INST 4

.

Possible variations in program flow which may occur after interrupts are disabled:

.

ORI #03,MR

II

INST 1

II+1

II

INST 2

INST 1

INST 2

INST 3

INST 4

.

II+1

INST 2

INST 3

INST 4

.

II

II+1

INST 3

INST 4

.

INST 3 ← See note 1

II

II+1

INST 4

.

Note 1: INST 3 may be executed at that point only if the preceding instruction (INST 2)

was a single-word instruction.

Note 2: II = Interrupt Instruction from maskable interrupt.

The following program flow WILL NOT occur because the ORI instruction becomes

effective after a pipeline latency of four instruction cycles:

7 - 6

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

.

ORI #03,MR ; Disable interrupts.

INST 1

INST 2

INST 3

INST 4

II

II+1

; Interrupts disabled.

.

Program flow without interrupts after interrupts are re-enabled:

.

ANDI #00,MR

;enable interrupts

INST 1

INST 2

INST 3

INST 4

.

Program flow with interrupts after interrupts are re-enabled:

.

ANDI #00,MR

INST 1

INST 2

INST 3

;Enable interrupts

;Uninterruptable

;II fetched

INST 4

;II+1 fetched

II

II+1

.

The DO instruction is another instruction which begins execution during the decode cycle

of the pipeline. As a result, there are a number of restrictions concerning access conten-

tion with the program controller registers which are accessed by the DO instruction. The

ENDDO instruction has similar restrictions. Appendix A contains additional information

on the DO and ENDDO instruction restrictions.

Case 5: A resource contention problem can occur when one instruction is using a regis-

ter during its decode while the instruction executing is accessing the same resource.

One example of this is:

MOVEC

DO

X:$100,SSH

#$10,END

The problem occurs because the MOVEC instruction loads the contents of X:$100 into

the SSH during T3 of its execute cycle. The DO instruction that follows pushes the stack

MOTOROLA

PROCESSING STATES

7 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

(LA → SSH, LC → SSL) during T3 of its decode cycle. Therefore the two instructions try

writing to the SSH simultaneously and conflict.

7.2.2 Summary of Pipeline Related Restrictions

A summary of the instruction sequences that cause pipeline effects is given in the follow-

ing paragraphs. Additional information concerning the individual instructions can be

found in Appendix A.

7.2.2.1 DO Instruction Restrictions

The DO instruction must not be immediately preceded by any of the following instruc-

tions:

• BFCHG/BFCLR/BFSET LA, LC, SSH, SSL or SP

• MOVEC/MOVEM to LA, LC, SSH, SSL or SP

• MOVEC/MOVEM from SSH

7.2.2.2 Restrictions Near the End of DO Loops

Proper DO loop operation is guaranteed if no instruction starting at address LA-2, LA-1

or LA specifies the program controller registers SR, SP, SSL, LA, LC or (implicitly) PC as

a destination register; or specifies SSH as a source or destination register. Also, SSH

can not be specified as a source register in the DO instruction itself.

These restricted instructions include:

- at LA-2, LA-1 and LA:

• DO

• BFCHG/BFCLR/BFSET LA, LC, SR, SP, SSH, or SSL

• BFTST SSH

• MOVEC/MOVEM/MOVEP from SSH

• MOVEC/MOVEM/MOVEP to LA, LC, SR, SP, SSH, or SSL

• ANDI/ORI MR

- at LA:

• any two word instruction

• Jcc, Bcc, JMP, BRA, JScc, BScc, JSR, BSR

• REP, RESET, RTI, RTS, STOP, WAIT

Other restrictions:

• DO SSH,xxxx

• JSR/JScc/BSR/BScc to (LA), if Loop Flag is set

7 - 8

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NORMAL PROCESSING STATE

7.2.2.3 ENDDO Instruction Restrictions

The ENDDO instruction must not be immediately preceded by any of the following

instructions:

• BFCHG/BFCLR/BFSET LA, LC, SR, SSH, SSL or SP

• MOVEC/MOVEM to LA, LC, SR, SSH, SSL or SP

• MOVEC/MOVEM from SSH

• ANDI/ORI MR

7.2.2.4 RTI and RTS Instruction Restrictions

The RTI instruction must not be immediately preceded by any of the following instruc-

tions:

• BFCHG/BFCLR/BFSET SR, SSH, SSL or SP

• MOVEC/MOVEM to SR, SSH, SSL or SP

• MOVEC/MOVEM from SSH

• ANDI MR, ANDI CCR

• ORI MR, ORI CCR

The RTS instruction must not be immediately preceded by any of the following instruc-

tions:

• BFCHG/BFCLR/BFSET SSH, SSL or SP

• MOVEC/MOVEM to SSH, SSL or SP

• MOVEC/MOVEM from SSH

7.2.2.5 SP and SSH/SSL Register Manipulation Restrictions

In addition to all the above restrictions concerning SP, SSH, and SSL, the following

instruction sequences are illegal:

• BFCHG/BFCLR/BFSET SP

• MOVEC/MOVEM/MOVEP from SSH or SSL

and

• MOVEC/MOVEM to SP

• MOVEC/MOVEM/MOVEP from SSH or SSL

Also the instruction MOVEC SSH,SSH is illegal.

7.2.2.6 Rn, Nn, and Mn Register Restrictions

If an address register (R0-R3, N0-N3, or M0-M3) is changed with a move type instruction

(LUA, Tcc, MOVE, MOVEM, MOVEC or parallel move), the new contents will not be

MOTOROLA

PROCESSING STATES

7 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

available for use as a pointer until the second following instruction. This restriction does

not apply to registers updated as part of an indirect addressing mode.

7.2.2.7 Fast Interrupt Routine Restrictions

BRKcc, DO, SWI, STOP, and WAIT may not be used in a fast interrupt routine.

7.3

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Exception processing in a digital signal processing environment is primarily associated

with transfer of data between DSP memory or registers and a peripheral device. When

an interrupt occurs, a limited context switch must be performed with minimum overhead.

When a hardware interrupt is received, it is synchronized on instruction boundaries so

that the first two interrupt instruction words can be inserted into the instruction stream.

Suppose that the interrupt is stored in the interrupt pending latch during the current

instruction fetch cycle. During the next cycle, which is the decode cycle of the current

instruction, the PC will be updated to fetch the next instruction. However, in the following

cycle, which is the execution cycle of the current instruction, the address placed on the

program address bus (PAB) comes from the appropriate interrupt start address, rather

than from the PC. Note that the PC is frozen until exception processing terminates.

Figure 7-2 illustrates the effect of the interrupt controller, which is simply to insert two

instruction words into the processor’s instruction stream.

The following one-word instructions are aborted when they are fetched in the cycle pre-

ceding the fetch of the first interrupt instruction word — REP, REPcc, BRKcc, STOP,

WAIT, RESET, RTI, RTS, Jcc, Bcc, JMP, BRA, BScc, JScc, JSR, and BSR.

Two-word instructions are aborted when the first interrupt instruction word fetched will

replace the fetch of the second word of the two word instruction. Aborted instructions are

re-fetched again when program control returns from the interrupt routine. The PC is

adjusted appropriately prior to the end of the decode cycle of the aborted instruction.

If the first interrupt word fetch occurs in the cycle following the fetch of a one-word

instruction not listed above or the second word of a two-word instruction, that instruction

will complete normally prior to the start of the interrupt routine.

7 - 10

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i*

i

n3

n2

n1

n4

n3

n2

ii1

n4

n3

ii2

ii1

n4

n5

ii2

ii1

n6

n5

ii2

n7

n6

n5

n8

n7

n6

ii3

n8

n7

ii4

ii3

n8

Decode

ii4

ii3

Execute

Instruction

decode Order

1

2

3

4

5

6

7

8

9

10

11

i = interrupt request

ii = interrupt instruction word

n = normal instruction word

* subsequent interrupts are enabled at this time

Figure 7-2 Interrupt Pipeline Action

The following cases have been identified where service of an interrupt might encounter

an extra delay:

1. If a long interrupt routine is used to service an SWI then the processor priority

level is set to 3. Thus, all interrupts except for other level three interrupts are

disabled until the SWI service routine terminates with an RTI (unless the SWI

service routine software lowers the processor priority level).

2. While servicing an interrupt, the next interrupt service will be delayed according

to the following rule:

After the first interrupt instruction word reaches the instruction decoder, at least

three more instructions will be decoded before decoding the next first interrupt

instruction word. If any one pair of instructions being counted is the REP in-

struction followed by an instruction to be repeated then the combination is

counted as two instructions independently of the number of repeats done.

Sequential REP combinations will cause pending interrupts to be rejected and

can not be interrupted until the sequence of REP combinations ends.

3. The following instructions are not interruptable: BRKcc, SWI, STOP, WAIT, and

RESET.

4. The REP and REPcc instructions and the instruction being repeated are not in-

terruptable.

MOTOROLA

PROCESSING STATES

7 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

5. Instructions using a Read-Modify-Write bus access cannot be interrupted dur-

ing their bus access.

During an interrupt instruction fetch, two instruction words are fetched, the first from the

interrupt starting address and the second from the interrupt starting address +1 loca-

tions.

7.3.1 Interrupt Types

Two types of interrupt routines may be used: fast and long. The fast routine consists of

the two automatically inserted interrupt instruction words. These words can contain any

un-restricted single two-word instruction or any two one-word instructions (see Appendix

A - section A.8 “Instruction Sequence Restrictions” for a list of restrictions). Fast interrupt

routines are never interruptable.

CAUTION

Status is not preserved during a fast interrupt routine; therefore, instructions

which modify status should not be used at the interrupt starting address and

interrupt starting address +1.

If one of the instructions in the fast routine is a jump or branch to subroutine, then a long

interrupt routine is formed. The long interrupt routine should be terminated by an RTI.

Long interrupt routines are interruptable by higher priority interrupts.

7.3.2 Interrupt Arbitration

External interrupts are internally synchronized with the processor clock (this takes up to

three T cycles) before their interrupt pending flags are set. Each separate external inter-

rupt and internal interrupt has its own independent flag. After each instruction is exe-

cuted in normal processing mode, all interrupts are arbitrated. This includes all hardware

interrupts that have been latched into their respective interrupt pending flags and all

internal interrupts. During arbitration, each interrupt’s IPL is compared with the interrupt

mask in the SR and the interrupt is either allowed or disallowed. The remaining interrupts

are prioritized according to the priority shown in Table 7-5 and the highest priority inter-

rupt is chosen. The interrupt vector is then calculated so that the Program Interrupt Con-

troller can fetch the first interrupt instruction. Interrupt arbitration and control occurs

concurrently with the fetch-decode-execute cycle and takes two instruction cycles. Inter-

rupts from a given source are not buffered. The interrupt pending flag for the chosen

interrupt is not cleared until the second interrupt vector of the chosen interrupt is being

fetched. A new interrupt from the same source will not be accepted for the next interrupt

arbitration until that time.

7 - 12

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

The internal “interrupt acknowledge” signal is used to clear the edge-triggered interrupts’

flags, the Stack Error, Illegal Interrupt and SWI. Peripheral interrupt requests that need a

read/write action to some register DO NOT receive this signal, and those interrupts will

remain pending until their registers are read/written. Also, level-triggered interrupts will

not be cleared. Note that the acknowledge signal will be generated after generation of

the interrupt vectors, and not before.

However, the first instruction word of the next interrupt service will reach the decoder

only after the decoding of at least four instructions following the decoding of the first

instruction of the previous interrupt.

7.3.3 Interrupt Instruction Fetch

The interrupt controller generates an interrupt instruction fetch address which points to

the first instruction word of a two-word fast interrupt routine. This address is used for the

next instruction fetch, instead of the PC, and the interrupt instruction fetch address + 1 is

used for the subsequent instruction fetch. While the interrupt instructions are being

fetched, the PC is inhibited from being updated. After the two interrupt words have been

fetched, the PC is used for any following instruction fetches.

After the interrupt instructions have been fetched, they are guaranteed to be executed.

This is true even if the instruction that is currently being executed is a change of flow

instruction (i.e., JMP, JSR, etc.) that would normally ignore the instructions in the pipe.

After the interrupt instruction fetch, the PC will point to the instruction that would have

been fetched if the interrupt instructions had not been substituted.

7.3.4 Interrupt Instruction Execution

Interrupt instruction execution is considered to be “fast” if neither of the instructions of the

interrupt service routine causes a change of flow. A jump or branch to subroutine within a

fast interrupt routine forms a long interrupt which is terminated with an RTI instruction to

restore the PC and SR from the stack and return to normal program execution. Reset is

a special exception which will normally contain only a JMP instruction at the exception

start address. At the programmer’s option, almost any instruction can be used in the fast

interrupt routine. The restricted instructions include SWI, STOP, and WAIT. Figure 7-3,

Figure 7-4, Figure 7-5 show the fast and the long interrupt service routines. Notice that

the fast interrupt executes only two instructions and then automatically resumes execu-

tion of the main program where it left off whereas the long interrupt must be told to return

to the main program by executing an RTI instruction.

7.3.4.1 Fast Interrupt

Figure 7-3 illustrates the effect of a fast interrupt routine in the stream of instruction

fetches.

MOTOROLA

PROCESSING STATES

7 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Figure 7-4 shows the sequence of instruction fetches between two fast interrupts. Note

that there is a total of four fetches between the two interrupt fetches (two after the first

interrupt and two preceding the second interrupt). The requirement for these four fetches

establishes the maximum rate at which the DSP will respond to interrupts, namely one

interrupt every six instructions.

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i*

i

n3

n2

n1

n4

n3

n2

ii1

n4

n3

ii2

f1

n5

f2

n6

n5

f2

n7

n6

n5

n8

n7

n6

ii3

n8

n7

ii4

f3

Decode

f4

f3

Execute

n4

f1

n8

Instruction

decode Order

1

2

3

4

5

6

7

8

9

10

11

f = fast interrupt instruction word (non-control-flow-change)

i = interrupt request

ii = interrupt instruction word

n = normal instruction word

* subsequent interrupts are enabled at this time

Figure 7-3 Fast Interrupt Pipeline Action

The sequence:

REP

#N

Instruction

is counted as 2 instructions regardless the value of N.

Execution of a fast interrupt routine always follows the following rules:

1. No JSR or BSR located at either of the two interrupt vector addresses. If Jscc

or Bscc are used, the interrupt remains a fast interrupt if the condition is false.

2. The processor status is not saved.

3. The fast interrupt routine may (but should not) modify the status of the normal

instruction stream.

4. The fast interrupt routine may contain any single two-word instruction or any

two one-word instructions except SWI, STOP, and WAIT.

7 - 14

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

5. The PC, which contains the address of the next instruction to be executed in

normal processing, remains unchanged during a fast interrupt routine.

6. The fast interrupt returns without an RTI.

7. Normal instruction fetching resumes using the PC following the completion of

the fast interrupt routine.

8. A fast interrupt is not interruptable.

9. The primary application is to move data between memory and I/O devices.

7.3.4.2 Long Interrupt

A jump to subroutine instruction within the fast interrupt routine forms a long interrupt

routine. Execution of a long interrupt routine always follows the following rules:

1. A JSR, BSR, JScc or BScc with true condition to the starting address of the in-

terrupt service routine is located at one of the two interrupt vector addresses.

2. During execution of the jump to subroutine instruction, the PC and SR are

stacked. The interrupt mask bits of the SR are updated to mask interrupts of the

same or lower priority. The Loop Flag and Scaling Mode bits are reset.

3. The first instruction word of the next interrupt service (of higher IPL) will reach

the decoder only after the decoding of at least four instructions following the de-

coding of the first instruction of the previous interrupt.

4. The interrupt service routine can be interrupted i.e., nested interrupts are sup-

ported.

5. The long interrupt routine can be any length and should be terminated by an

RTI, which restores the PC and SR from the stack.

Figure 7-4 illustrates the effect of a long interrupt routine on the instruction pipeline. A

short JSR (that is, a JSR with 8-bit absolute address) is used to form the long interrupt

routine. For this example, word 4 of the long interrupt routine is an RTI. A subsequent

interrupt is shown to illustrate the non-interruptible nature of the early instructions in the

long interrupt service routine. In this example, the interrupts are reenabled, not because

sr4 was an RTI, but because it was the fourth instruction decoded after ii1 was decoded

and found to be a JSR instruction.

Either one of the two instructions of the fast interrupt can be the JSR instruction that

forms the long interrupt. Notice that if the first fast interrupt vector instruction is a short

JSR, the second instruction is never used.

MOTOROLA

PROCESSING STATES

7 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

7.3.4.3 Case of the REP Instruction

A REP instruction is treated as a single two-word instruction regardless of how many

times it repeats the second instruction of the pair. Instruction fetches are suspended and

will be reactivated only after the loop counter is decremented to one

See Figure 7-5 for an example of interrupt service when the instruction that receives the

internal interrupt service request is the REP instruction (n3 in Figure 7-5). During the

repeated executions of the instruction that follows the REP instruction (n4), instruction

fetches are suspended. The fetches will be reactivated only after the loop counter is dec-

remented to one. During the execution of n4, no interrupts will be serviced. When LC

finally reaches one, the fetches are reinitiated and the interrupt can be serviced. In Fig-

ure 7-5 it can be seen that n5 (loaded into the instruction latch from the backup instruc-

tion latch) is decoded and executed as well as n6 before the first interrupt vector.

Sequential REP operations will cause pending interrupts to be rejected and can not be

interrupted until the sequence of REP operations ends. The reason that REP operations

are not interruptable is that the instruction being repeated is not refetched. While that

instruction is repeating, no instructions are fetched or decoded and an interrupt can not

be inserted.

7.3.5 Interrupt Sources

Exceptions may originate from any of the 32 vector addresses listed in Table 7-1 The

corresponding interrupt starting addresses for each interrupt source are shown. Interrupt

starting addresses are internally-generated addresses which point to the first instruction

of the fast interrupt service routine. The interrupt starting address for each interrupt is an

address constant for minimum overhead. Thirty-two interrupt starting address locations

are provided. These addresses are located in the first 64 locations of program memory.

When an interrupt is serviced, the instruction at the interrupt starting address is fetched

first. If it is known a priori that certain interrupts will not be used, those interrupt vector

locations can be used for program or data storage.

The 32 interrupts are prioritized into four levels. Level 3 is the highest priority level and is

not maskable. Levels 0-2 are maskable. The interrupts within each level are prioritized

according to a predefined priority that is discussed in the next sub-section. The level

three interrupts - Reset, Illegal Instruction, Stack Error and SWI, are discussed individu-

ally.

7.3.5.1 Hardware Interrupt Sources

There are two types of hardware interrupts in the DSP: internal and external. The internal

interrupts include all of the on-chip peripheral devices (Host Interface, SSIs and Timer).

Each internal interrupt source is latched and serviced if it is not masked. When it is ser-

7 - 16

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i*

i

n3

n2

n1

n4

n3

n2

ii1

n4

n3

ii2

JSRf

n4

sr1

–

sr2

sr1

sr3

sr2

sr1

sr4

sr3

sr2

sr5

RTI

sr3

n5

–

ii1

n5

Decode

Execute

JSRf NOP

RTI

NOP

Instruction

decode Order

1

2

3

4

5

6

7

8

9

instruction after the RTI is always fetched but not

decoded when RTI has been recognized

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i*

i

sr5

RTI

sr3

n5

–

ii1

n5

ii2

ii1

n5

n6

ii2

ii1

n7

n6

ii2

n8

n7

n6

n9

n8

n7

Decode

Execute

RTI

NOP

Instruction

decode Order

8

9

19

11

12

13

14

i = interrupt request

ii = interrupt instruction word

JSRf = fast JSR (JSR with 8-bit absolute address)

n = normal instruction word

sr = service routine word

* subsequent interrupts are enabled at this time

Figure 7-4 Long Interrupt Pipeline Action

MOTOROLA

PROCESSING STATES

7 - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i%

n4

i*

n3

n2

n1

n5

–

n6

n5

n4

ii1

n6

n5

ii2

ii1

n6

n7

ii2

ii1

n8

n7

ii2

n9

n8

n7

Decode

REP

n2

n4

Execute

REP NOP

Instruction

decode Order

1

2

3

4

5

6

7

8

9

10

11

i = interrupt request

ii = interrupt instruction word

n = normal instruction word

n3 = REP #2 instruction

n4 = instruction being repeated twice

n5 = instruction that waits in the backup instruction latch

% interrupt rejected at this time

* subsequent interrupts are enabled at this time

Figure 7-5

Example of Interrupt Service when

Interrupt is Presented to REP Instruction

viced, the interrupt is cleared. Each internal hardware source has independent enable

control and priority level control.

The external hardware interrupts include RESET, IRQA, and IRQB. The RESET interrupt

is level sensitive and is the highest level interrupt (priority 3). The IRQA and IRQB inter-

rupts can be programmed to be level sensitive or edge sensitive. The level sensitive

interrupts will not be cleared automatically when they are serviced and therefore must be

cleared by other means to prevent multiple interrupts. The edge sensitive interrupts are

latched as pending on the high-to-low transition of the interrupt input and automatically

cleared when the interrupt is serviced. IRQA and IRQB interrupts can be programmed to

one of three maskable priority levels: level 0, 1, or 2. Additionally, both of these interrupts

have independent enable control.

When the IRQA or IRQB interrupts are disabled in the IPR register, the pending request

will be ignored regardless of whether the interrupt input was defined as level sensitive or

edge sensitive. If the interrupt is defined as edge sensitive, its edge detection latch will

remain in the reset state as long as (1) the interrupt is disabled or (2) if the interrupt is

defined as level sensitive. If the level sensitive interrupt is disabled while the interrupt is

pending, the pending interrupt will be cancelled. However, if the first instruction of the

interrupt has been fetched, it will not be cancelled.

7 - 18

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Table 7-1 Interrupt Sources

Interrupt

Starting

Address

IPL

Interrupt Source

$0000

$0002

$0004

$0006

$0008

$000A

$000C

$000E

$0010

$0012

$0014

$0016

$0018

$001A

$001C

$001E

$0020

$0022

$0024

$0026

$0028

$002A

$002C

$002E

$0030

$0032

$0034

$0036

$0038

$003A

$003C

$003E

3

Hardware RESET

Illegal Instruction

Stack Error

Reserved

SWI

IRQA

IRQB

Reserved

SSI0 Receive Data with Exception Status

SSI0 Receive Data

SSI0Transmit Data with Exception Status

SSI0 Transmit Data

SSI1 Receive Data with Exception Status

SSI1 Receive Data

SSI1 Transmit Data with Exception Status

SSI1 Transmit Data

Timer Overflow

Timer Compare

Host DMA Receive Data

Host DMA Transmit Data

Host Receive Data

3

0-2

Host Transmit Data

Host Command (default)

Available for Host Command

Interrupt service starts by fetching the instruction word in the first vector location and is

considered finished when the fetch of the instruction word in the second vector location

happens. In the case of an edge-triggered interrupt, the internal latch is automatically

cleared when the second vector location is fetched. The fetch of the first vector location

DOES NOT GUARANTEE that the second location will be fetched. Figure 7-6 illustrates

one case where the second vector location is not fetched. In Figure 7-6 the SWI instruc-

tion “discards” the fetch of the first interrupt vector to ensure that the SWI vectors will be

fetched. Instruction n4 is decoded as a SWI while ii1 is being fetched. Execution of the

MOTOROLA

PROCESSING STATES

7 - 19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i*

i

i*

--

n3

n2

n1

n4

n3

n2

n5

ii1

--

ii3

--

ii4

sw1

--

sw2

sw1

--

sw3

sw2

sw1

sw4

sw3

sw2

Decode

SWI

n3

JSR

Execute

SWI

NOP NOP NOP

JSR

Instruction

decode Order

1

2

3

4

5

6

7

i = interrupt request

i* = interrupt request generated by SWI

ii1 = 1st vector of interrupt i

ii3 = 1st SWI vector (1-word JSR)

ii4 = 2nd SWI vector

n = normal instruction word

n4 = SWI

sw = instructions pertaining to the SWI long interrupt routine

Figure 7-6 Software Interrupt Mechanism

SWI requires that ii1 be discarded and the two SWI instructions (ii3 and ii4) be fetched

instead.

CAUTION

On all level sensitive interrupts, the interrupt must be externally released be-

fore interrupts are internally re-enabled or the processor will be interrupted

repeatedly until the interrupt is released.

7.3.5.2 Software Interrupt Sources

There are two software interrupt sources - Illegal Instruction Interrupt (III) and Software

Interrupt (SWI).

7.3.5.2.1

Illegal Instruction Interrupt

III is a non-maskable interrupt (IPL 3) which is serviced immediately following the execu-

tion of the ILLEGAL instruction or the attempted execution of an illegal instruction (any

undefined operation code). Illegal instruction interrupts are fatal errors. Only a long inter-

rupt routine should be used for the III routine. As shown in Figure 7-7, if a fast interrupt is

chosen, everything being frozen after the decode of n5 (II), this same instruction will be

decoded again after execution of the two fast interrupt words. Execution will therefore

loop forever between the illegal instruction and its fast interrupt routine. Even when a

long interrupt is used, no RTI or RTS should be used at the end of the interrupt routine,

since return from the illegal instruction interrupt to the main code will result in decoding

7 - 20

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

the illegal instruction again. During the illegal instruction interrupt service, the JSR

located in the III vector will normally stack the address of the illegal instruction. The user

may examine the stack (using MOVE SSH,dest) to locate the offending illegal instruc-

tion. The ILLEGAL instruction is useful for triggering the illegal interrupt service to see if

the III routine is capable of recovery from illegal instructions.

There are two cases in which the stacked address will not point to the illegal instruction:

1. If the illegal instruction is one of the two instructions at an interrupt vector loca-

tion, and is fetched during a regular interrupt service, the processor will stack

the address of the next sequential instruction in the normal instruction flow (the

regular return address of the interrupt routine that had the illegal opcode in its

vector).

2. If the illegal instruction follows a REP instruction (see Figure 7-8), the DSP will

effectively execute the illegal instruction as a repeated NOP, the interrupt vec-

tor will then be inserted in the pipeline. The next instruction will be fetched but

not decoded or executed. The processor will stack the address of the next se-

quential instruction (i.e., n8 in Figure 7-8) which is two instructions after the il-

legal instruction.

In DO loops, if the illegal instruction is in the LA location, and the instruction preceding it

(i.e. at LA-1) is being interrupted with a normal interrupt, the LC will be decremented as if

the loop had reached the LA instruction. When the interrupt service ends and the instruc-

tion flow returns to the loop, the illegal instruction will be refetched (since it is the next

sequential instruction in the flow). The loop state machine will again decrement LC

because the LA instruction is being executed. At this point, the illegal instruction will trig-

ger the illegal instruction interrupt. Notice that the loop state machine decremented LC

twice in one loop due to the presence of the illegal opcode at the LA location. This is a

special condition that only happens during this situation.

7.3.5.2.2 Software Interrupt

SWI is a non-maskable interrupt (IPL 3) which is serviced immediately following the soft-

ware interrupt instruction execution. A long interrupt service routine is usually used. The

difference between a SWI and a JSR instruction is that the SWI sets the interrupt mask

to prevent interrupts with an IPL below three from being serviced. Masking out lower

level interrupts makes the SWI very useful for setting breakpoints in monitor programs.

The JSR instruction does not affect the interrupt mask.

7.3.5.3 Stack Error Interrupt

The stack error interrupt is non-maskable (IPL 3). An overflow or underflow of the stack

causes a stack error interrupt (see Section 5 for additional information on the stack error

MOTOROLA

PROCESSING STATES

7 - 21

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

n3

n2

n1

n4

n3

n2

n5

n4

n3

n6

II

-

--

-

ii1

--

ii2

ii1

--

n5

ii2

ii1

Decode

--

II

-

Execute

n4

NOP

--

ii2

NOP

Instruction

decode Order

1

2

3

4

5

6

7

i = interrupt request

ii = interrupt instruction word

II = Illegal Instruction

P memory

i1

i2

P:$0004

n = normal instruction word

n3

n4

n5=II

n6

Figure 7-7

Infinite Looping on Fast Illegal Instruction Interrupt Processing

flag). The stack error interrupt is caused by a non-recoverable error condition and is vec-

tored to P:$0002. Since the stack error is non-recoverable, a long interrupt should be

used to service the interrupt and the service routine should not end in an RTI. Executing

a RTI instruction “pops” the stack which has already been corrupted.

7.3.6 Interrupt Priority Structure

Four levels of interrupt priority are provided. Interrupt priority levels (IPLs) numbered 0,

1, and 2, are maskable with level 0 as the lowest level. Level 3 (the highest level), is non-

maskable. The only level 3 interrupts are Reset, Illegal Instruction, Stack Error and SWI.

The interrupt mask bits (I1, I0) in the status register reflect the current processor priority

level and indicate the interrupt priority level needed for an interrupt source to interrupt the

processor (see Table 7-2). Interrupts are inhibited for all priority levels less than the cur-

rent processor priority level. However, level 3 interrupts are not maskable and therefore

can always interrupt the processor.

7 - 22

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXCEPTION PROCESSING (INTERRUPT PROCESSING)

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

n3

n2

n1

n4

n3

n2

n5

n4

n3

n6

REP

n4

n7

II

-

ii1

--

ii2

ii1

--

n8

ii2

ii1

Decode

--

n8

ii2

Execute

REP NOP

--

Instruction

decode Order

1

2

3

4

5

6

7

8

i = interrupt request

ii = interrupt instruction word

II = Illegal Instruction

n = normal instruction word

Figure 7-8 Repeated Illegal Instruction

Table 7-2 Status Register Interrupt Mask Bits

I1

I0

Exceptions

Permitted

Exceptions

Masked

0

1

0

1

0

1

IPL 0,1,2,3

IPL 1,2,3

IPL 2,3

None

IPL 0

IPL 0,1

IPL 0,1,2,

IPL 3

7.3.6.1 Interrupt Priority Levels (IPL)

The interrupt priority level for each on-chip peripheral device and for each external inter-

rupt source (IRQA, IRQB) can be programmed under software control. Each on-chip or

external peripheral device can be programmed to one of the three maskable priority lev-

els (IPL 0, 1, or 2). Interrupt priority levels are set by writing to the Interrupt Priority Reg-

ister shown in Figure 7-9. This read/write register specifies the interrupt priority level for

each of the interrupting devices (HOST, SSIs, Timer, IRQA, IRQB). In addition, this reg-

ister specifies the trigger mode of both external interrupt sources and it is used to enable

or disable the individual external interrupts. This register is cleared on RESET. Table 7-3

defines the interrupt priority level bits. Table 7-4 defines the external interrupt trigger

mode bits.

MOTOROLA

PROCESSING STATES

7 - 23

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

RESET STATE PROCESSING

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

TL TL S1L S1L S0L S0L HL HL

*

IBL IBL IBL IAL IAL IAL

1

0

1

0

1

0

1

0

2

1

0

2

1

0

IRQA IPL

IRQA mode

IRQB IPL

IRQB mode

Reserved

HOST IPL

SSI0 IPL

SSI1 IPL

TM IPL

*Read as zero and written with zero for future compatibility.

Figure 7-9 Interrupt Priority Register IPR (Addr X:$FFDF)

Table 7-3 Interrupt Priority Level Bits

xxL1 xxL0

Enabled

IPL

0

1

0

1

0

1

No

-

Yes

0

1

2

Table 7-4 External Interrupt Trigger Mode Bits

IxL2

Trigger Mode

0

1

Level

Negative Edge

7.3.6.2 Exception Priorities within an IPL

If more than one exception is pending when an instruction is executed, the interrupt with

the highest priority level is serviced first. When multiple interrupt requests with the same

IPL are pending, a second fixed priority structure within that IPL determines which inter-

rupt is serviced. The fixed priority of interrupts within an IPL and the interrupt enable bits

for all interrupts are shown in Table 7-5 The interrupt enable bits for the HOST, SSIs,

and TM are located in the control registers associated with their respective on-chip

peripherals.

7.4

RESET STATE PROCESSING

The reset processing state is entered in response to the external RESET pin being

asserted (a hardware reset). Upon entering the reset state:

7 - 24

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

WAIT STATE PROCESSING

1. internal peripheral devices are reset, and their pins revert to general-purpose

I/O pins.

2. the modifier registers are set to $FFFF.

3. the interrupt priority register is cleared.

4. the BCR is set to $43FF, thereby inserting 31 wait states in all external memory

accesses.

5. the stack pointer is cleared.

6. the loop flag, forever flag, scaling mode are cleared in the MR register, the in-

terrupt mask bits are set, and all CCR bits are cleared.

7. the OMR bits CD (Clockout Disable), SD (Stop delay), R (Rounding), SA (Sat-

uration) are cleared.

The DSP remains in the reset state until RESET is deasserted. Upon leaving the reset

state:

1. the chip operating mode bits of the OMR are loaded from the external mode se-

lect pins (MODA, MODB, MOBC).

2. program execution begins at program memory address $E000 in normal ex-

panded mode or at $0000 in all other operation modes. The first instruction

must be fetched and then decoded before executing. Therefore, the first in-

struction is executed two instruction cycles after the first instruction fetch. Two

NOPs are executed in the two instruction cycles before the first instruction is

executed.

The internal peripheral devices (HI, SSI0, SSI1, and ports A, B, and C) can be reset by

several methods – hardware (HW) reset, software (SW) reset, individual (I) reset, and

stop (ST) reset. Depending on the type of reset, the registers of these devices will be

affected differently (see SECTIONS 8,9,10,11,12 for additional information on the inter-

nal peripherals).

7.5

WAIT STATE PROCESSING

The wait processing state is a low power consumption state entered by execution of the

WAIT instruction. In the wait state, the internal clock is disabled to all internal circuitry

except the internal peripherals. All internal processing is halted until an unmasked inter-

rupt occurs or the DSP is reset. The bus arbitration circuits (BR, BG, and BB pins)

remain active during the Wait state if the DSP was in the slave mode (MC=0) before

entering the WAIT state. The wait state is one of two low power states.

MOTOROLA

PROCESSING STATES

7 - 25

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

WAIT STATE PROCESSING

Figure 7-10 shows a WAIT instruction being fetched, decoded, and executed. It is

fetched as n3 in this example and during decode is recognized as a WAIT instruction.

The following instruction (n4) is aborted and the internal clock is disabled from all internal

circuitry except the internal peripherals. The processor stays in this state until an inter-

rupt or reset is recognized. The response time is variable due to the timing of the inter-

rupt with respect to the internal clock. Figure 7-10 shows the result of a fast interrupt

bringing the processor out of the wait state. The two appropriate interrupt vectors are

fetched and put in the instruction pipe. The next instruction fetched is n4 which had been

aborted earlier. Instruction execution proceeds normally from this point on.

Figure 7-11 shows an example of the WAIT instruction being executed at the same time

that an interrupt is pending. Instruction n4 is aborted as before. There is a five instruction

cycle delay caused by the WAIT instruction and then the interrupt is processed normally.

The internal clocks are not turned off and the net effect is that of executing eight NOP

instructions between the execution of n2 and ii1.

7 - 26

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

WAIT STATE PROCESSING

Table 7-5 Exception Priorities within an IPL

Priority

Exception

Enabled by

Control Control

Register Register

Bit No. Address

Level 3 (Non-maskable)

Highest

Hardware RESET

Illegal Instruction Interrupt

Stack Error

—

Lowest

Highest

SWI

Level 0, 1, 2 (Maskable)

IRQA (External Interrupt)

IRQA

mode bits

0, 1

X:$FFDF

IRQB (External Interrupt)

IRQB

3, 4

mode bits

Host Command Interrupt

Host/DMA RX Data Interrupt

Host/DMA TX Data Interrupt

HCIE

HRIE

HTIE

RIE

2

0

X:$FFC4

X:$FFD1

1

SSI0 RX Data with

Exception Status

15

SSI0 RX Data

RIE

TIE

15

14

X:$FFD1

SSI0 TX Data with

Exception Status

SSI0 TX Data

TIE

RIE

14

15

X:$FFD1

X:$FFD9

SSI1 RX Data with

Exception Status

SSI1 RX Data

RIE

TIE

15

14

X:$FFD9

SSI1 TX Data with

Exception Status

SSI1 TX Data

TIE

OIE

CIE

14

9

X:$FFD9

X:$FFEC

Timer Overflow Interrupt

Timer Compare Interrupt

10

MOTOROLA

PROCESSING STATES

7 - 27

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

Int. Ctr cyc1

Int. Ctr cyc2

Fetch

i

i*

n3

n2

n1

n4

WAIT

n2

-

ii1

ii2

ii1

n4

ii2

ii1

n5

n4

ii2

n6

n5

n4

Decode

Execute

WAIT

-

Instruction

decode Order

1

2

3

4

5

6

i = interrupt request

ii = interrupt instruction word

n = normal instruction word

Figure 7-10 WAIT Instruction

During the wait state, the BR/BG/BB circuits remain active if the DSP was in the slave

mode. Before BR is asserted (see Table 7-6), all Port A signals are driven. The control

signals are deasserted, the data signals are inputs and the address signals remain as

the last address read or written. When BG is asserted, all signal are three-stated (high

impedance). Immediately after BR is deasserted, the R/W, PS/DS, and TS signals are

driven high — all other signals remain three-stated. During the first T0 clock state follow-

ing the exit from the wait state, control signals PS/DS, TS are again driven — the data

and address signals remain three-stated. During first external access, all signals return

to their normal operating mode.

Table 7-6 BR/BG During WAIT (Slave Mode)

Before BR

Asserted

While BG

Asserted Deasserted

After BR

After Return to

Normal State

from Wait State

After 1st

External Access

Signal

PS/DS

TS

Output

I/O

Hi-Z

Output

Hi-Z

Output

I/O

Output

(Read)

R/W

Data

Hi-Z

Address

Output

Hi-Z

Output

7.6

STOP STATE PROCESSING

The stop processing state is the lowest power consumption state and is entered by the

execution of the STOP instruction. In the stop state, all circuits are powered down except

7 - 28

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

Interrupt Synchronized and

Recognized as Pending

5 Instruction Cycle Delay

Int. Ctr cyc1

i

Int. Ctr cyc2

Fetch

i*

n3

n2

n1

n4

WAIT

n2

-

ii1

ii2

ii1

Decode

Execute

ii2

ii1

WAIT

-

Instruction

decode Order

1

2

3

4

5

i = interrupt request

ii = interrupt instruction word

n = normal instruction word

Figure 7-11 Simultaneous Wait Instruction and Interrupt

for (1) the ED register, (2) the PLL when it is enabled, and (3) the CLKO circuitry when

clockout is used. If the PLL and CLKO circuitry are not being used when the STOP

instruction is executed, they will be powered down; however, the input buffer used to

square EXTAL will still be active but will not dissipate power if the EXTAL pin is

grounded. The chip clears all peripherals and external interrupts (IRQA, IRQB) when

entering the stop state. Stack errors that were pending, remain pending. The priority lev-

els of the peripherals remain as they were before the stop instruction was executed. The

on-chip peripherals are held in their respective individual reset states while in the stop

state.

All activity in the processor is halted until one of the following actions occurs:

1. A low level is applied to the IRQA pin.

2. A low level is applied to the RESET pin.

Either of these actions will gate on the oscillator and, after a clock stabilization delay,

clocks to the processor and peripherals will be re-enabled. The clock stabilization delay

period is determined by the stop delay (SD) bit in the OMR.

The STOP sequence is composed of eight instruction cycles called STOP cycles. These

are differentiated from normal instruction cycles because the fourth cycle is stretched an

indeterminate period of time while the four phase clock is turned off.

MOTOROLA

PROCESSING STATES

7 - 29

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

IRQA

Fetch

Decode

Execute

STOP

n3

n2

n1

n4

-

n4

STOP

n2

STOP

-

cycle count

1

2

3

4

5

6

7

8

(9)

resume stop cycle count 4, in-

terrupts enabled

Clock Stopped

524KT or 28T cycle

count started

Figure 7-12 STOP Instruction Sequence

The STOP instruction is fetched in STOP cycle 1 of Figure 7-12, decoded in STOP cycle

2 (which is where it is first recognized as a stop command) and executed in STOP cycle

3. The next instruction (n4) is fetched during STOP cycle 2 but is not decoded in STOP

cycle 3 because, by that time the STOP instruction prevents the decode. The processor

stops the clock and enters the stop mode. The processor will stay in the stop mode until

it is restarted.

Figure 7-13 shows the case of the IRQA signal being asserted to exit the stop state. If

the exit from stop state was caused by a low level on the IRQA pin then the processor

IRQA

Fetch

Decode

Execute

n3

n2

n1

n4

STOP

n2

-

n4

STOP

-

STOP

cycle count

1

2

3

4

5

6

7

8

(9)

resume stop cycle count 4, in-

terrupts enabled

Clock Stopped

524KT or 28T cycle

count started

Figure 7-13 STOP Instruction Sequence Followed by IRQA

7 - 30

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

will service the highest priority pending interrupt. If no interrupt is pending then the pro-

cessor resumes at the instruction following the STOP instruction that caused the entry

into the stop state.

An IRQA deasserted before the end of the STOP cycle count will not be recognized as

pending. If IRQA is asserted when the STOP cycle count completes, then an IRQA inter-

rupt will be recognized as pending and arbitrated with any other interrupts if the IRQA

was defined as level sensitive.

Specifically, when IRQA is asserted, the internal clock generator is started and begins a

delay determined by the SD bit of the OMR. If the internal clock oscillator is used, the SD

19

bit should be set to 0 which enables a delay count of 524K T cycles (i.e., [2 -4]T cycles)

to allow the clock oscillator to stabilize. If a stable external clock is used, the SD bit may

5

be set to 1 which enables a 28 T (i.e., [2 -4]T) cycle delay.

The following description assumes that SD=0 (the 524K T counter is used). During the

524K T count, interrupts are ignored until the last few count cycles. At this time, the inter-

rupts are synchronized. At the end of the 524K T cycle delay period, the chip restarts

instruction processing, the 4th stop cycle is completed (interrupt arbitration occurs at this

time) and stop cycles 5,6,7, and 8 are executed (it takes 17T from the end of the 524K T

delay to the first instruction fetch). If the IRQA signal is released (pulled high) after 4T

minimum but less than 524K T cycles, no IRQA interrupt will occur and the instruction

fetched after STOP cycle 8 will be the next sequential instruction (n4 in Figure 7-14). An

IRQA interrupt will be serviced (as shown in Figure 7-13) if (1) the IRQA signal had previ-

ously been initialized as level sensitive, (2) it is held low from the end of the 524K T cycle

delay counter to the end of stop cycle count 8, and (3) no interrupt with a higher interrupt

level is pending. If IRQA is not asserted during the last part of the STOP instruction

sequence (6,7, and 8), and no interrupts are pending, the processor will refetch the next

sequential instruction (n4). Since in Figure 7-13 the IRQA signal is asserted, the proces-

sor will recognize the interrupt and then fetch and execute the instructions at P:$0008

and P:$0009 which are the IRQA interrupt vector locations.

To ensure servicing IRQA immediately after leaving the STOP state, the following steps

must be taken before the execution of the STOP instruction:

1. Define IRQA as level sensitive.

2. Define IRQA priority as higher than the other sources and higher than the pro-

gram priority.

3. Ensure that no stack error is pending.

MOTOROLA

PROCESSING STATES

7 - 31

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

4. Execute the STOP instruction and enter the STOP state.

5. Recover from the STOP state by asserting the IRQA pin and holding it asserted

for the whole clock recovery time. If it is low, the IRQA vector will be fetched.

6. The exact elapsed time for clock recovery is unpredictable, the external device

that asserts IRQA must wait for some positive feedback, like a specific memory

access or a change in some predetermined I/O pin, before deasserting IRQA.

19

The STOP sequence totals 524K T cycles (i.e., [2 -4]T cycles) if SD=0 or 28 T cycles (if

SD=1) in addition to the period with no clocks from the STOP fetch to the IRQA vector

fetch (or next instruction). However, there is an additional delay if the internal oscillator is

used. An indeterminate period of time is needed for the oscillator to begin oscillating and

then stabilize its amplitude. The processor will still count 524K T cycles but the period of

the first oscillator cycles will be irregular so an additional period of approximately 20,000

T should be allowed for this to happen. If an external oscillator is used and it is already

stabilized, no additional time need be provided.

If the STOP instruction is executed when the IRQA signal is asserted, the clock genera-

tor will not be stopped, but the 4-phase clock will be disabled for the duration of the 524K

T cycle (or 28 T cycle) delay count. This means that in this case the STOP looks like a

524K + 32 T cycle (or 28T+ 32T cycle) NOP, since the STOP instruction itself is 8

instruction cycles long (32 T).

A stack error interrupt pending before entering the STOP state is not cleared and will

remain pending. During the clock stabilization delay, all peripheral and external interrupts

are cleared and ignored except stack error. If the on-chip peripherals have interrupts

enabled in (1) their respective control registers and (2) in the interrupt priority register,

then interrupts will be immediately pending after the clock recovery delay and will be ser-

viced before continuing with the next instruction. If peripheral interrupts must be dis-

abled, the user should disable them either with the control registers or with the interrupt

priority register before the STOP instruction is executed.

If the RESET pin had been used to restart the processor (see Figure 7-14), the 524K T

cycle delay counter would not have been used, all pending interrupts would be dis-

carded, and the processor would immediately enter the RESET processing state. The

stabilization time required for the clock (RESET should be asserted for this time) is only

50 T for a stabilized external clock but is the same 550,000 T for the internal oscillator.

These stabilization times are recommended times and are not imposed by internal timers

or time delays. The DSP fetches instructions immediately when it exits reset. If the user

wishes to use the 524K T (or 28 T) delay counter, it can be started by asserting IRQA for

a short time (about 2 clock cycles) to exit the stop state.

7 - 32

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

RESET

Fetch

Decode

Execute

n3

n4

-

n4

n2

n1

STOP

n2

STOP

-

STOP

cycle count

1

2

3

4

5

6

7

8

(9)

processor leaves RESET state

Clock Stopped

enter RESET state

Figure 7-14 STOP Instruction Sequence Recovering with RESET

When in the stop state, the Port A bus is “frozen”. The state of each pin immediately

before executing the STOP instruction will be held until the DSP leaves the stop state.

Port A is not three-stated and the BR/BG/BB circuits are not operational. However, Port

A will remain three- stated if BG was asserted (in the slave mode) before the STOP com-

mand was executed. One way to release the Port A bus for use while the DSP is in the

STOP state is to use a Port B or Port C pin to assert BR (in the slave mode) before exe-

cuting the STOP instruction.

MOTOROLA

PROCESSING STATES

7 - 33

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

STOP STATE PROCESSING

7 - 34

PROCESSING STATES

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 8

BUS OPERATION

MOTOROLA

BUS OPERATION

8 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

8.1

8.2

8.3

8.3.1

8.3.2

8.3.3

8.3.4

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

SYNCHRONOUS BUS OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . 8-3

BUS HANDSHAKE AND ARBITRATION . . . . . . . . . . . . . . . . . . . . . . 8-5

Bus Arbitration signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5

Bus Arbitration between Two DSPs . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6

Bus Arbitration between a DSP56156 and an MC68020 . . . . . . . . . . 8-7

Bus Arbitration with External Bus Arbitrator . . . . . . . . . . . . . . . . . . . . 8-9

8 - 2

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

8.1

INTRODUCTION

DSP56100 family external bus timing is defined by the operation of the Address Bus,

Data Bus, and Bus Control pins described in the User’s Manual for each of the DSPs in

the DSP56100 family. The external bus is designed to interface with a wide variety of

memory and peripheral devices, from high speed static RAMs to slower memory

devices. Figure 8-1 shows a static RAM design using 15 ns memories.

Vcc

MCM6209-15

E

Program

OE

and

data

RD

WE

WR

DSP56156

A15

memory

64K x 4 bits

PS/DS

A0-A14

D0-D15

CS

D0-D15

TA

Figure 8-1

Example of SRAM Connection to a 60 MHz DSP56156 Using One Wait-State

External bus timing is controlled by the TA control signal and by the Bus Control Regis-

ters (BCR). The BCR and TA control the bus interface signal timing. Wait state insertion

is controlled by the BCR to provide fixed bus access timing, and by TA to provide

dynamic bus access timing. The number of wait states is determined by the TA input or

by the BCR, whichever is longer.

8.2

SYNCHRONOUS BUS OPERATION

A synchronous external bus cycle consists of at least 4 internal clock phases. Each syn-

chronous external memory access requires the following procedure:

1. The external memory address is defined by Address Bus A0-A15 and Memory

Reference signal PS/DS. These signals change in the first phase of the exter-

nal bus cycle. Memory Reference signal PS/DS has the same timing as the

Address Bus and may be used as an additional address line. The Address sig-

nals and PS/DS are also used to generate chip select for the appropriate

memory chips. Chip select changes the memory devices from low power

standby mode to active mode and begins the read access time. This allows

slower memories to be used since the chip select signals are address based

rather than read or write enable based.

MOTOROLA

BUS OPERATION

8 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SYNCHRONOUS BUS OPERATION

2. When the Address lines and PS/DS are stable, data transfer is enabled by the

Transfer Strobe TS signal. TS is asserted to qualify the Address signals and

PS/DS as stable and to perform the read or write data transfer. TS is asserted

in the second phase of the bus cycle.

3. Wait states are inserted into the bus cycle controlled by a wait state counter or

by TA, whichever is longer. The wait state counter is loaded from the BCR. If

the wait state number determined by these two factors is zero, no wait state is

inserted into the bus cycle and TS is deasserted in the fourth phase. If the wait

state number determined is W, then W wait states are inserted into the instruc-

tion cycle. Each wait state introduces one clock cycle delay (two phases

each). TA is sampled by the DSP on every rising edge of T2.

4. When Transfer Strobe TS is deasserted at the end of a bus cycle, the data is

latched in the destination device. At the end of a read cycle, the DSP latches

the data internally. At the end of a write cycle, the external memory latches the

data. The Address signals remain stable until the first phase of the next exter-

nal bus cycle to minimize power dissipation. The PS/DS signal is set high dur-

ing periods of no bus activity and the data signals are three-stated.

E0

AWE0

AWE1

E1

TA

R/W

TS

SWE

G

MCM6290-20

16Kx16bits

Synchronous

RAM

16-bit

DSP

A13

PS/DS

address

data

A0-A12

D0-D15

EXTAL

CLK

OSC

50 MHz

CLK

DLE

CLK*

Figure 8-2

MCM6290 16K x 16 Synchronous SRAM Used in 50 MHz 16-bit DSP System

8 - 4

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

Figure 8-2 shows an example of a 50 MHz 16-bit DSP connected to a 16K x 16-bit, 20

ns, synchronous RAM. Note that the PS/DS control signal is used as an additional

address line allowing a single external memory device to be used to store both program

(8k words) and data (8k words) memory.

8.3

BUS HANDSHAKE AND ARBITRATION

Bus transactions are governed by a single bus master. Bus arbitration determines which

device becomes the bus master. The arbitration logic implementation is system depen-

dent, but must result in at most one device becoming the bus master (even if multiple

devices request bus ownership) at any given time.

8.3.1 Bus Arbitration signals

Three signals are provided for bus arbitration. These signals are:

BR

Bus Request: Input in the slave mode; output in the master mode

In the master mode, this output is asserted by the DSP requesting the bus to

indicate that the DSP wants to use the bus. The output is held asserted until the

DSP no longer needs the bus. This includes when the DSP is the bus master

as well as when it is not actively using the bus but retains bus mastership.

In the slave mode, this input is asserted by an external device to indicate to the

DSP that the external device wants control of the external bus. In the slave

mode, when BR is asserted, the DSP always relinquishes the bus.

BG

BB

Bus Grant: Output in the slave mode; input in the master mode

In the master mode, this input is asserted by the bus arbitration controller to sig-

nal the DSP that the DSP is the bus master-elect. BG is valid only when the bus

is not busy. The Bus Busy signal is described below.

In the slave mode, this output pin is asserted by the DSP in response to a bus

request BR. When BG is asserted, the DSP no longer drives the bus.

Bus Busy: Output when bus master; input when not bus master

This pin is asserted by the device (bus master) that received bus ownership

from the bus arbitration controller. The master holds BB asserted for the dura-

tion of its bus possession. When asserted, BB indicates that the DSP is driving

the bus. BB deasserted indicates that the DSP is not driving the bus. BB may

be used as a three-state enable control for external address, data and bus con-

trol signal buffers.

MOTOROLA

BUS OPERATION

8 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

The BB input is monitored by the DSP when it is the potential bus master (i.e.,

after BG has been asserted). The DSP will become bus master when BB is

deasserted.

Note: A DSP which is programmed as a bus master comes out of reset without pos-

session of the bus. A DSP which is programmed as a bus slave comes out of

reset with possession of the bus.

8.3.2 Bus Arbitration between Two DSPs

Figure 8-3 shows two DSPs sharing the same external bus. The three bus arbitration

pins BR, BG, and BB allow for direct connection without external logic. The bus arbitra-

tion is explained below.

The two DSPs in Figure 8-3 share a common clock and common hardware reset cir-

cuitry. DSP-1 leaves the reset state in the master mode (MC tied high) while DSP-2

leaves the reset state in the slave mode (MC tied low).

Figure 8-4, Figure 8-5, and Figure 8-6 show the bus arbitration between the two proces-

sors.

When DSP-1 needs the bus for an external access, BRm is asserted during T0. BGm is

sampled by DSP-1 during the clock’s falling edge. When BGm is asserted by DSP-2,

RESET

CLK

DSP-1

DSP-2

BRm

BGm

BB

BRs

BGs

BBs

MC

VCC

MC

data

Master

Mode

Slave

Mode

address

control

Shared

External

Memory

Figure 8-3 Bus Arbitration Between Two 16-bit DSPs

8 - 6

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

DSP-1 starts sampling BB on the clock’s falling edge and starts a bus cycle on the

clock’s first rising edge after BB is sampled and recognized. DSP-1 then assumes bus

mastership by asserting BB. DSP-1 deasserts BRm when BGm has been received and

the external bus is released. BRm is deasserted during T0. BB remains asserted as long

as DSP-1 drives the bus.

When DSP-2 receives a bus request on its BR input, it will three-state its A0-A15, D0-

D15, TS, R/W, PS/DS pins at the earliest possible time while deasserting the BB pin. It

then asserts BG and its BB pin becomes an input. When the BR input is deasserted,

DSP-2 deasserts BG and DSP-2 regains bus control after sampling and recognizing BB

as deasserted.

When the master wishes to “park” on the bus (i.e., remain master even when it is not

making external accesses) it can set the RH bit in the BCR. This causes BR to remain

asserted until the RH bit is cleared. Bus parking is illustrated in Figure 8-5.

8.3.3 Bus Arbitration between a DSP56156 and an MC68020

Figure 8-7 shows a DSP in the master mode sharing the same external bus with an

MC68020. The three bus arbitration pins BR, BG, and BB allow direct connection without

external logic. The bus arbitration is explained below.

After hardware RESET, the DSP is set in the master mode (MC is tied is to VCC).

T0 T1 T2 Tw T2 Tw T2 Tw T2 Tw T2 Tw T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0

DSP-1

CLK

T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2

DSP-2

slave samples BR

slave recognizes BR

slave samples BR

CLK

master recognizes BG

slave grants the bus

master samples BG

BR

master gets on the

bus

master samples

BB high

master

recognizes BB high

BG

BB

slave drives the bus

master drives the

bus

Figure 8-4 Master Requests and Gets the Bus for One Access

MOTOROLA

BUS OPERATION

8 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2

T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0

DSP-1

CLK

DSP-2

CLK

slave samples

BR

slave recognizes

BR

master samples

master recognizes

BG

slave deasserts BG

slave recognizes

BB high

slave samples

BR

BG

BB

BB high

slave gets on the

master gives

up bus

bus

slave drives the bus

Figure 8-5 Slave Gets the Bus Back After One Master Access

T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2 T3 T0 T1 T2

DSP-1

CLK

slave recognizes BR

RH set by

Master

DSP-2

CLK

slave samples BR

Master asserts BR even if no access

master samples BG

Slave grants

the bus

BR

BG

BB

master gets on the

master samples BB high

bus

slave drives the bus

master drives the

bus

This pattern repeats each

time the master accesses

the bus while RH=1; BB

will stay asserted as long

as DSP owns the bus.

Figure 8-6 Bus Parking by the Master

When the DSP needs the bus for an external access, it asserts BR. When BGm is

8 - 8

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

asserted by the MC68020, the DSP starts a bus cycle after sampling BB and BB is deas-

serted. The DSP assumes bus mastership by asserting BB and then deasserts BR if it

only wants the bus for one cycle. BR remains asserted for a series of consecutive exter-

nal accesses or when the bus request hold bit (RH) of the BCR register is set. BB

remains asserted as long as the DSP drives the bus and as long as BG remains

asserted. When BG is deasserted, BB is deasserted at the end of the last external bus

access.

When the MC68020 receives a bus request on its BR input, it will assert BG at the earli-

est possible time. BG will not be asserted until the end of a read-modify-write operation.

BG will be deasserted by the MC68020 when the new bus master has asserted BGACK.

8.3.4 Bus Arbitration with External Bus Arbitrator

Systems that include several devices that can become bus master require external cir-

cuitry to assign priorities to the devices. This circuitry allows only the device with the

highest priority to become bus master when two or more devices attempt to become bus

master simultaneously. Figure 8-8 shows an example of bus arbitration with several

DSPs and other CPUs.

Bus arbitration is handled by a central bus arbitrator, using individual request/grant lines

to each potential bus master. The arbitration protocol can operate in parallel with bus

transfer activity allowing fast bus acquisition. The arbitration sequence occurs as follows:

1. All candidates for bus ownership assert their respective BR signals as soon as

DSP56156

MC68020

BR

BG

BB

BR

BG

BGACK

Vcc

MC

data

16-bit

DSP

Master

address

control

Shared

External

Memory

Figure 8-7 Bus Arbitration Between a DSP56156 and an MC68020

MOTOROLA

BUS OPERATION

8 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

they need the bus.

2. The arbitration logic designates a bus master-elect by asserting the BG signal

for that device.

3. The master-elect tests BB to insure that the previous master has relinquished

the bus. If BB is deasserted, then the master-elect takes control of the bus. If a

higher priority bus request occurs before the BB signal was deasserted, then

the arbitration logic may replace the current master-elect with the higher prior-

ity candidate (Figures 15-8 and 15-9 show the arbitration timing). However,

only one BG signal is allowed be asserted at any one time.

4. The new bus master begins its bus transfers after BB is asserted.

5. At anytime, the arbitration logic can signal the current bus master to relinquish

the bus by deasserting BG. A DSP56156 bus master releases its ownership

(deasserts BB) after completing the current external bus access and after rec-

ognizing BG is deasserted. If BG is not deasserted, the DSP56156 bus master

does not deassert BR, remains bus master, and continues to assert BB. If an

instruction is executing a Read-Modify-Write external access, the DSP will

only relinquish the bus after completing the whole Read-Modify-Write

sequence.

The DSP56156 has one control bit (RH) to permit software control of the BR and one

status bit (BS) to verify whether it owns the bus mastership. If the RH bit in the BCR reg-

ister is set, the DSP holds its BR signal asserted as long as requests for bus transfers

BUS ARBITER

BR1

BG1

BR2

BG2

BRn

BGn

CPU

DSP56156 #2

DSP56156 #1

BB1

BB2

BBn

Figure 8-8 Bus Arbitration Between Several 16-bit DSPs and Other Processors

8 - 10

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

are pending. As long as the RH bit is set, BR will remain asserted. This situation is called

“bus parking” and allows the current bus master to use the bus repeatedly without re-

arbitration.

MOTOROLA

BUS OPERATION

8 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BUS HANDSHAKE AND ARBITRATION

8 - 12

BUS OPERATION

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 9

DSP56100 FAMILY ON-CHIP PLL

xdx

∫

Φ

VCO

MOTOROLA

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

9 - 1

Freescale Semiconductor, Inc.

SECTION CONTENTS

9.1

9.2

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-3

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR0 . . . . . 9-4

PCR0 Feedback Divider Bits (YD7-YD0) Bits 0-7 . . . . . . . . . . . . . . . . 9-4

PCR0 Input Divider Bits (ID3-ID0) Bits 8-11 . . . . . . . . . . . . . . . . . . . . 9-5

PCR0 Power Divider Bits (PD3-PD0) Bits 12-15 . . . . . . . . . . . . . . . . 9-5

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1 . . . . . 9-5

PCR1 Reserved Bits — Bits 0-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5

PCR1 CLKO Select Bits (CS1-CS0) Bits 10 and 11 . . . . . . . . . . . . . . 9-5

PCR1 Phase Select Bit (PS) Bit 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

PCR1 PLL Power Down Bit (PLLD) Bit 13 . . . . . . . . . . . . . . . . . . . . . 9-6

PCR1 PLL Enable Bit (PLLE) Bit 14 . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6

PCR1 Voltage Controlled Oscillator Lock Bit (LOCK) Bit 15 . . . . . . . . 9-7

9.2.1

9.2.2

9.2.3

9.3

9.3.1

9.3.2

9.3.3

9.3.4

9.3.5

9.3.6

9 - 2

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

MOTOROLA

Freescale Semiconductor, Inc.

INTRODUCTION

9.1

INTRODUCTION

The DSP56100 Family does not contain an on-chip oscillator. An external system clock

must be provided through the EXTAL input pin. The on-chip phase locked loop (PLL) can

be used to generate the DSP5616 core system clock or it can be bypassed allowing the

DSP5616 core to directly use the clock provided on the EXTAL pin.

Figure 9-1 shows the general block diagram of the on-chip frequency synthesizer.

The 4-bit divider ID3-ID0 defines the resolution of the PLL and divides the incoming clock

rate fed to the PLL. The eight down counter bits YD7-YD0 control down counting in the

PLL feedback loop causing it to divide by the value YD+1 (any number between 1 and

256) which effectively multiplies the frequency out of the PLL. The VCO output can be di-

0

15

vided down by any power of 2 between 2 and 2 before entering the core using the 4-

bits PD3-PD0 of the control register PCR1. The system frequency on the DSP core is con-

trolled by the frequency control bits of the PLL control register PCR0 as follows:

PD

Fosc = {Fext÷[ID+1]}x[YD+1]÷ (2 )

where ID is the value contained in ID3-ID0, YD is the value contained in YD7-YD0, and

PD is the value contained in PD3-PD0. Fext is a squared and delayed version of the clock

signal applied to the EXTAL input pin.

Note: The STOP instruction does not power down the PLL if the PLL is enabled

(PLLD=0) when entering the STOP mode. STOP will power down the ID register if

the PLL is disabled (PLLD=1) when entering the STOP mode. (see Section 9.3.4).

MOTOROLA

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

9 - 3

Freescale Semiconductor, Inc.

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR0

XCF

0.01µF

0.1µF

SXFC

GNDS

VDDS

100KΩ

EXTAL

ID3-ID0

PD3-PD0

PLLE=1

PLLE=0

PHASE

COMP.

÷ 1 to ÷16

4-bit Divider

0

15

Filter

VCO

÷ 2 to ÷2

Fosc

1000pF

4-bit Power Of 2 Divider

YD7-YD0

CS1-CS0

÷ 1 to ÷256

PS=0

PS=1

8-bit PLL Down Counter

CLKO

÷ 2

Internal Phase PH0

On-chip Frequency Synthesis Control/Status Registers

15

14

13

12

PS

11

CS1

10

CS0

9

*

8

*

READ-WRITE

PLL CONTROL

REGISTER (PCR1)

ADDRESS $FFDC

LOCK PLLE PLLD

7

*

6

*

5

*

4

*

3

*

2

*

1

*

0

*

15

PD3

14

PD2

13

PD1

12

PD0

11

ID3

10

ID2

9

ID1

8

ID0

READ-WRITE

PLL CONTROL

REGISTER (PCR0)

ADDRESS $FFDB

7

YD7

6

YD6

5

YD5

4

YD4

3

YD3

2

YD2

1

YD2

0

YD0

*: Reserved bits

Figure 9-1 DSP56100 Family Frequency Synthesizer

Block Diagram and Control Registers

9.2

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR0

The Clock Synthesis Control Register PCR0 is a 16-bit read/write register used to direct

the operation of the on-chip clock synthesis. The PCR0 controls the frequency program-

ming of the PLL. The PCR0 control bits are described in the following sections.

All PCR0 bits of are cleared by DSP hardware. Software reset does not affect this register.

9.2.1

PCR0 Feedback Divider Bits (YD7-YD0) Bits 0-7

The eight feedback divider bits YD7-YD0 control the down counter in the feedback loop,

causing it to divide by the value YD+1 where YD is the value contained in the eight bits.

Changing these bits requires a time delay for the Voltage Controlled Oscillator (VCO) to

lock again.

9 - 4

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

MOTOROLA

Freescale Semiconductor, Inc.

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1

The LOCK bit is cleared any time a new value is written to the YD bits.

The resulting DSP core system clock must be within the limits specified by the technical

data sheet. The frequency of the VCO should also remain higher than the minimum value

specified in this data sheet.

9.2.2

PCR0 Input Divider Bits (ID3-ID0) Bits 8-11

The four input divider bits are used to divide the input clock frequency by any number be-

tween 1 and 16. The output of the divider is used as input for the phase comparator of the

PLL. If ID is the value contained in the four bits, the input clock to the PLL is divided by

ID+1.

Any time a new value is written to the ID bits, the LOCK bit is cleared.

9.2.3

PCR0 Power Divider Bits (PD3-PD0) Bits 12-15

The four power divider bits are used to divide the VCO output clock frequency by any pow-

0

15

er of two between 2 and 2 (i.e., 1, 2, 4, 8, 16, 32, …, 16384, or 32768). The output of

the divider can be used as the operating clock for the DSP core, as shown in Figure 9-1.

Writing to the PD bits does not affect the LOCK condition of the PLL.

The PD bits can be used to switch the DSP core back and forth from a high MIPS rate to

a very low speed, low power mode without having to wait and check for the PLL to lock

on a new frequency.

9.3

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1

The Clock Synthesis Control Register PCR1 is a 16-bit read/write register used to direct

the operation of the on-chip clock synthesizer. The PCR1 control bits are described in the

following sections.

All PCR1 bits are cleared by DSP hardware. Software reset does not affect this register.

9.3.1

PCR1 Reserved Bits — Bits 0-9

These bits are reserved and should be written as zero by the user.

9.3.2 PCR1 CLKO Select Bits (CS1-CS0) Bits 10 and 11

The two CLKO Select bits CS1-CS0 enable one of three possible clocks to be output to

the CLKO pin when the CD bit in the OMR register is cleared (see Figure 9-1). After hard-

ware reset, the internal DSP core clock PH0 (phase zero) is output to the CLKO pin. PH0

is a delayed version of the DSP core master clock, Fosc. Changing the value of the two

bits CS1-CS0 according to Table 9-1, Fext or Fext/2 can be selected to be output on CL-

KO. Fext is a squared and delayed version of the signal applied to the EXTAL input pin.

MOTOROLA

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

9 - 5

Freescale Semiconductor, Inc.

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1

Table 9-1 CLKOUT Pin Control

CS1

CS0

CLKO

0

1

0

1

0

1

PH0

Reserved

Fext

Fext/2

9.3.3

PCR1 Phase Select Bit (PS) Bit 12

This bit is used to select the DSP core clock when the PLL output is not selected

(PLLE=0). When this bit is cleared, a squared version of EXTAL is selected as Fosc.

When this bit is set, the output of the ID divider is selected as Fosc.

9.3.4

PCR1 PLL Power Down Bit (PLLD) Bit 13

When the PLLD bit is set, the on-chip PLL is powered down. When this control bit is

cleared, the on-chip PLL is turned on. This bit should not be set when the PLLE bit is set.

If the PLL has to be turned off before entering the STOP mode, the following sequence

will have to be executed before the STOP instruction:

- Clear the PLLE bit (switch back to EXTAL)

- Set the PLLD bit (power down the PLL)

- Execute the STOP instruction.

Setting the PLLD bit clears the LOCK bit. Setting the PLLD bit powers down the complete

PLL block including the PD and YD registers.

9.3.5

PCR1 PLL Enable Bit (PLLE) Bit 14

When the PLLE bit is set, the DSP5616 core system clock is generated by the on-chip

PLL. Table 9-2 summarizes the function of the three bits — PLLE, PLLD and PS. The

state of the PLL is defined by the PLLD bit. When the PLLD bit is set, the PLL is in the

power down mode. When the PLLD bit is cleared, the PLL is in the active mode. Before

turning the PLL off, the PLLE bit should be cleared in order to by-pass the PLL. The PLL

can then be put in power down mode by setting PLLD.

If the output frequency of the PLL has to be changed by re-programming the YD bits while

the PLL output is used by the core (PLLE=1; PLLD=0), the following sequence of opera-

tions should be performed:

- Clear the PLLE bit to switch back to EXTAL

9 - 6

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

MOTOROLA

Freescale Semiconductor, Inc.

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1

- Program the YD bits (only after clearing PLLE)

- Wait for the LOCK bit to be set

- Set PLLE after the LOCK bit is tested high.

Table 9-2 PLL Operations

PLLE

PLLD

PS

Fosc

PLL Mode

0

1

0

1

0

1

0

1

0

1

x

Fext

Active

Power Down

Active

Fext÷[ID+1]

Power Down

Active

PD

{Fext÷[ID+1]}x[YD+1]÷ (2

Reserved

)

—

9.3.6

PCR1 Voltage Controlled Oscillator Lock Bit (LOCK) Bit 15

This status bit shows whether the Voltage Controlled Oscillator (VCO) has locked on the

desired frequency or not. When the LOCK bit is set, the VCO has locked; when the LOCK

bit is cleared, the VCO has not locked yet. This bit is cleared when setting the PLLD bit

and when changing the value of ID or YD bits. The LOCK bit is not cleared when clearing

the PLLE bit without changing the values of PLLD, YD, or ID.

This bit is read-only and cannot be written by the DSP core.

MOTOROLA

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

9 - 7

Freescale Semiconductor, Inc.

ON-CHIP CLOCK SYNTHESIS CONTROL REGISTER PCR1

EXTAL

CLKO

ID3-ID0

PD3-PD0

PLLE=1

PHASE

COMP.

÷ 1 to ÷16

0

15

Filter

VCO

÷ 2 to ÷2

4-bit Power of two Divider

Fosc

4-bit Divider

PS=0 PS=1

YD7-YD0

CS1-CS0

PLLE=0

÷ 1 to ÷256

8-bit PLL Down Counter

÷ 2

Internal Phase PH0

On-chip Frequency Synthesis Control/Status Register (PCR1) ADDRESS X:$FFDC

15

14

13

12 11

10

9

8

7

6

5

4

3

2

1

0

LOCK PLLE PLLD PS CS1 CS0

** **

**

** **

**

LOCK

0

1

PLL unlocked

PLL locked

PLLE PLLD 00

PLL active but not used as Fosc

PLL powered down

PLL active and used as Fosc

Reserved

01

10

11

PHASE

SELECT

CS1-CS0

CLKO

0

1

00

01

10

11

Squared EXTAL selected as Fosc if PLLE=0

Squared EXTAL/ID selected as Fosc if PLLE=0

PH0 output to CLKO when enabled by the CD bit (bit 7) of the OMR

reserved

Fext output to CLKO when enabled by the CD bit (bit 7) of the OMR

Fext/2 output to CLKO when enabled by the CD bit (bit 7) of the OMR

Select

On-chip Frequency Synthesis Control/Status Register (PCR0) ADDRESS X:$FFDB

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

PD3 PD2 PD1 PD0 ID3

ID2 ID1 ID0 YD7 YD6 YD5 YD0 YD3 YD2 YD1 YD0

0

8

PD3-PD0

Clock

$0

$1

$2

$3

$4

$5

$6

Divide the VCO output clock by 1 (2 )

8

9

Divide the VCO output clock by 256 (2 )

1

9

Divide the VCO output clock by 2 (2 )

Divide the VCO output clock by 512 (2 )

2

10

Output

Divider

Divide the VCO output clock by 4 (2 )

A

B

C

D

E

Divide the VCO output clock by 1024 (2

Divide the VCO output clock by 2048 (2

Divide the VCO output clock by 4096 (2

Divide the VCO output clock by 8192 (2

Divide the VCO output clock by 16384 (2

)

14

15

3

11

12

13

Divide the VCO output clock by 8 (2 )

4

Divide the VCO output clock by 16 (2 )

5

Divide the VCO output clock by 32 (2 )

6

Divide the VCO output clock by 64 (2 )

)

7

$7

$0

$1

$2

$3

$4

$5

$6

$7

Divide the VCO output clock by 128 (2 )

Divide the input clock by 1

Divide the input clock by 2

Divide the input clock by 3

Divide the input clock by 4

Divide the input clock by 5

Divide the input clock by 6

Divide the input clock by 7

Divide the input clock by 8

F

8

9

A

B

C

D

E

F

Divide the VCO output clock by 32768 (2

Divide the input clock by 9

Divide the input clock by 10

Divide the input clock by 11

Divide the input clock by 12

Divide the input clock by 13

Divide the input clock by 14

Divide the input clock by 15

Divide the input clock by 16

ID3-ID0

Input

Clock

Divider

YD7-YD0

VCO

Down

$YD

Multiplies by YD+1

Counter

value

Figure 9-2 On-Chip Frequency Synthesizer Programming Model Summary.

9 - 8

D_FS_oP_r5_M6_o1_r_G_e0_o0_In_t_f_oF_o_:A_r_w_mM_w_aI_t_wL_io_.Y_f_n_re_OO_e_n_sN_c_T-_a_hC_l_i_e_sH_.c_PIP_o_ro_m_dP_uL_cL_t,

MOTOROLA

Freescale Semiconductor, Inc.

SECTION 10

ON-CHIP EMULATION (OnCE)

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

10.10

10.11

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

EMULATION AND TEST PINOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3

ONCE CONTROLLER AND SERIAL INTERFACE . . . . . . . . . . . . . . 10-5

OnCE BREAKPOINT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-9

TRACE/STEP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11

METHODS OF ENTERING THE DEBUG MODE . . . . . . . . . . . . . . . . 10-12

PIPELINE INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-14

PAB HISTORY BUFFER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-15

SERIAL PROTOCOL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . 10-18

DSP56100 TARGET SITE DEBUG SYSTEM REQUIREMENTS . . . 10-20

USING THE OnCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-21

10 - 2

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

10.1 INTRODUCTION

The purpose of this Section is to describe a set of circuits which will be used for hardware/

software emulation and debug on the DSP56100 family. OnCE provides a means of inter-

acting with the DSP and any memory mapped peripherals non-intrusively so that a user

may examine registers, memory or on-chip peripherals. To achieve this, special circuits

and dedicated pins on the DSP are used to avoid sacrificing any user accessible on-chip

resource. A key feature of the special OnCE pins is to allow the user to insert the DSP into

his target system yet retaining debug control, especially in the cases of devices specified

without external bus. The need for a costly cable which brings out the footprint of any chip

on traditional emulator systems is eliminated.

Figure 10-1 illustrates a block diagram of the Emulation and test serial interface.

10.2 EMULATION AND TEST PINOUT

10.2.1

Debug Serial Input/OnCE Status 0 (DSI/OS0)

The DSI/OS0 pin, when input, is the pin through which serial data or commands are pro-

vided to the OnCE controller. The data received on the DSI pin is recognized only when

the DSP has entered the debug mode of operation. Data is always shifted into the OnCE

serial port most significant bit (MSB) first on the falling edge of the OnCE serial clock,

DSCK. When an output, this pin in conjuction with the OS1 pin, provides information about

the chip status when debug mode cannot be entered in response to an external request.

The DSI/OS0 pin is an output when not in Debug Mode (i.e., until the acknowledge signal

is issued to the Command Controller). When switching from output to input, the pin is

three-stated. In order to avoid any possible glitches, an external pull-down resistor should

be attached to this pin. During hardware reset, this pin is defined as an output and it is

driven low.

10.2.2

Debug Serial Clock/OnCE Status 1 (DSCK/OS1)

The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to

the OnCE controller. The serial clock provides pulses required to shift data into and out of

the OnCE serial port. Data is shifted into the chip via the DSI pin on the falling edge of

DSCK and is shifted out of the chip via the DSO pin on the rising edge of DSCK. When

an output, this pin, in conjunction with the OS0 pin, provides information about the chip

status when debug mode cannot be entered in response to an external request. The

DSCK/OS1 pin is an output when not in Debug Mode (until the acknowledge signal is is-

sued to the Command Controller). When switching from output to input, the pin is first

three-stated. In order to avoid any possible glitches, an external pull-down resistor should

be attached to this pin. During hardware reset, this pin is defined as output and it is driven

low.

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EMULATION AND TEST PINOUT

PDB PILB GDB

Breakpoint and

Trace Logic

Pipeline

Information

DSCK/OS1

DSI/OS0

OnCE

Controller

and

PAB

Serial

Interface

DR

DSO

XAB

PAB

Breakpoint Register

and

FIFO

Comparator

Note: PILB = Program Instruction Latch Bus

Figure 10-1 OnCE Block Diagram

Table 10-1 shows the status of the chip as a function of the two output pins OS0:OS1.

Table 10-1 Function of OS1:OS0

OS1 OS0

Status

0

1

0

1

0

1

Normal state

STOP or WAIT mode

DSP busy state (external accesses with wait state)

reserved

10.2.3

Debug Serial Output (DSO)

The DSO pin, while in debug mode, is the serial output that permits reading the data con-

tained in one of the OnCE controller registers as specified by the last command received

from the external command controller. Data is shifted out of the chip via the DSO pin on

the rising edge of DSCK. An acknowledgment pulse will be sent on the DSO pin when:

1. the chip enters the OnCE mode (external, DR, hardware breakpoint, software

breakpoint or trace) to indicate that the chip is ready to accept OnCE com-

mands. This pulse is 3T long.

2. a “do nothing” operation (no go, no exit) is selected to indicate that the input

command register is ready to receive a new command. This pulse is 4T long.

3. the requested data (before a read) is available to indicate that the serial shift

registers are ready to receive clocks to start transmitting data to the DSO pin.

This pulse is 4T long.

10 - 4

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ONCE CONTROLLER AND SERIAL INTERFACE

4. the shift registers are ready to receive clocks to receive data (before a write)

from the DSI pin. This pulse is 4T long.

5. the shift registers have finished shifting in the new data (after a write) to indi-

cate that the input command register is now ready to receive new instruction.

This pulse is 4T long.

6. an instruction has completed execution (go, no exit; repeat an instruction).

This pulse is 4T long.

Data is always shifted out the OnCE serial port most significant bit (MSB) first on the rising

edge of DSCK. When not in debug mode, the DSO pin is driven high. During hardware

reset this pin is driven high.

10.2.4

Debug Request Input (DR)

The DR input is an active low pin that provides a means of entering the debug mode of

operation from the external command controller. This pin, when asserted, will cause the

DSP to finish the current instruction being executed, save the instruction pipeline informa-

tion, enter the debug mode and wait for commands to be entered from the debug serial

input line.

10.3 ONCE CONTROLLER AND SERIAL INTERFACE

The OnCE Controller and Serial Interface contains the following blocks: input shift regis-

ter, bit counter, OnCE decoder and the status/control register. Figure 10-2 illustrates a

block diagram of the OnCE serial interface.

10.3.1

OnCE Input Shift Register (OISR)

The OISR is an 8-bit shift register that receives the serial data from the DSI line. The data

is clocked into the register on the falling edge of the clock applied to the DSCK pin. After

the 8th bit is received the OISR will stop shifting in new data. The latched data will be used

as input for the OnCE Decoder. The data is always shifted into the OISR most significant

bit (MSB) first.

10.3.2

OnCE Bit Counter (OBC)

The OBC is a 4-bit counter (0…15) associated with shifting in and out the data bits. The

OBC is incremented by the falling edges of the DSCK. The OBC is cleared at reset and

whenever the DSP acknowledges that the Debug Mode has been entered. The OBC sup-

plies two signals to the OnCE Decoder: one indicating that the first 8 bits were shifted-in

(so a new command is available) and the second indicating that 16 bits were shifted-in

(the data associated with that command is available) or that 16 bits were shifted-out (the

data required by a read command was shifted out).

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ONCE CONTROLLER AND SERIAL INTERFACE

8-bit register

OnCE Input

Shift Register

SER_IN (DSI)

CLK_IN (DSCK)

(OISR)

ISBKPT

ISDEBUG

BIT7

Bit Counter

(OBC)

ISTRACE

OnCE

Decoder

(ODEC)

BIT15

ISHWDBG

(DR)

4-bit counter

ISSWDBG

Status and Control

Register

STR

SER_OUT (DSO)

(OSCR)

STW

16-bit register

MODE SELECT

REGREAD REGWRITE

Note: ISxxxx = Interrupt Service xxxx

Figure 10-2 OnCE Controller and Serial Interface

10.3.3

OnCE Decoder (ODEC)

The ODEC is the supervisor of the entire OnCE activity. It receives as input the 8-bit com-

mand from the OISR, two signals from OBC (one indicating that 8 bits have been received

and the other that 16 bits have been received), and one signal indicating that the DSP has

halted. The ODEC generates all the strobes required for reading and writing the selected

OnCE registers.

10.3.4

OnCE Status and Control Register (OSCR)

The (OSCR is a 16-bit register used to select the events that will put the chip in Debug

Mode. Breakpoints may be disabled or enabled on one memory space. The Trace Mode

of operation is also selected through OSCR.

OSCR is shown in Table 10-2 and the control bits are described in the following para-

graphs.

10 - 6

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ONCE CONTROLLER AND SERIAL INTERFACE

Table 10-2 OnCE Status and Control Register (OSCR)

Status

Control

15

*

14

*

13

*

12

11

10

9

8

7

*

6

*

5

*

4

3

2

1

0

*

TO HBO SBO

TME BS1 BS0 BE1 BE0

10.3.4.1

OSCR Breakpoint Enables (BE0-BE1) Bit 0-1

These control bits enable or disable the breakpoint logic and select the type of memory

operations (read; write; access) upon which the breakpoint logic operates. These bits are

cleared on hardware reset.

BE1

BE0

Selection

0

1

0

1

0

1

Breakpoint disabled

Breakpoint enabled on memory write

Breakpoint enabled on memory read

Breakpoint enabled on memory access

10.3.4.2

OSCR Breakpoint Selection (BS0-BS1) Bits 2-3

These control bits select if the Breakpoints will be recognized on program memory fetch,

program memory access, X memory access or second X memory read. These bits are

cleared on hardware reset.

BS1 BS0

Selection

0

Breakpoint on program memory fetch (fetch of the first word of instructions which

are actually executed; not of those which are killed, not of those which are the sec-

ond word of two-word instructions, and not of jumps which are not taken)

0

1

Breakpoint on any program memory access (any MOVEM instructions, fetches of

instructions which are executed and of instructions which are killed, fetches of sec-

ond word of two-word instructions, and fetches of jumps which are not taken

1

0

1

Breakpoint on first X memory (xab1) access

Breakpoint on second X memory (xab2) read

(xab2 cannot be used to write data into the X memory)

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ONCE CONTROLLER AND SERIAL INTERFACE

The decoding scheme for BS(1:0) and BE(1:0) is as follows:

Function

BS(1:0)

BE(1:0)

disable

XX

00

program fetch

00

01

10

11

any program write or fetch

any program read or fetch

any program access or fetch

01

10

11

XAB1

write

read

access

10

01

10

11

disable

XAB2

11

01

10

11

read

10.3.4.3

OSCR Trace Mode Enable (TME) Bit 4

This control bit, when set, enables the Trace Mode. When the Trace Mode is enabled, the

chip will enter the Debug Mode whenever the execution of an instruction is completed and

the Trace Counter is zero. This bit is cleared on hardware reset.

10.3.4.4

OSCR (Reserved) Bits 5-7

These bits are reserved for future use and read as zero. Reserved bits should be written

as zero for future compatibility.

10.3.4.5

OSCR Software Breakpoint Occurrence (SBO) Bit 8

This read-only status bit is set when the debug mode has been entered by a DEBUG or

DEBUGcc instruction. It is used by the external command controller to determine how the

debug mode was entered. This bit is cleared when leaving the debug mode and is also

cleared on hardware reset.

10.3.4.6

OSCR Hardware Breakpoint Occurrence (HBO) Bit 9

This read-only status bit is set when a OnCE hardware breakpoint occurs. It is used by

the external command controller to determine how the debug mode was entered. This bit

is cleared when leaving the debug mode and it is also cleared on hardware reset.

10 - 8

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OnCE BREAKPOINT LOGIC

10.3.4.7

OSCR Trace Occurrence (TO) Bit 10

This read-only status bit is set when the debug mode of operation is entered from a dec-

rement to zero of the trace counter and the trace mode has been armed. This bit is cleared

on reset and when leaving the debug mode.

10.3.4.8

OSCR Reserved – Bits 11-15

These bits are reserved for future use and read as zero. Reserved bits should be written

as zero for future compatibility.

10.4 OnCE BREAKPOINT LOGIC

Other processors traditionally set a breakpoint in program memory by replacing the in-

struction at the breakpoint address with an illegal instruction which causes a breakpoint

exception. This technique is limiting in that breakpoints can only be set in RAM at the be-

ginning of an opcode and not on an operand. Using such techniques, breakpoints can

never be set in data memory.

On the other hand, by using address comparators, breakpoints may be set on program

memory opcodes or any data memory location. This significantly increases the program-

mer’s ability to monitor what the program is doing real-time.

The breakpoint logic can be enabled for Program memory breakpoints or for Data memory

breakpoints. It contains an address latch, a register that stores the breakpoint address, a

comparator and a counter. Figure 10-3 illustrates a block diagram of the OnCE Breakpoint

Logic.

10.4.1

OnCE Breakpoint Logic Operation

The address comparator register is useful in halting a program at a specific point to ex-

amine/change registers or memory. Using the address comparator to set breakpoints en-

ables the user to set breakpoints in RAM or ROM while in any operating mode.

The address comparator will cause a logic true signal when the comparison of its value is

equal to the address on the bus. The breakpoint counter is then decremented if greater

than zero. If the breakpoint counter is equal to zero, it is not decremented and a break-

point occurs.

Conditional jump addresses produced by the instruction pipeline that are equal to the pro-

gram address being monitored are only valid if the conditional jump instruction occurs,

otherwise the conditional jump address is ignored. Program memory address breakpoints

occur after the opcode or operand is executed and the breakpoint counter has been dec-

remented to zero.

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

OnCE BREAKPOINT LOGIC

XAB1 XAB2 PAB

ER EW

SER_IN

SER_OUT

CLK_IN

MEMORY

ADDRESS LATCH

BREAKPOINT

ADDRESS REGISTER

T3

T0

OMAL

OMBAR

OMAC

COMPARATOR

RESET

BKCTW

T3

BE

T2

BKCTR

OMBC

LD

SER_IN

SER_OUT

CLK_IN

BREAKPOINT

COUNTER

BKPT

BREAKPOINT

CONTROL

DEC

COUNT 0

ISBKPT

Figure 10-3 Breakpoint Logic

Data memory address breakpoints also occur after the execution of the instruction which

formed the data memory address and the breakpoint counter has decremented to zero.

The breakpoint registers are controlled by the debug status and control register (OSCR).

10.4.2

Breakpoint Counter

The breakpoint counter is a 16-bit counter that is useful for stopping at the nth iteration of

a program loop or when the nth occurrence of a data memory access occurs. This infor-

mation significantly decreases algorithm debug and provides a means of checking hot

spots in program segments as well as peripheral or data memory accesses.

The breakpoint counter becomes a powerful tool when debugging real-time fast interrupt

sequences such as servicing an A/D or D/A convertor or stopping after a specific number

of host transfers have occurred. The breakpoint counter is cleared by reset.

10.4.3

OnCE Memory Address Latch (OMAL)

The Memory Address Latch (OMAL) is a 16-bit register that latches the PAB, XAB1, or

XAB2 on every cycle.

10 - 10

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

TRACE/STEP MODE

10.4.4

Memory Breakpoint Address Register (OMBAR)

The Memory Breakpoint Address Register (OMBAR) is a 16-bit register that stores the

memory breakpoint address. OMBAR is available for read/write operations only through

the OnCE serial interface. Before enabling breakpoints, OMBAR must be loaded by the

command controller.

10.4.5

Memory Address Comparator (OMAC)

The Memory Address Comparator (OMAC) is a 16-bit comparator that compares the cur-

rent memory address (stored by OMAL) with Memory Address Register (OMBAR). If

OMAC is equal to OMAL then the comparator delivers a signal indicating that the break-

point address has been reached.

10.4.6

Memory Breakpoint Counter (OMBC)

The Program Memory Breakpoint Counter (OMBC) is a 16-bit counter which is loaded

with a value equal to the number of times minus one that a program or data memory ad-

dress should occur before a breakpoint is acknowledged. On each occurrence the counter

is decremented. When the counter has reached the value of zero and a new occurrence

takes place, a signal is generated and, if breakpoints are enabled in OSCR, the chip will

enter the Debug Mode. OMBC is available for read/write operations only through the

OnCE serial interface. Before enabling Memory Breakpoints, OMBC must be loaded by

the command controller.

10.5 TRACE/STEP MODE

When in the special trace mode, the DSP will not cause an interrupt exception but instead

will enter the debug operation mode and wait for further instructions from the debug serial

port. Single or multiple instructions can be traced.

10.5.1

Trace Counter

The trace mode has a 16-bit counter associated with it so that more than one instruction

may be executed before returning back to the debug mode of operation. The objective of

the counter is to allow the user to take multiple instruction steps in real-time with no inter-

ference from the debug mode. This feature helps the software developer debug sections

of code which do not have a normal flow or are getting hung up in infinite loops. The trace

counter also enables the user to debug areas of code which are time critical.

To enable the trace mode of operation the counter is loaded with a value, the program

counter is set to the start location of the instruction(s) to be executed real-time, the trace

mode is selected in the debug status register (OSCR) and the DSP exits the debug mode

by executing the appropriate command issued by the external command controller. Upon

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

METHODS OF ENTERING THE DEBUG MODE

exiting the debug mode the counter is decremented after each execution of an instruction.

Interrupts are serviceable and all instructions executed including fast interrupt services

will decrement the trace counter. Upon decrementing to zero the DSP will re-enter the de-

bug mode, the trace occurrence bit in the debug status/control register (OSCR) will be set

and the debug serial output pin DSO will be toggled to indicate that the DSP OnCE port

is requesting service.

Note: The trace count should be loaded with one less than (i.e., N-1) the number of in-

structions that the user wants to execute (e.g., to single step one instruction, the

trace counter is loaded with a zero).

The Trace counter is cleared by hardware reset. Figure 10-4 illustrates a block diagram

of the Trace Counter logic.

10.6 METHODS OF ENTERING THE DEBUG MODE

Entering the Debug Mode is acknowledged by the chip by toggling the DSO line for 3 T

cycles. This informs the external command controller that the chip has entered the Debug

Mode and is waiting for commands. There are seven ways in which the Debug Mode may

be entered. They are:

1. External Request During Hardware Reset

2. External Request During Normal Activity

3. External Request During STOP

4. External Request During WAIT

5. Software Request During Normal Activity

6. Enabling Trace Mode

7. Enabling Breakpoints

10.6.1

External Request During Hardware Reset

Holding the DR line asserted during the assertion of RESET will cause the chip to enter

the Debug Mode. After receiving the acknowledge, the command controller must deassert

the DR line. Note that in this case the chip does not perform any fetch or memory access

before entering the Debug Mode.

10.6.2

External Request During Normal Activity

Holding the DR line asserted during the normal chip activity will cause the chip to finish

execution of the current instruction and then enter the Debug Mode. After receiving the

10 - 12

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

METHODS OF ENTERING THE DEBUG MODE

acknowledge the command controller must deassert the DR line. Note that in this case

the chip completes execution of the current instruction and stops after the newly fetched

instruction enters the instruction latch. This process is the same for any newly fetched in-

struction including instructions fetched during interrupt processing or instructions that will

be killed by the interrupt processing.

10.6.3

External Request During STOP

Asserting DR when the chip is in the stop state (i.e., it has executed a STOP instruction)

causes the chip to exit the stop state and enter the Debug Mode. The chip will wake up

from the stop state normally (finish executing STOP) and halt after the next instruction en-

ters the instruction latch. After receiving the acknowledge, the command controller must

deassert DR. Note that in this case the chip completes the execution of the STOP instruc-

tion and halts after the next instruction enters the instruction latch.

10.6.4

External Request During WAIT

Asserting DR when the chip is in the wait state (i.e. has executed a WAIT instruction)

causes the chip to exit wait state and enter the Debug Mode. The chip will wake up from

the wait state normally (finish executing WAIT) and halt after the next instruction enters

the instruction latch. After receiving the acknowledge, the command controller must deas-

sert DR. Note that in this case the chip completes execution of the WAIT instruction and

halts after the next instruction enters the instruction latch.

10.6.5

Software Request During Normal Activity

Upon executing the DEBUG or DEBUGcc instructions (with condition true for DEBUGcc),

the chip will enter Debug Mode after the instruction following the DEBUG/DEBUGcc in-

struction has entered the instruction latch.

RESET

TRCTW

TRCTR

LD

SER_IN

SER_OUT

CLK_IN

TRACE

COUNTER

END OF

INSTRUCTION

DEC

COUNT 0

ISTRACE

Figure 10-4 Trace Counter Logic

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PIPELINE INFORMATION

10.6.6

Enabling Trace Mode

When the chip is operating in Trace Mode and the Trace Counter reaches a value of zero,

the chip will enter the Debug Mode after completing execution of the instruction that

caused the Trace Counter to decrement. Only those instructions that are actually execut-

ed may cause the Trace Counter to decrement i.e. a killed instruction (instruction discard-

ed during the interrupt process) will not decrement the Trace Counter and will not cause

the chip to enter the Debug Mode.

10.6.7

Enabling Breakpoints

The chip will enter the Debug Mode after completing execution of the instruction that

caused the Breakpoint Counter to decrement when:

1. operating in the Trace Mode when the Breakpoint Counter has reached zero

or

2. when operating in Normal Mode with the Breakpoint mechanism enabled and

the Breakpoint Counter has reached zero.

In the case of breakpointing on:

1. Program memory addresses, the breakpoint will be acknowledged immedi-

ately after the execution of the instruction accessed at the specified address.

2. Data memory addresses the breakpoint will be acknowledged after the com-

pletion of the instruction following the instruction that caused the access at the

specified address.

10.7 PIPELINE INFORMATION

The previous chip pipeline state must be reconstructed to resume normal chip activity

when returning from the Debug Mode. Figure 10-5 illustrates a block diagram of Pipeline

Information Registers. Only the PDB register and the PIL register are used to reconstruct

the pipeline as it was before debug. the PAB History Buffer, PAB Register for Fetch and

PAB Register for Decode are only used for status information. When loading a one word

instruction into the PDB and issuing a GO command, the hardware internally transfers the

PDB to the PIL and then executes the instruction. When loading a two word instruction,

the first word is loaded into the PDB. As the second word is loaded to the PDB, the first

word is automatically transferred to the PIL and then execution takes place.

10 - 14

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PAB HISTORY BUFFER

10.7.1

OnCE PDB Register (OPDBR)

The PDB Register (OPDBR) is a read/write, 16-bit latch that stores the value of the Pro-

gram Data Bus generated by the last Program Memory access of the DSP before the De-

bug Mode is entered. OPDBR is available for read/write operations only through the serial

interface. This register is affected by the operations performed during the Debug Mode

and must be restored by the command controller when returning to normal mode.

10.7.2

OnCE PIL Register (OPILR)

The OPILR is a read only 16-bit latch that stores the instruction present in the Instruction

Latch when the Debug Mode is entered. OPILR is available for read operations only

through the serial interface. If a write is selected for this register, i.e., R/W = 0 and RS4-

RS0 = 01011, then zeros will be shifted into the OPILR. This register is affected by the

operations performed during the Debug Mode and must be restored by the command con-

troller when returning to normal mode. Since there is no direct write access to this register,

this task is accomplished by writing the OPDBR first and then the data from OPDBR is

latched in OPILR.

10.7.3

OnCE GDB Register (OGDBR)

The OGDBR is a read only 16-bit latch that stores the value of the Global Data Bus. OGD-

BR is available for read operations only through the serial interface. OGDBR is required

as a means of passing information between the chip and the command controller. OGD-

BR will be mapped on the X internal IO space at address $FFFF. Whenever the command

controller needs information such as a register or memory value it will force the chip to

execute an instruction that brings that information to the OGDBR. Then, the contents of

the OGDBR will be delivered serially to the command controller by the command “READ

GDB REGISTER”.

10.8 PAB HISTORY BUFFER

To ease the debugging activity and keep track of the program flow, a First-In-First-Out,

read only, buffer is provided. It stores the addresses of the last five instructions that were

executed as well as the addresses of the last fetched instruction and of the instruction cur-

rently in the instruction latch.

Figure 10-6 illustrates a block diagram of the Program Address Bus FIFO.

10.8.1

OnCE PAB Register for Fetch (OPABFR)

The OPABFR is a read only 16-bit latch that stores the address of the last instruction that

was fetched before the Debug Mode was entered. OPABFR is available for read opera-

tions only through the serial interface. This register is not affected by the operations per-

formed during the Debug Mode.

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PAB HISTORY BUFFER

PDB

PDBW PDBR T3

SER_IN

SER_OUT

CLK_IN

PDB SHIFT

REGISTER

OPDBR

PIIDB

PIIBR T3

PILB SHIFT

REGISTER

SER_OUT

CLK_IN

OPILR

GDB

GDBR

T3

GDB SHIFT

REGISTER

SER_OUT

CLK_IN

OGDBR

Figure 10-5 Pipeline Information Registers

10.8.2

OnCE PAB Register for Decode (OPABDR)

The 16-bit OPABDR stores the address of the instruction currently in the Instruction Latch.

This is the instruction that would have been decoded if the chip would not have entered

the Debug Mode. OPABDR is available for read operations only through the serial inter-

face. This register is not affected by the operations performed during the Debug Mode.

10.8.3

OnCE PAB FIFO

The FIFO is implemented as a circular buffer containing five 16-bit registers and one 3-bit

counter. All registers have the same address but any read access to the FIFO will cause

an increment of the counter thus pointing to the next FIFO register. The registers are se-

rially available for read to the command controller through their common FIFO address.

The FIFO is not affected by the operations performed during the Debug Mode except for

the FIFO pointer increment when reading the FIFO. Figure 10-6 illustrates a block dia-

gram of the Program Address Bus FIFO.

Caution

To ensure FIFO coherence, a complete set of five reads of the FIFO must be

performed. This is necessary due to the fact that each read increments the

FIFO pointer thus causing it to point to the next location. After five reads the

pointer will point to the same location as before starting the read procedure.

10 - 16

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

PAB HISTORY BUFFER

PAB

DSP FETCH ADDRESS

READ DECODE ADDRESS

(OPABFR)

DECODE ADDRESS

(OPABDR)

CIRCBUFRD

CIRCBUFWR

PAB

REGISTER #0

PAB

REGISTER #1

CIRCBUFINC

CIRCBUFDEC

PAB

REGISTER #2

CIRCULAR

POINTER

DECODER

PAB

REGISTER #3

PAB

REGISTER #4

PFSHRR PFSHRW

PAB FIFO

SHIFT REGISTER

SER_OUT

CLK_IN

Figure 10-6 Program Address Bus FIFO

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SERIAL PROTOCOL DESCRIPTION

7

6

5

4

3

2

1

0

R/W

GO

EX

RS4

RS3

RS2

RS1

RS0

Figure 10-7 OnCE Command Format

10.9 SERIAL PROTOCOL DESCRIPTION

In order to permit an efficient means of communication between the command controller

and the DSP chip, the following protocol has been adopted. Before starting any debugging

activity, the command controller has to wait for an acknowledge from the chip which in-

forms the command controller that it has entered the Debug Mode. Note that in case of a

breakpoint, trace or software DEBUG/DEBUGcc instruction, the acknowledge itself is the

one that initiates the debug session. The command controller communicates with the chip

by sending 8-bit commands that may be accompanied by 16-bit data. After sending a

command, the command processor starts waiting for the chip to acknowledge execution

of the command. The command processor may send a new command only after the chip

has acknowledged execution of the previous command.

10.9.1

OnCE Commands

There are two type of commands: read commands (when the chip will deliver required da-

ta) and write commands (when the chip will receive data and will write it in one of the on

chip resources). The commands are 8 bits long and have the format shown in Figure 10-7.

10.9.1.1

OnCE Register Select (RS4-RS0) Bits 0-4

The Register Select bits define which register is source(destination) for the read(write) op-

eration.

10 - 18

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SERIAL PROTOCOL DESCRIPTION

RS4-RS0

Register Selected

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

101xx

11xx0

11x0x

110xx

11111

Debug Status/Control (OSCR)

Memory Breakpoint Counter (OMBC)

Reserved

Trace Counter (OTC)

Memory Breakpoint Address (OMBAR)

Reserved

Global Data Bus (Transfer) Register (OGDBR)

Program Data Bus (OPDBR) Register

Program Address Bus (OPABFR) Latch for Fetch

Instruction Latch (OPILR)

Clear Breakpoint Counter

Reserved

Clear Trace Counter

Reserved

Program Address Bus FIFO and Increment Counter

Reserved

Program Address Bus (OPABDR) Latch for Decode

Reserved

No Register Selected

10.9.1.2

OnCE Exit Command (EX) Bit 5

Bit 5 in the OnCE command word is the exit command. To leave the OnCE mode and re-

enter the normal operating mode, both the EX and GO bits must be asserted in the OnCE

input command register. There are three exit conditions:

1. If EX and GO are set, the chip will leave the Debug Mode, execute the DSP

instruction in the pipeline and then resume normal operation. If the register

select bits are set to $1F (RS4-RS0 = 11111) then the last instruction (the in-

struction in the PILB) is re-executed.

2. If EX is set without GO, then when the OnCE has finished writing the instruc-

tion latch (PILB) register, the OnCE state machine will get another command

instead of leaving the OnCE mode.

3. If EX is set without GO, then when the OnCE is finished writing the PDB

(PILB) register, the OnCE state machine will get another command instead of

leaving the OnCE mode.

There is no acknowledgment on the DSO pin when the chip leaves the OnCE mode fol-

lowing a GO or an EX.

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP56100 TARGET SITE DEBUG SYSTEM REQUIREMENTS

EX

Action

0

1

Remain in Debug Mode

Leave Debug Mode

10.9.1.3

OnCE Go Command (GO) Bit 6

If GO is set, execute instruction. There is no acknowledgment on the DSO pin when the

chip leaves the OnCE mode following a GO or an EX.

GO

Action

0

1

Inactive (no action taken)

Execute DSP instruction

10.9.1.4

OnCE Read/Write Command (R/W) Bit 7

R/W

Action

0

1

Write the data associated with the command into the register specified by RS4-RS0

Read the data contained in the register specified by RS4-RS0

10.10 DSP56100 TARGET SITE DEBUG SYSTEM REQUIREMENTS

A typical debug environment consists of a target system where the DSP resides in the

user defined hardware. The debug serial port interfaces to the command convertor over

a six wire link consisting of the four debug serial lines, a ground and reset wire. The reset

wire is optional and is only used to reset the DSP and its associated circuitry.

The command controller acts as the medium between the DSP target system and a host

computer. The host computer interfaces to the controller using a standard RS232 three

wire cable or the Application Development System parallel bus. A jumper option on the

command controller board will select which method of communications will be used. This

allows a variety of different host computers to communicate with the controller circuit. The

controller circuit provides several important functions. It acts as a serial debug port driver,

host computer command interpreter, and DSP controller. The DSP acts as a slave when

in the debug mode and provides data only upon request. The controller issues commands

based on the host computer inputs from a user interface program which communicates

with the user.

10 - 20

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

10.11 USING THE OnCE

The following notations are used:

Commands require eight clocks

ACK = Wait for acknowledge on DSO line

CLK = Issue 16 clocks to read out data from selected register

10.11.1 Begin Debug Activity

Debug activity begins on an instruction boundary after the DR pin is asserted, a DEBUGcc

opcode is executed, a trace countdown occurs, or a breakpoint register countdown oc-

curs. If the instruction executing when the DR pin is asserted is a REP instruction or the

instruction following a REP instruction, then the debug activity will begin after the instruc-

tion following the REP instruction finishes being repeated. The first ACK indicates that the

OnCE controller is ready to receive commands and data. Most of the Debug activities will

have the following beginning:

ACK

1. Save pipeline information:

a. Send command READ PDB REGISTER

b. ACK

c. CLK

d. Send command READ OPILR

e. ACK

f. CLK

2. Read PAB FIFO and fetch/decode info (this step is optional):

a. Send command READ PAB address for fetch

b. ACK

c. CLK

d. Send command READ PAB address for decode

e. ACK

f. CLK

g. Send command READ FIFO REGISTER (and increment pointer)

h. ACK

i. CLK

j. Send command READ FIFO REGISTER (and increment pointer)

k. ACK

l. CLK

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 21

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

m. Send command READ FIFO REGISTER (and increment pointer)

n. ACK

o. CLK

p. Send command READ FIFO REGISTER (and increment pointer)

q. ACK

r. CLK

s. Send command READ FIFO REGISTER (and increment pointer)

t. ACK

u. CLK

10.11.2 Displaying a Specified Register

1. Send command WRITE PDB REGISTER and GO (no EX)

(ODEC selects PDB as destination for serial data.)

2. ACK

3. Send the 16-bit opcode: “MOVE reg, x:OGDB

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

generates PRNEW and releases the chip from the “halt” state and the contents of

the register specified in the instruction is loaded in the GDB REGISTER. The

PRCYC1 signal (an internal signal) that marks the end of the instruction brings the

chip again in the “halt” state and an acknowledge is issued to the command

controller)

4. ACK

5. Send command READ GDB REGISTER

(ODEC selects GDB as the source for serial data and an acknowledge is issued to

the command controller)

6. ACK

7. CLK

10.11.3 Displaying X Memory Area Starting from Address xxxx

This command uses Rn to minimize serial traffic.

1. Send command WRITE PDB REGISTER and GO (no EX).

(ODEC selects PDB as destination for serial data.)

2. ACK

10 - 22

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

3. Send the 16-bit opcode: “MOVE R0,x:OGDB”

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

generates PRNEW and releases the chip from the “halt” state and the contents of

R0 are loaded in the GDB REGISTER. The PRCYC1 signal that marks the end of

the instruction brings the chip again to the “halt” state and an acknowledge is

issued to the command controller)

4. ACK

5. Send command READ GDB REGISTER

(ODEC selects GDB as the source for serial data and an acknowledge is issued to

the command controller)

6. ACK

7. CLK

(The command controller generates 16 clocks that shift out the contents of the

GDB register. The value of R0 is thus saved and will be restored before exiting the

Debug Mode)

8. Send command WRITE PDB REGISTER (no GO, no EX).

(ODEC selects PDB as destination for serial data.)

9. ACK

10.Send the 16-bits of opcode: “MOVE #$xxxx,R0”

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

generates PRNEW so the PILR is loaded with the opcode. An acknowledge is

issued to the command controller)

11.ACK

12.Send command WRITE PDB REGISTER and GO (no EX).

(ODEC selects PDB as destination for serial data.)

13.ACK

14.Send the 16-bits of the 2nd word of: “MOVE #$xxxx,R0” (the xxxx field) where xxxx

is the address to be read.

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

releases the chip from the “halt” state and the instruction starts execution. The

PRCYC1 signal that marks the end of the instruction brings the chip again to the

“halt” state and an acknowledge is issued to the command controller)

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 23

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

15.ACK

16.Send command WRITE PDB REGISTER and GO (no EX).

(ODEC selects PDB as destination for serial data.)

17. ACK

18.Send the 16-bit opcode: “MOVE X:(R0)+,x:OGDB”

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

generates PRNEW and releases the chip form the “halt” state and the contents of

X:(R0) are loaded in the GDB REGISTER. The PRCYC1 signal that marks the end

of the instruction brings the chip again in the “halt” state and an acknowledge is

issued to the command controller)

19.ACK

20.Send command READ GDB REGISTER

(ODEC selects GDB as source for serial data and an acknowledge is issued to the

command controller)

21.ACK

22.CLK

23.Send command NO SELECTION and GO (no EX).

(ODEC releases the chip from the “halt” state and the instruction is executed once

again (in a “REPEAT-like” fashion. The PRCYC1 signal that marks the end of the

instruction brings the chip again to the “halt” state and an acknowledge is issued

to the command controller.)

24.ACK

25.Send command READ GDB REGISTER

(ODEC selects GDB as source for serial data and an acknowledge is issued to the

command controller.)

26.ACK

27.CLK

28.Repeat from step 23 until the entire memory area is examined. At the end of the

process R0 has to be restored.

10 - 24

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

10.11.4 Returning from Debug Mode to Normal Mode

There are two cases for returning from the debug mode. In case 1, control will be returned

to the program that was running before debug was initiated and in case 2, the registers

will be changed to jump to a different program. There is no acknowledgment on the DSO

pin when the chip leaves the OnCE mode following a GO, EX. This is a special case of

the “write a register” option.

10.11.4.1 Case 1: Returning from Debug Mode to Normal Mode

1. Send command WRITE PDB REGISTER (no GO, no EX).

(ODEC selects the PDB register as destination for serial data. Also ODEC selects

the on-chip PAB register as source for the PAB bus. After the PAB was driven an

acknowledge is issued to the command controller)

2. ACK

3. Send the 16-bits of the saved PILB (instruction latch) value.

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

generates PRNEW so the entire chip loads the opcode. An acknowledge is issued

to the command controller)

4. ACK

5. Send command WRITE PDB REGISTER (GO, EX).

(ODEC selects PDB as destination for serial data.)

6. ACK

7. Send the 16-bits of the saved PDB value.

(After all 16-bits have been received, the PDB register drives the PDB. ODEC

releases the chip form the “halt” state and the Debug Mode bit in OSCR is cleared.

The chip continues to execute instructions until a Debug Mode condition occurs)

10.11.4.2 Case 2: Jump to a New Program (Go from Address $xxxx).

1. Send command WRITE PDB REGISTER (no GO, no EX).

(ODEC selects PDB as destination for serial data.)

2. ACK

MOTOROLA

ON-CHIP EMULATION (OnCE)

10 - 25

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

USING THE OnCE

3. Send 16 bits of the opcode of a two word jump instruction instead of the saved PIL

(instruction latch) value.

(After all the 16-bits have been received, the PDB register drives the PDB. ODEC

causes the DSP to load the opcode. An acknowledge is issued to the command

controller.)

4. ACK

5. Send command WRITE PDB REGISTER (GO, EX).

(ODEC selects PDB as destination for serial data.)

6. ACK

7. Send 16 bits of the target absolute address ($xxxx). The chip will resume fetching

from the target address (you do not have to worry about the pipeline). Note that the

trace counter will count this instruction so the current trace counter may need to be

corrected if the trace mode enable bit in the OSCR has been set.

(e. g., After 16 bits have been received, the PDB register drives the PDB. ODEC

releases the chip from the “halt” state and the Debug Mode bit in OSCR is cleared.

The chip executes first the jump instruction and will then fetch the instruction from

the target address. The chip continues to execute instructions from that address

until a Debug Mode condition occurs.)

10 - 26

ON-CHIP EMULATION (OnCE)

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 11

APPLICATION DEVELOPMENT TOOLS

MOTOROLA

APPLICATION DEVELOPMENT TOOLS

11 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

SOFTWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

MACRO CROSS ASSEMBLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3

LINKER/LIBRARIAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

SIMULATOR PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-4

HARDWARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5

HARDWARE FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-7

SOFTWARE FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

OPERATING ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-8

11 - 2

APPLICATION DEVELOPMENT TOOLS

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SOFTWARE

11.1 SOFTWARE

All software support products run on the following platforms — IBM PC, Macintosh ,

and SUN workstation. The software, written in C, consists of an assembler, linker, and

simulator which are marketed as an integrated product.

11.2 MACRO CROSS ASSEMBLER

The ASM56100 Macro Cross Assembler program is a full-featured macro cross assem-

bler that translates one or more source fields containing DSP instruction mnemonics,

operands, and assembler directives into relocatable object modules that are relocated

and linked by the Motorola DSP Linker in the Relocation mode. In the Absolute mode,

the assembler will generate absolute executable files. The assembler recognizes the full

instruction set and all addressing modes of the DSP56100 family.

This assembler offers the usual complement of features found in modern assemblers,

such as conditional assembly, file inclusion, nested macros with support for macro librar-

ies (via the MACLIB directive), and modular programming constructs ordinarily found

only in higher level languages.

The unique architecture and parallel operation of the DSP demands special purpose

facilities and programming aids which this assembler readily provides. These include

built-in functions for common transcendental math computations such as sine, cosine,

log, and square root functions; arbitrary expressions and modulo operations; and direc-

tives to define circular and bit-reversed data buffers. Moreover, the assembler incorpo-

rates extensive error checking and reporting to indicate programming violations peculiar

to the digital signal processing environment or stemming from the advanced features of

the DSP. These include errors for improper nesting of hardware DO loops and improper

address boundaries for circular data buffers and bit-reversed buffers.

The assembler also generates source code listings which include numbered source

lines, optional titles and subtitles, optional instruction cycle counts, symbol table and

cross-reference listings, and memory use reports.

To summarize, features of the assembler are:

• Produces relocatable object modules compatible with the DSP linker program in

the Relocation mode

• Produces absolute executable files compatible with the Simulator program

(SIM56100) in the Absolute mode

• Supports full instruction set, memory spaces, and parallel data transfer fields of the

DSP

• Modular programming features including local labels, sections, and external

definition/reference directives

MOTOROLA

APPLICATION DEVELOPMENT TOOLS

11 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LINKER/LIBRARIAN

• Nested macro libraries

• Complex expression evaluation including boolean operators

• Built-in functions for data conversion, string comparison, and common transcendental

math operations

• Directives to define circular and bit-reversed buffers

• Extensive error checking and reporting

11.3 LINKER/LIBRARIAN

The linker relocates and links relocatable object modules from the Macro Cross Assem-

bler to create an absolute executable file which can be loaded directly into the

DSP56100 simulator or converted to Motorola S-record format for PROM burning.

The librarian utility will merge into a single file multiple separate relocatable object mod-

ules. This facilitates not having to reassemble known bug-free routines every time the

mainline program is assembled.

11.4 SIMULATOR PROGRAM

The SIM56100 Simulator program is a software tool for developing programs and algo-

rithms for the DSP. This program exactly emulates all of the functions (except for the

OnCE) of the DSP including all on-chip peripheral operations, the entire internal and

external memory space, all memory and register updates associated with program code

execution, and all exception processing activity. This enables the Simulator program to

provide an accurate measurement of code execution time which is so critical in digital

signal processing applications.

The Simulator program executes DSP object code generated by the Linker or the Simu-

lator’s internal single-line assembler. The object code is loaded into the simulated DSP

memory map. Instruction execution can proceed until a user-defined breakpoint is

encountered; or in single-step mode, stopping after each instruction has been executed.

During program debug, the registers or memory locations may be displayed or changed.

The Simulator package includes linkable object code libraries of simulator functions that

were used to create the simulator. The libraries allow a customized simulator to be built

and integrated with unique system simulations. Source code for some of the functions,

such as the terminal I/O functions and external memory accesses, is provided to allow

close simulation of the particular application.

To summarize, features of the Simulator program are:

Summary of simulator features:

• Multiple device simulation

11 - 4

APPLICATION DEVELOPMENT TOOLS

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

HARDWARE

• Source level symbolic debug of assembly source programs

• Conditional or unconditional breakpoints

• Program patching using a Single-Line Assembler/Disassembler

• Instruction and Cycle timing counters

• Session and/or Command Logging for later reference

• Input/Output ASCII files for device peripherals

• Help file and Help line display of Simulator commands

• Macro command definition and execution

• Display Enable/Disable of Registers and Memory

• Hexadecimal/Decimal/Binary calculator

11.5 HARDWARE

Each DSP56100 family member has an Application Development System (ADS). All of

these are essentially identical in operation and features. The differences that do exist are

due to the specific nature of each chip. While the example here is the DSP56156, all

DSP56100 family ADS’s operate in essentially the same way. Upgrading an ADS to run

a different Motorola DSP is done by purchasing and plugging in a new Application Devel-

opment Module (see Figure 11-1).

The DSP56156 ADS is a four component system which acts as a development tool for

designing, debugging, and evaluating real-time DSP56156 target system equipment.

The ADS simplifies evaluation of the user’s prototype hardware/software product by

making all of the essential DSP56156 timing and I/O circuitry easily accessible. The ADS

takes full advantage of the On-Chip Emulation (OnCE) circuits of the DSP to allow the

user to control the target non-intrusively.

An IBM PC, Macintosh II, or SUN acts as the medium between the user and the DSP

hardware. The four components consist of an Application Development Module (ADM)

which contains a DSP56156 processor and control circuitry, a HOST-BUS interface

board for controlling up to 8 ADMs, a command convertor board which interacts with the

target OnCE serial debug port, and a software program which interacts with the user and

controls the ADM(s) and/or target system.

DSP algorithm development is simplified with features such as multiple file I/O capability

to the target under DSP56156 program control and immediate access to a hex/fractional

arithmetic calculator. The ADS is fully compatible with the DSP56100CLASx design-in

software package and may act as an accelerator for testing DSP56156 algorithms.

DSP56156 programs may be executed in real-time or by single/multiple stepping through

instructions.

MOTOROLA

APPLICATION DEVELOPMENT TOOLS

11 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

HARDWARE

As many as 99 conditional and/or unconditional software breakpoints may be placed in

ADM program memory. A hardware breakpoint range may be set to halt program execu-

tion whenever a program or data address falls within the specified range. All breakpoints

may have actions associated with them or may cause an immediate halt and display of

enabled registers.

Figure 11-1 illustrates the ADS being used as a hardware evaluation tool or software

accelerator. The ADM card has a 10 pin connector which provides an access point for

the command convertor OnCE interface.

Figure 11-2 illustrates the ADS being used as an emulator where the user has a defined

37 pin

Interface

Cable

DSP56156 User Application Circuits

(Host Computer)

IBM PC,

Macintosh

Sun 3

Host Computer

Interface Card

OnCE Command Convertor

Application Development Module (ADM)

Figure 11-1 Application Development

Target DSP56156

System

DSP56156

OnCE

37 pin

Interface

Cable

(Host Computer)

IBM PC,

Serial

Macintosh

Sun

Interface

Host Computer

Interface Card

OnCE Command Convertor

Figure 11-2 Target Circuit Emulation

11 - 6

APPLICATION DEVELOPMENT TOOLS

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

HARDWARE FEATURES

target system and needs to debug the hardware or software without any special target

footprint cable which could be intrusive or limiting. Here the user must provide an access

point for the 10 pin OnCE interface cable. This may be a simple 2 row x 5 set of test

points.

The ADM hardware, as illustrated in Figure 11-3, provides up to 64K words of user-con-

figurable high-speed SRAM with no wait states required on the external bus of the

DSP56156. There are also sockets for 2K to 8K words of user-program EPROM on the

external bus. The ADM provides easy access to all DSP56156 pins via a 96-pin Euro-

card male connector as well as a 96 pin Berg male stake connector. This enables the

user to design full-speed application circuits which may be connected to the DSP using

standard Euro-card prototype boards.

Emulation of a target system is made easy by disconnecting the command convertor

board from the ADM and connecting the 10 pin OnCE serial port cable to the target sys-

tem. This allows the user to control the target system non-intrusively so that real-time

execution may achieved at the maximum clock frequency of the DSP56156.

11.6 HARDWARE FEATURES

• Full speed operation

• Multiple ADM support with programmable

• ADM addressing 8K Words of Configurable Static RAM expandable to

64K words.

2-8K

16-64K

SRAM

EPROM

96-pin

Expansion

Connector

Port B

Reset/

Clock/

Mode Control

DSP56156

Port C

OnCE

Figure 11-3 Application Development Module

MOTOROLA

APPLICATION DEVELOPMENT TOOLS

11 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SOFTWARE FEATURES

• 2K Words of EPROM with sockets expandable to 64K words.

• Stand-Alone operation of ADM after initial development.

• Full support of program/data memory maps.

• 96 pin Connector provides access to all DSP56156 pins.

• OnCE Command Convertor card for non-intrusive Real Time Emulation.

• Special peripheral connectors available for easy access to DSP

peripherals.

• 3V emulation support in target environments

11.7 SOFTWARE FEATURES

• Single/Multiple stepping through DSP56156 object programs.

• Conditional or unconditional software and hardware breakpoints.

• Program patching using a Single-Line Assembler/Disassembler.

• Session and/or Command Logging for later reference.

• Loading and Saving of files to/from ADM Memory.

• Macro command definition and execution.

• Display Enable/Disable of Registers and Memory.

• Debug commands which support Multiple DSP56156 development.

• Hexadecimal/Decimal/Binary Fractional calculator.

• System commands from within ADS User Interface Program.

• Multiple Input/Output file access from DSP56156 object programs.

• On-line help screens for each command and DSP56156 register.

• Compatible with the DSP56100CLASX Assembler and Simulator

11.8 OPERATING ENVIRONMENT

The minimum hardware requirements for the DSP56156ADS User Interface Program

include: IBM PC-DOS/MS-DOS v3.x, 4.x, or 5.x; Macintosh II with 1 Mbyte of RAM and

running Mac OS 4.2 or later; or SUN-4 running BSD 4.2 with SUNOS 4.1.2 or Solaris 2.x.

11 - 8

APPLICATION DEVELOPMENT TOOLS

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION 12

ADDITIONAL SUPPORT

Dr. BuB Electronic Bulletin Board

Audio

Codec Routines

DTMF Routines

Fast Fourier

Transforms

Filters

Floating-Point

Routines

Motoroollaa

DSP

Functions

Lattice Filters

Matrix Operations

Reed-Solomon

Encoder

Sorting Routines

Speech

Standard I/O Equates

Tools and Utilities

Motorola DSP Product Support

DSP56100CLASx Assembler/Simulator

C Language Compiler

DSP56156ADSx Application Development System

MOTOROLA

ADDITIONAL SUPPORT

12 - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

12.1

12.2

12.3

12.4

12.5

12.6

12.7

12.8

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

THIRD PARTY SUPPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3

MOTOROLA DSP PRODUCT SUPPORT . . . . . . . . . . . . . . . . . . . . . 12-4

SUPPORT INTEGRATED CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . 12-6

MOTOROLA DSP NEWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-7

MOTOROLA FIELD APPLICATION ENGINEERS . . . . . . . . . . . . . . . 12-7

DSP APPLICATIONS HELP LINE – (512) 891-3230 . . . . . . . . . . . . . 12-7

DESIGN HOTLINE – 1-800-521-6274 . . . . . . . . . . . . . . . . . . . . . . . . 12-7

DSP MARKETING INFORMATION – (512) 891-2030 . . . . . . . . . . . . 12-7

DSP THIRD-PARTY SUPPORT INFORMATION – (512) 891-3098 . 12-7

DSP UNIVERSITY SUPPORT – (512) 891-3098 . . . . . . . . . . . . . . . . 12-7

DSP TRAINING COURSES – (602) 897-3665 or (800) 521-6274 . . . 12-8

Dr. BuB ELECTRONIC BULLETIN BOARD . . . . . . . . . . . . . . . . . . . . 12-8

REFERENCE BOOKS AND MANUALS . . . . . . . . . . . . . . . . . . . . . . . 12-18

12.9

12.10

12.11

12.12

12.13

12.14

12 - 2

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

12.1

INTRODUCTION

This section is intended as a guide to the DSP support services and products offered by

Motorola. This includes training, development hardware and software tools, telephone

support, etc.

12.2

THIRD PARTY SUPPORT

User support from the conception of a design through completion is available from Motor-

ola and third-party companies as shown in the following list:

Motorola

Third Party

Design

Data Sheets

Data Acquisition Packages

Filter Design Packages

Operating System Software

Simulator

Application Notes

Application Bulletins

Software Examples

Prototyping Assembler

Linker

Logic Analyzer with

DSP561xx ROM Packages

Data Acquisition Cards

DSP Development System

Cards

C Compiler

Simulator

Application Development

System (ADS)

In-Circuit Emulator

Cable for ADS

Operating System Software

Debug Software

Design

Verification

Application Development

System (ADS)

In-Circuit Emulator

Simulator

Data Acquisition Packages

Logic Analyzer with

DSP561xx ROM Packages

Data Acquisition Cards

DSP Development System

Cards

Application-Specific

Development Tools

Debug Software

Specific information on the companies that offer these products is available by calling the

DSP third party information number given in Section 12.10.

MOTOROLA

ADDITIONAL SUPPORT

12 - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOTOROLA DSP PRODUCT SUPPORT

The following is a partial list of the support available for the DSP561xx. Additional

information on DSP56100 family members can be obtained through Dr. BuB or the

appropriate support telephone service.

12.3

MOTOROLA DSP PRODUCT SUPPORT

• DSP56100CLASx Design-In Software Package which includes:

Relocatable Macro Assembler

Linker

Simulator (simulates single or multiple DSP561xxs)

Librarian

• DSP561xx Applications Development System (ADS)

• Support Integrated Circuits

• DSP Bulletin Board (Dr. BuB)

• Motorola DSP Newsletter

• Motorola Technical Service Engineers (TSEs)

See your local telephone directory for the Motorola Semiconductor Sector sales

ofﬁce telephone number.

• Design Hotline

• Applications Assistance

• Marketing Information

• Third-Party Support Information

• University Support Information

12.3.1

DSP56100CLASx Assembler/Simulator

12.3.1.1 Macro Cross Assembler and Simulator Platforms

1. IBM PCs and clones using an 80386 or upward compatible processor

2. Macintosh computers with a NU-BUS expansion port

3. SUN computer

12.3.1.2 Macro Cross Assembler Features

• Production of relocatable object modules compatible with linker program when in

relocatable mode

• Production of absolute ﬁles compatible with simulator program when in absolute

mode

• Supports full instruction set, memory spaces, and parallel data transfer ﬁelds of

the DSP561xx

12 - 4

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOTOROLA DSP PRODUCT SUPPORT

• Modular programming features: local labels, sections, and external deﬁnition/ref-

erence directives

• Nested macro processing capability with support for macro libraries

• Complex expression evaluation including boolean operators

• Built-in functions for data conversion, string comparison, and common transcen-

dental math functions

• Directives to deﬁne circular and bit-reversed buffers

• Extensive error checking and reporting

12.3.1.3 Simulator Features

• Simulation of all DSP56100 family DSPs

• Simulation of multiple DSP56100 family DSPs

• Linkable object code modules:

–Nondisplay simulator library

–Display simulator library

• C language source code for:

–Screen management functions

–Terminal I/O functions

–Simulation examples

• Single stepping through object programs

• Conditional or unconditional breakpoints

• Program patching using a single-line assembler/disassembler

• Instruction, clock cycle, and histogram counters

• Session and/or command logging for later reference

• ASCII input/output ﬁles for peripherals

• Help-line display and expanded on-line help for simulator commands

• Loading and saving of ﬁles to/from simulator memory

• Macro command deﬁnition and execution

• Display enable/disable of registers and memory

• Hexadecimal/decimal/binary calculator

12.3.2

Application Development Systems

• Application Development Systems (ADS) are available for all family members. Up-

grading an ADS to run a different Motorola DSP is done by purchasing and plug-

ging in a new Application Development Module.

MOTOROLA

ADDITIONAL SUPPORT

12 - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SUPPORT INTEGRATED CIRCUITS

12.3.2.1 DSP561xxADSx Application Development System Hardware Features

• Full-speed operation

• Multiple application development module (ADM) support with programmable ADM

addresses

• User-conﬁgurable RAM for DSP561xx code development

• Expandable monitor ROM

• 96-pin Euro-card connector making all pins accessible

• In-circuit emulation capabilities using OnCE

• Separate berg pin connectors for alternate accessing of serial or host/DMA ports

• ADM can be used in stand-alone conﬁguration

• No external power supply needed when connected to a host platform

• 3V emulation support in target environments

12.3.2.2 DSP561xxADSx Application Development System Software Features

• Full-speed operation

• Single/multiple stepping through DSP561xx object programs

• Up to 99 conditional or unconditional breakpoints

• Program patching using a single-line assembler/disassembler

• Session and/or command logging for later reference

• Loading and saving ﬁles to/from ADM memory

• Macro command deﬁnition and execution

• Display enable/disable of registers and memory

• Debug commands supporting multiple ADMs

• Hexadecimal/decimal/binary calculator

• Host operating system commands from within ADS user interface program

• Multiple OS I/O ﬁle access from DSP561xx object programs

• Fully compatible with the DSP56100CLASx design-in software package

• On-line help screens for each command and DSP561xx register

12.4

SUPPORT INTEGRATED CIRCUITS

• DSP56ADC16 16-bit, 100-kHz analog-to-digital converter

• DSP56401 AES/EBU processor

• DSP56200 FIR ﬁlter

12 - 6

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOTOROLA DSP NEWS

12.5

MOTOROLA DSP NEWS

The Motorola DSP News is a quarterly newsletter providing information on new products,

application briefs, questions and answers, DSP product information, third-party product

news, etc. This newsletter is free and is available upon request by calling the marketing

information phone number listed below.

12.6

MOTOROLA FIELD APPLICATION ENGINEERS

Information and assistance for DSP applications is available through the local Motorola

field office. See your local telephone directory for telephone numbers or call (512)891-

2030.

12.7

DSP APPLICATIONS HELP LINE – (512) 891-3230

Design assistance for specific DSP applications is available by calling this number.

12.8

DESIGN HOTLINE – 1-800-521-6274

This is the Motorola number for information pertaining to any Motorola product.

12.9

DSP MARKETING INFORMATION – (512) 891-2030

Marketing information including brochures, application notes, manuals, price quotes, etc.

for Motorola DSP-related products are available by calling this number.

12.10 DSP THIRD-PARTY SUPPORT INFORMATION – (512) 891-3098

Information concerning third-party manufacturers using and supporting Motorola DSP

products is available by calling this number. Third-party support includes:

Filter design software

Logic analyzer support

Boards for VME, IBM-PC/XT/AT, MACII, SPARC, HP300

Development systems

Data conversion cards

Operating system software

Debug software

Additional information is available on Dr. BuB and in DSP News.

12.11 DSP UNIVERSITY SUPPORT – (512) 891-3098

Information concerning university support programs and university discounts for all

Motorola DSP products is available by calling this number.

MOTOROLA

ADDITIONAL SUPPORT

12 - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DSP TRAINING COURSES – (602) 897-3665 or (800) 521-6274

12.12 DSP TRAINING COURSES – (602) 897-3665 or (800) 521-6274

Training information on the DSP56100 family members is available by writing:

Motorola SPS Training and Technical Operations

Mail Drop EL524

P. O. Box 21007

Phoenix, Arizona 85036

or by calling the number above. A technical training catalog is available which describes

these courses and gives the current training schedule and prices.

12.13 Dr. BuB ELECTRONIC BULLETIN BOARD

Dr. BuB is an electronic bulletin board providing free source code for a large variety of

topics that can be used to develop applications with Motorola DSP products. The software

library includes files including FFTs, FIR filters, IIR filters, lattice filters, matrix algebra

routines, companding routines, floating-point routines, and others. In addition, the latest

product information and documentation (including information on new products and

improvements on existing products) is posted. Questions concerning Motorola DSP

products posted on Dr. BuB are answered promptly.

Dr. BuB is open 24-hour a day, 7 days per week and offers the DSP community informa-

tion on Motorola’s DSP products, including:

• Public domain source code for Motorola’s DSP products including the DSP56000

family, the DSP56100 family and the DSP96002

• Announcements about new products and policies

• Technical discussion groups monitored by DSP application engineers

• Confidential mail service

• Calendar of events for Motorola DSP

• Complete list of Motorola DSP literature and ordering information

• Information about the Third-Party and University Support Programs.

To logon to the bulletin board, follow these instructions:

1. Set the character format on your modem to 8 data bits, no parity, 1 stop bit,

then dial (512) 891-3771. Dr. BuB will automatically set the data transfer rate

to match your modem (9600, 4800, 2400, 1200 or 300 BPS).

2. Once the connection has been established, you will see the Dr. BuB login

prompt (you may have to press the carriage return a couple times). If you just

want to browse the system, login as guest. If you would like all the privileges

that are normally allowed on the system, enter new at the login prompt.

12 - 8

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

3. If you open a new account, you will be asked to answer some questions such

as name, address, phone number, etc. After answering these questions, you

will have immediate access to all features of the system including download

privilege, electronic mail and participation in discussion groups.

4. You will have an hour of access time for each call (upload and download time

doesn’t count against you) and you can call as often as you like. If you need

more time on line, just send an electronic mail request to the system operator

(sysop).

The following is a partial list of the software available on Dr. BuB.

Document ID

12.13.1 Audio

rvb1.asm

Version

Synopsis

Size

1.0

Easy-to-read reverberation routine

Same as RVB1.ASM but optimized

Code for C-QUAM AM stereo decoder

Help file for STEREO.ASM

17056

15442

4830

rvb2.asm

stereo.asm

stereo.hlp

620

dge.asm

Digital Graphic Equalizer code from

14880

12.13.2 Benchmarks

Appendix B.1 through B.2.26 DSP56116 (DSP56100 Family) Benchmarks 44436

Appendix B.3 through B.3.9 DSP56116 (DSP56100 Family) Benchmarks 6329

12.13.3 Codec Routines

loglin.asm

1.0

Companded CODEC to linear PCM data

conversion

4572

loglin.hlp

Help for loglin.asm

1479

2184

1993

4847

loglint.asm

loglint.hlp

linlog.asm

1.0

1.1

Test program for loglin.asm

Help for loglint.asm

Linear PCM to companded CODEC data

conversion

linlog.hlp

Help for linlog.asm

1714

12.13.4 DTMF Routines

clear.cmd

data.lod

det.asm

1.0

Explained in read.me file

119

421

Subroutine used in IIR DTMF

5923

MOTOROLA

ADDITIONAL SUPPORT

12 - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

dtmf.asm

Version

1.0

Synopsis

Main routine used in IIR DTMF

Memory for DTMF routine

Size

10685

48

dtmf.mem

1.0

dtmfmstr.asm

dtmfmstr.mem

dtmftwo.asm

ex56.bat

1.0

Main routine for multichannel DTMF

Memory for multichannel DTMF routine

7409

41

1.0

10256

94

1.0

genxd.lod

1.0

Data file

183

genyd.lod

1.0

Data file

180

goertzel.asm

goertzel.lnk

goertzel.lst

load.cmd

1.0

Goertzel routine

Link file for Goertzel routine

List file for Goertzel routine

4393

6954

11600

46

1.0

tstgoert.mem

sub.asm

1.0

Memory for Goertzel routine

Subroutine linked for use in IIR DTMF

Instructions

384

1.0

2491

738

read.me

1.0

12.13.5 Fast Fourier Transforms

sincos.asm

sincos.hlp

1.2

Sine-Cosine Table Generator for FFTs

Help for sincos.asm

1185

887

sinewave.asm

1.1

Full-Cycle Sine wave Table Generator

Generator Macro

1029

sinewave.hlp

fftr2a.asm

fftr2a.hlp

for sinewave.asm

1395

3386

2693

999

1.1

1.2

1.0

Radix 2, In-Place, DIT FFT (smallest)

Help for fftr2a.asm

fftr2at.asm

fftr2at.hlp

fftr2b.asm

fftr2b.hlp

Test Program for FFTs (fftr2a.asm)

Help for fftr2at.asm

563

Radix 2, In-Place, DIT FFT (faster)

Help for fftr2b.asm

4290

3680

5991

3231

3727

fftr2c.asm

fftr2c.hlp

Radix 2, In-Place, DIT FFT (even faster)

Help for fftr2c.asm

fftr2d.asm

Radix 2, In-Place, DIT FFT (using

DSP56001 sine-cosine ROM tables)

fftr2d.hlp

Help for fftr2d.asm

3457

12 - 10

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

fftr2dt.asm

fftr2dt.hlp

fftr2e.asm

fftr2e.hlp

Version

Synopsis

Test program for fftr2d.asm

Help for fftr2dt.asm

Size

1287

614

1.0

1024 Point, Non-In-Place, FFT (3.39ms)

Help for fftr2e.asm

8976

5011

984

fftr2et.asm

fftr2et.hlp

dct1.asm

Test program for fftr2e.asm

Help for fftr2et.asm

408

1.1

1.0

Discrete Cosine Transform using FFT

Help file for dct1.asm

5493

970

dct1.hlp

fftr2cc.asm

Radix 2, In-place Decimation-in-time

complex FFT macro

6524

fftr2cc.hlp

1.0

Help file for fftr2cc.asm

3533

6584

fftr2cn.asm

Radix 2, Decimation-in-time Complex FFT

macro with normally ordered input/output

fftr2cn.hlp

1.0

Help file for fftr2cn.asm

2468

9723

fftr2en.asm

1024 point, not-in-place, complex FFT

macro with normally ordered input/output

fftr2en.hlp

dhit1.asm

1.0

Help file for fftr2en.asm

4886

1851

Routine to compute Hilbert transform

in the frequency domain

dhit1.hlp

1.0

Help file for dhit1.asm

1007

fftr2bf.asm

Radix-2, decimation-in-time FFT with

block floating point

13526

fftr2bf.hlp

1.0

Help file for fftr2bf.asm

1578

3172

fftr2aa.asm

FFT program for automatic scaling

12.13.6 Filters

fir.asm

1.0

Direct Form FIR Filter

Help for fir.asm

545

2161

1164

656

fir.hlp

firt.asm

1.0

Test program for fir.asm

iir1.asm

Direct Form Second Order All Pole

IIR Filter

iir1.hlp

Help for iir1.asm

1786

1157

801

iir1t.asm

iir2.asm

1.0

Test program for iir1.asm

Direct Form Second Order All Pole

IIR Filter with Scaling

MOTOROLA

ADDITIONAL SUPPORT

12 - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

iir2.hlp

Version

Synopsis

Help for iir2.asm

Size

2286

1311

776

iir2t.asm

1.0

Test program for iir2.asm

iir3.asm

Direct Form Arbitrary Order All

Pole IIR Filter

iir3.hlp

Help for iir3.asm

2605

1309

713

iir3t.asm

iir4.asm

1.0

Test program for iir3.asm

Second Order Direct Canonic IIR Filter

(Biquad IIR Filter)

iir4.hlp

Help for iir4.asm

2255

1202

842

iir4t.asm

iir5.asm

1.0

Test program for iir4.asm

Second Order Direct Canonic IIR Filter

with Scaling (Biquad IIR Filter)

iir5.hlp

Help for iir5.asm

2803

1289

923

iir5t.asm

iir6.asm

1.0

Test program for iir5.asm

Arbitrary Order Direct Canonic IIR

Filter

iir6.hlp

Help for iir6.asm

3020

1377

900

iir6t.asm

iir7.asm

iir7.hlp

1.0

Test program for iir6.asm

Cascaded Biquad IIR Filters

Help for iir7.asm

3947

1432

5818

1981

974

iir7t.asm

lms.hlp

1.0

Test program for iir7.asm

LMS Adaptive Filter Algorithm

Implements the transposed IIR filter

Help file for transiir.asm

transiir.asm

transiir.hlp

12.13.7 Floating-Point Routines

fpdef.hlp

2.0

Storage format and arithmetic

representation definition

10600

fpcalls.hlp

fplist.asm

fprevs.hlp

fpinit.asm

fpadd.asm

2.1

2.0

Subroutine calling conventions

Test file that lists all subroutines

Latest revisions of floating-point lib

Library initialization subroutine

Floating point add

11876

1601

1799

2329

3860

12 - 12

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

fpsub.asm

fpcmp.asm

fpmpy.asm

fpmac.asm

fpdiv.asm

Version

2.1

Synopsis

Floating point subtract

Size

3072

2605

2250

2712

3835

2873

2026

1953

2127

3953

2053

1771

2119

5615

2904

1862

2.1

Floating point compare

2.0

Floating point multiply

2.1

Floating point multiply-accumulate

Floating point divide

2.0

fpsqrt.asm

fpneg.asm

fpabs.asm

fpscale.asm

fpfix.asm

2.0

Floating point square root

Floating point negate

2.0

Floating point absolute value

Floating point scaling

2.0

Floating to fixed point conversion

Fixed to floating point conversion

Floating point CEIL subroutine

Floating point FLOOR subroutine

Solution for LPC coefficients

Help file for DURBIN.ASM

Floating point FRACTION subroutine

fpfloat.asm

fpceil.asm

fpfloor.asm

durbin.asm

durbin.hlp

2.0

1.0

fpfrac.asm

2.0

12.13.8 Functions

log2.asm

1.0

Log base 2 by polynomial

approximation

1118

log2.hlp

Help for log2.asm

719

1018

2262

676

log2t.asm

1.0

Test program for log2.asm

Normalizing base 2 logarithm macro

Help for log2nrm.asm

log2nrm.asm

log2nrm.hlp

log2nrmt.asm

exp2.asm

1.0

Test program for log2nrm.asm

1084

926

Exponential base 2 by polynomial

approximation

exp2.hlp

Help for exp2.asm

759

1019

991

exp2t.asm

sqrt1.asm

1.0

Test program for exp2.asm

Square Root by polynomial

approximation, 7 bit accuracy

sqrt1.hlp

Help for sqrt1.asm

779

sqrt1t.asm

1.0

Test program for sqrt1.asm

1065

MOTOROLA

ADDITIONAL SUPPORT

12 - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

Version

Synopsis

Size

sqrt2.asm

1.0

Square Root by polynomial

approximation, 10 bit accuracy

899

sqrt2.hlp

sqrt2t.asm

sqrt3.asm

sqrt3.hlp

sqrt3t.asm

tli.asm

Help for sqrt2.asm

776

1031

1388

794

1.0

Test program for sqrt2.asm

Full precision Square Root Macro

Help for sqrt3.asm

1.0

1.1

Test program for sqrt3.asm

1053

3253

Linear table lookup/interpolation

routine for function generation

tli.hlp

1.1

1.0

1.1

Help for tli.asm

1510

601

bingray.asm

bingrayt.asm

rand1.asm

rand1.hlp

Binary to Gray code conversion macro

Test program for bingray.asm

Pseudo Random Sequence Generator

Help for rand1.asm

991

2446

704

12.13.9 Lattice Filters

latfir1.asm

latfir1.hlp

1.0

Lattice FIR Filter Macro

Help for latfir1.asm

1156

6327

1424

1174

latfir1t.asm

latfir2.asm

1.0

Test program for latfir1.asm

Lattice FIR Filter Macro

(modified modulo count)

latfir2.hlp

latfir2t.asm

latiir.asm

latiir.hlp

Help for latfir2.asm

1295

1423

1257

6402

1407

1334

1.0

Test program for latfir2.asm

Lattice IIR Filter Macro

Help for latiir.asm

latiirt.asm

latgen.asm

1.0

Test program for latiir.asm

Generalized Lattice FIR/IIR

Filter Macro

latgen.hlp

Help for latgen.asm

5485

1269

1407

7475

1595

latgent.asm

latnrm.asm

latnrm.hlp

latnrmt.asm

1.0

Test program for latgen.asm

Normalized Lattice IIR Filter Macro

Help for latnrm.asm

1.0

Test program for latnrm.asm

12 - 14

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

Version

Synopsis

Size

12.13.10 Matrix Operations

matmul1.asm

matmul1.hlp

matmul2.asm

matmul2.hlp

matmul3.asm

1.0

[1x3][3x3]=[1x3] Matrix Multiplication

Help for matmul1.asm

1817

527

1.0

General Matrix Multiplication, C=AB

Help for matmul2.asm

2650

780

1.0

General Matrix Multiply-Accumulate,

C=AB+Q

2815

matmul3.hlp

Help for matmul3.asm

865

12.13.11 Reed-Solomon Encoder

readme.rs

rscd.asm

newc.c

1.0

Instructions for Reed-Solomon coding

5200

Reed-Solomon coder for DSP56000 simulator 5822

Reed-Solomon coder coded in C

Include file for R-S coder

4075

7971

4011

table1.asm

table2.asm

Include file for R-S coder

12.13.12 Sorting Routines

sort1.asm

sort1.hlp

1.0

Array Sort by Straight Selection

Help for sort1.asm

1312

1908

689

sort1t.asm

sort2.asm

sort2.hlp

1.0

1.1

Test program for sort1.asm

Array Sort by Heapsort Method

Help for sort2.asm

2183

2004

700

sort2t.asm

1.0

2.0

Test program for sort2.asm

12.13.13 Speech

lgsol1.asm

Leroux-Gueguen solution for PARCOR

(LPC) coefficients

4861

lgsol1.hlp

Help for lgsol1.asm

3971

6360

durbin1.asm

1.2

Durbin Solution for PARCOR

(LPC) coefficients

durbin1.hlp

adpcm.asm

adpcm.hlp

Help for durbin1.asm

3616

120512

14817

54733

9952

1.0

32 kbits/s CCITT ADPCM Speech Coder

Help file for adpcm.asm

adpcmns.asm

adpcmns.hlp

Nonstandard ADPCM source code

Help file for adpcmns.asm

MOTOROLA

ADDITIONAL SUPPORT

12 - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Dr. BuB ELECTRONIC BULLETIN BOARD

Document ID

Version

Synopsis

Size

g722.zip

1.11

G.722 Speech Processing Code

(pkzip file for PC)

235864

g722.tar.Z

1.11

G.722 Speech Processing Code

(Compressed tar file for Unix)

339297

12.13.14 Standard I/O Equates

ioequ16.asm

ioequ.asm

1.1

1.0

DSP56100 Standard I/O Equate File

Motorola Standard I/O Equate File

Lower Case Version of ioequ.asm

Standard Interrupt Equate File

10329

8774

8788

1082

ioequlc.asm

intequ.asm

intequlc.asm

Lower Case Version of intequ.asm

12.13.15 Tools and Utilities

srec.c

4.10

Utility to convert DSP56000 OMF format

to SREC.

38975

srec.doc

srec.h

4.10

1.1

Manual page for srec.c.

Include file for srec.c

7951

3472

srec.exe

sloader.asm

Srec executable for IBM PC

22065

3986

Serial loader from the SCI port for the

DSP56001

sloader.hlp

sloader.p

1.1

Help for sloader.asm

2598

736

Serial loader s-record file for download

to EPROM

parity.asm

1.0

Parity calculation of a 24-bit number in

accumulator A

1641

parity.hlp

parityt.asm

parityt.hlp

dspbug

1.0

Help for parity.asm

936

685

259

882

Test program for parity.asm

Help for parityt.asm

Ordering information for free debug

monitor for DSP56000/DSP56001

12.13.16 Current DSP56200 Related Software

p1

p2

p3

p4

1.0

Information on 56200 Filter Software

Interrupt Driven Adaptive Filter Flowchart.

“C” code implementation of p2

6343

10916

25795

10361

Polled I/O Adaptive Filter Flowchart

12 - 16

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

Document ID

Version

Synopsis

Size

24806

9535

p5

p6

p7

p8

p9

1.0

1.1

1.0

“C” code implementation of p4

Interrupt Driven Dual FIR Filter Flowchart.

“C” code implementation of p6

Polled I/O Dual FIR Filter Flowchart

“C” code implementation of p8

28489

9656

28525

12.14 REFERENCE BOOKS AND MANUALS

A list of DSP-related books is included here as an aid for the engineer who is new to the

field of DSP. This is a partial list of DSP references intended to help the new user find

useful information in some of the many areas of DSP applications. Many books could be

included in several categories but are not repeated.

12.14.1 General DSP

ADVANCED TOPICS IN SIGNAL PROCESSING

Jae S. Lim and Alan V. Oppenheim

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988

APPLICATIONS OF DIGITAL SIGNAL PROCESSING

A. V. Oppenheim

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978

DISCRETE-TIME SIGNAL PROCESSING

A. V. Oppenheim and R. W. Schafer

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1989

DIGITAL PROCESSING OF SIGNALS THEORY AND PRACTICE

Maurice Bellanger

New York, NY: John Wiley and Sons, 1984

DIGITAL SIGNAL PROCESSING

Alan V. Oppenheim and Ronald W. Schafer

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975

DIGITAL SIGNAL PROCESSING: A SYSTEM DESIGN APPROACH

David J. DeFatta, Joseph G. Lucas, and William S. Hodgkiss

New York, NY: John Wiley and Sons, 1988

FOUNDATIONS OF DIGITAL SIGNAL PROCESSING AND DATA ANALYSIS

J. A. Cadzow

New York, NY: MacMillan Publishing Company, 1987

MOTOROLA

ADDITIONAL SUPPORT

12 - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

HANDBOOK OF DIGITAL SIGNAL PROCESSING

D. F. Elliott

San Diego, CA: Academic Press, Inc., 1987

INTRODUCTION TO DIGITAL SIGNAL PROCESSING

John G. Proakis and Dimitris G. Manolakis

New York, NY: Macmillan Publishing Company, 1988

MULTIRATE DIGITAL SIGNAL PROCESSING

R. E. Crochiere and L. R. Rabiner

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1983

SIGNAL PROCESSING ALGORITHMS

S. Stearns and R. Davis

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988

SIGNAL PROCESSING HANDBOOK

C.H. Chen

New York, NY: Marcel Dekker, Inc., 1988

SIGNAL PROCESSING – THE MODERN APPROACH

James V. Candy

New York, NY: McGraw-Hill Company, Inc., 1988

THEORY AND APPLICATION OF DIGITAL SIGNAL PROCESSING

Rabiner, Lawrence R., Gold and Bernard

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1975

12.14.2 Digital Audio and Filters

ADAPTIVE FILTER AND EQUALIZERS

B. Mulgrew and C. Cowan

Higham, MA: Kluwer Academic Publishers, 1988

ADAPTIVE SIGNAL PROCESSING

B. Widrow and S. D. Stearns

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985

ART OF DIGITAL AUDIO, THE

John Watkinson

Stoneham. MA: Focal Press, 1988

DESIGNING DIGITAL FILTERS

Charles S. Williams

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1986

DIGITAL AUDIO SIGNAL PROCESSING AN ANTHOLOGY

John Strawn

William Kaufmann, Inc., 1985

12 - 18

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

DIGITAL CODING OF WAVEFORMS

N. S. Jayant and Peter Noll

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984

DIGITAL FILTERS: ANALYSIS AND DESIGN

Andreas Antoniou

New York, NY: McGraw-Hill Company, Inc., 1979

DIGITAL FILTERS AND SIGNAL PROCESSING

Leland B. Jackson

Higham, MA: Kluwer Academic Publishers, 1986

DIGITAL SIGNAL PROCESSING

Richard A. Roberts and Clifford T. Mullis

New York, NY: Addison-Welsey Publishing Company, Inc., 1987

INTRODUCTION TO DIGITAL SIGNAL PROCESSING

Roman Kuc

New York, NY: McGraw-Hill Company, Inc., 1988

INTRODUCTION TO ADAPTIVE FILTERS

Simon Haykin

New York, NY: MacMillan Publishing Company, 1984

MUSICAL APPLICATIONS OF MICROPROCESSORS (Second Edition)

H. Chamberlin

Hasbrouck Heights, NJ: Hayden Book Co., 1985

12.14.3 C Programming Language

C: A REFERENCE MANUAL

Samuel P. Harbison and Guy L. Steele

Prentice-Hall Software Series, 1987.

PROGRAMMING LANGUAGE - C

American National Standards Institute,

ANSI Document X3.159-1989

American National Standards Institute, inc., 1990

THE C PROGRAMMING LANGUAGE

Brian W. Kernighan, and Dennis M. Ritchie

Prentice-Hall, Inc., 1978.

12.14.4 Controls

ADAPTIVE CONTROL

K. Astrom and B. Wittenmark

New York, NY: Addison-Welsey Publishing Company, Inc., 1989

MOTOROLA

ADDITIONAL SUPPORT

12 - 19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

ADAPTIVE FILTERING PREDICTION & CONTROL

G. Goodwin and K. Sin

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984

AUTOMATIC CONTROL SYSTEMS

B. C. Kuo

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1987

COMPUTER CONTROLLED SYSTEMS: THEORY & DESIGN

K. Astrom and B. Wittenmark

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984

DIGITAL CONTROL SYSTEMS

B. C. Kuo

New York, NY: Holt, Reinholt, and Winston, Inc., 1980

DIGITAL CONTROL SYSTEM ANALYSIS & DESIGN

C. Phillips and H. Nagle

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984

ISSUES IN THE IMPLEMENTATION OF DIGITAL FEEDBACK COMPENSATORS

P. Moroney

Cambridge, MA: The MIT Press, 1983

12.14.5 Graphics

CGM AND CGI

D. B. Arnold and P. R. Bono

New York, NY: Springer-Verlag, 1988

COMPUTER GRAPHICS (Second Edition)

D. Hearn and M. Pauline Baker

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1986

FUNDAMENTALS OF INTERACTIVE COMPUTER GRAPHICS

J. D. Foley and A. Van Dam

Reading MA: Addison-Wesley Publishing Company Inc., 1984

GEOMETRIC MODELING

Michael E. Morteson

New York, NY: John Wiley and Sons, Inc.

GKS THEORY AND PRACTICE

P. R. Bono and I. Herman (Eds.)

New York, NY: Springer-Verlag, 1987

ILLUMINATION AND COLOR IN COMPUTER GENERATED IMAGERY

Roy Hall

New York, NY: Springer-Verlag

12 - 20

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

POSTSCRIPT LANGUAGE PROGRAM DESIGN

Glenn C. Reid - Adobe Systems, Inc.

Reading MA: Addison-Wesley Publishing Company, Inc., 1988

MICROCOMPUTER DISPLAYS, GRAPHICS, AND ANIMATION

Bruce A. Artwick

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1985

PRINCIPLES OF INTERACTIVE COMPUTER GRAPHICS

William M. Newman and Roger F. Sproull

New York, NY: McGraw-Hill Company, Inc., 1979

PROCEDURAL ELEMENTS FOR COMPUTER GRAPHICS

David F. Rogers

New York, NY: McGraw-Hill Company, Inc., 1985

RENDERMAN INTERFACE, THE

Pixar

San Rafael, CA. 94901

12.14.6 Image Processing

DIGITAL IMAGE PROCESSING

William K. Pratt

New York, NY: John Wiley and Sons, 1978

DIGITAL IMAGE PROCESSING (Second Edition)

Rafael C. Gonzales and Paul Wintz

Reading, MA: Addison-Wesley Publishing Company, Inc., 1977

DIGITAL IMAGE PROCESSING TECHNIQUES

M. P. Ekstrom

New York, NY: Academic Press, Inc., 1984

DIGITAL PICTURE PROCESSING

Azriel Rosenfeld and Avinash C. Kak

New York, NY: Academic Press, Inc., 1982

SCIENCE OF FRACTAL IMAGES, THE

M. F. Barnsley, R. L. Devaney, B. B. Mandelbrot, H. O. Peitgen,

D. Saupe, and R. F. Voss

New York, NY: Springer-Verlag

12.14.7 Motorola DSP Manuals

MOTOROLA DSP LINKER/LIBRARIAN REFERENCE MANUAL

Motorola, Inc., 1992.

MOTOROLA

ADDITIONAL SUPPORT

12 - 21

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

MOTOROLA DSP ASSEMBLER REFERENCE MANUAL

Motorola, Inc., 1992.

MOTOROLA DSP SIMULATOR REFERENCE MANUAL

Motorola, Inc., 1992.

MOTOROLA DSP56000/DSP56001 USER’S MANUAL

Motorola, Inc.,1990.

MOTOROLA DSP56100 FAMILY MANUAL

Motorola, Inc.,1992.

MOTOROLA DSP56156 USER’S MANUAL

Motorola, Inc.,1992.

MOTOROLA DSP56166 USER’S MANUAL

Motorola, Inc.,1992.

MOTOROLA DSP96002 USER’S MANUAL

Motorola, Inc.,1989.

12.14.8 Numerical Methods

ALGORITHMS (THE CONSTRUCTION, PROOF, AND ANALYSIS OF

PROGRAMS)

P. Berliout and P. Bizard

New York, NY: John Wiley and Sons, 1986

MATRIX COMPUTATIONS

G. H. Golub and C. F. Van Loan

John Hopkins Press, 1983

NUMERICAL RECIPES IN C - THE ART OF SCIENTIFIC PROGRAMMING

William H. Press, Brian P. Flannery,

Saul A. Teukolsky, and William T. Vetterling

Cambridge University Press, 1988

NUMBER THEORY IN SCIENCE AND COMMUNICATION

Manfred R. Schroeder

New York, NY: Springer-Verlag, 1986

12.14.9 Pattern Recognition

PATTERN CLASSIFICATION AND SCENE ANALYSIS

R. O. Duda and P. E. Hart

New York, NY: John Wiley and Sons, 1973

12 - 22

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

CLASSIFICATION ALGORITHMS

Mike James

New York, NY: Wiley-Interscience, 1985

Spectral Analysis:

STATISTICAL SPECTRAL ANALYSIS, A NONPROBABILISTIC THEORY

William A. Gardner

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988

THE FAST FOURIER TRANSFORM AND ITS APPLICATIONS

E. Oran Brigham

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1988

THE FAST FOURIER TRANSFORM AND ITS APPLICATIONS

R. N. Bracewell

New York, NY: McGraw-Hill Company, Inc., 1986

12.14.10 Speech

ADAPTIVE FILTERS – STRUCTURES, ALGORITHMS, AND APPLICATIONS

Michael L. Honig and David G. Messerschmitt

Higham, MA: Kluwer Academic Publishers, 1984

DIGITAL CODING OF WAVEFORMS

N. S. Jayant and P. Noll

Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984

DIGITAL PROCESSING OF SPEECH SIGNALS

Lawrence R. Rabiner and R. W. Schafer

Englwood Cliffs, NJ: Prentice-Hall, Inc., 1978

LINEAR PREDICTION OF SPEECH

J. D. Markel and A. H. Gray, Jr.

New York, NY: Springer-Verlag, 1976

SPEECH ANALYSIS, SYNTHESIS, AND PERCEPTION

J. L. Flanagan

New York, NY: Springer-Verlag, 1972

SPEECH COMMUNICATION – HUMAN AND MACHINE

D. O’Shaughnessy

Reading, MA: Addison-Wesley Publishing Company, Inc., 1987

12.14.11 Telecommunications

DIGITAL COMMUNICATION

Edward A. Lee and David G. Messerschmitt

Higham, MA: Kluwer Academic Publishers, 1988

MOTOROLA

ADDITIONAL SUPPORT

12 - 23

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

REFERENCE BOOKS AND MANUALS

DIGITAL COMMUNICATIONS

John G. Proakis

New York, NY: McGraw-Hill Publishing Co., 1983

12 - 24

ADDITIONAL SUPPORT

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

APPENDIX A

PRELIMINARY

DSP56100 FAMILY INSTRUCTION SET

MAC(su,uu)

• Arithmetic

ABS

• Bit Field

• Program

NEG

Manipulation

BFTSTL

Control

Bcc

NEGC

NORM

RND

ADC

ADD

BFTSTH

BSR

ASL

BFCLR

BRA

SBC

ASL4

ASR

BFSET

BScc

DEBUG

DEBUGcc

Jcc

SUB

BFCHG

SUBL

SWAP

Tcc

ASR4

ASR16

CLR

• Loop

DOLoop

JMP

DO FOREVER

ENDDO

TFR

CLR24

CMP

JSR

TFR2

TST

JScc

BRKcc

CMPM

DEC

NOP

TST2

ZERO

• Move

LEA

REP

DEC24

DIV

REPcc

RESET

RTI

MOVE

• Logical

AND

MOVE(C)

MOVE(I)

MOVE(M)

MOVE(P)

MOVE(S)

DMAC

EXT

ANDI

EOR

RTS

IMAC

IMPY

STOP

SWI

LSL

INC

LSR

WAIT

INC24

MAC

NOT

OR

MACR

MPY

ORI

ROL

MPYR

MPY(su,uu)

ROR

MOTOROLA

A - 1

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

SECTION CONTENTS

A.1

A.1.1

A.2

A.3

A.3.1

A.4

A.5

A.6

A.7

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

Instruction Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3

NOTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4

ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8

Addressing Mode Modifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-11

CONDITION CODE COMPUTATION . . . . . . . . . . . . . . . . . . . . . . . . . A-12

DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-17

INSTRUCTION TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-226

FUNCTIONAL SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-236

A - 2

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INTRODUCTION

A.1 INTRODUCTION

This appendix contains detailed information about each instruction in the DSP56100 family instruction set.

An instruction guide is presented first to help in understanding the individual instruction descriptions. This

is followed by sections on notation and addressing modes. Since the move instruction is a parallel move

with an ALU NOP, the parallel moves are grouped with the MOVE instruction. The instructions are then de-

scribed in alphabetical order.

A.1.1 Instruction Guide

The following information is included in each instruction description with the goal of making each description

self-contained:

Name and Mnemonic: The mnemonic is highlighted in bold type for easy reference.

Assembler Syntax and Operation: For each instruction syntax the corresponding operation is symbolically

described. If there are several operations indicated on a single line in the operation field, those operations

do not necessarily occur in the order shown but are generally assumed to occur in parallel. If a parallel data

move is allowed it will be indicated in parenthesis in both the assembler syntax and operation fields. If a

letter in the mnemonic is optional it will be shown in parenthesis in the assembler syntax field.

Description: A complete text description of the instruction is given together with any special cases and/or

condition code anomalies which the user should be aware of when using that instruction.

Example: An example of the use of the instruction is given. The example is shown in the DSP56100 assem-

bler source code format. Most arithmetic and logical instruction examples include one or two parallel data

moves to illustrate the many types of parallel moves that are possible. The example includes a complete

explanation which discusses the contents of the registers referenced by the instruction (but not those refer-

enced by the parallel moves) both before and after the execution of the instruction. Most examples are de-

signed to be easily understood without the use of a calculator. The contents shown in registers are in hexa-

decimal format.

Condition Codes: The status register is depicted with the condition code bits which can be affected by the

instruction highlighted in bold type. Not all bits in the status register are used. Those which are reserved are

indicated with a double asterisk and are read as zeros.

Instruction Format: The instruction fields, the instruction opcode and the instruction extension word are

specified for each instruction syntax. When the extension word is optional it is so indicated. The values

which can be assumed by each of the variables in the various instruction fields are shown under the instruc-

tion fields heading. Note that the symbols used in decoding the various opcode fields of an instruction are

completely arbitrary. Furthermore, the opcode symbols used in one instruction are completely independent

of the opcode symbols used in a different instruction.

Timing: The number of oscillator clock cycles required for each instruction syntax is given. This information

provides the user a basis for comparison of the execution times of the various instructions in oscillator clock

MOTOROLA

A - 3

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NOTATION

cycles. Please refer to Table A-1 and the section entitled “Instruction Timing” for a complete explanation

of instruction timing including the meaning of the symbols “aio”, “ap”, “ax”, “ax2”, “ea”, “jx”, “mv”, “mvb”,

“mvc”, “mvm”, “mvp”, “rx”, “wio”, “wp”, and “wx”.

Memory: The number of program memory words required for each instruction syntax is given. This informa-

tion provides the user a basis for comparison of the number of program memory locations required for each

of the various instructions in 16-bit program memory words. Please refer to Table A-1 and the section enti-

tled “Instruction Timing” for a complete explanation of instruction memory requirements including the

meaning of the symbols “ea” and “mv”.

A.2 NOTATION

Each instruction description contains symbols used to abbreviate certain operands and operations. Table

A-1 lists the symbols used and their respective meanings.

Table A-1 Instruction Description Notation

Data ALU Registers Operands

Xn

Yn

An

Bn

X

Input register X1 or X0 (16 bits)

Input register Y1 or Y0 (16 bits)

Accumulator registers A2, A1, A0 (A2 - 8 bits, A1 and A0 - 16 bits)

Accumulator registers B2, B1, B0 (B2 - 8 bits, B1 and B0 - 16 bits)

Input register X = X1:X0 (32 bits)

Y

Input register Y = Y1:Y0 (32 bits)

A

Accumulator A = A2:A1:A0 (40 bits) *

B

Accumulator B = B2:B1:B0 (40 bits) *

* Note: In data move operations, shifting and limiting is performed when this register is specified as a

source operand. When specified as a destination operand, sign extension and possibly zero-

ing are performed.

A - 4

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NOTATION

Table A-1 Instruction Description Notation (continued)

Address ALU Registers Operands

Rn

Address registers R0 thru R3 (16 bits)

Nn

Address offset registers N0 through N3 (16 bits)

Program Controller Registers

PC

Program counter register (16 bits)

MR

CCR

SR

Mode register (8 bits)

Condition code register (8 bits)

Status register = MR:CCR (16 bits)

OMR

LA

LC

Operating mode register (8 bits)

Hardware loop address register (16 bits)

Hardware loop counter register (16 bits)

System stack pointer register (6 bits)

Upper portion of the current top of the stack (16 bits)

Lower portion of the current top of the stack (16 bits)

System stack RAM = SSH:SSL (15 locations by 32 bits)

SP

SSH

SSL

SS

Address Operands

ea

Effective address

eax

xxxx

xx

Effective address for X bus

Absolute address (16 bits)

Short jump address (8 bits)

aa

ee

AA

pp

<…>

X:

Absolute short address (5 bits, zero extended)

6 bit PC relative signed address

6-bit absolute signed address

I/O short address (5 bits, one’s extended)

Specifies the contents of the specified address

X memory reference

P:

Program memory reference

Miscellaneous Operands

S,Sn

D,Dn

D[n]

#xx

#xxxx

Source operand register

Destination operand register

Bit n of D destination operand register

Immediate short data (8 bits)

Immediate data (16 bits)

MOTOROLA

A - 5

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NOTATION

Table A-1 Instruction Description Notation (continued)

Unary Operators

x

The over bar is the negation operator

PUSH

PULL

READ

PURGE

| |

Push specified value onto the system stack (SS) operator

Pull specified value from the system stack (SS) operator

Read the top of the system stack (SS) operator

Delete the top value on the system stack (SS) operator

Absolute value operator

Binary Operators

+

Addition operator

-

Subtraction operator

*

Multiplication operator

÷,/

+

|,•

Division operator

Logical inclusive OR operator

Logical AND operator

Logical exclusive OR operator

“Is transferred to” operator

Concatenation operator

→

:

SS

System stack RAM = SSH:SSL (15 locations by 32 bits)

Addressing Mode Operators

<<

<

I/O short addressing mode force operator

Short addressing mode force operator

>

Long addressing mode force operator

#

Immediate addressing mode operator

#>

#<

Immediate long addressing mode force operator

Immediate short addressing mode force operator

Mode Register (MR) Symbols

LF

FV

Loop Flag bit indicating when a DO loop is in progress

ForeVer flag bit indicating when a DOFOREVER loop is in progress

S1,S0 Scaling Mode bits indicating the current scaling mode

Interrupt Mask bits indicating the current interrupt priority level

I1,I0

A - 6

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

NOTATION

Table A-1 Instruction Description Notation (continued)

Condition Code Register (CCR) Symbols (standard definitions)

S

Sticky set during moves from accumulators to memory according to its

definition (see Section 5.3 and A.4)

L

E

Limit bit indicating arithmetic overflow and/or data shifting/limiting

Extension bit indicating if the integer portion of A or B is in use

U

N

Z

Unnormalized bit indicating if the A or B result is unnormalized

Negative bit indicating if bit 39 of the A or B result is set

Zero bit indicating if the A or B result equals zero

V

C

Overflow bit indicating if arithmetic overflow has occurred in A or B

Carry bit indicating if a carry or borrow occurred in A or B result

Instruction Timing Symbols

aio

ap

The time required to access an I/O operand

The time required to access a P memory operand

ax

The time required to access an X memory operand

axx

ea

eab

jx

mv

mvb

mvc

mvm

mvp

rx

The time required to access X memory operands for double read

The time or number of words required for an effective address calculation

The time required for an effective address calculation for branch instructions

The time required to execute part of a jump-type instruction

The time or number of words required for a move-type operation

The time required to execute part of a bit manipulation instruction

The time required to execute part of a MOVEC instruction

The time required to execute part of a MOVEM instruction

The time required to execute part of a MOVEP instruction

The time required to execute part of an RTI or RTS instruction

The number of wait states used in accessing external P memory

The number of wait states used in accessing external X memory

wp

wx

Other Symbols

()

Optional letter, operand or operation

Any arithmetic or logical instruction which allows parallel moves

Extension register portion of an accumulator (A2 or B2)

Least significant

(…)

EXT

LS

LSP

MS

Least significant portion of an accumulator (A0 or B0)

Most significant

MSP

r

Most significant portion of an accumulator (A1 or B1)

Rounding constant

S/L

Sign Ext

Zero

Shifting and/or limiting on a Data ALU register

Sign extension of a Data ALU register

Zeroing of a Data ALU register

MOTOROLA

A - 7

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

A.3 ADDRESSING MODES

The addressing modes are grouped into three categories — register direct, address register indirect and

special. These addressing modes are summarized in Table A-2. All address calculations are performed in

the Address ALU to minimize execution time and loop overhead. Addressing modes specify whether the

operands are in registers, in memory or in the instruction itself (such as immediate data) and provide the

specific address of the operands.

The register direct addressing mode can be subclassified according to the specific register addressed. The

data registers include X1, X0, Y1, Y0, X, Y, A2, A1, A0, B2, B1, B0, A, and B. The control registers include

SR, OMR, SP, SSH, SSL, LA, LC, CCR, and MR.

Address register indirect modes use an address register Rn (R0-R3) to point to locations in X and P mem-

ory. The contents of the Rn address register is the effective address of the specified operand, except in the

“indexed by offset” mode where the effective address is (Rn+Nn). Address register indirect modes use an

address modifier register Mn to specify the type of arithmetic to be used to generate the ea. If an addressing

mode specifies an address offset register, the given address offset register is used to update the corre-

sponding address register. The Rn address register may only use the corresponding address offset register

Nn and the corresponding address modifier register Mn. For example, the address register R0 may only use

the N0 address offset register and the M0 address modifier register during actual address computation and

address register update operations. This unique implementation is extremely powerful and allows the user

to easily address a wide variety of DSP oriented data structures. All address register indirect modes use at

least one set of address registers (Rn, Nn, and Mn), and the double X memory read uses two sets of ad-

dress registers, one for the first X memory read and one for the second X memory read. Only R3:N3 can

be used for this second X memory read and R3 is updated only using the linear arithmetic.

The special addressing modes include immediate and absolute addressing modes as well as implied refer-

ences to the program counter (PC), the system stack (SSH or SSL), and program (P) memory.

Addressing modes may also be categorized by the ways in which they may be used. Table A-3 shows the

various categories to which each addressing mode belongs. The following classifications will be used in the

instruction descriptions.

A - 8

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

Table A-2 DSP56100 Family Addressing Modes

Operand Reference

Uses Mn

Modifier

Addressing Mode

Register Direct

S

C

D

A

P

X XX

Data or Control Register

Address Register Rn

Address Modifier Register Mn

Address Offset Register Nn

No

X

Address Register Indirect

No Update

No

Yes*

Yes

Yes*

Yes

X

Postincrement by 1

Postdecrement by 1

Postincrement by Offset Nn

Indexed by Offset Nn

Predecrement by 1

X

PC Relative

Long Displacement

Short Displacement

Address Register

No

X

Special

Upper word of accumulator

Immediate Data

Immediate Short Data

Absolute Address

Absolute Short Address

Short Jump Address

I/O Short Address

No

X

Implicit

X

Indexed by short displacement

Where:

S = System Stack Reference

P = Program Memory Reference

C =Program Controller Register Reference

X = X Memory Reference

D = Data ALU Register Reference

XX = Double X Memory Read

A = Address ALU Register Reference

*note: M3 is not used for updating R3 in the second read in the X memory

MOTOROLA

A - 9

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

Table A-3 DSP56100 Family Addressing Mode Encoding

Addressing

Categories

Assembler

Addressing Mode

Register Direct

U

P

M

A

Syntax

Data or Control Register

Address Register

Address Offset Register

Address Modifier Register

X

(Table A-1)

Rn

Nn

Mn

Address Register Indirect

No Update

X

(Rn)

(Rn)+

(Rn)-

(Rn)+Nn

(Rn+Nn)

-(Rn)

Postincrement by 1

Postdecrement by 1

Postincrement by Offset Nn

Indexed by Offset Nn

Predecrement by 1

X

Special

Upper word of accumulator

Immediate Data

Absolute Address

X

(A1) or (B1)

#xxxx

xxxx

Immediate Short Data

Short Jump/Branch Address

Absolute Short Address

I/O Short Address

#xx

AA or ee

aa

X

pp

Implicit

Indexed by short displacement

X

R2+xx

Where:

Update Mode (U) The Update Addressing mode is used to modify registers without

any associated data move

Parallel Mode (P) The Parallel Addressing mode is used in instructions where two

effective addresses are required

Memory Mode (M) The Memory Addressing mode is used to refer to operands in

memory using an effective addressing field

Alterable Mode (A) The Alterable Addressing mode is used to refer to alterable or writ-

The address register indirect addressing modes require that the offset register number be the same as the

address register number. The assembler syntax “Nn” supports this feature. The assembler syntax “N” may

be used instead of “Nn” in the address register indirect memory addressing modes. If “N” is specified, the

offset register number is the same as the address register number.

A - 10

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADDRESSING MODES

A.3.1 Addressing Mode Modifiers

The addressing mode selected in the instruction word is further specified by the contents of the address

modifier register Mn. The addressing mode update modifiers (M0-M3) are shown in Table A-4. There are

no restrictions on the use of modifier types with any address register indirect addressing mode.

Table A-4 Addressing Mode Modifier Summary

16-bit Modifier Reg. (M0-M3)

MMMMMMMMMMMMMMMM

Address Calculation Arithmetic

0000000000000000

0000000000000001

0000000000000010

Reverse Carry (Bit Reversed)

Modulo 2

Modulo 3

0111111111111110

0111111111111111

Modulo 32767

Modulo 32768

1000000000000000

Reserved

1111111111111110

1111111111111111

Reserved

Linear (Modulo 65536)

where MMMMMMMMMMMMMMMM = 16-bit Modifier Register Contents

MOTOROLA

A - 11

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

A.4 CONDITION CODE COMPUTATION

The condition code portion of the status register consists of 8 defined bits:

C — Carry

V — Overflow

Z — Zero

N — Negative

U — Unnormalized

E — Extension

L — Limit

S — Sticky

The C,V,Z,N,U,E, and S bits are true condition code bits that reflect the condition of the result of a data ALU

operation. These condition code bits are not affected by address ALU calculations or by data transfers (ex-

cept for the S and L bits) over the XDB, GDB data buses. The L bit is a latching overflow bit which indicates

that an overflow has occurred in the Data ALU or that limiting has occurred when reading a Data ALU reg-

ister. This limiting occurs as the result of a data bus move operation with limiting accumulator data through

the data shifter/limiters. The S bit is a latching bit useful in implementing block floating point FFT algorithms.

When a move to X memory from an accumulator is made, the S bit is set to indicate that scaling should be

implemented on the next FFT pass.

The standard definition of the condition codes is given below. Exceptions to these are given in Table A-5.

C (Carry)

Set if a carry is generated out of the most significant bit of the result for an addition.

Also set if borrow is generated in a subtraction. The carry or borrow is generated out

of bit 39 of the result. Clear otherwise.

V (Overflow)

Set if an arithmetic overflow occurs in the 40 bit result. This indicates that the result

is not representable in the accumulator register and the accumulator register has

overflowed. Cleared otherwise. In Saturation Mode, an arithmetic overflow occurs

in the 32 bit result. This indicates that the result is not representable in the accumu-

lator register without the extension part. The accumulator register has overflowed.

Cleared otherwise.

Z (Zero)

Set if the result equals zero. Cleared otherwise.

N (Negative)

U (Unnormalized)

Set if the most significant bit, bit 39, of the result is set. Cleared otherwise.

Set if the two most significant bits of the MSP portion of the result are the same.

Cleared otherwise. The MSP portion is defined by the scaling mode and the U bit is

computed as follows:

S1

S0

Scaling Mode

U bit Computation

0

1

0

1

0

No scaling

Scale down

Scale up

U = (Bit 31 Bit 30)

U = (Bit 32 Bit 31)

U = (Bit 30 Bit 29)

A - 12

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

E (Extension)

Cleared if all the bits of the integer portion of the result are the same; that is, the bit

patterns 00…00 or 11…11. Set otherwise. The integer portion is defined by the scal-

ing mode and the E bit is computed as follows:

S1

S0

Scaling Mode

Integer Portion

0

1

0

1

0

No scaling

Scale down

Scale up

Bits 39,38,…,32,31

Bits 39,38,…,32

Bits 39,38,…,32,31,30

If E is cleared, then the low-order fractional portion contains all the significant bits and

the high order integer portion is sign extended. In this case, the accumulator exten-

sion register can be ignored. This flag is meaningless if saturation has occurred (the

saturation flag is set, SAT=1).

L (Limit)

Set if the overflow bit V is set. Also set if the data shifter/limiters perform a limiting

operation. In Saturation Mode, the L limit is set by the saturation of the 32 bit result.

Not affected otherwise. The L bit is latched once it is set. The L bit is cleared only by

the processor reset or an instruction that explicitly clears it. The L bit is affected by

data movement operations which read the accumulator registers.

S (Sticky)

Set on moves of accumulators to X memory. This can happen when using a MOVE

instruction or in a parallel move. The S bit is computed according to scaling modes

as follows:

S1

S0

Scaling Mode

Integer Portion

0

1

0

1

0

No scaling

Scale down

Scale up

S=Bit 30 Bit 29

S=Bit 31 Bit 30

S=Bit 29 Bit28

Note:The S bit is a “sticky” bit in the status register. It is cleared only

during reset, ANDI operation, or a move to the status register.

MOTOROLA

A - 13

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

Figure A-1 details how each instruction affects the condition codes. The convention for the notation that is

used in the condition code register representation is:

* set according to the standard definition by the result of the operation

— not affected by the operation

0 cleared

1 set

U undefined, meaningless

? set according to the special computation definition by the result of the operation.

Note that the condition code computation shown in Table A-5 may differ from that defined in the opcode

descriptions. This indicates that the standard definition may be used to generate the specific condition code

result. For example, the Z flag computation for the CLR instruction is shown below as the standard definition

while the opcode description indicates that the Z flag is always set. Table A-5 gives the chip implementation

viewpoint while the opcode description gives the user viewpoint.

A - 14

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

Table A-5 Condition Code Computations

MOTOROLA

A - 15

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

Instruction

S

L

E

U

N

Z

V

C

Notes

Instruction

S

L

E

U

N

Z

V

C

Notes

ABS

ADC

ADD

AND

ANDI

*

—

*

—

*

?

*

—

?

*

—

?

*

?

*

?

*

0

?

—

*

—

?

LSL

LSR

LEA

MAC

MACxx

MACR

*

—

*

—

*

—

*

—

*

—

*

?

—

*

?

—

*

0

—

*

?

—

9,10,11

9,10,12

9,10

2

ASL

ASL4

ASR

ASR4

ASR16

*

—

*

—

*

?

*

?

0

?

1, 3

15,16

4

17

18

MOVE

*

—

*

—

*

?

—

*

—

?

—

?

—

?

—

?

—

?

—

?

MOVE(C)

MOVE(I)

MOVE(M)

MOVE(P)

MOVE(S)

MPY

14

—

*

—

*

—

*

—

*

—

*

—

BFCHG

BFCLR

BFSET

BFTSTH

BFTSTL

—

*

—

?

5

6

5

6

MPYxx

MPYR

*

NEG

NEGC

NOP

NORM

NOT

*

—

*

—

*

—

*

—

*

—

*

—

?

*

—

Bcc

—

*

BRA

BRKcc

BScc

BSR

1

9,10

*

—

?

0

OR

ORI

REP

REPcc

RESET

*

?

*

—

?

—

?

—

?

—

?

—

0

?

—

?

—

9,10

7

CHKAAU

CLR

CLR24

CMP

—

*

—

*

—

*

—

*

?

*

?

*

?

*

?

0

*

—

*

21,22,23

19

—

CMPM

*

RND

ROL

ROR

*

—

*

—

*

?

*

?

*

0

—

?

DEC

DEC24

DIV

*

—

*

—

*

—

*

—

*

?

—

*

?

*

?

9,10,11

9,10,12

19

1,8

DMAC

—

RTI

—

?

—

*

?

—

*

?

—

*

?

—

*

?

—

*

?

—

*

?

—

*

13

RTS

SBC

STOP

DO

—

*

—

?

—

?

—

0

—

*

—

DOFOREVER —

—

*

—

DEBUG

DEBUGcc

ENDDO

EOR

—

*

SUB

*

—

*

—

*

—

*

—

*

—

*

—

*

?

—

*

—

SUBL

SWAP

SWI

1

9, 10

EXT

—

*

—

*

—

?

*

—

?

*

—

*

—

?

*

—

?

*

—

*

ILLEGAL

IMAC

IMPY

INC

Tcc

TFR

TFR2

TFR3

TST

—

*

—

*

—

*

—

*

—

*

—

*

—

0

—

0

19,25,26

INC24

*

?

*

19

0

TST2

—

*

0

24

Jcc

—

WAIT

ZERO

—

*

—

*

—

*

—

*

—

*

—

*

—

JMP

JScc

JSR

Note 1

V — Set if an arithmetic overflow occurs in the 40 bit result. Also set if the most significant

A - 16

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CONDITION CODE COMPUTATION

bit of the destination operand is changed as a result of the left shift. Cleared otherwise.

Note 2

All? bits — Cleared if the corresponding bit in the immediate data is cleared and if the op-

erand is the CCR. Not affected otherwise.

Note 3

Note 4

Note 5

C — Set if bit 39 of source operand is set. Cleared otherwise.

C — Set if bit 0 of source operand is set. Cleared otherwise.

C — Set if all bits specified by the mask are set. Cleared otherwise. Ignore bits which are

not set in the mask.

Note 6

Note 7

C — Set if all bits specified by the mask are cleared. Cleared otherwise. Ignore bits which

are not set in the mask.

All? bits — Set if the corresponding bit in the immediate data is set and if the operand is the

CCR. Not affected otherwise.

Note 8

C — Set if bit 39 of the result is cleared. Cleared otherwise.

N — Set if bit 31 of the result is set. Cleared otherwise.

Z — Set if bits 16-31 of the result are zero. Cleared otherwise.

C — Set if bit 31 of the source operand is set. Cleared otherwise.

C — Set if bit 16 of the source operand is set. Cleared otherwise.

All? bits — Set according to value pulled from the stack.

Note 9

Note 10

Note 11

Note 12

Note 13

Note 14

All? bits — If SR is specified as a destination operand, set according to the corresponding

bit of the source operand. If SR is not specified as a destination operand, L is set if data

limiting occurred. All? bits are not affected otherwise.

Note 15

V — Set if an arithmetic overflow occurs in the 40 bit result. Also set if bit 5 through 39 are

not the same.

Note 16

Note 17

Note 18

Note 19

Note 20

Note 21

C — Set if bit 36 of source operand is set. Cleared otherwise.

C — Set if bit 3 of source operand is set. Cleared otherwise.

C — Set if bit 15 of source operand is set. Cleared otherwise.

Z — Set if the 24 most significant bits of the destination result are all zeroes.

In Saturation mode, only bits 31-32 of the result are examined for saturation.

V — Set if the result of the last address ALU update performed a modulo wrap. Cleared if

the result of the last address ALU did not perform a modulo wrap.

Note 22

Note 23

Z — Set if the result of the last address ALU update is 0. Cleared if the result of the last

address ALU is positive.

N — Set if the result of the last address ALU update is negative. Cleared if the result of the

last address ALU is positive.

Note 24

Note 25

Note 26

(L,E,U should be set to 0)

U,E — Will not be set correctly by this instruction

V — Set to zero regardless of the overflow

MOTOROLA

A - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DESCRIPTIONS

A.5 DESCRIPTIONS

The following section describes each instruction in the DSP56100 family instruction set in complete detail.

The format of each instruction description is given in the Instruction Guide at the beginning of Appendix A.

Instructions which allow parallel moves include the notation “(parallel move)” in both the Assembler Syntax

and the Operation fields. The example given with each instruction discusses the contents of all the registers

and memory locations referenced by the opcode — operand portion of that instruction though not those ref-

erenced by the parallel move portion of that instruction. Please refer to the “Parallel Move Descriptions”

which follow the MOVE instruction description for a complete discussion of parallel moves including exam-

ples which discuss the contents of all the registers and memory locations referenced by the parallel move

portion of an instruction.

Whenever an instruction uses an accumulator as both a destination operand for a Data ALU operation and

as a source for a parallel move operation, the parallel move operation will use the value in the accumulator

prior to execution of any Data ALU operation.

Whenever a bit in the Condition Code Register is defined according to the standard definition as given in

Section A.4 entitled “Condition Code Computation”, a brief definition will be given in normal text in the

Condition Code section of that instruction description. Whenever a bit in the Condition Code Register is de-

fined according to a special definition for some particular instruction, the complete special definition of that

bit will be given in the Condition Code section of that instruction in bold text to alert the user to any special

conditions concerning its use.

The definition and thus the computation of both the E (Extension) and U (Unnormalized) bits of the Condition

Code Register (CCR) varies according to the scaling mode being used. Please refer to the section entitled

“Condition Code Computation” for complete details.

Note: The signed integer portion of an accumulator is not necessarily the same as either the A2 or B2 ex-

tension register portion of that accumulator. The signed integer portion of an accumulator is defined accord-

ing to the scaling mode being used and can consist of the most significant 8,9 or 10 bits of an accumulator.

Please refer to the “Condition Code Computation” section for complete details.

MOTOROLA

INSTRUCTION SET

A - 17

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ABS

Absolute Value

ABS

Operation:

Assembler Syntax:

|D|

→

D

(parallel move)

ABS

D

(parallel move)

Description: Take the absolute value of the destination operand D and store the result in the destination

accumulator.

Example:

ABS

A

X:(R0)+,X1

;take ABS. value, move data into X1, update R0

A Before Execution

A After Execution

FF

A2

FFFF

A1

FFF2

A0

00

A2

0000

A1

000E

A0

Explanation of Example: Prior to execution, the 40-bit

A

accumulator contains the value

$FF:FFFF:FFF2. Since this is a negative number, the execution of the ABS instruction

takes the two’s complement of that value and returns $00:0000:000E.

Note: For the case in which the D operand equals $80:0000:0000 (-256.0), the ABS instruction will cause

an overflow to occur since the result cannot be correctly expressed using the standard 40-bit, fixed

point, two’s complement data representation. Data limiting does not occur i.e., A is not set to the

limiting value of $7F:FFFF:FFFF but remains unchanged.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

E

U

N

Z

V

— Set if A or B result equals zero

— Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

A - 18

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ABS

Absolute Value

ABS

Instruction Format:

ABS

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

1

m

R

H

W

1

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for de-

tails on the m, RR, HHH, and W data fields.

D

A

B

F

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 19

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADC

Add Long with Carry

ADC

Operation:

Assembler Syntax:

S + C + D →

D

(no parallel move)

ADC S,D

(no parallel move)

Description: Add the source operand S and the carry bit C of the condition code register to the destina-

tion operand D and store the result in the destination accumulator. Long words (32 bits)

may be added to the (40-bit) destination accumulator.

Note: The carry bit is set correctly for multiple precision arithmetic using long word operands if the exten-

sion register of the destination accumulator (A2 or B2) is the sign extension of bit 31 of the destina-

tion accumulator (A or B).

Example:

; 64 bit addition:

Y1:Y0:X1:X0 + B2:B1:B0:A1:A0 = B2:B1:A1:A0

ADD

ADC

X,A

Y,B

;add 32-bit LS words;

;add 32-bit MS words with carry

0000

Y1

0001

Y0

8000

X1

0000

X0

(Y1:Y0 not affected by the operation)

(X1:X0 not affected by the operation)

B Before Execution

A Before Execution

00

B2

0000

B1

0001

B0

FF

A2

8000

A1

0000

A0

B After Execution

A After Execution

00

B2

0000

B1

0003

B0

FF

A2

0000

A1

0000

A0

Explanation of Example: This example illustrates long word double precision (64-bit) addition using the

ADC instruction. Prior to execution of the ADD and ADC instructions, the 64-bit value

$0000:0001:8000:0000 is loaded into the Y and X registers (Y:X), respectively. The other

double precision 64-bit value $0000:0001:8000:0000 is loaded into the B and A accumula-

tors (B:A), respectively. Since the 32-bit value loaded into the A accumulator is automati-

cally sign extended to 40 bits and the other 32-bit long word operand is internally sign ex-

tended to 40 bits during instruction execution, the carry bit will be set correctly after the ex-

ecution of the ADD X,A instruction. The ADC Y,B instruction then produces the correct MS

40-bit result. The actual 64-bit result is stored in B1:B0:A1:A0.

A - 20

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADC

Add Long with Carry

ADC

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

V

C

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result is zero. Cleared otherwise

— Set if overflow has occurred in A or B result

— Set if a carry (or borrow) occurs from bit 39 of A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ADC

S,D

Opcode:

15

0

12 11

8

1

7

0

4

0

3

F

0

J

0

1

0

1

0

1

Instruction Fields:

S,D

J

F

X,A

X,B

Y,A

Y,B

0

1

0

1

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 21

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADD

Add

ADD

Operation:

Assembler Syntax:

S + D →

D

(parallel move)

ADD S,D

(parallel move)

Description: Add the source operand S to the destination operand D and store the result in the destina-

tion accumulator. Words (16 bits), long words (32 bits) and accumulators (40 bits) may be

added to the destination accumulator.

Note: The carry bit is set correctly using word or long word source operands if the extension register of

the destination accumulator (A2 or B2) is the sign extension of bit 31 of the destination accumulator

(A or B). The carry bit is always set correctly using accumulator source operands.

Example:

:

ADD

X0,A

:

X0,A

:

X:(R0)+,X0

A,X:(R1)+

X:(R3)+,X1

;16-bit add, update X1,X0,R0,R3

;16-bit add, save accumulator

Before Last Execution

After Last Execution

00

A2

0100

A1

0000

A0

00

A2

00FF

A1

0000

A0

FFFF

X0

FFFF

X0

Explanation of Example: Prior to execution, the16-bit X0 register contains the value $FFFF and the 40-

bit A accumulator contains the value $00:0100:0000. The ADD instruction automatically ap-

pends the 16-bit value in the X0 register with 16 LS zeros, sign extends the resulting 32-bit

long word to 40 bits and adds the result to the 40- bit A accumulator. Thus, 16-bit operands

are added to the MSP portion of A or B (A1 or B1) because all arithmetic instructions as-

sume a fractional, two’s complement data representation. Note that 16-bit operands can be

added to the LSP portion of A or B (A0 or B0) by loading the 16-bit operand into X0 or Y0,

forming a 32-bit word by loading X1 or Y1 with the sign extension of X0 or Y0 and executing

an ADD X,A or ADD Y,A instruction.

A - 22

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ADD

Add

ADD

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

— Set if overflow has occurred in A or B result

— Set if a carry (or borrow) occurs from bit 39 of A or B result

E

U

N

Z

V

C

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

Opcode:

ADD

m

S,D

(parallel move)

15

1

12 11

8

W

8

7

0

7

0

4

0

4

u

3

F

3

F

0

J

0

u

R

1

R

H

K

H

K

0

r

0

r

J

15

0

12 11

1

m

K

u

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields. See the “Dual X Memory Read” de-

scription in the parallel move section for details on the mm, KKK, and rr data fields.

one parallel operation

two parallel reads

S,D

B,A

A,B

X,A

X,B

Y,A

Y,B

J J J

0 0 0

0 1 0

0 1 1

F

0

1

0

1

0

1

0

S,D

J J J

F

1

0

1

0

1

0

1

S,D

u u u u

F

0

1

0

1

0

1

0

S,D

u u u u

F

1

X0,B 1 0 0

Y0,A 1 0 1

Y0,B 1 0 1

X1,A 1 1 0

X1,B 1 1 0

Y1,A 1 1 1

Y1,B 1 1 1

X0,A 0 0 0 0

X0,B 0 0 0 0

Y0,A 0 0 0 1

Y0,B 0 0 0 1

X1,A 0 0 1 0

X1,B 0 0 1 0

Y1,A 0 0 1 1

Y1,B 0 0 1 1

B,A

A,B

1 1 0 0

0

1

X0,A 1 0 0

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 23

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

AND

LogicalAND

AND

Assembler Syntax:

Operation:

S•D[31:16] → D[31:16]

(parallel move)

AND S,D

(parallel move)

where • denotes the logical AND operator

Description: Logically AND the source operand S with bits 31-16 of the destination operand D and store

the result in bits 31-16 of the destination accumulator. This instruction is a 16-bit operation.

The remaining bits of the destination operand D are not affected.

Example:

AND

X0,A

:

(R2)-N2

;AND X0 with A1, update R2 using N2

Before Execution

After Execution

00

A2

1234

A1

5678

A0

00

A2

1200

A1

5678

A0

FF00

X0

FF00

X0

Explanation of Example: Prior to execution, the 16-bit X0 register contains the value $FF00 and the 40-

bit A accumulator contains the value $00:1234:5678. The AND X0,A instruction logically

AND’s the 16-bit value in the X0 register with bits 31-16 of the A accumulator (A1) and

stores the 40-bit result in the A accumulator.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

N

Z

V

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Set if bit 31 of A or B result is set

— Set if bits 31-16 of A or B result are zero

— Always cleared

A - 24

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

AND

LogicalAND

AND

Instruction Format:

AND

S,D

(parallel move)

Opcode:

15

12 11

8

7

0

4

0

3

F

0

J

1

m

R

H

W

1

J

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

S,D

J J

F

0

1

0

1

0

1

0

1

X0,A 0 0

X0,B 0 0

Y0,A 0 1

Y0,B 0 1

X1,A 1 0

X1,B 1 0

Y1,A 1 1

Y1,B 1 1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 25

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ANDI

ANDImmediate

ANDI

Operation:

Assembler Syntax:

#xx • D →

D

(no parallel move)

AND(I) #xx,D

where • denotes the logical AND operator

Description: Logically AND the 8-bit immediate operand (#xx) with the contents of the destination control

register D and store the result in the destination control register. The condition codes are

affected only when the condition code register (CCR) is specified as the destination oper-

and.

Restrictions: The ANDI #xx,MR instruction cannot be used immediately before an ENDDO or RTI in-

struction and cannot be one of the last three instructions in a DO loop (at LA-2, LA-1 or LA).

The ANDI #xx,CCR instruction cannot be used immediately before an RTI instruction.

Example:

:

AND

#$FE,CCR

:

;clear carry bit C in cond. code register

SR Before Execution

xx31

SR After Execution

xx30

MR:CCR

Explanation of Example: Prior to execution, the 8-bit condition code register (CCR) contains the value

$31. The AND #$FE,CCR instruction logically AND’s the immediate 8-bit value $FE with

the contents of the condition code register and stores the result in the condition code reg-

ister.

A - 26

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ANDI

ANDImmediate

ANDI

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

For CCR operand:

S

L

— Cleared if bit 7 of the immediate operand is cleared

— Cleared if bit 6 of the immediate operand is cleared

— Cleared if bit 5 of the immediate operand is cleared

— Cleared if bit 4 of the immediate operand is cleared

— Cleared if bit 3 of the immediate operand is cleared

— Cleared if bit 2 of the immediate operand is cleared

— Cleared if bit 1 of the immediate operand is cleared

— Cleared if bit 0 of the immediate operand is cleared

E

U

N

Z

V

C

For MR and OMR operands:

The condition codes are not affected using these operands

Instruction Format:

AND(I)

#xx,D

Opcode:

15

12 11

8

0

7

i

4

i

3

i

0

1

E

i

Instruction Fields::

#xx = 8-bit Immediate Short Data — i i i i i i i i

D

E E

MR

0 1

CCR 1 1

OMR 1 0

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 27

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASL

Arithmetic Shift Accumulator Left

ASL

Assembler Syntax:

ASL

D

(parallel move)

Operation:

0

(parallel move)

C

D2

D1

D0

Description: Arithmetically shift the destination operand D one bit to the left and store the result in the

destination accumulator. The MS bit of D prior to instruction execution is shifted into the car-

ry bit C and a zero is shifted into the LS bit of the destination accumulator D.

Example:

ASL

A

(R3)-

;multiply A by 2, update R3

Before Execution

After Execution

A5

A2

0123

A1

0123

A0

4A

A2

0246

A1

0246

A0

0300

0373

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $A5:0123:0123.

Execution of the ASL A instruction shifts the 40-bit value in the A accumulator one bit to the

left and stores the result back in the A accumulator. The C bit of CCR (bit 0) is set by the

operation because bit 39 of A was set prior to the instruction execution. The V bit of CCR

(bit 1) is also set because bit 39 of A has changed during the instruction execution. The U

bit of CCR (bit 4) is set because the result is unnormalized, the E bit of CCR (bit 5) is set

because the signed integer portion of the result is in use, and the L bit of CCR (bit 6) is also

set because an overflow has occurred.

A - 28

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASL

Arithmetic Shift Accumulator Left

ASL

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

— Set if bit 39 of A or B result is changed due to left shift

— Set if bit 39 of A or B was set prior to instruction execution

E

U

N

Z

V

C

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ASL

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

1

m

R

H

W

0

1

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 29

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASL4

4-bit Arithmetic Shift Accumulator Left

ASL4

Assembler Syntax:

ASL4

D

(no parallel move)

Operation:

36

0

C

D2

D1

D0

Description: Arithmetically shift the destination operand D four bits to the left and store the result in the

destination accumulator. Bit 36 of D (bit 4 of D2) prior to instruction execution is shifted into

the carry bit C and zeros are shifted into the four LS bits of the destination accumulator D.

Example:

ASL4

A

;scaled four times to the left

Before Execution

After Execution

B5

A2

0123

A1

0123

A0

50

A2

1230

A1

1230

A0

0300

0373

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $B5:0123:0123.

Execution of the ASL4 A instruction shifts the 40-bit value in the A accumulator four bits to

the left and stores the result ($50:1230:1230) back in the A accumulator.The C bit of CCR

(bit 0) is set by the operation because bit 36 of A was set prior to the instruction execution.

The V bit of CCR (bit 1) is also set because bit 39 of A has changed during the instruction

execution. The U bit of CCR (bit 4) is set because bit 31 and 30 of the result are equal, the

E bit of CCR (bit 5) is set because the signed integer portion of the result is in use, and the

L bit of CCR (bit 6) is also set because an overflow has occurred.

Warning:

The saturation mode is ALWAYS disabled during execution of ASL4, even when the satu-

ration bit (SA) of the OMR is set.

ASL4 A (or B) can be followed by a MOVE A,A (or B,B) for proper operation when the sat-

uration mode is turned on. However, the “V” bit of the status register will never be set by

the saturation of the accumulator during the MOVE A,A (of B,B). Only the “L” bit will then

be set. If the “V” bit needs to be tested by the user program, ASL4 has to be substituted by

a repetition of four ASLs.

Refer to Sections 5.3 and 5.8 for more details.

A - 30

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASL4

4-bit Arithmetic Shift Accumulator Left

ASL4

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

L

— Set if overflow has occurred in result

E

U

N

Z

V

C

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

— Set if bit 35 through 39 of A or B are not the same before the shift

— Set if bit 36 of A or B was set prior to instruction execution

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ASL4

D

Opcode:

15

0

12 11

8

1

7

0

4

1

3

F

0

1

0

1

0

1

0

1

0

Instruction Fields:

D

F

A

B

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 31

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR

Arithmetic Shift Accumulator Right

ASR

Assembler Syntax:

ASR

D

(parallel move)

Operation:

C

(parallel move)

D2

D1

D0

Description: Arithmetically shift the destination operand D one bit to the right and store the result in the

destination accumulator. The LS bit of D prior to instruction execution is shifted into the car-

ry bit C and the MS bit of D is held constant.

Example:

:

ASR

B

X:-(R3),R3

;divide B by 2 (unless B is -1), update R3, load R3

Before Execution

After Execution

A8

B2

A864

B1

A865

B0

D4

B2

5432

B1

5432

B0

0300

0329

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit

B

accumulator contains the value

$A8:A864:A865. Execution of the ASR B instruction shifts the 40-bit value in the B accu-

mulator one bit to the right and stores the result back in the B accumulator. The C bit of

CCR (bit 0) is set by the operation because bit 0 of A was set prior to the instruction exe-

cution. The N bit of CCR (bit 3) is also set because bit 39 of the result in A is set. The E bit

of CCR (bit 5) is set because the signed integer portion of B is used by the result.

A - 32

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR

Arithmetic Shift Accumulator Right

ASR

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

— Always cleared

— Set if bit 0 of A or B was set prior to instruction execution

E

U

N

Z

V

C

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ASR

D

(parallel move)

12 11

Opcode:

15

1

8

7

0

4

1

3

F

0

m

R

H

W

0

1

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program words

MOTOROLA

INSTRUCTION SET

A - 33

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR4

4-bit Arithmetic Shift Accumulator Right

ASR4

Assembler Syntax:

ASR4

D

(no parallel move)

Operation:

3

C

D2

D1

D0

Description: Arithmetically shift the destination operand D four bits to the right and store the result in the

destination accumulator. Bit 3 of D prior to instruction execution is shifted into the carry bit

C and the 4 MS bits of D are set to the MSB of D prior to instruction execution.

Example:

ASR4

B

Before Execution

After Execution

A8

B2

A864

B1

A86C

B0

FA

B2

8A86

4A86

B0

B1

0300

0329

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit

B

accumulator contains the value

$A8:A864:A86C. Execution of the ASR4 B instruction shifts the 40-bit value in the B accu-

mulator four bit to the right and stores the result back in the B accumulator. The C bit of

CCR (bit 0) is set by the operation because bit 3 of B was set prior to the instruction exe-

cution. The N bit of CCR (bit 3) is also set because bit 39 of the result in B is set. The E bit

of CCR (bit 5) is set because the signed integer portion of B is used by the result.

A - 34

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR4

4-bit Arithmetic Shift Accumulator Right

ASR4

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

V

C

— Always cleared

— Set if bit 3 of A or B was set prior to instruction execution

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ASR4

D

Opcode:

15

0

12 11

8

1

7

0

4

1

3

F

0

1

0

1

0

1

0

Instruction Fields:

D

F

A

B

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program words

MOTOROLA

INSTRUCTION SET

A - 35

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR16 16-bit Arithmetic Shift Accumulator Right ASR16

Assembler Syntax:

ASR16

Operation:

D

(no parallel move)

15

C

(no parallel move)

D2

D1

D0

Description: Arithmetically shift the destination operand D 16 bits to the right and store the result in the

destination accumulator. The MS bit of D0 (bit 15 of D), prior to instruction execution, is

shifted into the carry bit C and the MS bits of D are signed extended.

Example:

ASR16

A

Before Execution

After Execution

A8

A2

A864

A1

A864

A0

FF

A2

FFA8

A864

A0

A1

0000

0019

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit

A

accumulator contains the value

$A8:A864:A864. Execution of the ASR16 A instruction shifts the 40-bit value in the A accu-

mulator 16 bits to the right and stores the result back in the A accumulator. The C bit of

CCR (bit 0) is set by the operation because bit 15 of A was set prior to the instruction exe-

cution. The N bit of CCR (bit 3) is also set because bit 39 of the result in A is set. The U bit

of CCR (bit 4) is set because bit 31 and bit 30 of the result are equal.

A - 36

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ASR16 16-bit Arithmetic Shift Accumulator Right ASR16

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

V

C

— Always cleared

— Set if bit 15 of A or B was set prior to instruction execution

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

ASR16

D

(parallel move)

12 11

Opcode:

15

0

8

1

7

0

4

1

3

F

0

1

0

1

0

1

0

Instruction Fields:

D

F

A

B

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program words

MOTOROLA

INSTRUCTION SET

A - 37

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFCHG

Test Bit Field and Change

BFCHG

Operation:

Assembler Syntax:

(<bit field> of destination) → (<bit field> of destination)

BFCHG

#iiii,X:<aa>

#iiii,X:<pp>

#iiii,X:<ea>

#iiii,D

Description: Test up to 8 bits grouped within a byte of the destination operand, complement them and

store the result in the destination memory location. The bits to be tested are selected by an

immediate 16-bit hexadecimal number in which every bit set is to be tested and changed.

The bits to be tested need to be located in the same byte (low byte for bits 0-7; middle byte

for bits 4-11; high byte for bits 8-15). This instruction performs a read-modify-write opera-

tion on the destination memory location or register and requires two destination accesses.

This instruction is very useful for performing I/O bit manipulation.

Example:

BFCHG #$0310,X:<<$FFE2

;test and change bits 4,8,9 in I/O Port B Data Register

Before Execution

After Execution

X:$FFE2

0010

X:$FFE2

0300

0000

SR=MR:CCR

Explanation of Example: Prior to execution, the 16-bit X memory location X:$FFE2 (I/O Port B Data

Register) contains the value $0010. Execution of the instruction tests the state of the bits

4,8,9 in X:$FFE2, does not set the carry bit C in CCR because all of these bits were not set,

and then complements the bits.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

For destination operand SR:

— Changed if specified in the field

For other destination operands:

L

C

— Set if data limiting occurred during 40-bit source move

— Set if the all bits specified by the mask are set

Warning:

Bit field instructions should always be used with a mask different from zero.

A - 38

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFCHG

Test Bit Field and Change

Instruction Format and Opcode:

BFCHG

#iiii,X:<aa>

#iiii,X:<pp>

15

0

12 11

8

7

4

p

3

p

0

p

P

0

1

Destination

0

1

0

1

0

1

0

1

i

1

i

P

i

p

i

p

i

X:<aa>5 bit Absolute

Short Address (aaaaa)

X:<pp>5 bit I/O Short

Address = ppppp

B

0

i

BFCHG

12 11

#iiii,X:<ea>

15

0

8

7

4

3

0

RR

Destination

0

1

0

1

0

1

0

1

i

0

1

— — —

R

i

R

i

00

01

10

11

X:(R0)

X:(R1)

X:(R2)

X:(R3)

B

0

i

“—” = don’t care

BFCHG

#iiii,DDDDD

12 11

15

8

0

7

1

4

3

0

1

0

1

0

1

0

i

D

i

D

B

0

i

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Instruction Fields for second word: BBB Field active

100

010

001

upper byte (bit 8-15)

middle byte (bit 4-11)

lower byte (bit 0-7)

iiiiiiii = 8-bit immediate short data (mask)

Timing:

Memory:

4 + mvb oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 39

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFCLR

Clear Bit Field

BFCLR

Operation:

Assembler Syntax:

0 → (<bit field> of destination)

BFCLR #iiii,X:<aa>

BFCLR #iiii,X:<pp>

BFCLR #iiii,X:<ea>

BFCLR #iiii,D

Description: Clear up to 8 bits grouped within a byte of the destination operand and store the result in

the destination memory location. The bits to be cleared are selected by an immediate 16-

bit hexadecimal number in which every bit set is to be cleared. The bits to be cleared need

to be located in the same byte (low byte for bits 0-7; middle byte for bits 4-11; high byte for

bits 8-15). This instruction performs a read-modify-write operation on the destination mem-

ory location or register and requires two destination accesses. This instruction is very use-

ful for performing I/O bit manipulation.

Example:

BFCLR #$0310,X:<<$FFE2

;test and clear bits 4,8,9 in I/O Port B Data Register

Before Execution

After Execution

X:$FFE2

7F95

X:$FFE2

7C85

0000

SR=MR:CCR

Explanation of Example: Prior to execution, the 16-bit X memory location X:$FFE2 (I/O Port B Data

Register) contains the value $7F95. Execution of the instruction tests the state of the bits

4,8,9 in X:$FFE2, clear the carry bit C in CCR because not all these bits were set, and then

clears the bits.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

For destination operand SR:

— Cleared as defined in the field and if specified in the field

For other destination operands:

L

C

— Set if data limiting occurred during 40-bit source move

— Set if the all bits specified by the mask are set

Clear if the not all bits specified by the mask are set

Warning:

Bit field instructions should always be used with a mask different from zero. If the mask is

zero, the instruction essentially executes two NOPs.

A - 40

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFCLR

Clear Bit Field

BFCLR

Instruction Format and Opcode:

BFCLR

#iiii,X:<aa>

#iiii,X:<pp>

15

0

12 11

8

7

4

p

3

p

0

p

P

Destination

0

1

0

1

0

1

i

1

i

P

i

p

i

p

i

0

X:<aa>5 bit Absolute

Short Address (aaaaa)

X:<pp>5 bit I/O Short

Address = ppppp

1

B

0

i

BFCLR

12 11

#iiii,X:<ea>

15

0

8

7

4

3

0

RR

Destination

0

1

0

1

0

1

i

0

1

— — —

R

i

R

i

00

01

10

11

X:(R0)

X:(R1)

X:(R2)

X:(R3)

B

1

0

i

“—” = don’t care

BFCLR

#iiii,DDDDD

12 11

15

8

0

7

1

4

3

0

1

0

1

0

i

D

i

D

B

0

i

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Instruction Fields for second word: BBB Field active

100

010

001

upper byte (bit 8-15)

middle byte (bit 4-11)

lower byte (bit 0-7)

iiiiiiii = 8-bit immediate short data

Timing:

Memory:

4 + mvb oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 41

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFSET

Set Bit Field

BFSET

Operation:

Assembler Syntax:

1 → (<bit field> of destination)

BFSET #iiii,X:<aa>

BFSET #iiii,X:<pp>

BFSET #iiii,X:<ea>

BFSET #iiii,D

Description: Set up to 8 bits grouped within a byte of the destination operand and store the result in the

destination memory location. The bits to be set are selected by an immediate 16-bit hexa-

decimal number in which every bit set is to be tested and set. The bits to be set need to be

located in the same byte (low byte for bits 0-7; middle byte for bits 4-11; high byte for bits

8-15). This instruction performs a read-modify-write operation on the destination memory

location or register and requires two destination accesses. This instruction is very useful for

performing I/O bit manipulation.

Example:

BFSET #$F400,X:<<$FFE2

;test and set bits 10,12,13,14,15 in I/O Port B

;Data Register

Before Execution

After Execution

X:$FFE2

8921

X:$FFE2

FD21

0000

SR=MR:CCR

Explanation of Example: Prior to execution, the 16-bit X memory location X:$FFE2 (I/O Port B Data

Register) contains the value $8921. Execution of the instruction tests the state of bits

10,12,13,14,15 in X:$FFE2, does not set the carry bit C in CCR because all these bits were

not set, and then sets the bits.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

For destination operand SR:

— Set as defined in the field and if specified in the field

For other destination operands:

L

C

— Set if data limiting occurred during 40-bit source move

— Set if the all bits specified by the mask are set

Warning:

Bit field instructions should always be used with a mask different from zero. If the mask is

zero, the instruction essentially executes two NOPs.

A - 42

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFSET

Set Bit Field

BFSET

Instruction Format and Opcode:

BFSET

#iiii,X:<aa>

#iiii,X:<pp>

15

0

12 11

8

7

4

p

3

p

0

p

P

0

1

Destination

0

1

0

1

0

1

i

1

i

P

i

p

i

p

i

X:<aa>5 bit Absolute

Short Address (aaaaa)

X:<pp>5 bit I/O Short

Address = ppppp

B

0

i

BFSET

12 11

#iiii,X:<ea>

15

0

8

7

4

3

0

RR

Destination

0

1

0

1

0

1

i

0

1

— — —

R

i

R

i

00

01

10

11

X:(R0)

X:(R1)

X:(R2)

X:(R3)

B

0

i

“—” = don’t care

BFSET

#iiii,DDDDD

12 11

15

8

0

7

1

4

3

0

1

0

1

0

i

D

i

D

B

0

i

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Instruction Fields for second word: BBB Field active

100

010

001

upper byte (bit 8-15)

middle byte (bit 4-11)

lower byte (bit 0-7)

iiiiiiii = 8-bit immediate short data

Timing:

Memory:

4 + mvb oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 43

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFTSTH

Test Bit Field High

BFTSTH

Operation:

Assembler Syntax:

<bit field> of destination

BFTSTH

#iiii,X:<aa>

#iiii,X:<pp>

#iiii,X:<ea>

#iiii,D

Description: Test high up to 8 bits grouped within a byte of the destination operand. The bits to be tested

are selected by an immediate 16-bit hexadecimal number in which every bit set is to be test-

ed. The bits to be tested need to be located in the same byte (low byte for bits 0-7; middle

byte for bits 4-11; high byte for bits 8-15). If all the bits tested were high, the C condition bit

is set. This instruction is very useful for performing I/O flag polling.

Example:

BFTSTH #$0310,X:<<$FFE2

;test high bits 4,8,9 in I/O Port B Data Register

Before Execution

After Execution

X:$FFE2

0FF0

X:$FFE2

0FF0

0000

0001

SR=MR:CCR

Explanation of Example: Prior to execution, the 16-bit X memory location X:$FFE2 (I/O Port B Data

Register) contains the value $0FF0. Execution of the instruction tests the state of bits 4,8,9

in X:$FFE2 and sets the carry bit C in CCR because all these bits were set.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

L

C

— Set if data limiting occurred during 40-bit source move

— Set if the all bits specified by the mask are set

WARNING:

Bit field instructions should always be used with a mask different from zero. If the mask is

zero, the instruction essentially executes two NOPs.

A - 44

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFTSTH

Test Bit Field High

BFTSTH

Instruction Format and Opcode:

BFTSTH

#iiii,X:<aa>

#iiii,X:<pp>

15

0

12 11

8

7

4

p

3

p

0

p

P

0

1

Destination

0

1

0

1

0

i

1

i

P

i

p

i

p

i

X:<aa>5 bit Absolute

Short Address (aaaaa)

X:<pp>5 bit I/O Short

Address = ppppp

B

0

i

BFTSTH

12 11

#iiii,X:<ea>

15

0

8

7

4

3

0

RR

Destination

0

1

0

1

0

i

0

1

— — —

R

i

R

i

00

01

10

11

X:(R0)

X:(R1)

X:(R2)

X:(R3)

B

0

i

“—” = don’t care

BFTSTH

#iiii,DDDDD

12 11

15

8

0

7

0

4

3

0

1

0

1

0

i

D

i

D

B

0

i

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Instruction Fields for second word: BBB Field active

100

010

001

upper byte (bit 8-15)

middle byte (bit 4-11)

lower byte (bit 0-7)

iiiiiiii = 8-bit immediate short data

Timing:

Memory:

4 + mvb oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 45

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFTSTL

Test Bit Field Low

BFTSTL

Operation:

Assembler Syntax:

<bit field> of destination

BFTSTL #iiii,X:<aa>

BFTSTL #iiii,X:<pp>

BFTSTL #iiii,X:<ea>

BFTSTL #iiii,D

Description: Test low up to 8 bits grouped within a byte of the destination operand. The bits to be tested

are selected by an immediate 16-bit hexadecimal number in which every bit set is to be test-

ed. The bits to be tested need to be located in the same byte (low byte for bits 0-7; middle

byte for bits 4-11; high byte for bits 8-15). If all the bits tested were low, the C condition bit

is set. This instruction is very useful for performing I/O flag polling.

Example:

BFTSTL #$0310,X:<<$FFE2

;test low bits 4,8,9 in I/O Port B Data Register

Before Execution

After Execution

X:$FFE2

18EC

X:$FFE2

18EC

0000

0001

SR=MR:CCR

Explanation of Example: Prior to execution, the 16-bit X memory location X:$FFE2 (I/O Port B Data

Register) contains the value $18EC. Execution of the instruction tests the state of bits 4,8,9

in X:$FFE2 and sets the carry bit C in CCR because all these bits were cleared.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

L

C

— Set if data limiting occurred during 40-bit source move

— Set if the all bits specified by the mask are cleared

WARNING:

Bit field instructions should always be used with a mask different from zero. If the mask is

zero, the instruction essentially executes two NOPs.

A - 46

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BFTSTL

Test Bit Field Low

BFTSTL

Instruction Format and Opcode:

BFTSTL

#iiii,X:<aa>

#iiii,X:<pp>

15

0

12 11

8

7

4

p

3

p

0

p

P

0

1

Destination

0

1

0

1

0

i

1

i

P

i

p

i

p

i

X:<aa>5 bit Absolute

Short Address (aaaaa)

X:<pp>5 bit I/O Short

Address = ppppp

B

0

i

BFTSTL

12 11

#iiii,X:<ea>

15

0

8

7

4

3

0

RR

Destination

0

1

0

1

0

i

0

1

— — —

R

i

R

i

00

01

10

11

X:(R0)

X:(R1)

X:(R2)

X:(R3)

B

0

i

“—” = don’t care

BFTSTL

#iiii,DDDDD

12 11

15

8

0

7

0

4

3

0

1

0

1

0

i

D

i

D

B

0

i

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Instruction Fields for second word: BBB Field active

100

010

001

upper byte (bit 8-15)

middle byte (bit 4-11)

lower byte (bit 0-7)

iiiiiiii = 8-bit immediate short data

Timing:

Memory:

4 + mvb oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 47

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Bcc

Operation:

Branch Conditionally

Bcc

Assembler Syntax:

If cc, then PC+label → PC

Bcc

xxxx

ee

else PC+1

→ PC

If cc, then PC+Rn

else PC+1

→ PC

Bcc

Rn

Description: If the specified condition is true, program execution continues at location PC+displace-

ment. The PC contains the address of the next instruction. If the specified condition is false,

the program counter (PC) is incremented and program execution continues sequentially.

Short displacement (6 bit signed value), long displacement (16 bit signed value) and ad-

dress register PC relative addressing modes may be used. The 6-bit data is signed extend-

ed to form the effective address.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Restrictions: — A Bcc instruction used within a DO loop cannot begin at the address LA within

that DO loop.

— A Bcc instruction cannot be repeated using the REP instruction.

— Not allowed between addresses P:$0 and P:$40.

Example:

BNN

R2

;jump to P:(PC+R2) if not normalized

Explanation of Example: In this example, program execution is transferred to the address P:(PC+R2) if

the result is not normalized. If the specified condition is not true, no jump is taken and the

program counter is incremented by one.

A - 48

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Bcc

Branch Conditionally

Bcc

Condition Codes Affected:

The condition codes are not affected by this instruction.

Instruction Format and Opcode:

Bcc xxxx

15

12 11

8

7

4

1

3

c

0

c

0

x

0

x

0

x

0

x

1

x

1

x

1

— —

1

x

c

x

c

x

“—” = don’t care

Instruction Fields: xxxx = 16-bit signed relative branch address

Timing: 4+ jx oscillator clock cycles Memory:

Instruction Format and Opcode:

Bcc aa

2 program words

0

15

12 11

8

7

4

e

3

e

0

1

0

1

c

e

Instruction Fields:

Timing: 4 + jx oscillator clock cycles

Instruction Format and Opcode:

ee = 6-bit signed relative short branch address

Memory:

1 program word

Bcc

Rn

RR

Rn

15

0

12 11

8

1

7

4

0

3

c

0

c

00

01

10

11

R0

R1

R2

R3

0

1

R

1

c

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

Instruction Fields:

cc = 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

MOTOROLA

INSTRUCTION SET

A - 49

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BRA

Branch

BRA

Operation:

Assembler Syntax:

PC+label → PC

BRA

xxxx

aa

PC+Rn → PC

BRA

Rn

Description: Branch to the location in program memory at location PC+displacement. The PC contains

the address of the next instruction. Short displacement (8 bit signed value), long displace-

ment (16-bit signed value) and address register PC relative addressing modes may be

used. The 8-bit data is signed extended to form the effective address.

Restrictions: — A BRA instruction used within a DO loop cannot begin at the address LA within that DO

loop.

— A BRA instruction cannot be repeated using the REP instruction.

— Not allowed between addresses P:$0 and P:$40.

Example:

BRA

R2

;jump to P:(PC+R2)

Explanation of Example:

In this example, program execution is transferred to the address P:(PC+R2)

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 50

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BRA

Branch

BRA

Instruction Format and Opcode:

BRA xxxx

15

0

12 11

8

1

7

0

4

1

3

1

0

x

0

x

0

x

0

x

0

x

0

x

0

x

1

x

1

x

— —

x

“—” = don’t care

Instruction Fields: xxxx = 16-bit signed relative branch address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

BRA

aa

15

0

12 11

8

1

7

a

4

a

3

a

0

a

0

1

0

1

a

Instruction Fields: aa = 8-bit signed relative short branch address

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

BRA

15

Rn

0

RR

Rn

12 11

8

1

7

0

4

0

3

1

0

00

01

10

11

R0

R1

R2

R3

0

1

R

Timing:

Memory:

4 + jx oscillator clock cycles

1program word

MOTOROLA

INSTRUCTION SET

A - 51

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BRKcc

Exit Current DO Loop Conditionally

BRKcc

Operation:

Assembler Syntax:

If cc, then

else

LA+1→PC; SSL(LF,FV) → SR; SP-1 → SP;

BRKcc

SSH → LA; SSL → LC; SP-1 → SP

PC+1 → PC

Description: Exit conditionally the current hardware DO loop before the current loop counter (LC) equals

one. It also terminates the DO FOREVER loop. If the value of the current DO loop counter

(LC) is needed, it must be read before the execution of the BRKcc instruction. Initially, the

PC is updated from the LA, the loop flag (LF) and the ForeVer flag (FV) are restored and

the remaining portion of the status register (SR) is purged from the system stack. The loop

address (LA) and the loop counter (LC) registers are then restored from the system stack.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Restrictions: Due to pipelining and the fact that the BRKcc instruction accesses the program controller reg-

isters, the BRKcc instruction must not be immediately preceded by any of the following instructions:

MOVEC to LA, LC, SR, SSH, SSL or SP

MOVEC from SSH

ORI MR

ANDI MR

Also, the BRKcc instruction cannot be the next to last instruction in a DO loop (at LA-1). It cannot be the

only instruction of a DO loop.

A - 52

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BRKcc

Exit Current DO Loop Conditionally

BRKcc

Example:

DO

Y0,END_LP

;exec. loop ending at END_LP (Y0) times

:

MOVEC

CMP

LC,A

Y1,A

;get current value of loop counter (LC)

;compare loop counter with value in Y1

BRKNE

;go to first instruction after Do loop if LC not equal to Y1

:

;

:

;

:

;(last instruction word in DO loop)

;(first instruction AFTER DO loop)

END_LP MOVE

#$123456,X1

Explanation of Example: This example illustrates the use of the BRKcc instruction to terminate the cur-

rent DO loop. The value of the loop counter (LC) is compared with the value in the Y1 reg-

ister to determine if execution of the DO loop should continue. Note that the BRKcc instruc-

tion updates certain program controller registers and automatically jumps past the end of

the DO loop. Thus, no JMP/BRA instruction needs to be included after the BRKcc to trans-

fer program control to the first instruction past the end of the DO loop.

Condition Codes Affected:

The condition codes are not affected by this instruction.

Instruction Format:

BRKcc

Opcode:

15

0

12 11

8

1

7

0

4

1

3

c

0

c

0

c

Instruction Fields:

cc = 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

Timing:

Memory:

2 oscillator clock cycles when cc not true; 8 oscillator clock cycles when cc true

1 program word

MOTOROLA

INSTRUCTION SET

A - 53

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BScc

Operation:

Branch to Subroutine Conditionally

BScc

Assembler Syntax:

If cc, then

SP+1

PC

SR

→ SP

→ SSH

→ SSL

BScc xxxx

PC+xxxx → PC

else

PC+1

→ PC

If cc, then

SP+1

PC

SR

PC+Rn

PC+1

→ SP

BScc Rn

→ SSH

→ SSL

→ PC

else

Description: If the specified condition is true, program execution continues at location PC+displace-

ment. The PC contains the address of the next instruction. If the specified condition is false,

the program counter (PC) is incremented and program execution continues sequentially.

Long displacement (16 bit signed value) and address register PC relative addressing

modes may be used.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Restrictions: — A BScc instruction used within a DO loop cannot begin at the address LA within that

DO loop.

— A BScc instruction used within a DO loop cannot specify the loop address LA as its tar-

get.

— A BScc instruction cannot be repeated using the REP instruction.

— Not allowed between addresses P:$0 and P:$40.

A - 54

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BScc

Branch to Subroutine Conditionally

BScc

Example:

BSLS

R2

;jump to subroutine at P:(PC+R2) if limit set

Explanation of Example: In this example, program execution is transferred to the subroutine at address

P:(PC+R2) if the limit bit is set. If the specified condition is not true, no jump is taken and

the program counter is incremented by one.

Condition Codes Affected:

The condition codes are not affected by this instruction.

Instruction Format and Opcode:

BScc

xxxx

15

0

12 11

8

1

7

4

1

3

c

0

c

0

x

0

x

0

x

0

x

1

x

1

x

— —

0

x

c

x

c

x

“—” = don’t care

Instruction Fields: xxxx = 16-bit signed relative branch address

Timing: 4 + jx oscillator clock cycles Memory:

2 program words

Instruction Format and Opcode:

BScc

Rn

RR

Rn

15

0

12 11

8

1

7

4

0

3

c

0

00

01

10

11

R0

R1

R2

R3

0

1

R

0

c

Timing:

Memory:

4 + jx oscillator clock cycles

1 program words

Instruction Fields:

cc = 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

MOTOROLA

INSTRUCTION SET

A - 55

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BSR

Branch to Subroutine

BSR

Assembler Syntax:

Operation:

SP+1

PC

SR

→ SP

→ SSH

→ SSL

BSR

xxxx

PC+xxxx → PC

SP+1

PC

SR

→ SP

BSR

Rn

→ SSH

→ SSL

→ PC

PC+Rn

Description: Branch to subroutine in program memory at location PC+displacement. The PC contains

the address of the next instruction. Long displacement (16 bit signed value) and address

register PC relative addressing modes may be used.

Restrictions: — A BSR instruction used within a DO loop cannot begin at the address LA within that DO

loop.

— A BSR instruction used within a DO loop cannot specify the loop address LA as its tar-

get.

— A BSR instruction cannot be repeated using the REP instruction.

— Not allowed between addresses P:$0 and P:$40.

Example:

BSR

R2

;jump to P:(PC+R2)

Explanation of Example:

In this example, program execution is transferred the subroutine at address P:(PC+R2)

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 56

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

BSR

Branch to Subroutine

BSR

Instruction Format and Opcode:

BSR xxxx

15

0

12 11

8

1

7

0

4

1

3

1

0

x

0

x

0

x

0

x

0

x

0

x

0

x

1

x

0

x

— —

x

“—” = don’t care

Instruction Fields:

xxxx = 16-bit signed relative branch address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

Instruction Format and Opcode:

BSR

Rn

RR

Rn

15

0

12 11

8

1

7

0

4

0

3

1

0

00

01

10

11

R0

R1

R2

R3

0

1

0

R

Timing:

Memory:

4 + jx oscillator clock cycles

1 program words

MOTOROLA

INSTRUCTION SET

A - 57

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CHKAAU

Check Address ALU Result

CHKAAU

Operation:

Assembler Syntax:

Affects V, Z and N bit of CCR according to last Address ALU result

CHKAAU (no parallel move)

Description: Update the V, Z, and N flags in the CCR according to the result of the address calculation.

Only alterable addressing modes will give meaningful flag updates. When the last address

ALU operation was performed on a double read, the update of the CCR is done according

to the result on the first address ALU register.

Example:

CHKAAU

Explanation of Example: see above description.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

N

— Set if bit 15 (MSB) of the result of the address calculation with linear or modulo

modifier is set. Cleared otherwise.

Z

V

— Set if result of the address calculation equals zero. Cleared otherwise.

— Set if overflow occurred out the MSB during address calculation with linear modifi-

er. Set if wraparound occurred during address calculation with modulo modifier.

Cleared otherwise.

Notes:

1. When CHKAAU is used after a double parallel memory read, the first memory read

(i.e., the read not addressed by R3) will affect the flags.

2. When CHKAAU is used after an LEA, the condition codes will not be affected.

A - 58

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CHKAAU

Check address ALU result

CHKAAU

Instruction Format:

CHKAAU

Opcode:

15

0

12 11

8

0

7

0

4

0

3

0

1

0

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 59

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLR

Clear Accumulator

CLR

Operation:

Assembler Syntax:

0

→ D

(parallel move)

CLR

D

(parallel move)

Description: Clear the destination accumulator. This is a 40-bit clear instruction.

Example:

CLR

A

A,X0

;save A into X0 before clearing it

Before Execution

After Execution

12

A2

3456

A1

789A

A0

00

A2

0000

A1

0000

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the CLR A instruction clears the 40-bit A accumulator to zero.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Always cleared

— Always set

— Always cleared

E

U

N

Z

V

— Always set

— Always cleared

A - 60

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLR

Clear Accumulator

CLR

Instruction Format:

CLR

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

0

3

F

0

1

m

R

H

W

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 61

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLR24

Clear 24 MS-bits of Accumulator

CLR24

Operation:

Assembler Syntax:

0 → bit 16-39 of D

(parallel move)

CLR24

D

(parallel move)

Description: Clear the 24 MS bit of the destination accumulator. This is a 24-bit clear instruction.

Example:

CLR24

A

X:(B1),X1

;clear 24 MS bit of A; update X1

Before Execution

After Execution

12

A2

3456

A1

789A

A0

00

A2

0000

A1

789A

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the CLR24 A instruction clears the 24 MS bits of the accumulator A.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Always cleared

— Always set

— Always cleared

E

U

N

Z

V

— Always set

— Always cleared

A - 62

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CLR24

Clear 24 MS-bits of Accumulator

CLR24

Instruction Format:

CLR24

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

1

m

R

H

W

1

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 63

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CMP

Compare

CMP

Operation:

Assembler Syntax:

D - S

(parallel move)

CMP

S,D

(parallel move)

Description: Subtract the two operands and update the condition code register. The result of the sub-

traction operation is not stored.

Note: This instruction subtracts 40-bit operands. When a word is specified as S, it is sign extended and

zero filled to form a valid 40-bit operand. In order for the carry to be set correctly as a result of the

subtraction, D must be properly sign extended. D can be improperly sign extended by writing A1

or B1 explicitly prior to executing the compare so that A2 or B2, respectively, may not represent the

correct sign extension. This note particularly applies to the case where it is extended to compare

16-bit operands such as X0 with A1.

Example:

CMP

Y0,A X0,X:(R1)+N1

;comp. Y0 and A, save X0

Before Execution

After Execution

00

A2

0020

A1

0000

A0

00

A2

0020

A1

0000

A0

0024

Y0

0024

Y0

0300

0319

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $00:0020:0000

and the 16-bit Y0 register contains the value $0024. Execution of the CMP Y0,A instruction

automatically appends the 16-bit value in the Y0 register with 16 LS zeros, sign extends the

resulting 32-bit long word to 40 bits, subtracts the result from the 40-bit A accumulator and

updates the condition code register leaving accumulator A unchanged.

A - 64

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CMP

Compare

CMP

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if result equals zero

E

U

N

Z

V

C

— Set if overflow has occurred in result

— Set if a carry (or borrow) occurs from bit 39 of the result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

CMP

S,D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

J

m

R

H

W

1

0

J

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

S,D

B,A

A,B

X0,A 1 0 0

X0,B 1 0 0

Y0,A 1 0 1

J J J

0 0 0

F

0

1

0

1

0

S,D

J J J

F

1

0

1

0

1

Y0,B 1 0 1

X1,A 1 1 0

X1,B 1 1 0

Y1,A 1 1 1

Y1,B 1 1 1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 65

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CMPM

Compare Magnitude

CMPM

Operation:

Assembler Syntax:

|D| - |S|

(parallel move)

CMPM S,D

(parallel move)

Description: Subtract the two operands and update the condition code register. The result of the sub-

traction operation is not stored.

Note: This instruction subtracts absolute values (magnitude) of 40-bit operands. When a word is specified

as S, it is sign extended and zero filled to form a valid 40-bit operand. In order for the carry to be

set correctly as a result of the subtraction, D must be properly sign extended. D can be improperly

sign extended by writing A1 or B1 explicitly prior to executing the compare so that A2 or B2, respec-

tively, may not represent the correct sign extension. This note particularly applies to the case

where it is extended to compare 16-bit operands such as X0 with A1.

Example:

CMPM

Y0,A X:(B1),X1

;comp. |Y0| and |A|, update X1

Before Execution

After Execution

00

A2

0006

A1

0000

A0

00

A2

0006

A1

0000

A0

FFF7

Y0

FFF7

Y0

0000

0019

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $00:0006:0000

and the 16-bit Y0 register contains the value $FFF7. Execution of the CMPM Y0,A instruc-

tion automatically appends the 16-bit value in the Y0 register with 16 LS zeros, sign extends

the resulting 32-bit long word to 40 bits, takes the absolute value of the resulting number,

subtracts the result from the absolute value of the 40-bit A accumulator and updates the

condition code register leaving the accumulator A unchanged.

A - 66

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

CMPM

Compare Magnitude

CMPM

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if result equals zero

E

U

N

Z

V

C

— Set if overflow has occurred in result

— Set if a carry (or borrow) occurs from bit 39 of the result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

CMPM

S,D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

J

m

R

H

W

1

J

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

S,D

B,A

A,B

X0,A 1 0 0

X0,B 1 0 0

Y0,A 1 0 1

J J J

0 0 0

F

0

1

0

1

0

S,D

J J J

F

1

0

1

0

1

Y0,B 1 0 1

X1,A 1 1 0

X1,B 1 1 0

Y1,A 1 1 1

Y1,B 1 1 1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 67

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEBUG

Enter Debug Mode

DEBUG

Operation:

Assembler Syntax:

Enter the debug mode

DEBUG

Description: Enter the debug mode and wait for OnCE commands.

Condition Codes Affected:

Not affected

A - 68

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEBUG

Enter Debug Mode

DEBUG

Instruction Format:

DEBUG

Opcode:

15

0

12 11

8

0

7

0

4

0

3

0

1

0

Timing:

Memory:

4 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 69

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEBUGcc Enter Debug Mode Conditional DEBUGcc

Operation:

Assembler Syntax:

If cc, then

else

enter the debug mode

DEBUGcc

PC+1 → PC

Description: If the specified condition is true, enter the debug mode and wait for OnCE commands. If

the specified condition is false, continue with the next instruction.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Example:

The following is an example on conditional breakpoint setting using Debugcc:

By replacing the MAC instruction by

a JSR instruction as follows:

:

A conditional breakpoint can be set

on the MAC instruction of the fol-

lowing sequence of code:

:

ASR4

JSR

ADD

:

A

Break

X1,A

ASR4

MAC

ADD

A

X0,Y1,A

X1,A

:

Break

DEBUGcc

MAC

RTS

X0,Y1,A

A - 70

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEBUGcc Enter Debug Mode Conditional DEBUGcc

Condition Codes Affected:

Not affected

Instruction Format:

DEBUGcc

Opcode:

15

0

12 11

8

0

7

0

4

1

3

c

0

c

0

1

0

c

Instruction Fields:

cc = 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

Timing:

Memory:

4 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 71

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEC

Decrement Accumulator

DEC

Operation:

Assembler Syntax:

D-1

→ D

(parallel move)

DEC

D

(parallel move)

Description: Decrement by one the destination accumulator. This is a 40-bit decrement instruction.

Example:

DEC

A

A,X0

;save A into X0 before decrementing it

Before Execution

After Execution

12

A2

3456

A1

789A

A0

12

A2

3456

A1

7899

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the DEC A instruction decrements by one the 40-bit A accumulator.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if result equals zero

E

U

N

Z

V

C

— Set if overflow has occurred in result

— Set if a carry (or borrow) occurs from bit 39 of the result

A - 72

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEC

Decrement Accumulator

DEC

Instruction Format:

DEC

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

0

3

F

0

m

R

H

W

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 73

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEC24

Decrement 24 MS-bit of Accumulator

DEC24

Operation:

Assembler Syntax:

D2:D1-1 → D2:D1

(parallel move);

DEC24

D

(parallel move)

D0 is unchanged

Description: Decrement by one the 24 MS bits of the destination accumulator.

Example:

DEC24

A

X:(B1),X1

;Decrement 24 MS bit of A; update X1

Before Execution

After Execution

12

A2

3456

A1

789A

A0

12

A2

3455

A1

789A

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the DEC24 A instruction decrements by one the 24 MS bit of the accumulator

A.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if the 24 most significant bit of the result are all zeroes

— Set if overflow has occurred in result

E

U

N

Z

V

C

— Set if a carry (or borrow) occurs from bit 39 of the result

A - 74

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DEC24

Decrement 24 MS-bit of Accumulator

DEC24

Instruction Format:

DEC24

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

0

3

F

0

1

m

R

H

W

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 75

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DIV

Divide Iteration

DIV

Assembler Syntax:

DIV

S,D

(parallel move)

Operation:

If D[39] S[15] = 1

then

C;

D1+ S → D1

D1 - S → D1

D2

D1

D0

else

D0

Description: Divide the destination operand D (dividend) by the source operand S (divisor) and store the

result in the destination accumulator D. The 32-bit dividend must be a positive fraction

which has been sign extended to 40-bits and is stored in the full 40-bit destination

accumulator D. The 16-bit divisor is a signed fraction and is stored in the source op-

erand S. Each DIV iteration calculates one quotient bit using a nonrestoring fractional divi-

sion algorithm (see the description on the next page). After execution of the first DIV in-

struction, the destination operand holds both the partial remainder and the formed quotient.

The partial remainder occupies the high order portion of the destination accumulator D and

is a signed fraction. The formed quotient occupies the low order portion of the destination

accumulator D (A0 or B0) and is a positive fraction. One bit of the formed quotient is shifted

into the LSB of the destination accumulator at the start of each DIV iteration. The formed

quotient is the true quotient if the true quotient is positive. If the true quotient is negative,

the formed quotient must be negated. Valid results are obtained only when |D| < |S| and

the operands are interpreted as fractions. Note that this condition ensures that the mag-

nitude of the quotient is less than one (i.e., is fractional) and precludes division by zero.

The DIV instruction calculates one quotient bit based on the divisor and the previous partial

remainder. To produce an N-bit quotient, the DIV instruction is executed N times where N

is the number of bits of precision desired in the quotient, 1< N<16. Thus, for a full precision

(16 bit) quotient, 16 DIV iterations are required. In general, executing the DIV instruction N

times produces an N-bit quotient and a 32-bit remainder which has (32 - N) bits of precision

and whose N MS bits are zeros. The partial remainder is not a true remainder and must be

corrected due to the nonrestoring nature of the division algorithm before it may be used.

Therefore, once the divide is complete, it is necessary to reverse the last DIV operation and

restore the remainder to obtain the true remainder.

The DIV instruction uses a nonrestoring fractional division algorithm which consists of the following opera-

tions:

1. Compare the source and destination operand sign bits: An exclusive OR operation is performed on

bit 39 of the destination operand D and bit 15 of the source operand S;

A - 76

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DIV

Divide Iteration

DIV

2. Shift the partial remainder and the quotient: the 40-bit destination accumulator D is shifted one bit

to the left. The carry bit C is moved into the LSB (bit 0) of the accumulator;

3. Calculate the next quotient bit and the new partial remainder: The 16-bit source operand S (signed

divisor) is either added to, or subtracted from, the MSP portion of the destination accumulator (A1

or B1) and the result is stored back into the MSP portion of that destination accumulator. If the result

of the exclusive OR operation described above was a “1” (i.e., the sign bits were different), the

source operand S is added to the accumulator. If the result of the exclusive OR operation was a “0”

(i.e., the sign bits were the same), the source operand S is subtracted from the accumulator. Due

to the automatic sign extension of the 16-bit signed divisor, the addition or subtraction operation

correctly sets the carry bit C of the condition code register with the next quotient bit.

Example: (4 Quadrant division, 16-bit signed quotient, 32-bit signed remainder)

ABS

A

A,B

;make dividend positive, copy A1 to B1

;save rem. sign in X:$0

;quotient sign in N bit of CCR

;clear carry bit C (quotient sign bit)

;form a 16-bit quotient

;form quotient in A0, remainder in A1

;save quotient and remainder in B1,B0

;go to SAVEQ if quotient is positive

;complement quotient if N bit set

;save quotient in Y1, get signed divisor

;get absolute value of signed divisor

;restore remainder in B1

MOVE

EOR

ANDI

REP

DIV

TFR

JPL

NEG B

B,X:$0

Y0,B

#$FE,CCR

#$10

Y0,A

A,B

SAVEQ

SAVEQ TFR

Y0,B

B

A,B

B0,Y1

ABS

ADD

BFTSTL

BCS

MOVE

NEG B

…

#$8000,X:$0

DONE

#$0,B0

;test sign of remainder

;go to DONE if remainder is positive

;clear LS 16 bits of B

;complement remainder if negative

DONE

Before Execution

0E66

After Execution

00

A2

D7F2

A0

00

A2

121E

A1

6544

A0

A1

0000

1234

6544

1234

Y1

Y0

Y1

Y0

00

B2

0000

00

B2

2452

6544

B1

B0

B1

B0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the 40-bit, sign extended

fractional dividend D (D = $00:0E66:D7F2 = 0.112513535656035 (approx.)) and the 16-bit

Y0 register contains the 16-bit, signed fractional divisor S (S = $1234 = 0.1422119). Since

|D| < |S|, the execution of the divide routine given above stores the correct 16-bit signed

MOTOROLA

INSTRUCTION SET

A - 77

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DIV

Divide Iteration

DIV

quotient in the 16-bit Y1 register (A/Y0 = 0.7911072 = $6544 = Y1). The partial remainder

is restored by reversing the last DIV operation and adding back the absolute value of the

signed divisor in Y0 to the partial remainder in A1. This produces the correct LS16 bits of

the 32-bit signed remainder in the 16-bit B1 register. Note that the remainder is really a 32-

bit value which has 16 bits of precision. Thus, the correct 32-bit remainder is $0000:2452

which is approximately 0.000004329718649.

Note: The divide routine used in the example above assumes that the sign extended 40-bit signed frac-

tional dividend is stored in the A accumulator and that the 16-bit signed fractional divisor is stored

in the Y0 register. This routine produces a full 16-bit signed quotient and a 32-bit signed remainder.

This routine may be greatly simplified for the case in which only unsigned operands are used to pro-

duce a 16-bit positive quotient and a 32-bit positive remainder, as shown below.

1 Quadrant division, 16-bit unsigned quotient, 32-bit unsigned remainder

ANDI

REP

DIV

#$FE,CCR

#$10

X0,A

;clear carry bit C (quotient sign bit)

;form a 16-bit quotient and remainder

;form quotient in A0, remainder in A1

;restore remainder in A1

ADD

X0,A

This last routine assumes that the 40-bit positive, fractional, sign extended dividend is stored in the

A accumulator and that the 16-bit positive, fractional divisor is stored in the X0 register. After exe-

cution, the 16-bit positive fractional quotient is stored in the A0 register while the LS 16-bits of the

32-bit positive fractional remainder are stored in the A1 register.

A - 78

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DIV

Divide Iteration

DIV

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

L

— Set if overflow bit V is set

V

— Set if the MS bit of the destination operand is changed as a result of the

instruction’s left shift operation

C

— Set if bit 39 of the result is cleared

Instruction Format:

DIV

S,D

0

(parallel move)

Opcode:

15

0

12 11

8

1

7

0

4

0

3

F

0

1

0

1

0

— —

1

D

“—” = don’t care

Instruction Fields:

S,D

D D

F

S,D

D D

F

X0,A 0 0

X0,B 0 0

Y0,A 0 1

Y0,B 0 1

0

1

0

1

X1,A 1 0

X1,B 1 0

Y1,A 1 1

Y1,B 1 1

0

1

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 79

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DMAC

Double (Multi) Precision

Multiply-Accumulate with 16-bit Right Shift

DMAC

Operation:

Assembler Syntax:

S1*S2+[D>>16] → D (no parallel move)

DMAC(ss,su,uu)

S1,S2,D

(no parallel move)

Description: Multiply the two 16-bit source operands S1 and S2 and add the product to the destination

accumulator D which has been previously shifted 16 bits to the right. The multiplication can

be performed on signed numbers (ss), unsigned numbers (uu), or mixed (unsigned x

signed, (su)) numbers. This instruction is optimized for multiprecision multiplication sup-

port.

Example:

:

DMACsu

:

Y1,X0,A

X0,A

;save A into X0 before decrementing it

Before Execution

After Execution

12

A2

3456

A1

789A

00

A2

00E0

A1

3388

A0

FFFF

X0

0067

Y1

0067

Y1

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the DMACsu Y1,X0,A multiplies the 16-bit signed value in Y1 by the 16-bit un-

signed value in X0, adds the result of the product to the accumulator A after A has been

shifted right and writes the final result in the accumulator A.

Warning:

The saturation mode is ALWAYS disabled during execution of DMAC, even when the sat-

uration bit (SA) of the OMR is set. Refer to Section 5.8.3 for more details.

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

L

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if result equals zero

E

U

N

Z

V

C

— Set if overflow has occurred in result

— Set if a carry (or borrow) occurs from bit 39 of the result

A - 80

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DMAC

Double (Multi) Precision

Multiply-Accumulate with 16-bit Right Shift

DMAC

Instruction Format:

DMAC(ss,su,uu)

S1,S2,D

(no parallel move)

Opcode:

15

0

12 11

8

1

7

1

4

1

3

F

0

1

0

1

0

s

Q

Instruction Fields:

S1,S2,D QQ F S1,S2,D QQ

F

Arithmetic

ss

Y0,X0,A 0 0 0 X1,Y0,A

Y0,X0,B 0 0 1 X1,Y0,B

Y1,X0,A 0 1 0 X1,Y1,A

Y1,X0,B 0 1 1 X1,Y1,B

1 0

1 1

0

1

0

1

ss

su

uu

0 –

10

11

Note: For DMACsu, the order of S1, S2 is

significant; S1 will always be the signed op-

erand (i.e., Y0,Y1, X1).

“—” = don’t care

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 81

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

Operation:

Assembler Syntax:

SP+1→SP; LA →SSH; LC→SSL; X:<ea> →LC

SP+1→SP; PC→SSH; SR→SSL; offset-1+PC→LA

1→ LF

DO

X:(Rn),expr

#xx,expr

S,expr

SP+1 → SP; LA → SSH; LC→ SSL; #xx → LC

SP+1→SP; PC→SSH; SR→SSL; offset-1+PC→LA

1→ LF

SP+1 → SP; LA → SSH; LC→ SSL; S → LC

SP+1→SP; PC→SSH; SR→SSL; offset-1+PC→LA

1→ LF

End of Loop:

SSL(LF) → SR; SP-1 → SP

SSH → LA; SSL → LC; SP-1 → SP

Description: Begin a hardware DO loop that is to be repeated the number of times specified in the in-

struction’s source operand and whose range of execution is terminated by the destination

operand (shown above as “expr”). No overhead other than the execution of this DO instruc-

tion is required to set up this loop. DO loops can be nested and the loop count can be

passed as a parameter. During the first instruction cycle, the current contents of the Loop

Address (LA) and the Loop Counter (LC) registers are pushed onto the system stack. The

DO instruction’s source operand is then loaded into the Loop Counter (LC) register. The LC

register contains the remaining number of times the DO loop will be executed and can be

accessed from inside the DO loop subject to certain restrictions. If LC equals zero, the DO

loop is not executed. If immediate short data is specified, the 8 LS bits of LC are loaded

with the 8-bit immediate value and the eight MS bits of LC are cleared.

During the second instruction cycle, the current contents of the Program Counter (PC) reg-

ister and the Status Register (SR) are pushed onto the system stack. Stacking LA, LC, PC,

and SR permits nesting DO loops. The DO instruction’s destination address (shown as off-

set which is derived from “expr”) is then loaded into the Loop Address (LA) register after

having been added to the PC. This 16-bit operand is located in the instruction’s 16-bit rel-

ative address extension word as shown in the opcode section. The value in the Program

Counter (PC) register pushed onto the system stack is the address of the first instruction

following the DO instruction (i.e., the first actual instruction in the DO loop). This value is

read (i.e., copied but not pulled) from the top of the system stack to return to the top of the

loop for another pass through the loop.

During the third instruction cycle, the Loop Flag (LF) is set. This results in the PC being re-

peatedly compared with LA to determine if the last instruction in the loop has been fetched.

If LA equals PC, the last instruction in the loop has been fetched and the Loop Counter (LC)

is tested. If LC is not equal to one, it is decremented by one and SSH is loaded into the PC

to fetch the first instruction in the loop again. If LC equals one, the “end of loop” processing

begins.

A - 82

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

When executing a DO loop, the instructions are actually fetched each time through the loop.

Therefore, a DO loop can be interrupted. DO loops can also be nested. When DO loops are

nested, the end of loop addresses must also be nested and are not allowed to be equal.

The assembler generates an error message when DO loops are improperly nested. Nested

DO loops are illustrated in the example.

Note: The assembler determines the offset needed to calculate the address to be loaded into LA at exe-

cution time. This offset is calculated by evaluating the end of loop expression “expr” and subtracting

the address of the next instruction following the DO instruction. This is done to accommodate the

case where the last word in the DO loop is a two word instruction. Thus, the end of loop expression

“expr” in the source code must represent the address of the instruction AFTER the last instruction

in the loop as shown in the example.

During the “end of loop” processing, the Loop Flag (LF) from the lower portion (SSL) of SP

is written into the Status Register (SR), the contents of the Loop Address (LA) register are

restored from the upper portion (SSH) of SP-1, the contents of the Loop Counter (LC) are

restored from the lower portion (SSL) of SP-1 and the Stack Pointer (SP) is decremented

by two. Instruction fetches now continue at the address of the instruction following the last

instruction in the DO loop. Note that LF is the only bit in the Status Register (SR) that is

restored after a hardware DO loop has been exited.

Note: The Loop Flag (LF) is cleared by a hardware reset.

Restrictions: The “end of loop” comparison described above actually occurs at instruction fetch time. That

is, LA is being compared with PC when the instruction at LA-2 is being executed. Therefore, instructions

which access the program controller registers and/or change program flow cannot be used in locations LA-

2, LA-1, or LA.

Proper DO loop operation is not guaranteed if an instruction starting at address LA-2, LA-1, or LA specifies

one of the program controller registers SR, SP, SSL, LA, LC, or (implicitly) PC as a destination register. Sim-

ilarly, the SSH program controller register may not be specified as a source or destination register in an in-

struction starting at address LA-2, LA-1, or LA. Additionally, the SSH register cannot be specified as a

source register in the DO instruction itself and LA cannot be used as a target for jumps to subroutine (i.e.,

BSR, JSR, BScc, or JScc to LA). A DO instruction cannot be repeated using the REP instruction.

MOTOROLA

INSTRUCTION SET

A - 83

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

The following instructions cannot begin at the indicated position(s) near the end of a DO loop:

At LA-2, LA-1 and LA

DO

MOVEC from SSH

MOVEC to LA, LC, SR, SP, SSH or SSL

ANDI MR

ORI MR

Two word instructions which read LC, SP, or SSL

At LA-1

At LA

ENDDO, BRKcc

Single word instructions which read LC, SP, or SSL

any two-word instruction*

Bcc, Jcc

RESET

RTI

BRA, JMP

RTS

BScc, JScc

STOP

WAIT

BSR, JSR

REP, REPcc

*This restriction applies to the situation in which the DSP Simulator’s single line assembler is used to change

the last instruction in a DO loop from a one-word instruction to a two-word instruction.

Other Restrictions

DO SSH,xxxx

BSR, JSR to (LA) whenever the Loop Flag (LF) is set

BScc, JScc to (LA) whenever the Loop Flag (LF) is set

A DO instruction cannot be repeated using the REP instruction.

Notes: Due to pipelining, if an address register (R0-R3, N0-N3 or M0-M3) is changed using a move-type

instruction (LUA, Tcc, MOVE, MOVEC, MOVEP, or parallel move), the new contents of the desti-

nation address register will not be available for use during the following instruction (i.e., there is a

single instruction cycle pipeline delay). This restriction also applies to the situation in which the last

instruction in a DO loop changes an address register and the first instruction at the top of the DO

loop uses that same address register. The top instruction becomes the following instruction be-

cause of the loop construct.

A - 84

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

Similarly, since the DO instruction accesses the program controller registers, the DO instruction must not

be immediately preceded by any of the following instructions:

Immediately before DO

MOVEC to LA, LC, SSH, SSL or SP

MOVEC from SSH

Example:

DO

#cnt1, END1

:

#cnt2, END2

;begin outer DO loop

;begin inner DO loop

DO

:

MOVE

ADD

A,X:(R0)+

:

A,B

:

;last instruction in inner loop

;(in outer loop)

;last instruction in outer loop

;first instruction after outer loop

END2

END1

X:(R1)+,X0

Explanation of Example: This example illustrates a nested DO loop. The outer DO loop will be executed

“cnt1” times while the inner DO loop will be executed (“cnt1” * “cnt2”) times. Note that the

labels END1 and END2 are located at the first instruction past the end of the DO loop, as

mentioned above, and are nested properly.

Condition Codes:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

LF — Set when a DO loop is in progress

— Set if data limiting occurred

L

Note: If A or B is specified as a source operand, the accumulator value is optionally shifted according to

the scaling mode bits in the status register. If the data out of the shifter indicates that the accumu-

lator extension is in use, the 16-bit data is limited to a maximum positive or negative saturation con-

stant. The shifted and limited value is loaded into LC, although A or B remain unchanged.

MOTOROLA

INSTRUCTION SET

A - 85

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

Instruction Format and Opcode:

DO

0

X:(Rn), expr

15

0

12 11

8

7

4

3

0

RR

Rn

0

1

0

— — —

R

00

01

10

11

R0

R1

R2

R3

Relative Address Displacement Extension

“—” = don’t care

DO

#xx, expr

8

15

12 11

7

i

4

i

3

i

0

i

iiii = immediate 8-bit

short data = iiiiiiii

0

1

0

i

Relative Address Displacement Extension

A - 86

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO

Start Hardware Do Loop

DO

0

S,expr

12 11

15

0

8

0

7

0

4

3

0

1

0

D

Relative Address Displacement Extension

S

D D D D D

S

D D D D D

S

D D D D D

S

D D D D D

X0 0 0 0 0 0

Y0 0 0 0 0 1

X1 0 0 0 1 0

Y1 0 0 0 1 1

SR

0 1 0 0 1

R0

R1

R2

R3

M0

M1

M2

M3

1 0 0 0 0

1 0 0 0 1

1 0 0 1 0

1 0 0 1 1

1 0 1 0 0

1 0 1 0 1

1 0 1 1 0

1 0 1 1 1

SSH 1 1 0 0 0

SSL 1 1 0 0 1

OMR 0 1 0 1 0

SP

A1

B1

A2

B2

0 1 0 1 1

0 1 1 0 0

0 1 1 0 1

0 1 1 1 0

0 1 1 1 1

LA

LC

N0

N1

N2

N3

1 1 0 1 0

0 1 0 0 0

1 1 1 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

A

B

0 0 1 0 0

0 0 1 0 1

A0 0 0 1 1 0

B0 0 0 1 1 1

Note: • For DO SP, expr

The actual value that will be loaded into the Loop Counter (LC) is the value of the Stack Pointer

(SP) before the execution of the DO instruction, incremented by one. Thus, if SP = 3, the execu-

tion of the DO SP, expr instruction will load the Loop Counter (LC) with the value LC = 4.

• For DO SSL, expr

The Loop Counter (LC) will be loaded with its previous value which was saved on the stack by

the DO instruction itself.

• If A or B is specified as a source operand, the accumulator value is optionally shifted according

to the scaling mode bits in the status register. If the data out of the shifter indicates that the accu-

mulator extension is in use, the 16-bit data is limited to a maximum positive or negative saturation

constant. The shifted and limited value is loaded into LC, although A or B remain unchanged.

Instruction Field for the second word:

expr = 16-bit PC Relative Address

Timing:

10 + mv oscillator clock cycles if the DO argument equals zero;

otherwise it is 6 + mv oscillator clock cycles

2 program words

Memory:

MOTOROLA

INSTRUCTION SET

A - 87

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO FOREVER Start Infinite Loop DO FOREVER

Operation:

Assembler Syntax:

SP+1→SP; LA →SSH; LC→SSL

SP+1→SP; PC→SSH; SR→SSL; expr-1+PC→LA

1→ LF; 1→FV

DO FOREVER expr

Description: Begin a hardware DO loop that is to be repeated for ever and whose range of execution is

terminated by the destination operand (shown above as “expr”). No overhead other than

the execution of this DO FOREVER instruction is required to set up this loop. DO FOREV-

ER loops can be nested. During the first instruction cycle, the current contents of the Loop

Address (LA) and the Loop Counter (LC) registers are pushed onto the system stack. The

loop counter (LC) register is pushed onto the stack but is not updated by this instruction.

During the second instruction cycle, the current contents of the Program Counter (PC) reg-

ister and the Status Register (SR) are pushed onto the system stack. Stacking the LA, LC,

PC, and SR registers permits nesting DO FOREVER loops. The DO FOREVER instruc-

tion’s destination operand (shown as “expr”) is then loaded into the Loop Address (LA) reg-

ister after having been added to the PC. This 16-bit operand is located in the instruction’s

16-bit relative address extension word as shown in the opcode section. The value in the

Program Counter (PC) register pushed onto the system stack is the address of the first in-

struction following the DO FOREVER instruction (i.e., the first actual instruction in the DO

FOREVER loop). This value is read (i.e., copied but not pulled) from the top of the system

stack to return to the top of the loop for another pass through the loop.

During the third instruction cycle, the Loop Flag (LF) and the ForeVer flag are set. This re-

sults in the PC being repeatedly compared with LA to determine if the last instruction in the

loop has been fetched. If LA equals PC, the last instruction in the loop has been fetched

and SSH is loaded into the PC to fetch the first instruction in the loop again. The loop

counter (LC) register is then decremented by one without being tested. This register can be

used by the programer to count the number of loops already executed.

When executing a DO FOREVER loop, the instructions are actually fetched each time

through the loop. Therefore, a DO FOREVER loop can be interrupted. DO FOREVER loops

can also be nested. When DO FOREVER loops are nested, the end of loop addresses must

also be nested and are not allowed to be equal. The assembler generates an error mes-

sage when DO FOREVER loops are improperly nested. Nested DO loops with one DO

FOREVER loop are illustrated in the example.

Note: The assembler determines the offset needed to calculate the address to be loaded into LA at exe-

cution time. This offset is calculated by evaluating the end of loop expression “expr” and subtracting

the address of the next instruction following the DO instruction. This is done to accommodate the

case where the last word in the DO FOREVER loop is a two word instruction. Thus, the end of loop

expression “expr” in the source code must represent the address of the instruction after the last

instruction in the loop as shown in the example.

A - 88

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO FOREVER Start Infinite Loop DO FOREVER

The loop counter (LC) register is never tested by the DO FOREVER instruction and the only way of

terminating the loop process is to use either the ENDDO or BRKcc instructions. LC is decremented

every time PC=LA so that it can be used by the programmer to keep track of the number of times

the DO FOREVER loop has been executed. If the programer wants to initialize LC to a particular

value before the DO FOREVER, care should be taken to save it before if the DO loop is nested. If

so, LC should also be restored immediately after exiting the nested DO FOREVER loop.

Restrictions: The “end of loop” comparison described above actually occurs at instruction fetch time. That

is, LA is being compared with PC when the instruction at LA-2 is being executed. Therefore, instructions

which access the PCU registers and/or change program flow cannot be used in locations LA-2, LA-1 or LA.

Proper DO FOREVER loop operation is not guaranteed if an instruction starting at address LA-2, LA-1, or

LA specifies one of the program control unit registers SR, SP, SSL, LA, or (implicitly) PC as a destination

register. Similarly, the SSH register may not be specified as a source or destination register in an instruction

starting at address LA-2, LA-1, or LA. Additionally, the SSH register cannot be specified as a source register

in the DO FOREVER instruction itself and LA cannot be used as a target for jumps to subroutine (i.e., BSR,

JSR, BScc, or JScc to LA). A DO FOREVER instruction cannot be repeated using the REP instruction.

The following instructions cannot begin at the indicated position(s) near the end of a DO FOREVER loop:

At LA-2, LA-1, and LA

DO

MOVEC from SSH

MOVEC to LA, SR, SP, SSH or SSL

ANDI MR

ORI MR

Two word instructions which read SP, or SSL

At LA-1

At LA

ENDDO, BRKcc

Single word instructions which read SP, or SSL

Any two-word instruction*

Bcc, Jcc

RESET

RTI

BRA, JMP

RTS

BScc, JScc

STOP

WAIT

BSR, JSR

REP, REPcc

*This restriction applies to the situation in which the DSP Simulator’s single line assembler is used to change

the last instruction in a DO FOREVER loop from a one-word instruction to a two-word instruction.

Other Restrictions

BSR, JSR to (LA) whenever the Loop Flag (LF) is set

BScc, JScc to (LA) whenever the Loop Flag (LF) is set

MOTOROLA

INSTRUCTION SET

A - 89

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO FOREVER Start Infinite Loop DO FOREVER

Note: Due to pipelining, if an address register (R0-R3, N0-N3 or M0-M3) is changed using a move-type

instruction (LEA, Tcc, MOVE, MOVEC, or parallel move), the new contents of the destination ad-

dress register will not be available for use during the following instruction (i.e., there is a single in-

struction cycle pipeline delay). This restriction also applies to the situation in which the last instruc-

tion in a DO loop changes an address register and the first instruction at the top of the DO loop uses

that same address register. The top instruction becomes the following instruction because of the

loop construct.

Similarly, since the DO instruction accesses the PCU registers, the DO instruction must not be immediately

preceded by any of the following instructions:

Immediately before DO

MOVEC to LA, SSH, SSL or SP

MOVEC from SSH

Example:

DO

#cnt1, END1

:

FOREVER,END2

;begin outer DO loop

;begin inner DO loop

DO

:

BEQ

REM

ENDDO

BRA

;ENDDO if not EQ

;ENDDO for leaving outer loop

;Branch to (END1) out of upper loop

END1

REM

:

BRKNN

;conditional exit of DO FOREVER; branch to END2 exiting

; loop

:

MOVE

ADD

A,X:(R0)+

:

A,B

:

;last instruction in inner loop

;first instruction in outer loop

;last instruction in outer loop

END2

END1

X:(R1)+,X0

;first instruction after outer loop

Explanation of Example: This example illustrates a nested DO loop with one DO FOREVER loop. The

outer DO loop will be executed “cnt1” times while the inner DO FOREVER loop will be ex-

ecuted till the ENDDO or BRKNN are executed. Note that the labels END1 and END2 are

located at the first instruction past the end of the DO loop, as mentioned above, and are

nested properly.

A - 90

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

DO FOREVER Start Infinite Loop DO FOREVER

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

L

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

V

C

LF

— Set when a DO loop is in progress

Instruction Format:

DO FOREVER expr

Opcode:

15

0

12 11

8

0

7

0

4

0

3

0

1

Relative Address Displacement Extension

Timing:

Memory:

6 oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 91

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ENDDO

End Current DO Loop

ENDDO

Operation:

Assembler Syntax:

SSL(LF,FV) → SR; SP-1 → SP

ENDDO

SSH → LA; SSL → LC; SP-1 → SP

Description: Terminate the current hardware DO loop before the current loop counter (LC) equals one.

It also terminates the DO FOREVER loop. If the value of the current DO loop counter (LC)

is needed, it must be read before the execution of the ENDDO instruction. Initially, the loop

flag (LF) and the ForeVer flag (FV) are restored from the system stack and the remaining

portion of the status register (SR) and the program counter (PC) are purged from the sys-

tem stack. The loop address (LA) and the loop counter (LC) registers are then restored from

the system stack.

Restrictions: Due to pipelining and the fact that the ENDDO instruction accesses the program controller

registers, the ENDDO instruction must not be immediately preceded by any of the following instructions:

Immediately before ENDDO MOVEC to LA, LC, SR, SSH, SSL or SP

MOVEC from SSH

ORI MR

ANDI MR

Also, the ENDDO instruction cannot be the next to last instruction in a DO loop (at LA-1).

Example:

DO

Y0,NEXT

:

;exec. loop ending at NEXT (Y0) times

MOVEC

CMP

JNE

ENDDO

JMP

LC,A

Y1,A

ONWARD

;get current value of loop counter (LC)

;compare loop counter with value in Y1

;go to ONWARD if LC not equal to Y1

;LC equal to Y1, restore all DO registers

;go to NEXT

:

;LC not equal to Y1, continue DO loop

;(last instruction in DO loop)

#$123456,X1

;(first instruction AFTER DO loop)

Explanation of Example: This example illustrates the use of the ENDDO instruction to terminate the cur-

rent DO loop. The value of the loop counter (LC) is compared with the value in the Y1 reg-

ister to determine if execution of the DO loop should continue. Note that the ENDDO in-

struction updates certain program controller registers but does not automatically jump past

the end of the DO loop. Thus, if this action is desired, a JMP/BRA instruction (i.e., JMP

NEXT as shown above) must be included after the ENDDO instruction to transfer program

control to the first instruction past the end of the DO loop.

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 92

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ENDDO

End Current DO Loop

ENDDO

Instruction Format:

ENDDO

Opcode:

15

0

12 11

8

0

7

0

4

0

3

1

0

1

0

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 93

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EOR

Logical Exclusive OR

EOR

Operation:

Assembler Syntax:

S

D[31:16] → D[31:16]

(parallel move)

EOR S,D

(parallel move)

Description: Logically Exclusive OR the source operand S with bits 31-16 of the destination operand D

and store the result in bits 31-16 of the destination accumulator. This instruction is a 16-bit

operation. The remaining bits of the destination operand D are not affected.

Example:

EOR

Y1,B

:

(R2)-

;Exclusive OR Y1 with B1, update R2

Before Execution

After Execution

00

B2

0005

B1

6789

B0

00

B2

0006

B1

6789

B0

0003

Y1

0003

Y1

Explanation of Example: Prior to execution, the 16-bit Y1 register contains the value $0003 and the 40-

bit B accumulator contains the value $00:0005:6789. The EOR Y1,B instruction logically

exclusive OR’s the 16-bit value in the Y1 register with bits 31-16 of the B accumulator (B1)

and stores the 40-bit result in the B accumulator. Note that the lower word of the accumu-

lator, B0, and the extension byte, B2, are not affected by the operation.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

N

Z

V

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Set if bit 31 of A or B result is set

— Set if bits 31-16 of A or B result are zero

— Always cleared

A - 94

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EOR

Logical Exclusive OR

EOR

Instruction Format:

EOR

S,D

(parallel move)

Opcode:

15

12 11

8

7

0

4

1

3

F

0

J

1

m

R

H

W

0

1

J

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

S,D

J J

F

0

1

0

1

0

1

0

1

X0,A 0 0

X0,B 0 0

Y0,A 0 1

Y0,B 0 1

X1,A 1 0

X1,B 1 0

Y1,A 1 1

Y1,B 1 1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 95

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXT

Sign Extend Accumulator

EXT

Operation:

Assembler Syntax:

bit 31 of D

→ [bit 39-32] of D

EXT

D

(no parallel move)

Description: Sign Extend the Destination accumulator from the most significant bit of the upper word (bit

31 of D). The LS word of the destination accumulator is not affected.

Example:

EXT

A

A Before Execution

A After Execution

FF

A2

6432

A1

0000

A0

00

A2

6432

A1

0000

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $FF:6432:0000.

Since bit 31 of A is cleared, the execution of the EXT instruction clears the extension bits

32-39 and returns $00:6432:0000 in A which is a positive value.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Always cleared

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

— Always cleared

V

A - 96

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

EXT

Sign Extend Accumulator

EXT

Instruction Format:

EXT

D

Opcode:

15

12 11

8

1

7

0

4

1

3

F

0

1

0

1

0

1

0

1

Instruction Fields:

D

F

A

B

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 97

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ILLEGAL

Illegal Instruction Interrupt

ILLEGAL

Operation:

Assembler Syntax:

Begin Illegal instruction exception routine

ILLEGAL

(no parallel move)

Description: Normal instruction execution is suspended and Illegal Instruction exception processing is

initiated. The interrupt priority level (I1, I0) is set to 3 in the status register if a long interrupt

service routine is used. The purpose of the Illegal interrupt is to force the DSP into an illegal

instruction exception for test purposes. If a fast interrupt is used with the ILLEGAL instruc-

tion, an infinite loop will be formed (an illegal instruction interrupt normally returns to the il-

legal instruction) which can only be broken by a hardware reset. Therefore, only long inter-

rupts should be used. Exiting an ILLEGAL instruction is a fatal error, the long exception rou-

tine should indicate this condition and cause the system to be restarted.

If the ILLEGAL instruction is in a DO loop at LA and the instruction at LA-1 is being inter-

rupted, then LC will be decremented twice due to the same mechanism that causes LC to

be decremented twice if JSR, REP,… are located at LA.

Since REP is uninterruptable, repeating an ILLEGAL instruction results in the interrupt not

being taken until after completion of the REP. After servicing the interrupt, program control

will return to the address of the second word following the ILLEGAL instruction. Of course,

the ILLEGAL interrupt service routine should abort further processing, and the processor

should be reinitialized.

Example:

ILLEGAL

Explanation of Example: see above description.

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 98

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

ILLEGAL

Illegal Instruction Interrupt

ILLEGAL

Instruction Format:

ILLEGAL

Opcode:

15

12 11

8

0

7

0

4

0

3

1

0

1

0

1

Timing:

Memory:

8 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 99

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IMAC

IntegerMultiply-Accumulate

IMAC

Operation:

Assembler Syntax:

(S1*S2+[D>>15])<15

→ D2:D1;

IMAC

S1,S2,D

(no parallel move)

sign extend D2; leave D0 unchanged

Description: Integer Multiply the two 16-bit signed integer source operands S1 and S2 and add the prod-

uct to the upper word (D1) of the destination accumulator D leaving the lower word (D0)

unchanged. A 15-bit shift as opposed to a 16-bit shift is required because of the inherent

fractional nature of the multiplier. This is discussed more fully in Section 3.2.3.

Note:

No overflow control or rounding are performed during integer multiply-accumulate instruc-

tions. The result is always a 16-bit signed integer result which is sign extended to 24 bits.

Example:

:

MOVE

IMAC

MOVE

:

R0,A

Y0,X0,A

X:(A1),B

; initialize A

; update A

; use A1 as memory pointer

Before Execution

After Execution

00 0014

A2 A1

00

A2

0008

A1

789A

A0

0003

X0

0004

Y0

Explanation of Example: Prior to execution, the 16-bit accumulator register A1 contains a 16-bit signed

integer value ($0008). The data ALU registers X0 and Y0 contains respectively two 16-bit

signed integer values $0003 and $0004. Execution of the IMAC X0,Y0,A instruction integer

multiplies X0 and Y0 and accumulates the result in A1. A0 remains unchanged and A2 is

sign extended.

A - 100

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IMAC

IntegerMultiply-Accumulate

IMAC

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Not defined

— Set if bit 39 of the result is set

— Set if the 24 MS bits of the result equal zero

Instruction Format:

IMAC

S1,S2,D

Opcode:

15

0

12 11

8

1

7

1

4

0

3

F

0

1

0

1

0

1

Q

Instruction Fields:

S1,S2,D QQQ F S1,S2,D QQQ

F

X0,X0,A 0 0 0

X0,X0,B 0 0 0

X1,X0,A 0 0 1

X1,X0,B 0 0 1

A1,Y0,A 0 1 0

A1,Y0,B 0 1 0

B1,X0,A 0 1 1

B1,X0,B 0 1 1

0

1

0

1

0

1

0

1

Y0,X0,A 1 0 0

Y0,X0,B 1 0 0

Y1,X0,A 1 0 1

Y1,X0,B 1 0 1

Y0,X1,A 1 1 0

Y0,X1,B 1 1 0

Y1,X1,A 1 1 1

Y1,X1,B 1 1 1

0

1

0

1

0

1

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 101

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IMPY

IntegerMultiply

IMPY

Operation:

Assembler Syntax:

(S1*S2)<15

→

D2:D1;

IMPY

S1,S2,D

(no parallel move)

sign extend D2; leave D0 unchanged

Description: Integer Multiply the two 16-bit signed integer source operands S1 and S2 and store the

product in the upper word (D1) of the destination accumulator D leaving the lower word (D0)

unchanged.

Note:

No overflow control or rounding are performed during integer multiply instructions. The re-

sult is always a 16-bit signed integer result which is sign extended to 24 bits.

Example:

:

IMPY

MOVE

:

Y0,X0,A

A1,R0

; form product

; initialize pointer

Before Execution

After Execution

00

A2

0008

A1

789A

00

A2

000C

A1

789A

A0

0003

X0

0004

Y0

Explanation of Example: Prior to execution, the 16-bit accumulator register A1 contains a 16-bit signed

integer value ($0008). The data ALU registers X0 and Y0 contain respectively two 16-bit

signed integer values $003 and $004. Execution of the IMPY X0,Y0,A instruction integer

multiplies X0 and Y0 and stores the result $C in A1. A0 remains unchanged and A2 is sign

extended.

A - 102

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

IMPY

IntegerMultiply

IMPY

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Not defined

— Set if bit 39 of the result is set

— Set if the 24 MS bits of the result equal zero

Instruction Format:

IMPY

S1,S2,D

Opcode:

15

0

12 11

8

1

7

1

4

0

3

F

0

1

0

1

0

Q

Instruction Fields:

S1,S2,D QQQ F S1,S2,D QQQ

F

X0,X0,A 0 0 0

X0,X0,B 0 0 0

X1,X0,A 0 0 1

X1,X0,B 0 0 1

A1,Y0,A 0 1 0

A1,Y0,B 0 1 0

B1,X0,A 0 1 1

B1,X0,B 0 1 1

0

1

0

1

0

1

0

1

Y0,X0,A 1 0 0

Y0,X0,B 1 0 0

Y1,X0,A 1 0 1

Y1,X0,B 1 0 1

Y0,X1,A 1 1 0

Y0,X1,B 1 1 0

Y1,X1,A 1 1 1

Y1,X1,B 1 1 1

0

1

0

1

0

1

0

1

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 103

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INC

Increment Accumulator

INC

Operation:

Assembler Syntax:

D+1

→ D

(parallel move)

INC

D

(parallel move)

Description: Increment by one the destination accumulator. This is a 40-bit increment instruction.

Example:

INC

A

A, X0

;save A into X0 before incrementing it

Before Execution

After Execution

12

A2

3456

A1

789A

A0

12

A2

3456

A1

789B

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the INC A instruction increments by one the 40-bit A accumulator.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if result equals zero

E

U

N

Z

V

C

— Set if overflow has occurred in result

— Set if a carry (or borrow) occurs from bit 39 of the result

A - 104

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INC

Increment Accumulator

INC

Instruction Format:

INC

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

0

3

F

0

m

R

H

W

0

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 105

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INC24

Increment 24 MS-bit of Accumulator

INC24

Operation:

Assembler Syntax:

D2:D1+1 → D2:D1

(parallel move);

INC24

D

(parallel move)

D0 is unchanged

Description: Increment by one the 24 MS bit of the destination accumulator.

Example:

INC24

A

X:(B1),X1

;Increment 24 MS bits of A; update X1

Before Execution

After Execution

12

A2

3456

A1

789A

A0

12

A2

3457

A1

789A

A0

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $12:3456:789A.

Execution of the INC24 A instruction increments by one the 24 MS bits of the accumulator

A.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of the result is in use

— Set if result is unnormalized

— Set if bit 39 of the result is set

— Set if the 24 most significant bit of the result are all zeroes

— Set if overflow has occurred in result

E

U

N

Z

V

C

— Set if a carry (or borrow) occurs from bit 39 of the result

A - 106

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

INC24

Increment 24 MS-bit of Accumulator

INC24

Instruction Format:

INC24

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

0

3

F

0

1

m

R

H

W

0

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 107

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Jcc

Jump Conditionally

Jcc

Operation:

Assembler Syntax:

If cc, then label → PC

else PC+1 → PC

Jcc

xxxx

If cc, then Rn

→ PC

Jcc

(Rn)

else PC+1 → PC

Description: If the specified condition is true, program execution continues at the effective address spec-

ified in the instruction. If the specified condition is false, the program counter (PC) is incre-

mented and program execution continues sequentially. Long displacement (16-bit signed

value) and address register addressing modes may be used.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Restrictions: — A Jcc instruction used within a DO loop cannot begin at the address LA within that DO

loop.

— A Jcc instruction cannot be repeated using the REP instruction.

Example:

JNN

(R2)

;jump to P:(R2) if not normalized

Explanation of Example: In this example, program execution is transferred to the address P:(R2) if the

result is not normalized. If the specified condition is not true, no jump is taken and the pro-

gram counter is incremented by one.

A - 108

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Jcc

Jump Conditionally

Jcc

Condition Codes Affected:

The condition codes are not affected by this instruction.

Instruction Format and Opcode:

Jcc xxxx

15

12 11

8

0

7

4

1

3

c

0

c

0

x

0

x

0

x

0

x

1

x

1

x

— —

1

x

c

x

c

x

“—” = don’t care

Instruction Fields:xxxx = 16-bit absolute target address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

Instruction Format and Opcode:

Jcc

Rn

RR

Rn

15

0

12 11

8

0

7

4

0

3

c

0

00

01

10

11

R0

R1

R2

R3

0

1

R

1

c

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

Instruction Fields:

cc

= 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

MOTOROLA

INSTRUCTION SET

A - 109

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JMP

Jump

JMP

Operation:

Assembler Syntax:

label → PC

Rn → PC

JMP

xxxx

(Rn)

Description: Jump to the location in program memory at the location given by the instruction’s effective

address. Long displacement (16-bit signed value) and address register addressing modes

may be used.

Restrictions: — A JMP instruction used within a DO loop cannot begin at address LA within that DO

loop.

— A JMP instruction cannot be repeated using the REP instruction.

Example:

JMP

(R2)

;jump to P:(R2)

Explanation of Example: In this example, program execution is transferred to the address P:(R2).

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 110

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JMP

Jump

JMP

Instruction Format and Opcode:

JMP xxxx

15

12 11

8

1

7

0

4

1

3

0

x

0

x

0

x

0

x

0

x

0

x

0

x

1

x

1

x

— —

x

“—” = don’t care

Instruction Fields:

xxxx = 16-bit signed absolute branch address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

Instruction Format and Opcode:

JMP

Rn

RR

Rn

15

0

12 11

8

1

7

0

4

0

3

0

00

01

10

11

R0

R1

R2

R3

0

1

R

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 111

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JScc

Jump to Subroutine Conditionally

JScc

Operation:

Assembler Syntax:

If cc, then SP+1 → SP

JScc xxxx

PC

SR

xxxx

→ SSH

→ SSL

→ PC

else PC+1 → PC

If cc, then SP+1 → SP

JScc Rn

PC

SR

Rn

→ SSH

→ SSL

→ PC

else PC+1 → PC

Description: If the specified condition is true, program execution continues at the location in program

memory given by the instruction’s effective address. If the specified condition is false, the

program counter (PC) is incremented and program execution continues sequentially. Long

displacement (16-bit signed value) and address register addressing modes may be used.

The term “cc” may specify the following conditions:

“cc” Mnemonic

Condition

CC (HS) — carry clear (higher or same)

CS (LO) — carry set(lower)

C=0

C=1

E=0

Z=1

E=1

EC

EQ

ES

GE

GT

LC

LE

LS

LT

— extension clear

— equal

— extension set

— greater than or equal

— greater than

— limit clear

— less than or equal

— limit set

— less than

N

V=0

Z+(N V)=0

L=0

Z+(N V)=1

L=1

N

V=1

N=1

Z=0

MI

— minus

NE

NR

PL

NN

— not equal

— normalized

— plus

Z+(U•E)=1

N=0

Z+(U•E)=0

— not normalized

where: U

denotes the logical complement of U,

denotes the logical OR operator,

denotes the logical AND operator,

denotes the logical Exclusive OR operator

+

•

Restrictions: — A JScc instruction used within a DO loop cannot begin at address LA within that DO

loop.

— A JScc instruction used within a DO loop cannot specify the loop address LA as its tar-

get.

— A JScc instruction cannot be repeated using the REP instruction.

A - 112

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JScc

Jump to Subroutine Conditionally

JScc

Example:

JSLS

R2

;jump to subroutine at P:(R2) if limit set

Explanation of Example: In this example, program execution is transferred to the subroutine at address

P:(R2) if the limit bit is set. If the specified condition is not true, no jump is taken and the

program counter is incremented by one.

Condition Codes Affected: The condition codes are not affected by this instruction.

Instruction Format and Opcode:

JScc

xxxx

15

0

12 11

8

0

7

4

1

3

c

0

c

0

x

0

x

0

x

0

x

1

x

1

x

— —

0

x

c

x

c

x

“—” = don’t care

Instruction Fields: xxxx = 16-bit absolute branch address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

Instruction Format and Opcode:

JScc

Rn

RR

Rn

15

0

12 11

8

0

7

4

0

3

c

0

00

01

10

11

R0

R1

R2

R3

0

1

R

0

c

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

Instruction Fields:

cc

= 4-bit condition code = cccc

Mnemonic

c

Mnemonic

c

CS(LO)

LT

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CC(HS)

GE

0

1

0

1

0

1

0

1

0

1

0

1

0

1

EQ

MI

NE

PL

NR

ES

NN

EC

LS

LC

LE

GT

MOTOROLA

INSTRUCTION SET

A - 113

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JSR

Jump to Subroutine

JSR

Operation:

Assembler Syntax:

SP+1 → SP

JSR

xxxx

PC

SR

xxxx

→ SSH

→ SSL

→ PC

SP+1 → SP

AA

PC

SR

AA

→ SSH

→ SSL

→ PC

SP+1 → SP

Rn

PC

SR

Rn

→ SSH

→ SSL

→ PC

Description: Jump to subroutine in program memory at the location given by the instruction’s effective

address. Short displacement (8 bit unsigned value), long displacement (16-bit absolute

address) and address register addressing modes may be used.

Restrictions: — A JSR instruction used within a DO loop cannot begin at address LA within that DO

loop.

— A JSR instruction used within a DO loop cannot specify the loop address LA as its tar-

get.

— A JSR instruction cannot be repeated using the REP instruction.

Example:

JSR

R2

;jump to absolute address pointed to by R2

Explanation of Example: In this example, program execution is transferred the subroutine at address

P:(R2)

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 114

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

JSR

Jump to Subroutine

JSR

Instruction Format and Opcode:

JSR xxxx

15

0

12 11

8

1

7

0

4

1

3

0

x

0

x

0

x

0

x

0

x

0

x

0

x

1

x

0

x

— —

x

“—” = don’t care

Instruction Fields: xxxx = 16-bit signed absolute branch address

Timing:

Memory:

4 + jx oscillator clock cycles

2 program words

Instruction Format and Opcode:

JSR AA

15

12 11

8

0

7

4

3

0

1

0

1

A

Instruction Fields: AA…A = 8-bit unsigned absolute short branch address

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

Instruction Format and Opcode:

JSR

Rn

RR

Rn

15

0

12 11

8

1

7

0

4

0

3

0

00

01

10

11

R0

R1

R2

R3

0

1

0

R

Timing:

Memory:

4 + jx oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 115

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LEA

Load Effective Address

LEA

Operation:

Assembler Syntax:

ea →

D

(no parallel move)

LEA

ea,D

Description: The address calculation specified is executed and the resulting effective address is stored

in the destination register. The source address register and the update mode used to com-

pute the updated address are specified by the effective address (ea). Note that the source

address register specified in the effective address is not updated. All update addressing

modes may be used.

Note: This instruction is considered to be a move-type instruction. Due to pipelining, the new contents of

the destination address register (R0-R3 or N0-N3) will not be available for use during the following instruc-

tion (i.e., there is a single instruction cycle pipeline delay).

Example:

LEA

(R0)+N0,R1

;update R1 using (R0)+N0

Before Execution

After Execution

R0

N0

R1

0003

0005

0004

R0

N0

R1

0003

0005

0008

Explanation of Example: Prior to execution, the 16-bit address register R0 contains the value $0003, the

16-bit address register N0 contains the value $0005 and the 16-bit address register R1 con-

tains the value $0004. Execution of the LEA (R0)+N0,R1 instruction adds the contents of

the R0 register to the contents of the N0 register and stores the resulting updated address

in the R1 address register. The contents of both the R0 and N0 address registers are not

affected.

Condition Codes Affected:

The condition codes are not affected by this instruction.

A - 116

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LEA

Load Effective Address

LEA

Instruction Format:

LEA

ea,Rn

Opcode:

TT

Destination

15

0

12 11

8

1

7

1

4

T

3

0

00

01

10

11

R0

R1

R2

R3

0

1

T

M

R

Instruction Format:

LEA

ea,Nn

Opcode:

NN

Destination

15

0

12 11

8

7

4

3

0

00

01

10

11

N0

N1

N2

N3

0

1

0

N

M

R

Instruction Fields:

MMRR

Effective Address

RR

Source

00RR

01RR

10RR

11RR

Rn

00

01

10

11

R0

R1

R2

R3

(Rn)+

(Rn)-

(Rn)+Nn

Timing:

Memory:

4 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 117

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LSL

Logical Shift Left

LSL

Assembler Syntax:

LSL

D

(parallel move)

Operation:

unch.

C

unchanged

D0

0

(parallel move)

D2

D1

Description: Logically shift bits 31-16 (D1) of the destination operand D one bit to the left and store the

result in the destination accumulator upper word D1. The MS bit of D1 (bit 31 of D) is shifted

into the carry bit C prior to instruction execution and a zero is shifted into the LS bit of the

D1 (bit 16 of D).

Example:

LSL

A

(R3)-

;multiply A1 by 2, update R3

Before Execution

After Execution

A5

A2

8123

A1

0123

A0

A5

A2

0246

A1

0123

A0

0000

0001

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit A accumulator contains the value $A5:8123:0123.

Execution of the LSL A instruction shifts the16-bit value in the A1 accumulator one bit to

the left and leaves A2 and A1 unchanged. The C bit of CCR (bit 0) is set by the operation

because bit 31 of A was set prior to the instruction execution.

A - 118

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LSL

Logical Shift Left

LSL

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

N

Z

V

C

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if bit 31 of A or B result is set

— Set if A1 or B1 result equals zero

— Always cleared

— Set if bit 31 of A or B was set prior to instruction execution

Instruction Format:

LSL

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

1

m

R

H

W

0

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 119

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LSR

Logical Shift Right

LSR

Assembler Syntax:

LSR

D

(parallel move)

Operation:

0

unch.

D2

unchanged

D0

C

(parallel move)

D1

Description: Logically shift bits 31-16 (D1) of the destination operand D one bit to the right and store the

result in the destination accumulator upper word D1. The LS bit of D1 (bit 16 of D) prior to

instruction execution is shifted into the carry bit C and zero is shifted into the MS bit of D1(bit

31 of D).

Example:

:

LSR

B

X:-(R3),R3

;divide B1 by 2, update R3, load R3

Before Execution

After Execution

A8

B2

0001

B1

A865

B0

A8

B2

0000

B1

A865

B0

0300

0305

SR=MR:CCR

Explanation of Example: Prior to execution, the 40-bit

B

accumulator contains the value

$A8:0001:A865. Execution of the LSR B instruction shifts the 16-bit value in the B1 register

one bit to the right and stores the result back in the B1 register. The C bit of CCR (bit 0) is

set by the operation because bit 0 of A1 was set prior to the instruction execution. The Z bit

of CCR (bit 2) is also set because the result in A1 is zero.

A - 120

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

LSR

Logical Shift Right

LSR

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

N

Z

V

C

— Computed according to the standard definition (see section A.4)

— Set if data limiting has occurred during parallel move

— Always cleared

— Set if A1 or B1 result equals zero

— Always cleared

— Set if bit 16 of A or B was set prior to instruction execution

Instruction Format:

LSR

D

(parallel move)

Opcode:

15

1

12 11

8

7

0

4

1

3

F

0

m

R

H

W

0

1

0

1

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

D

F

A

B

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program words

MOTOROLA

INSTRUCTION SET

A - 121

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MAC

Multiply-Accumulate

MAC

Operation:

Assembler Syntax:

D + S1 * S2 → D (one parallel move)

D + S1 * S2 → D (two parallel reads)

D + S1 * S2 → D D→ X:(Rn)+Nn S → D

MAC (+)S2,S1,D

MAC S1,S2,D

(one parallel move)

(two parallel reads)

D,X:(Rn)+Nn

S,D

Description: Multiply the two signed 16-bit source operands S1 and S2 and add/subtract the product to/

from the specified 40-bit destination accumulator D. The “-” sign option is used to negate

the specified product prior to accumulation. This option is not available when two parallel

read operations are performed. The instruction that accesses D is particularly useful for im-

plementing the Least Mean Square (LMS) adaptive filter algorithm (see Appendix B).

Example:

MAC

X1,Y1,A

X:(R2)+,Y1

X:(R3)+,X1

After Execution

Before Execution

00

A2

1000

0000

A0

00

A2

0A2B

0000

A0

A1

4000

3FFF

X1

F456

F454

Y1

Explanation of Example: Prior to execution, the 16-bit X1 register contains the value $4000, the 16-bit

Y1 register contains the value $F456 and the 40-bit A accumulator contains the value

$00:1000:0000. Execution of the MAC X1,Y1,A instruction multiplies the 16-bit signed val-

ue in the X1 register by the 16-bit signed value in Y1 and adds the resulting 32-bit product

to the 40-bit A accumulator and stores the result ($00:0A2B:0000) into the accumulator A.

In parallel, X1 and Y1 are updated with new values fetched from the data memory and the

two address registers R2 and R3 are post incremented by one.

Condition Codes Affected:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

E

U

N

Z

V

— Set if A or B result equals zero

— Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

A - 122

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MAC

Multiply-Accumulate

MAC

Instruction Format:

Opcode:

MAC

(+)S2,S1,D

(one parallel move)

15

12 11

8

7

1

4

0

3

F

0

Sign k

+

-

0

1

m

R

H

W

k

1

Q

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields.

Instruction Format:

Opcode:

MAC

S1,S2,D

(two parallel reads)

15

0

12 11

8

7

1

4

0

3

F

0

1

m

K

x

1

Q

Instruction Fields: Please see the “Dual X Memory Data Read” description in the parallel move sec-

tion for details on the mm and KKK data fields.

Instruction Format:

Opcode:

MAC

S1,S2,D

D,X:(Rn)+Nn

7

S,D

Q

(one memory write,

one data register move)

15

0

12 11

8

1

4

3

F

0

1

0

1

R

D

Q

Instruction Fields: Please see the “X Memory Data Write and Register Data Move” description in the

parallel move section for details on the RR and DD data fields.

One Or Two Parallel Operation

S1,S2,D QQQ F S1,S2,D QQQ

X0,X0,A 0 0 0 0 Y0,X0,A 1 0 0

X0,X0,B 0 0 0 1 Y0,X0,B 1 0 0

X1,X0,A 0 0 1 0 Y1,X0,A 1 0 1

X1,X0,B 0 0 1 1 Y1,X0,B 1 0 1

A1,Y0,A 0 1 0 0 Y0,X1,A 1 1 0

A1,Y0,B 0 1 0 1 Y0,X1,B 1 1 0

B1,X0,A 0 1 1 0 Y1,X1,A 1 1 1

B1,X0,B 0 1 1 1 Y1,X1,B 1 1 1

Two Parallel Reads

QQ F S1,S2,D

0 0 0 X1,Y0,A

0 0 1 X1,Y0,B

0 1 0 X1,Y1,A

0 1 1 X1,Y1,B

F

0

1

0

1

0

1

0

1

S1,S2,D

X0,Y0,A

X0,Y0,B

X0,Y1,A

X0,Y1,B

QQ

1 0

1 1

F

0

1

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 123

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MACR

Multiply-Accumulate and Round

MACR

Operation:

Assembler Syntax:

D + S1 * S2 + r → D (one parallel move)

D + S1 * S2 + r → D (two parallel reads)

MACR

(+)S2,S1,D

S1,S2,D

(one parallel operation)

(two parallel reads)

Description: Multiply the two signed 16-bit source operands S1 and S2, add/subtract the product to/from

the specified 40-bit destination accumulator D, and round the result using the specified

rounding. The rounded result is stored in the destination accumulator. Refer to the round

instruction for more complete information on the convergent rounding process. The “-” sign

option is used to negate the specified product prior to accumulation. This option is not avail-

able when two parallel reads are performed. The default sign option is “+”.

Example:

MACR

-X0,Y1,A A0,X0

Before Execution

After Execution

00

A2

1000

1234

A0

00

A2

15D5

0000

A0

A1

4000

1234

X0

F456

F454

Y1

Explanation of Example: Prior to execution, the 16-bit X0 register contains the value $4000 (0.5), the 16-

bit Y1 register contains the value $F456 (-0.0911255) and the 40-bit A accumulator con-

tains the value $00:1000:1234 (0.125002169981599). Execution of the MACR-X0,Y1,A in-

struction multiplies the 16-bit signed value in the X0 register by the 16-bit signed value in

Y1 and substracts the resulting 32-bit product to the 40-bit A accumulator, rounds the result

and stores the result ($00:15D5:0000) into the accumulator A (-X0 * Y1 + A =

0.170562744140625). In parallel, A0 is saved into X0 before the result is stored in A. In this

example, the default rounding (convergent rounding) is performed.

A - 124

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MACR

Multiply-Accumulate and Round

MACR

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

Z

V

C

S

L

— Computed according to the standard definition (see section A.4)

— Set if limiting (parallel move) or overflow has occurred in result

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

E

U

N

Z

V

— Set if A or B result equals zero

— Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

Opcode:

MACR

(+)S1,S2,D

(one parallel operation)

15

12 11

8

7

1

4

1

3

F

0

Sign k

one parallel operation

k

1

Q

+

-

0

1

Instruction Format:

Opcode:

MACR

S1,S2,D

(two parallel reads)

15

12 11

8

7

1

4

1

3

F

0

two parallel reads

— —

1

Q

“—” = don’t care

Instruction Fields:

One Parallel Operation

Two Parallel Reads

QQ F S1,S2,D

0 0 0 X1,Y0,A

0 0 1 X1,Y0,B

0 1 0 X1,Y1,A

0 1 1 X1,Y1,B

S1,S2,D

X0,Y0,A

X0,Y0,B

X0,Y1,A

X0,Y1,B

QQ

1 0

1 1

F

S1,S2,D QQQ F S1,S2,D QQQ

X0,X0,A 0 0 0 0 Y0,X0,A 1 0 0

X0,X0,B 0 0 0 1 Y0,X0,B 1 0 0

X1,X0,A 0 0 1 0 Y1,X0,A 1 0 1

X1,X0,B 0 0 1 1 Y1,X0,B 1 0 1

A1,Y0,A 0 1 0 0 Y0,X1,A 1 1 0

A1,Y0,B 0 1 0 1 Y0,X1,B 1 1 0

B1,X0,A 0 1 1 0 Y1,X1,A 1 1 1

B1,X0,B 0 1 1 1 Y1,X1,B 1 1 1

F

0

1

0

1

0

1

0

1

0

1

0

1

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 125

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MAC(su,uu)

Mixed Multiply-Accumulate

MAC(su,uu)

Operation:

Assembler Syntax:

D + S1 * S2 → D

(S1 unsigned, S2 unsigned)

(S1 signed, S2 unsigned)

MACuu

MACsu

S1,S2,D

(no parallel move)

Description: Multiply the two 16-bit source operands S1 and S2 and add the product to the specified 40-

bit destination accumulator D. One or two of the source operands can be unsigned. This

mixed arithmetic multiply-accumulate does not allow a parallel move and can be used for

multiple precision multiplications.

Example:

MACuu

MACsu

X1,Y1,A

FFFF

X1

0062

Y1

Before MACuu Execution

After MACuu Execution

00

A2

1000

A1

0000

A0

00

A2

10C3

A1

FFC3

A0

Before MACsu Execution

After MACsu Execution

00

A2

10C3

A1

FFC3

A0

C4

A2

10C3

A1

FEFF

A0

Explanation of Example: The 16-bit X1 register contains the value $FFFF and the 16-bit Y1 register

contains the value $0062.

Execution of the MACuu X1,Y1,A instruction multiplies the 16-bit unsigned value in the X1

register by the 16-bit unsigned value in Y1, then adds the result to the accumulator A and

stores the unsigned result back into the accumulator A.

Execution of the MACsu X1,Y1,A instruction multiplies the 16-bit signed value in the X1 reg-

ister by the 16-bit unsigned value in Y1, then adds the result to the accumulator A and

stores the signed result back into the accumulator A.

Warning:

The saturation mode is always disabled during execution of MAC(su,uu), even when the

saturation bit (SA) of the OMR is set. Refer to Section 5.8.3 for more details.

A - 126

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MAC(su,uu)

Mixed Multiply-Accumulate

MAC(su,uu)

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

L

5

4

3

2

1

0

LF

*

S1 S0 I1 I0

S

E

U

N

Z

V

C

E

U

N

Z

— Set if the signed integer portion of A or B result is in use

— Set according to the standard definition of the U bit

— Set if bit 39 of A or B result is set

— Set if A or B result equals zero

V

— Set if overflow has occurred in A or B result

Note: The definition of the E and U bits varies according to the scaling mode being used. Please refer to

Section A.4 entitled “Condition Code Computation” for complete details.

Instruction Format:

MAC(uu)

MAC(su)

S1,S2,D

Opcode:

15

0

12 11

8

1

7

1

4

0

3

F

0

1

0

1

0

1

s

Q

Instruction Fields:

S1,S2,D

Y0,X0,A

Y0,X0,B

Y1,X0,A

Y1,X0,B

QQ F S1,S2,D

0 0 0 X1,Y0,A

0 0 1 X1,Y0,B

0 1 0 X1,Y1,A

0 1 1 X1,Y1,B

QQ

1 0

1 1

F

0

1

0

1

Arithmetic

s

su

uu

0

1

Note: For MACsu, the order of S1, S2 is sig-

nificant; the signed value will be taken from

S1 while the unsigned value will be taken

from S2.

Timing:

Memory:

2 oscillator clock cycles

1 program word

MOTOROLA

INSTRUCTION SET

A - 127

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOVE

Move Data

MOVE

Operation:

Assembler Syntax:

one move

two memory reads

one parallel memory move plus

one data register move

#xxxx → D (see Move(C) instruction)

MOVE

(one parallel operation)

(double memory read)

(memory access, register move)

MOVE

#xxxx,D

Description: This instruction is equivalent to a Data ALU NOP with a parallel data move as described in

Section A.4 entitled “Parallel Move Descriptions”. Refer to that section for more informa-

tion.

When a 40-bit accumulator (A or B) is specified as a source operand S, the accumulator

value is optionally shifted according to the scaling mode bits S0 and S1 in the system status

register (SR). If the data out of the shifter indicates that the accumulator extension register

is in use and the data is to be moved into a 16-bit destination, the value stored in the des-

tination D is limited to a maximum positive or negative saturation constant to minimize trun-

cation error. Limiting does not occur if an individual 16-bit accumulator register (A1, A0, B1,

or B0) is specified as a source operand instead of the full 40-bit accumulator (A or B). This

limiting feature allows block floating point operations to be performed with error detection

since the L bit in the condition code register is latched (i.e., sticky).

When a 40-bit accumulator (A or B) is specified as a destination operand D, any 16-bit

source data to be moved into that accumulator is automatically extended to 40 bits by sign-

extending the MS bit of the source operand (bit 15) and appending the source operand with

16 LS zeros. Note that the automatic sign-extension and zeroing features may be circum-

vented by specifying the destination register to be one of the individual 16-bit accumulator

registers (A1 or B1).

Example:

MOVE

X0,A1

;move X0 to A1 without sign extension or zeroing

Before Last Execution

After Last Execution

FF

A2

FFFF

A0

FF

A2

1234

FFFF

A0

A1

1234

X0

Explanation of Example: Prior to execution, the 40-bit

A

accumulator contains the value

$FF:FFFF:FFFF and the 16-bit X0 register contains the value $1234. Execution of the

MOVE X0,A1 instruction moves the 16-bit value in the X0 register into the 16-bit A1 register

without automatic sign extension and without automatic zeroing.

A - 128

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MOVE

Move Data

MOVE

Condition Codes Affected:

MR

15 14 13 12 11 10

CCR

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

S

L

— Set according to standard definition of the S bit.

— Set if data limiting has occurred during parallel move

Instruction Format and Opcode:

MOVE

(one parallel move)

15

12 11

8

7

4

1

3

0

1

m

R

H

W

0

Instruction Format and Opcode:

MOVE

(double memory read)

15

12 11

8

7

4

1

3

0

1

m

K

0

r

0

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the m, RR, HHH, and W data fields. See the “Dual X Memory Read” de-

scription in the parallel move section for details on the mm, KKK, and rr data fields.

Timing:

Memory:

2 + mv oscillator clock cycles

1 program word

Instruction Format and Opcode:

MOVE X:(R2+xx),D

;for W=0

-or-

MOVE S,X:(R2+xx)

;for W=1

15

12 11

8

1

7

4

3

0

1

0

B

0

B

0

B

0

B

0

B

0

B

— — — —

H

W

1

0

1

“—” = don’t care

Instruction Fields: Please see the “X Memory Data Move” description in the parallel move section for

details on the HHH and W data fields.

Timing:

Memory:

2 + mv oscillator clock cycles

2 program words

MOTOROLA

INSTRUCTION SET

A - 129

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

Parallel Move Descriptions

Thirty two Data ALU instructions provide the capability of specifying an optional parallel operation. This par-

allel operation can be a data bus movement over the X Data Bus with optional address register update, an

address register update without data bus movement or a Data ALU register transfer.

Eight major Data ALU instructions provide the capability of dual X memory read with address register up-

date. These Data ALU instructions have been selected for optimal performance on frequently used DSP

algorithm critical loops.

Two Data ALU instructions, MPY and MAC, provide the capability of one parallel X memory read plus one

Data ALU register transfer. These two instructions allow for very high performance adaptive transversal fil-

tering.

Seven types of parallel moves are permitted, including register to register moves, register to memory moves

and memory to register moves. However, not all addressing modes are allowed for each type of memory

reference. Addressing mode restrictions which apply to specific types of moves are noted in the individual

move operation descriptions. The following section contains detailed descriptions about each type of paral-

lel move operation.

The symbols used in decoding the various opcode fields of an instruction or parallel move are completely

arbitrary. Furthermore, the opcode symbols used in one instruction or parallel move are completely inde-

pendent of the opcode symbols used in a different instruction or parallel move.

A - 130

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

No Parallel Data Move

Operation:

Assembler Syntax:

(…)

where (…) refers to any arithmetic or logical instruction.

Description: All Data ALU operations can be performed without any parallel move.

Example:

:

ADD X0,A

;add X0 to A (no parallel move)

:

Explanation of Example: This is an example of an instruction which allows parallel moves but doesn’t

have one.

Condition Codes Affected:

The condition codes are not affected by this type of parallel move.

Instruction Format:

(…)

Opcode:

15

0

12 11

8

0

7

4

3

0

1

0

1

0

1

Data ALU Opcode

Instruction Fields: (defined by Data ALU instruction)

Timing:

Memory:

mv oscillator clock cycles

mv program words

MOTOROLA

INSTRUCTION SET

A - 131

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

Register to Register Data Move

Operation:

Assembler Syntax:

S → D

(…)

S,D

(…);

where (…) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Move the source register S to the destination register D.

If the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumu-

lator, that same accumulator or portion of that accumulator may not be specified as a destination D in the

parallel data bus move operation. Thus, if the opcode-operand portion of the instruction specifies the 40-bit

A accumulator as its destination, the parallel data bus move portion of the instruction may not specify A0,

A1, A2, or A as its destination D. Similarly, if the opcode-operand portion of the instruction specifies the 40-

bit B accumulator as its destination, the parallel data bus move portion of the instruction may not specify B0,

B1, B2, or B as its destination D. That is, duplicate destinations are not allowed within the same instruction.

If the opcode-operand portion of the instruction specifies a given source or destination register, that same

register or portion of that register may be used as a source S in the parallel data bus move operation. This

allows data to be moved in the same instruction in which it is being used as a source operand by a Data

ALU operation. That is, duplicate sources are allowed within the same instruction.

Note: The MOVE A,B operation will result in a 16-bit positive or negative saturation constant being stored

in the B1 portion of the B accumulator if the signed integer portion of the A accumulator is in use.

The opposite is true for the MOVE B,A instruction.

Example:

MACR

-X0,Y0,B

A,X1

Before Execution

After Execution

01

A2

0008

A1

789A

01

A2

0008

A1

789A

A0

0003

7FFF

X1

Explanation of Example: Prior to execution, the 16-bit X1 register contains the value $0003 and the 40-

bit accumulator A contains the value $01:0008:789A. Execution of the parallel move portion

of the instruction, A,X1, moves the contents of A1 into the X1. Limiting is performed by the

shifter limiter because the data stored in A before instruction execution is using the integer

portion of A. The example assumes no scaling is selected in the MR register.

A - 132

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

Register to Register Data Move

Condition Codes:

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

S

L

— Set according to the standard definition of the S bit.

— Set if data limiting has occurred during parallel move

Instruction Format:

(…)

S,D

Opcode:

15

0

12 11

8

I

7

4

3

0

1

0

I

Data ALU Opcode

Instruction Fields:

S,D

I I I I

X0,F

Y0,F

X1,F

Y1,F

A,X0

B,Y0

A0,X0

B0,Y0

F,F

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1100

1101

1110

1111

F,F

A,X1

B,Y1

A0,X1

B0,Y1

F is the accumulator which is not used by the

parallel Data ALU operation.

(in the case of no Data ALU operation, A is chosen)

Timing:

Memory:

mv oscillator clock cycles

mv program words

MOTOROLA

INSTRUCTION SET

A - 133

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

Address Register Update

Operation:

Assembler Syntax:

(…); ea → Rn

(…)

ea

where (…) refers to any arithmetic or logical instruction which allows such parallel operations.

Description: Update the specified address register according to the specified effective addressing

mode. Two update addressing modes may be used (postdecrement by one; postincrement

by the offset register).

Example:

RND B

(R3)+N3

;round value in B into B1, R3+N3 → R3

Before Execution

After Execution

R3

0007

R3

000B

N3

0004

N3

0004

Explanation of Example:

Prior to execution, the 16-bit address register R3 contains the value $0007

and the 16-bit address offset register N3 contains the value $0004. Execution of the parallel

move portion of the instruction, (R3)+N3, updates the R3 address register according to the

specified effective addressing mode by adding the value in the R3 register to the value in

the N3 register and storing the 16-bit result back in the R3 address register.

Condition Codes Affected:

The condition codes are not affected by this type of parallel operation.

A - 134

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

Address Register Update

Instruction Format:

(…)

ea

0

Opcode:

15

0

12 11

8

7

4

3

0

1

0

z

R

Data ALU Opcode

Instruction Fields:

RR

Rn

ea

z

00

01

10

11

R0

R1

R2

R3

(Rn)-

(Rn)+Nn

0

1

Timing:

Memory:

mv oscillator clock cycles

mv program words

MOTOROLA

INSTRUCTION SET

A - 135

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

X Memory Data Move

Operation:

Assembler Syntax:

(…)

X:<ea> → D

S → X:<ea>

(…)

X:<ea>,D

S,X:<ea>

where (…) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Move the specified word operand from/to X memory. Two indirect addressing modes may

be used (postincrement by one and postincrement by the offset register) as well as a spe-

cial addressing mode using the upper word of the accumulator which is not used by the

Data ALU operation.

If the arithmetic or logical opcode-operand portion of the instruction specifies a given destination accumu-

lator, that same accumulator or portion of that accumulator may not be specified as a destination D in the

parallel data bus move operation. Thus, if the opcode-operand portion of the instruction specifies the 40-bit

A or B accumulator as its destination, the parallel data bus move portion of the instruction may not specify

A0/B0, A1/B1, A2/B2, or A/B as its destination D. That is, duplicate destinations are not allowed within the

same instruction.

Exceptions:

— DEC24, INC24, CLR24, OR, AND, NOT, EOR, LSL, LSR, ROL, and ROR allow the

lower portion of the accumulator (A0 or B0) to be the destination of the parallel move

even if this accumulator is used by the Data ALU operation because these instructions

only affect the MS 16 or 24 bits of the accumulator.

— TST, CMP, CMPM allow both the accumulator and its lower portion (A and A0, B and

B0) to be the parallel move destination even if this accumulator is used by the Data ALU

operation. These instructions do not have a true destination.

If the opcode-operand portion of the instruction specifies a given source or destination register, that same

register or portion of that register may be used as a source S in the parallel data bus move operation. This

allows data to be moved in the same instruction in which it is being used as a source operand by a Data

ALU operation. That is, duplicate sources are allowed within the same instruction.

Example:

MOVE

ASL

#$100,R2

#4,X1

A

X1,X:(R2)+

; A*2 → A; save X1 in X:(R2); increment R2

Before Execution

After Execution

R2

0100

0000

R2

0101

0004

X:$100

Explanation of Example:

Prior to execution, the 16-bit R2 address register contains the value $100

and the 16-bit X memory location X:$0100 contains the value $0000. Execution of the parallel move portion

of the instruction, X1,X:(R2)+ uses the R2 address register to move the contents of the X1 register into the

16-bit X memory location X:$1000. R2 is then incremented by one.

A - 136

INSTRUCTION SET

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

X Memory Data Move

Move

:

Condition Codes Affected

MR

CCR

15 14 13 12 11 10

9

8

7

6

5

4

3

2

Z

1

0

LF

*

S1 S0 I1 I0

S

L

E

U

N

V

C

S

L

— Set according to the standard definition of the S bit.

— Set if data limiting has occurred during parallel move

Note: The MOVE A,X:<ea> or MOVE B,X:<ea> operation will result in a 16-bit positive or negative satu-

ration constant being stored in the specified 16-bit X memory location if the signed integer portion

of the A accumulator or B accumulator, respectively, is in use.

Instruction Format:

(…)

X:<ea>,D

S,X:<ea>

Opcode and instruction Fields:

15

12 11

8

7

4

3

0

1

m

R

H

W

Data ALU Opcode

where “RR” refers to an Address Register R0-R3

HHH

S,D

HHH

S,D

Reg.

read S

write D

W

0

1

ea

(Rn)+

(Rn)+Nn

m

0

1

000

001

010

011

X0

Y0

X1

Y1

100

101

110

111

A

B

A0

B0

Timing:

mv oscillator clock cycles

Memory:

1 program word

Instruction Format:

(…)

X:(F1),D

S,X:(F1)

Opcode and instruction Fields:

15

12 11

8

7

4

3

0

1

0

1

H

W

Data ALU Opcode

HHH

S,D

HHH

S,D

Reg.

read S

write D

W

0

1

000

001

010

011

X0

Y0

X1

Y1

100

101

110

111

A

B

A0

B0

F1 is the upper word of the accumulator which

is not used by the parallel Data ALU operation

(in case of no Data ALU operation, A1 is chosen as F)

Timing:

mv oscillator clock cycles

Memory:

mv program words

MOTOROLA

INSTRUCTION SET

A - 137

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Parallel

Move

Parallel

Move

X Memory Data Move with short displacement

Operation:

Assembler Syntax:

(…)

X:(R2+xx) → D

S → X:(R2+xx)

(…)

X:(R2+xx),D

S,X:(R2+xx)

where (…) refers to any arithmetic or logical instruction which allows parallel moves.

Description: Move the specified word operand from/to X memory. The indirect addressing mode on R2

indexed by a short (8 bits) signed displacement value is used. The 8-bit signed value is sign

extended to 16 bits before being added to R2. For example, X:(R2+$F0) and X:(R2-$10)

will access the same memory location.