DP8466B [ETC]
;
ETC 
June 1990
DP8466B Disk Data Controller
General Description
The DP8466B Disk Data Controller (DDC) is an intelligent
Features
Y
Easily conforms to any standard drive interface
Compatible with floppy, hard and optical disk drives
Compatible with 8, 16 or 32-bit microprocessor systems
Programmable disk format
Y
peripheral which interfaces Winchester or Floppy disk drives
to microprocessor based systems. It transfers data between
a buffer memory or host system and the serial bit data
stream with disk rates up to 25M-bits per second. High
speed system data transfer is possible with full on-chip DMA
control of buffer or main memory. The 16-bit system I/O
interface allows use with any popular 8-bit, 16-bit or 32-bit
microprocessor. Programmable track format enables recon-
figuration of the DDC for different drive types in a multiple
drive environment. Using other National DP846X series disk
data path chips, the DP8466B conforms to ST506, SMD
and ESDI standard drive interfaces, as well as to intelligent
standard interfaces such as SCSI (SASI) and IPI.
Y
Y
Y
Sector lengths up to 64k bytes, with up to 255 sectors
per track
Y
Y
Y
Y
Y
Programmable 32 or 48-bit ECC polynomial
Internal ECC correction in less than a sector time
Disk data rate to 25M bits per second
Multiple sector transfer capability
32 byte internal FIFO data buffer with interleavable
burst capability
Y
Y
Y
Y
8 or 16-bit wide data transfers
Single 32-bit or dual 16-bit DMA channel addresses
Up to 10M bytes per second DMA transfer rate
The DP8466B is available in three performance versions
DP8466BN-12, DP8466BN-20 and DP8466BN-25.
a
5V supply, 48 pin DIP, microCMOS process
Part
Number
Max Disk
Data Rate
Max DMA
Transfer Rate
DP8466BN-25
DP8466BN-20
DP8466BN-12
25 Mbit/sec
20 Mbit/sec
12 Mbit/sec
10 Mbyte/sec
8 Mbyte/sec
6 Mbyte/sec
TL/F/5282–1
FIGURE 1. Typical System Configuration
Table of Contents
1.0 INTRODUCTION
10.0 SYSTEM CONFIGURATIONS
11.0 ABSOLUTE MAXIMUM RATINGS
2.0 PIN DESCRIPTION
3.0 INTERNAL REGISTERS OF THE DDC
4.0 DDC OPERATION
12.0 DC ELECTRICAL CHARACTERISTICS
13.0 AC ELECTRICAL CHARACTERISTICS AND
TIMING DIAGRAMS
5.0 FORMAT, READ AND WRITE
6.0 CRC/ECC
14.0 AC TEST CONDITIONS
15.0 MISCELLANEOUS TIMING INFORMATION
16.0 FUNCTIONAL STATUS
17.0 HELPFUL HINTS
7.0 DATA TRANSFERS
8.0 INTERRUPTS
9.0 ADDITIONAL FEATURES
18.0 APPENDIX
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
MULTIBUSTM is a trademark of Intel Corp.
C
1995 National Semiconductor Corporation
TL/F/5282
RRD-B30M115/Printed in U. S. A.
1.0 Introduction
National’s DP8466B Disk Data Controller (DDC) chip is de-
signed to concentrate only on the data aspects of a disk
system, leaving the control signals to either a low cost sin-
gle chip controller or an I/O port from a microprocessor. For
this reason, the DDC will work with any standard drive inter-
face.
parameters. Once an error has been detected, the micro-
processor decides whether to re-read the sector during the
next revolution of the disk, or to attempt a correction. The
DDC can correct errors in a time shorter than that required
to read the next sector.
Key blocks in the DDC include a 32-byte FIFO and two 16-
bit DMA channels that give the chip a 10 megabyte per
second memory transfer capability. This high system data
throughout is needed for the high speed drives now becom-
ming available. The small FIFO allows for bursts of data to
take place on the bus, thereby leaving the bus free for use-
ful periods of time. The threshold for FIFO data storage is
selectable to allow for some degree of system latency. The
DDC allows for bursts of 2, 8, 16 or 24 bytes of data to be
transferred between the FIFO and memory. The width of the
data bus is selectable for either 8 or 16-bit transfers. The
system designer selects the threshold so that when the
FIFO contains the selected amount of data, the DDC will
issue a request. The CPU can continue its operation and
then stop to acknowledge the DDC, which then bursts the
data between FIFO and memory, before the FIFO has time
to overflow or underflow. With a 10 megabit per second disk
data rate and a 10 megabyte per second memory transfer
cycle, the bus will only be occupied for one-eighth of the
time transferring data between FIFO and memory. This
leaves the bus free for microprocessor usage for over 80%
of the time.
The DP8466B is an advanced VLSI chip, fabricated in Na-
tional’s latest 2 m CMOS technology, that allows for opera-
tion with disk data rates from the slowest floppy to the fast
Winchester and Optical data rates of 25 megabits per sec-
ond.
The CMOS design significantly helps the system designer
because of reduced power consumption. The chip typically
consumes 100 mW.
The DDC is designed for maximum programmability that not
only allows the user to select any drive type he wishes, but
also allows for different types of drives to be used on the
same system. The chip contains 64 registers that can be
loaded at any time by a microprocessor connected to the
chip’s bus. These registers determine the number of bytes
in each field of the format, and the byte pattern that each of
these fields will repeat. The number of data bytes per sector
is selectable from 1 byte to 64k bytes. Finally, both the
header field and the data field can each be appended with
either a Cyclic Redundancy Check (CRC) field (the 16-bit
code used on floppies) or a programmable Error Check and
Correct (ECC) field.
The DDC allows the user to load in any 32 or 48-bit ECC
polynomial from the microprocessor along with the format
Block Diagram
TL/F/5282–2
FIGURE 2. DDC
2
Connection Diagrams
Dual-In-Line Package
TL/F/5282–76
Top View
Order Number DP8466BN-12, DP8466BN-20 or DP8466BN-25
See NS Package Number N48A
TL/F/5282–3
Top View
Order Number DP8466BV-12, DP8466BV-20 or DP8466BV-25
See NS Package Number V68A
*This pin must be grounded if not used.
FIGURE 3
2.0 Pin Descriptions
2.1 BUS INTERFACE PINS
Symbol
DIP Pin No.
PCC Pin No.
Type
Function
CS
28
38
I
CHIP SELECT: Sets DDC as a standard I/O port for reading and writing
registers. Configures RD and WR pins as inputs when DMA is inactive.
This pin is ignored if on-chip DMA is enabled and performing a transfer.
INT
29
24
39
34
O
I
INTERRUPT: An interrupt can be generated on any error, or after
completion of a command, a correction cycle or any header operation.
RESET
RESET: Clears FIFO, Status and Error registers. Halts DMA immediately.
Halts disk read and write immediately. Does not affect parameter and
most count and command registers. On power-up, must be held low for at
least 32 RCLK cycles and 4 BCLK cycles. Note that both RCLK and BCLK
must be active for the reset cycle to complete.
RD
11
15
I/O
READ:
MICROPROCESSOR ACCESS MODE, with CS pin low and DMA
inactive (RACK AND LACK low): Places data from FIFO or register as
selected by pins RS0–5 onto the AD0–7 bus.
#
SLAVE MODE, with LACK pin high: Places data from FIFO onto the
AD0–7/AD0–15 bus.
#
MASTER MODE: When DMA is active, RD pin enables data from the
addressed device onto the address/data bus.
#
WR
10
14
I/O
WRITE:
MICROPROCESSOR ACCESS MODE, with CS low and DMA inactive
(RACK and LACK low): Latches data from AD0–7 bus to internal
registers selected by RS0–5.
#
SLAVE MODE, with LACK pin high: Latches data from AD0–7/AD0–15
bus to FIFO.
#
MASTER MODE: When DMA is active, WR pin enables data from the
address/data bus to the addressed device.
#
3
2.0 Pin Descriptions (Continued)
2.1 BUS INTERFACE PINS (Continued)
Symbol
BCLK
DIP Pin No.
PCC Pin No.
Type
Function
40
57
I
BUS CLOCK: Used as a reference clock when DDC is bus master. Used
only during reset and DMA operations. Maximum ratio of RCLK/BCLK is 4
for Word Mode, and 2 for Byte Mode.
RACK
LACK
38
39
54
56
I
I
REMOTE DMA ACKNOWLEDGE: System input granting use of the bus
for a remote DMA bus cycle. If RACK is de-asserted during a transfer, the
current transfer cycle will complete.
LOCAL DMA ACKNOWLEDGE: System input granting use of bus for a
local DMA bus cycle. If LACK is deasserted during a transfer, the current
transfer cycle will complete. LACK has priority over RACK.
RS0–5
AD0–7
35-30
48-41
41, 42
46-49
I
REGISTER SELECT: Used as address inputs to select internal registers
when CS pin is low.
e
1 and DMA is
58, 59
63–68
I/O
ADDRESS/DATA 0–7: These pins float if CS pin
inactive.
STANDARD I/O PORT, With DMA inactive and CS pin low: Command,
Parameter, Count and Status register data is transferred.
SLAVE MODE, with external DMA controller active and LACK pin high:
D0–7 are transferred between FIFO and memory.
#
#
#
MASTER MODE, with internal DMA active, and LACK pin high: A16–23,
A0–7 and D0–7 are transferred depending on DMA mode and bus
phase.
LRQ
36
51
O
LOCAL DMA REQUEST: Requests are automatically generated when the
FIFO needs to have data transferred.
AD8–15
1–8
1–7
12
I/O
ADDRESS/DATA 8–15:
STANDARD I/O PORT, with DMA inactive and CS pin low: These pins
are driven high.
#
SLAVE MODE, with external DMA active and LACK pin high: D8–15 are
transferred between FIFO and memory.
#
MASTER MODE, with internal DMA active and LACK pin high: A24–31,
A8–15 and D8–15 are transferred, depending on DMA mode and bus
phase.
#
ADS0
9
13
53
I/O
ADDRESS STROBE 0:
INPUT with DMA inactive: ADS0 latches RS0–5 inputs when low. When
high, data present on RS0–5 will flow through to internal register
decoder.
#
OUTPUT: ADS0 latches low order address bits (A0–15) to external
memory during DMA transfers.
#
ADS1/RRQ
37
O
ADDRESS STROBE 1/REMOTE REQUEST: In 32-bit DMA Mode, ADS1
latches high order address bits (A16–31) to external memory. For remote
DMA modes, RRQ pin is active high when SRI or SRO bits in the OC
register are set in non-tracking mode, or during a remote transfer in
tracking mode. (See RT register description in DMA REGISTERS Section.)
2.2 DISK INTERFACE PINS
Symbol
DIP Pin No.
PCC Pin No.
Type
Function
RCLK
25
35
I
READ CLOCK: Disk data rate clock. When RGATE is high, RCLK input
will be the recovered/separated clock from the recorded data and is used
to strobe data into the DDC. When RGATE is low, this input should
become the referenced clock which will be delayed and is used as WCLK
to strobe data to the drive. The transition between the recovered/
separated clock and reference clock must be made with no short pulses.
Short pulses are pulses that are less than the specified minimum RCLK
pulse widths which are specified in the AC timing section as rcl and rch. In
the event of any short pulses on RCLK or if RCLK is inactive for greater
than 10 ms, then the DDC could go into an indeterminant state. If this
happens, then the DDC needs to be reset and the format parameters must
be updated to ensure normal operation. Maximum ratio of RCLK/BCLK is
4 for word mode, and 2 for byte mode.
4
2.0 Pin Descriptions (Continued)
2.2 DISK INTERFACE PINS (Continued)
Symbol
DIP Pin No.
PCC Pin No.
Type
Function
RGATE
19
29
O
READ GATE: Set active high during any disk read operation. This pin
commands data separator to acquire lock. Enables RDATA input pin.
RDATA
WCLK
15
21
22
31
I
READ DATA: Accepts NRZ disk data from the data separator/decoder.
O
WRITE CLOCK: Used when NRZ data is on WDATA pin. Also active when
MFM data is used, but normally not utilized. WCLK frequency follows
RCLK pin.
WGATE
20
18
16
30
28
23
O
O
WRITE GATE: When writing data onto a disk, WGATE is asserted high
with the first bit of data and deasserted low after the last bit of data.
WGATE is also de-asserted on reset or on detection of an error.
WDATA
WRITE DATA: During any write operation, MFM or NRZ encoded data is
output to disk, dependent upon MFM bit status in the DF register. This pin
is inactive low when WGATE is low.
AMF/EPRE
I/O
ADDRESS MARK FOUND/EARLY PRECOMPENSATION: Address mark
input is monitored if the HSS bit in the DF register is low (for soft
sectoring). If the MFM bit in the DF register and the EP bit in the OC
register are both set, then this pin becomes the EPRE control. If both
functions are used, WGATE pin determines the function as follows:
WGATE asserted: EPRE output.
#
#
WGATE de-asserted: AMF input.
AME/LPRE
13
19
O
ADDRESS MARK ENABLE/LATE PRECOMPENSATION: If the MFM bit
in the DF register is low, AME will indicate that an address mark byte(s) is
being output on WDATA pin. If the MFM bit in the DF register and the EP
bit in the OC register are both set, LPRE control is output (if internal MFM
encoding is used).
SECTOR
INDEX
SDV
22
23
27
32
33
37
I
I
SECTOR PULSE: In hard sectored drives, this signal comes from the start
of a sector. In a soft sectored drive this pin must be tied low.
INDEX PULSE: This signal comes from the disk drive, indicating the start
of a track.
O
SERIAL DATA VALID: Asserted when the DDC is either issuing or
receiving header field, internal header CRC/ECC, data field, or internal
data CRC/ECC information. Mainly used for external ECC and
diagnostics.
EEF
26
17
36
24
O
I
EXTERNAL ECC FIELD: Only used if the External ECC Byte Count
register(s) are non-zero. Asserted when external ECC check bits are being
generated (WGATE high) and checked (RGATE high).
EXT STAT
EXTERNAL STATUS:IMPORTANT NOTE: This pin MUST be tied low if it
is not to be used. This pin has three functions:
1: If EEW bit in the RT register is set, the read and write strobes are
extended for both remote and local transfers as long as this pin is high.
This is the External Wait State function.
#
2: If the EEW bit in the RT register is low, this pin will accept a pulse
#
granting valid byte alignment on the last bit of the synch byte before
header or data bytes. This is an OR function with the internal synch
detect.
3: External ECC Check. Only used if External ECC Byte Count
#
register(s) are non-zero, and EEW bit in the RT register is low. After the
last byte of external ECC, this pin will accept a pulse confirming that
there has been no error. A CRC/ECC error will be flagged if this pulse is
not received.
a
V
CC
GND
14,
12
20, 21
16, 17
POWER, GROUND: 5V DC is required. It is suggested that a decoupling
capacitor be connected between these pins. It is essential to provide a
path to ground for the GND pin with the lowest possible impedance.
Otherwise any voltage spikes resulting from transient switching currents
will be reflected in the logic levels of the output pins.
5
FORMAT (Continued)
3.0 Internal Registers of the DDC
HA
Register
Bits Write Read
The numerous registers within the DDC are presented be-
low, grouped according to their function. A key is given as
an aid for the use of each register. The key data is only
suggested for common operation, and should not be con-
sidered as an absolute requirement. Following this listing is
a description of each register, in the order of which they are
listed below. The HA column at the left of this listing gives
the Hex Address of each register.
26 Header Byte 2 Control Register (HC2)
16 Header Byte 2 Pattern
5
8
5
8
5
8
5
8
5
5
8
5
8
5
8
5
8
8
8
8
5
5
8
8
8
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
27 Header Byte 3 Control Register (HC3)
17 Header Byte 3 Pattern
28 Header Byte 4 Control Register (HC4)
18 Header Byte 4 Pattern
KEY
29 Header Byte 5 Control Register (HC5)
19 Header Byte 5 Pattern
D
May be updated when a different drive type is se-
lected
2B ID External ECC Byte Count
2C ID Postamble Byte Count
3C ID Postamble Pattern
C
R
F
I
May be updated before each command
May be read at any idle time
Used during formatting
2D Data Preamble Byte Count
3D Data Preamble Pattern
Used during initialization
NO Operation is not possible
Ý
2E Data Synch 1 (AM) Byte Count
COMMAND
Register
Ý
3E Data Synch 1 (AM) Pattern
HA
Bits Write Read
Ý
2F Data Synch 2 Byte Count
10 Drive Command Register (DC)
11 Operation Command Register (OC)
35 Disk Format Register (DF)
00 Status Register (S)
8
8
8
8
8
8
8
C
C
NO
NO
NO
R
Ý
3F Data Synch 2 Pattern
3B Data Format Pattern
38 Sector Byte Count L
39 Sector Byte Count H
2A Data External ECC Byte Count
20 Data Postamble Byte Count
30 Data Postamble Pattern
34 Gap Byte Count
D
D
D
D
D
D
F
NO
NO
C
01 Error Register (E)
R
12 Sector Counter (SC)
R
13 Number of Sector Operations
Counter (NSO)
C
R
0F Header Byte Count (HBC)/Interlock
36 Header Diagnostic Readback (HDR)
3
8
F
R
R
3A Gap Pattern
F
NO
DMA
CRC/ECC
HA
Register
Bits Write Read
HA
Register
Bits Write Read
37 DMA Sector Counter (DSC)
37 Remote Transfer Register (RT)
36 Local Transfer Register (LT)
1A Remote Data Byte Count (L)
1B Remote Data Byte Count (H)
1C DMA Address Byte 0
8
8
8
8
8
8
8
8
8
NO
I
R
NO
NO
R
02 ECC SR Out 0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
NO
NO
NO
NO
NO
NO
D
R
03 ECC SR Out 1
R
I
04 ECC SR Out 2
R
C
C
C
C
C
C
05 ECC SR Out 3
R
R
06 ECC SR Out 4
R
R
07 ECC SR Out 5
R
1D DMA Address Byte 1
R
02 Polynomial Preset Byte 0 (PPB0)
03 Polynomial Preset Byte 1 (PPB1)
04 Polynomial Preset Byte 2 (PPB2)
05 Polynomial Preset Byte 3 (PPB3)
06 Polynomial Preset Byte 4 (PPB4)
07 Polynomial Preset Byte 5 (PPB5)
08 Polynomial Tap Byte 0 (PTB0)
09 Polynomial Tap Byte 1 (PTB1)
0A Polynomial Tap Byte 2 (PTB2)
0B Polynomial Tap Byte 3 (PTB3)
0C Polynomial Tap Byte 4 (PTB4)
0D Polynomial Tap Byte 5 (PTB5)
0E ECC/CRC Control (EC)
08 Data Byte Count L
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
R
1E DMA Address Byte 2
R
D
1F DMA Address Byte 3
R
D
D
FORMAT (See Note)
D
HA
Register
21 ID Preamble Byte Count
31 ID Preamble Pattern
Bits Write Read
D
5
8
5
8
5
8
5
8
5
8
D
D
D
D
D
D
D
D
D
D
R
R
R
R
R
R
R
R
R
R
D
D
Ý
22 ID Synch 1 (AM) Byte Count
D
Ý
32 ID Synch 1 (AM) Pattern
D
Ý
23 ID Synch 2 Byte Count
D
Ý
33 ID Synch 2 Pattern
D
24 Header Byte 0 Control Register (HC0)
14 Header Byte 0 Pattern
D
NO
NO
25 Header Byte 1 Control Register (HC1)
15 Header Byte 1 Pattern
09 Data Byte Count H
R
6
3.0 Internal Registers of the DDC (Continued)
DUAL-PURPOSE REGISTERS
RED: Re-enable DDC
Some of the above listed registers have dual functions de-
pending on whether they are being written to or read from.
These registers are repeated below to help clarify their op-
eration.
A 1 should be written into this location during the power up
initialization process (see POWER UP AND INITIALIZA-
TION Section), or after an error has been encountered in
order to re-enable the DDC to accept commands. (NOTE: If
the RES bit in the OC register has been set, a 0 should be
written to that location before this operation is performed.) If
no error has been encountered, and a command is being
issued, a zero should be written to this bit. The Re-enable is
an operation by itself and hence an interrupt will be generat-
ed on completion of the operation.
HA
Register
Bits Write Read
02 ECC SR Out 0
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
NO
D
R
NO
R
02 Polynomial Preset Byte 0 (PPB0)
03 ECC SR Out 1
NO
D
SAIS: Start at Index or Sector
03 Polynomial Preset Byte 1 (PPB1)
04 ECC SR Out 2
NO
R
0
Operation begins only upon receipt of an index
pulse.
NO
D
1
Operation begins on either an index pulse or sector
pulse for hard sector drives or immediately for soft
sector drives.
04 Polynomial Preset Byte 2 (PPB2)
05 ECC SR Out 3
NO
R
NO
D
MSO: Multi-sector Operation
05 Polynomial Preset Byte 3 (PPB3)
06 ECC SR Out 4
NO
R
0
1
Single-sector operation.
NO
D
Multi-sector operation using NSO register.
06 Polynomial Preset Byte 4 (PPB4)
07 ECC SR Out 5
NO
R
FMT: Format Mode
NO
D
0
1
No Format Operation.
When set, along with other DC register bits, will initi-
ate disk formatting upon receipt of an index pulse.
07 Polynomial Preset Byte 5 (PPB5)
08 Polynomial Tap Byte 0 (PTB0)
08 Data Byte Count (0)
NO
NO
R
D
HO1, 2: Header Operation Bits:
H02 H01
NO
D
0
0
IGNORE HEADER: associated data transfer
operation will take place with any valid sector
encountered.
09 Polynomial Tap Byte 1 (PTB1)
09 Data Byte Count (1)
NO
R
NO
NO
I
0
1
COMPARE HEADER: Normal mode used to find a
specific sector. The Header Pattern registers con-
tain the comparison pattern.
36 Header Diagnostic Readback (HDR)
36 Local Transfer Register (LT)
37 DMA Sector Counter (DSC)
37 Remote Transfer Register (RT)
R
NO
R
1
1
0
1
WRITE HEADER (Write ID): Normally used only
during Format mode to write ID patterns to disk.
READ HEADER (Read ID): Reads header informa-
tion from disk for diagnostic purposes.
NO
I
NO
Format Note: It is recommended that the Format Registers be reloaded
DO1, 2: Data Operation Bits:
D02 D01
after the following events:
1. A hardware or software reset of the chip
2. A Sector Not Found error
3. A Sector Overrun error
0
0
NO OPERATION: Can be used only with an Ignore
Header command. No disk operation is performed
with this combination, and it can be used along
with the RED command to re-enable the DDC (see
OPERATING MODES).
4. A Data Sync Error
0
1
CHECK DATA: No DMA action and no data move-
ment between disk and FIFO. CRC/ECC checks
are calculated and interrupts, if enabled, are as-
serted on proper conditions. DFE bit in Error regis-
ter will be set if a data CRC/ECC error occurs un-
less in Interlock Mode.
3.1 COMMAND REGISTERS
DRIVE COMMAND (DC) Hex Address (10) Write Only
The locations within this register, when written to, initiate
disk commands and chip functions. For a disk operation,
after the DDC has been configured, this register is loaded to
initiate command execution.
1
1
0
1
WRITE DATA: Initiates local DMA action to fill the
FIFO. Writes data to disk with the proper pre and
post appendages in the data field. FIFO is replen-
ished by local DMA.
Loading the DC register constitutes the initiation of a disk
operation and will hence generate an operation complete
interrupt.
READ DATA: Data enters FIFO from disk, and lo-
cal DMA transfer is initiated when the FIFO con-
tains the number of bytes specified by the Burst
Length in the LT register.
DO2 DO1 H02 H01 FMT MSO SAIS RED
7
6
5
4
3
2
1
0
The following table shows a list of valid commands combin-
ing the H01, H02, D01, D02, FMT bits from the DC register
and the FTF bit in the DF register. No other DC register
combinations are allowed.
7
3.0 Internal Registers of the DDC (Continued)
Valid DDC Commands
DC Register
DF Reg
Operation
D02
0
D01
0
H02
H01
FMT
0
FTF
X
0
0
1
0
1
0
1
0
0
0
0
1
1
No Operation
0
1
0
0
X
Check Data, Compare Header
0
1
1
0
X
Check Data, Write Header
0
1
1
0
X
Check Data, Read Header
1
0
0
0
X
Write Data, Ignore Header
1
0
0
0
X
Write Data, Compare Header, (normal write)
Write Data, Write Header
1
0
1
0
X
1
0
1
1
0
Write Data,Write Header, Format with No FIFO Table
Write Data, Write Header, FIFO Table Format
Read Data, Ignore Header, (recover data)
Read Data, Compare Header, (normal read)
Read Data, Read Header
1
0
1
1
1
1
1
0
0
X
1
1
0
0
X
1
1
1
0
X
OPERATION COMMAND (OC)
Hex Address (11)
SRI, SRO: Start Remote Input, Start Remote Output
Write Only
These bits are only operational in non-tracking mode. The
Remote Start Address and Remote Data Byte Count regis-
ters must be loaded first.
The fields within this register enable on-chip operations. In
non-tracking mode, a remote DMA operation will be initiated
by loading the SRO or SRI bits in this register.
SRI SRO
0
0
0
1
Remote DMA operation unchanged.
IR
7
SCC
6
EP
5
SRO
4
SRI
3
EHI
2
EI
1
RES
0
START REMOTE OUTPUT: Asserts RRQ pin
and RCB flag in Status register, to begin a re-
mote DMA operation from memory to I/O Port.
RES: Reset DDC
0
Clears a previously set RES function. Allows
normal operation.
1
1
0
1
START REMOTE INPUT: Asserts RRQ pin and
RCB flag in Status register, to begin a remote
DMA operation from I/O Port to local memory.
1
DDC immediately enters a stand-by mode. The
FIFO is reset, Status and Error registers are
cleared and all operations in progress are
stopped. DDC is placed in the Reset mode (see
OPERATING MODES). RGATE and WGATE
pins are de-asserted if active. All DMA counters
are cleared. Format Parameter, DMA Address
and ECC registers are unaffected.
STOP CURRENT REMOTE OPERATION: RRQ
pin is de-asserted and RCB flag is reset in
Status register.
EP: Enable Precompensation
0
Early and late precompensation signals are
forced low during a disk write operation.
1
Permits precompensation signals to be output to
external precompensation circuitry (see MFM
ENCODED DATA). This bit is only valid if the
MFM bit is set in the DF register.
EI: Enable Interrupts
0
1
Disabled, INT pin remains inactive high.
Enables interrupts generated by the following:
Correction cycle complete.
#
SCC: Start Correction Cycle
Error which sets ED bit in Status register.
#
#
0
1
No correction is attempted.
Command successfully completed (including
independent remote DMA transfer).
Setting this command will begin the internal cor-
rection cycle. The CCA flag in the Status register
is set and drive commands should not be issued
during this time. At the completion of the cycle,
an interrupt is issued.
EHI: Enable Header Interrupt
EI bit must be set if this bit is set.
0
1
Disabled.
IR: Interlock Required (Interlock Mode)
Interrupt issued at start of ID postamble field
when:
0
1
No interlock function.
The interlock (HBC) register must be written to
after the header operation has completed and
before the DDC encounters the data postamble
field. This allows updating of header bytes dur-
ing a Format operation or changing of drive
commands during a multi-sector operation. Nor-
mally used with the header interrupt enabled.
Header matches in Compare Header opera-
tion.
#
Header finished in Read, Write or Ignore
Header operation.
#
8
3.0 Internal Registers of the DDC (Continued)
DISK FORMAT (DF)
Hex Address (35)
Write Only
STATUS (S)
Hex Address (00)
Read Only
The RESET pin and the RES bit in the OC register reset all
of the bits in this register.
ID2 1D1 IH2 1H1 FTF HSS SAM MFM
7
6
5
4
3
2
1
0
ED CCA LCB RCB LRQ HMC NDC HF
MFM: MFM Encode
(See MFM Encoded Data section.)
7
6
5
4
3
2
1
0
HF: Header Fault
0
NRZ data is output on the WDATA pin when
WGATE is active.
This bit is valid after a Compare Header or Read
Header operation.
1
MFM data is output on the WDATA pin when
WGATE is active. Also configures AMF/EPRE
and AME/LPRE pins as EPRE and LPRE out-
puts when Write Gate is active. Precompensat-
ed outputs are enabled by the EP bit in the OC
register.
SET
CRC/ECC error detected in a header field.
RESET
This bit is reset when the DDC begins the next
disk operation after a new disk command has
been issued.
All ID fields entering the DDC during the opera-
tion are checked. The HF bit will be set if an
error is detected in any header field encoun-
tered. However, if the header being sought is
found and has no CRC/ECC error, the HF bit is
reset. This bit does not produce an error that will
stop operation, assert an interrupt, or set the ED
bit in the Status register in a compare header
operation, but will in a read header operation.
SAM: Start with Address Mark
(See Formatting section)
0
Address Marks will be generated in the synch
e
Ý
ated if MFM bit
1 fields if MFM bit
e
1, or AME will be gener-
0.
1
Address Mark Enable will be generated in ID
e
preamble if MFM bit
HSS: Hard or Soft Sectored
(See Hard Sector vs. Soft Sector Operation).
0.
This bit could provide useful diagnostic informa-
tion if a Sector Not Found error occurs (see Er-
ror Register in this section).
0
1
Sets DDC for soft sectored operation.
Sets DDC for hard sectored operation.
NDC: Next Disk Command
SET
DDC will accept a new command into the DC
register. The header operation is completing the
last sector being operated on.
FTF: FIFO Table Format
0
1
Formatting is done without the use of DMA.
The local DMA channel loads the correct num-
ber of header bytes (HBC register) per sector
into the FIFO from local memory. This data is
then substituted for the header bytes during a
format operation.
RESET
On receipt of a new disk command.
HMC: Header Match Completed
For each of the following, this bit is set and the
interrupt is generated at the start of the header
postamble field.
IH1, 2: Internal Header Appendage
Compare Header Operation:
IH2 IH1
SET
Header field correctly matched with no CRC/
ECC error.
0
0
No CRC/ECC is internally appended, but exter-
nal ECC must be attached.
RESET
At beginning of subsequent header operation.
Read Header Operation:
0
1
1
1
0
1
16-bit CRC CCITT polynomial is appended.
32-bit programmable ECC code is appended.
48-bit programmable ECC code is appended.
SET
Header field has been read with no CRC/ECC
error.
External ECC may be used with any internal CRC/ECC se-
lection. 1 to 31 bytes of external ECC may be added.
RESET
At beginning of subsequent header operation.
Ignore Header or Write Header Operation:
Always set at end of header field.
ID1, 2: Internal Data Appendage
SET
ID2, ID1
RESET
At beginning of subsequent header operation.
0
0
1
1
0
1
0
1
No CRC/ECC internally appended.
LRQ: Local Request
16-bit CRC CCITT polynomial is appended.
32-bit programmable ECC code is appended.
48-bit programmable ECC code is appended.
This bit follows the LRQ pin, and allows applica-
tion of the DDC in a polled mode.
LRQ pin is asserted.
SET
External ECC can be appended to any of the
four cases dependent upon the Data External
ECC Byte Count register.
RESET
LRQ pin is not asserted.
RCB: Remote Command Busy
Non-Tracking Mode:
SET
When OC register is loaded with a DMA instruc-
tion.
RESET
Upon completion of the instruction or upon inter-
nal or external reset.
9
3.0 Internal Registers of the DDC (Continued)
Tracking Mode:
NDS: No Data Synch
SET
When RRQ pin is first asserted in a disk write
mode, or when the Drive Command register is
loaded in a disk read mode.
SET
If a sector or index pulse occurs while the DDC
is waiting to byte align on the first data synch
Ý
Ý
field (synch 1 or synch 2), or if the DDC byte
aligns to the first synch word of the data field but
RESET
Upon completion of the instruction or upon inter-
nal or external reset.
Ý
does not match to subsequent bytes (synch
Ý
or synch 2).
1
LCB: Local Command Busy
RESET
Upon internal or external reset.
SET
When command requiring local DMA is loaded.
FDL: FIFO Data Lost
RESET
Upon completion of the last local or remote
DMA transfer (in tracking mode) or upon internal
or external reset.
SET
During a disk read operation if the FIFO over-
flows, or during a disk write operation if the FIFO
is read when it is empty.
CCA: Correction Cycle Active
RESET
Upon internal or external reset.
SET
On asserting SCC bit in the OC register.
CF: Correction Failed
RESET
At the end of the correction cycle, simultaneous-
ly with the INT pin, if enabled.
SET
If correction is attempted (SCC bit set in OC reg-
ister) and correction failed.
ED: Error Detected
RESET
Upon internal or external reset.
SET
On assertion of one or more bits in the Error
register.
LI: Late Interlock
RESET
Upon internal or external reset.
Will only occur if IR bit in OC register is set.
SET
Controlling logic has failed to write to the Inter-
lock (HBC) register before the end of the data
field of the present sector.
ERROR(E)
Hex Address (01)
Read Only
Any bit set in this register generates an interrupt (if EI bit in
the OC register is set) and stops the current operation. The
RESET pin and the RES bit in the OC register reset all of
the bits in this register.
RESET
Upon internal or external reset.
SECTOR COUNTER (SC)
Allowable Value 0–255 Hex Address (12)
Read/Write
LI CF FDL NDS SO SNF DFE HFASM
In a multi-sector operation, the SC register is first loaded
with the starting sector number. It is incremented after each
header operation is completed. The contents of the SC reg-
ister will replce any header Byte if the SSC bit is set in the
corresponding HC register.
7
6
5
4
3
2
1
0
HFASM: Header Failed Although Sector Number
Matched
(See HFASM description in ADDITIONAL FEA-
TURES)
NUMBER OF SECTOR OPERATIONS COUNTER (NSO)
SET
The header bytes(s) marked with the EHF bit in
the corresponding HC register(s) matched cor-
rectly, but other header bytes were in error.
Allowable Value 0–255 Hex Address (13)
Read/Write
In a multisector operation, the NSO register is loaded with
the number of sectors to be operated on. It is decremented
after every header operation. When zero, the command is
finished. This counter must be reloaded after a reset of the
DDC.
RESET
Upon internal or external reset.
DFE: Data Field Error
SET
On detection of a data field CRC/ECC error in a
Read Data or Check Data operation. This bit
may be set when another error occurs; especial-
ly an error occurring during a Write operation.
These errors would be Sector Overrun or FIFO
Data Lost.
HEADER BYTE COUNT (HBC)/INTERLOCK
Allowable Value 2–6
Hex Address (0F)
Read/Write
This register loads the DMA with the number of header
bytes to expect in a Read Header, or a Format operation
where FIFO table formatting is used. This register is also
used in interlock mode to signal completion of update. The
upper five bits of this register are pulled low when read.
RESET
Upon internal or external reset.
The RED command must be loaded into the DC
register if error correction is to be attempted.
SNF: Sector Not Found
HEADER DIAGNOSTIC READBACK (HDR)
SET
When header cannot be matched for two con-
secutive index pulses in any Compare Header
operation.
Hex Address (36)
Read Only
If a Compare Header/Check Data operation is performed
and an HFASM error occurs, the header bytes for that sec-
tor will have been loaded into the FIFO. By consecutively
reading this address, the header bytes are read from the
FIFO to the microprocessor. Data will be valid for only the
number of header bytes specified in the parameter RAM.
(NOTE: This is a dual function register, sharing operation
with the Local Transfer register, see DMA REGISTER.)
RESET
Upon internal or external reset.
SO: Sector Overrun
SET
If RGATE is active and FIFO is being written to
when a sector or index pulse is received. If
WGATE is active, this bit is set when a sector or
index pulse is received.
RESET
Upon internal or external reset.
SECTOR BYTE COUNT REGISTER (L, H)
An SO error will not occur during a Format oper-
ation.
Allowable Value 1–64k Hex Address (38, 39) Read/Write
The two bytes (most and least significant) that comprise this
register are loaded during initialization, and define the data
10
3.0 Internal Registers of the DDC (Continued)
field size for each sector. The number of bytes transferred
with local DMA is always equal to what has been loaded into
this register. Loading both with zero is not allowed.
1
When DMA tranfer is needed, the FIFO will re-
ceive (when writing) or deliver (when reading) an
exact burst of data.
LBL1, 2: Local Burst Length
3.2 DMA REGISTERS
LOCAL TRANSFER (LT) Hex Address (36) Write Only
LBL2 LBL1
0
0
1
1
0
1
0
1
1 word (2 byte)
4 word (8 byte)
8 word (16 byte)
12 word (24 byte)
This is a dual function register, sharing operation with the
Header Diagnostic Readback (HDR) register (see COM-
MAND REGISTERS). IMPORTANT NOTE: If any internal
DMA is being used, or if the Remote Data Byte Count regis-
ters will be read by the processor, the LT (and RT) register
must be loaded before the Sector Byte Count and Remote
Data Byte Count register pairs.
When reading from disk, these bits select the
number of bytes needed in the FIFO in order to
generate an LRQ signal. When writing, these
bits select the number of bytes that need to be
removed from a full FIFO in order to generate an
LRQ. In either case, if the LTEB bit is set, this bit
pair indicate how many data transfers will be al-
lowed before LRQ is removed.
LBL2 LBL1 LTEB LA LSRW RBO LWDT SLD
7
6
5
4
3
2
1
0
SLD: Select Local DMA Mode
0
SLAVE MODE: External DMA must be used in
place of on-chip DMA.
Ý
Note: Please refer to Section 17, Helpful Hints 29.
REMOTE TRANSFER (RT) Hex Address (37) Write Only
This is a dual function register, sharing operation with the
DMA Sector Counter (DSC) (see DSC at the end of this
section). If any internal DMA is being used, or if Remote
Data Byte Count registers will be read by the processor, the
RT (and LT) register must be loaded before the Sector Byte
Count and Remote Data Byte Count register pairs.
1
NON-TRACKING MODE: Local DMA is enabled.
Whenever local transfers are needed, the DDC
becomes the bus master.
TRACKING MODE: Local and remote DMA are
enabled. DMA transfers are interleaved (see
DMA in DATA TRANSFER section).
LWDT: Local Word Data Transfer
RBL2 RBL1 RTEB TM RSRW EEW RWDT SRD
2
0
1
Address increments by 1, 8 bit wide transfers.
7
6
5
4
3
1
0
Address increments by 2, 16 bit wide transfers.
Address, A0, remains unchanged as it was set
by the DMA address.
SRD: Select Remote DMA
0
Remote DMA inhibited, ADS1/RRQ pin is con-
figured as ADS1.
RBO: Reverse Byte Order
Valid if LWDT bit is set.
1
Remote DMA enabled. This is necessary but not
sufficient to start remote transfer.
0
First byte to/from FIFO is mapped onto the
AD0–7 bus.
RWDT: Remote Word Data Transfer
0
1
Remote address increments by 1.
1
First byte to/from FIFO is mapped onto AD8–15
bus (e.g. 68000).
Remote address increments by 2. Address A0
remains unchanged as it was set by the starting
DMA address.
LSRW: Local Slow Read And Write
0
1
DMA cycles are four clock periods.
EEW: Enable External Wait
DMA cycles are five clock periods. RD and WR
strobes are widened by one clock period.
0
No external wait states acknowledged. Func-
tions 2 and 3 of EXT STAT pin are enabled (see
PIN DESCRIPTIONS).
LA: Long Address
Valid only if SLD
Transfer register.
1
The EXT STAT pin will lengthen RD and WR
strobes during DMA transfers as long as it is
maintained at a high level.
e
e
0 in Remote
1, and SRD
0
16 address bits are issued and strobed by the
ADS0 pin. ADS1/RRQ is available for use by the
remote DMA.
RSRW: Remote Slow READ/WRITE
0
1
Remote DMA cycles are four clock periods long.
Remote DMA cycles are five clock periods long,
if external wait states are not asserted.
1
32 address bits are issued, the lower 16 are
strobed by ADS0 pin. The most significant 16
address lines are only issued when a rollover
from the least significant 16 address lines oc-
curs, or after loading the upper half of the 32-bit
address. When the upper 16 address lines are
issued, that DMA cycle is five clock cycles long
if no internal or external wait states are used.
TM: Tracking Mode
See Tracking Mode description in DATA
TRANSFER Section.
0
1
DMA channels are independent and addresses
are allowed to overlap.
DMA channel addresses are not allowed to
overlap.
LTEB: Local Transfer Exact Burst
0
When DMA tranfer is needed, the FIFO will be
filled when writing to disk or emptied when read-
ing from disk.
RTEB: Remote Transfer Exact Burst
If a remote transfer has been initiated, the RRQ
0
pin will remain asserted until the number of
bytes specified by the Remote Data Byte Count
registers has been transferred, or until the oper-
11
3.0 Internal Registers of the DDC (Continued)
ation is reset or SRI and SRO bits in the OC
register are both set when in non-tracking mode,
or when DMA sector counter reaches zero when
in tracking mode.
bytes). The Gap Byte Count register is the only one with 8
bits, allowing a field of up to 255 bytes in length.
The External ECC Count registers do not perform any pat-
tern repetition. The external ECC appendage is provided
from outside the DDC, and must be fit into the field whose
length is defined by these registers (0–31 bytes). If any field
is to be excluded from the disk format, the Byte Count regis-
ter associated with that field must be loaded with zero. This
is particularly important with the External ECC Byte Count
registers. If these are non-zero, the EXT STAT pin will ex-
pect a pulse for each external ECC field during a Read oper-
ation. If these pulses are not supplied, the operation will be
aborted in an error condition. Also, no more than two con-
secutive format fields may be deleted at one time.
1
If a remote transfer has been initiated, the RRQ
pin will remain asserted until the exact number
of bytes specified by RBL1 and RBL2 has been
transferred, or if any of the conditions described
in the previous paragraph occur.
RBL1, 2: Remote Burst Length
LBL2 LBL1
0
0
1
1
0
1
0
1
1 word (2 byte)
4 word (8 byte)
8 word (16 byte)
12 word (24 byte)
The Header Byte Control registers also do not perform any
pattern repetition, nor do they define field size. They are
provided for controlling the function of each corresponding
header byte.
REMOTE DATA BYTE COUNT (L, H)
Allowable Value 0–64k Hex Address (1A, 1B) READ/
WRITE
HEADER CONTROL (HC0–5)
Hex Address (24–29)
Read/Write
This pair of registers specifies the number of bytes in one
remote transfer using the 16-bit address of the remote DMA
channel. In the non-tracking mode, the remote DMA can
transfer 1–64k bytes independent of the local DMA. Load-
ing both registers with zero will be interpreted as a 64k byte
count. These registers are ignored in tracking mode.
There is one HC register for each of six Header Byte pattern
registers.
NU
4
NCP
3
EHF
2
SSC
1
HBA
0
HBA: Header Byte Active
0
DMA ADDRESS BYTE 0–3
The corresponding Header Byte is not included
in the header byte field and will not be used in
the ID operation. All other bits in each HC regis-
ter in which this bit is set to zero must also be
set to zero. A minimum of two Header Bytes
must be enabled out of six, with no more than
two disabled consecutively.
Allowable Value 0–255 Hex Address (1C–1F) READ/
WRITE
These address bytes are configured dependent on the cur-
rent DMA mode. In 32-bit mode, all four bytes form the
physical address with 1F containing the most significant
byte. In 16-bit mode, bytes 0 and 1 form the low and high
bytes of the local DMA channel, and bytes 2 and 3 form the
low and high of the remote DMA channel, if enabled.
1
The corresponding Header Byte contains valid
data and will be used in the ID operation.
SSC: Substitute Sector Counter
DMA SECTOR COUNTER (DSC)
0
The corresponding Header Byte as stored in the
Hex Address (37)
Read Only
pattern register is directly written to the disk for
a Write Header command, and will be compared
for Compare Header command.
This counter is only valid during tracking mode and holds
the difference between the number of sectors transferred by
the local and remote DMA channels. In tracking mode,
e
operation so invalid data is not exchanged between local
and host memory. This is a dual function register, sharing
operation with the Remote Transfer (RT) register described
earlier in this section.
1
The contents of the Sector Counter (SC) are
substituted for this Header Byte during a Write
Header command and compared during a Com-
pare Header command. This is normally used in
multisector operations.
when DSC
0, remote transfer is disabled in a disk read
EHF: Enable HFASM Function
3.3 FORMAT REGISTERS
See HFASM function description in ADDITIONAL FEA-
TURES.
The disk format is defined by using the format pattern and
control registers. Generally, these registers are set up in
pairs. In each pair, one register is loaded with an appropri-
ate 8-bit pattern that will be written to the disk during a
Format or Write command, or will be used during a Read or
Compare command for byte alignment or a comparison in
locating a sector. Refer toFigure 4, below, for a listing of the
format registers, and the manner in which they are paired.
The FORMAT, READ AND WRITE Section contains a listing
and description of each of the format fields.
0
1
HFASM function is disabled.
HFASM function is enabled. The corresponding
Header Byte is designated as that byte that
must match in order to generate an HFASM er-
ror, typically the sector number.
NCP: Not Compare
0
The corresponding Header Byte will be com-
pared normally.
The other register in the pair is used to control the use of
the corresponding pattern register. These Byte Count regis-
ters are loaded with a 5-bit binary number indicating the
number of times the associated pattern will be repeated,
therefore defining the size of that particular field (0–31
1
A valid comparison will always be assumed, re-
gardless of the true outcome.
NU: Not Used
This bit must be set to zero. If set to 1 unspeci-
fied operations may occur.
12
3.0 Internal Registers of the DDC (Continued)
Hex
Addr
Pattern
Source
Control
Function
Hex
Addr
Pattern Register
Control Register
ID Preamble
Ý
31
32
33
14
15
16
17
18
19
*
3C
3D
3E
3F
3B
Internal
Repeat 0–31x
Define/Control
21
22
23
24
25
26
27
28
29
2B
2C
2D
2E
2F
38
39
2A
20
34
ID Preamble Byte Count
Ý
ID Synch 1 (AM) Byte Count
ID Synch 1 (AM)
Ý
Ý
ID Synch
2
ID Synch 2 Byte Count
Header Byte 0
Header Byte 1
Header Byte 2
Header Byte 3
Header Byte 4
Header Byte 5
ID External ECC
ID Postamble
Data Preamble
Header Byte 0 Control
Header Byte 1 Control
Header Byte 2 Control
Header Byte 3 Control
Header Byte 4 Control
Header Byte 5 Control
ID External ECC Byte Count
ID Postamble Byte Count
Data Preamble Byte Count
External
Internal
0–31 Bytes
Repeat 0–31x
Ý
Ý
Data Synch 1 (AM) Byte Count
Ý
Data Synch 2 Byte Count
Sector Byte Count L
Data Synch 1 (AM)
Ý
Data Format
Data Synch
2
Field Size
1–64k Bytes
0–31 Bytes
Repeat 0–31x
Repeat 0–255x
Sector Byte Count H
Data External ECC
Data Postamble
Gap
*
30
3A
External
Internal
Data External ECC Byte Count
Data Postamble Byte Count
Gap Byte Count
*These are not pattern registers.
FIGURE 4. Format Registers
ECC/CRC Control (EC)
Hex Address (OE)
3.4 CRC/ECC REGISTERS
Write Only
The following registers are for programming and controlling
the CRC/ECC functions of the DDC. Many of these regis-
ters have dual functions, depending on whether they are
being written to or read from. Take care in noting which
these are, to avoid confusion later. Only a basic functional
description of these are provided here. Detailed instructions
on their use can be found in the CRC/ECC section.
DNE IDI IEO HNE CS3 CS2
CS1 CS0
7
6
5
4
3
2
1
0
CS0–CS3: Correction Span Selection Bits
These four bits program the number of bits that
the ECC circuit will attempt to correct. Errors
longer than the correction span will be treated
as non-correctable. The allowable correction
span is 3–15 bits. If a span outside this range is
loaded, the DDC will automatically default to a
span of three bits.
ECC SR OUT 0–5
Hex Address (02–07)
Read Only
The syndrome bytes for performing a correction are avail-
able from these registers, and are externally XOR’ed with
the errored data bytes. These are dual function registers,
sharing operation with the Polynomial Preset Bytes.
For example, a five bit correction span would load as:
POLYNOMIAL PRESET BYTES 0–5 (PPB0–5)
CS3
CS2
CS1
CS0
Hex Address (02–07)
Write Only
0
1
0
1
The ECC shift registers can be preset by loading a bit pat-
tern into these registers. These are dual function registers,
sharing operation with the ECC SR Out registers.
HNE: Header Non-Encapsulation
0
Header address mark and/or synch fields are
encapsulated in the CRC/ECC calculation.
1
Header address mark and/or synch fields are
not encapsulated in the CRC/ECC calculation.
POLYNOMIAL TAP BYTES (PTB0–5)
Hex Address (08–0D)
Write Only
NOTE: The SAM bit in the DF register must be
reset when performing a Compare or Read
These registers are used for programming the taps for the
internal 32 or 48-bit ECC polynomial. PTB0 and PTB1 are
dual function registers, sharing operation with the Data Byte
Counters.
Header operation, and the HNE bit is active low.
If this is not done, the CRC/ECC calculation will
begin at the synch word of the header, resulting
in a Header Fault that will abort a Read opera-
tion or a Sector Not Found error for a Compare
Header operation.
DATA BYTE COUNTER 0, 1 (LS, MS)
Hex Address (08, 09)
Read Only
The Data Byte Counters indicate the location of the byte in
error after an ECC cycle. These are dual function registers,
sharing operation with the Polynomial Tap Bytes 0 & 1. The
Sector Byte Count Register must be reloaded with the sec-
tor length plus the number of ECC bytes before the start of
a correction cycle. If the CF bit in the Error register is reset
after a correction, the Data Byte Counter will contain an
offset pointing to the first byte in error.
IEO: Invert ECC Out
See note under IDI bit, below.
0
Checkbits exiting ECC/CRC shift register are
unaltered.
1
Checkbits exiting ECC/CRC shift register are in-
verted.
13
3.0 Internal Registers of the DDC (Continued)
IDI: Invert Data In
address. The ADS0 line may be derived from a microproc-
essor address strobe such as ALE. In systems with a dedi-
cated address bus (demultiplexed), ADS0 may be pulled
high to allow address information to flow through the latch.
Finally, by applying CS and a RD or WR strobe, any of the
64 internal locations can be accessed. It is important to note
that most registers are read or write only. Some registers,
however, change function dependent on whether they are
being read from or written to (see Dual Function register list
in INTERNAL REGISTERS).
0
1
Data and checkbits entering the ECC/CRC shift
register are unaltered.
Data and checkbits entering the ECC/CRC shift
register are inverted.
NOTE: This inversion option has been included
for compatability with a few systems that require
ECC input and/or output inversion.
DNE: Data Non-Encapsulation
0
Data address mark and/or synch fields are en-
capsulated in the CRC/ECC calculation.
4.2 OPERATING MODES
The DDC can be thought of as operating in four modes:
RESET, COMMAND ACCEPT, COMMAND PERFORM and
ERROR. These modes are given here in order to provide a
functional operating description of the DDC, particularly
when an error has been encountered.
1
Data address mark and/or synch fields are not
encapsulated in the CRC/ECC calculation.
4.0 DDC Operation
Mode 1
RESET: All functions are stopped, and no com-
mand can be issued. During power up and be-
fore initalization, the DDC is held in this mode.
To leave this mode, pin 24 (RESET) must be
high, a 0 must be written to the RES location in
the OC register, and a RED command loaded
into the DC register. This places the DDC into
MODE 2.
4.1 MICROPROCESSOR ACCESS
The DDC requires microprocessor control to initiate opera-
tions and commands, and to check chip status. All registers
in the DDC appear as unique memory or I/O locations. Each
can be randomly accessed and operated on. When the
DMA is not performing a memory transfer, the chip can be
accessed as a memory location or standard I/O port. Only
eight bits of data may be transferred at this time, using pins
AD0–7 (the upper 8 bits of a 16 bit microprocessor are not
used). Six dedicated address pins (RS0–5) individually se-
lect all of the DDC’s internal registers. By using these dedi-
cated lines with an address strobe input (ADS0), the chip
can be used in both multiplexed and demultiplexed address
bus environments. The ADS0 and RS0–5 pins operate as a
fall through type latch. By asserting CS active low, the DDC
recognizes it has to be a slave and allows RD and WR to
effect the internal registers. With multiplexed address and
data lines, a positive strobe pulse on ADS0 will latch the
Mode 2
Mode 3
Mode 4
COMMAND ACCEPT: The DDC is free and
ready to receive the next command (NDC bit set
in Status register). Upon receipt of a command,
the DDC will enter MODE 3.
COMMAND PERFORM: The directed operation
is performed. If no error is encountered, the
DDC will return to MODE 2. An error will put the
DDC into MODE 4.
ERROR: The error needs to be serviced, and
then the DDC can be reset by MODE 1.
TL/F/5282–4
FIGURE 5. Microprocessor Access to DP8466B
14
4.0 DDC Operation (Continued)
4.3 POWER UP AND INITIALIZATION
In powering up the DDC, the counters and registers must be
initialized before a drive can be assigned and the appropri-
ate information loaded. This can be done by either holding
pin 24 (RESET) low, or by setting the internal RES bit in the
OC register. Both require that the DDC be held in the reset
condition for a minimum of 32 RCLK periods and 4 BCLK
periods before the reset condition can be cleared. Figure 7
shows a general algorithm for both methods. After power
up, and whenever a new drive is assigned, the appropriate
drive format registers need to be loaded before any drive
operation is performed.
TL/F/5282–5
FIGURE 6. DDC Operating Modes
TL/F/5282–6
Note 1: If the RE-ENABLE operation is accomplished by polling the status register and not enabling interrupt, then it should be polled for NDC bit set. When set, it
should remain set for at least 30 RCLKs before RE-ENABLE can be considered complete. The REN operation under worst case condition could take as long as
270 RCLKs.
Note 2: As shown various methods are possible for power up, and it is up to the user as to which is more suitable. The DDC should be reset and RCLK and BCLK
should be applied after power up, otherwise it may draw an excessive amount of current, and may cause bus contention.
FIGURE 7. Power Up and Initialization Algorithm
15
5.0 Format, Read and Write
POSTAMBLE:
GAP 3:
Allows read gate turn off time for the PLL
to unlock. Provides a pad so that the
write splice does not occur at the end of
the CRC.
5.1 DISK FORMATTING
The formatting process is carried out through the format
parameter and pattern registers (see FORMAT REGIS-
TERS). These registers should be loaded during the initiali-
zation process for the particular drive in use. The pattern
registers are loaded with the specific 8-bit pattern to be writ-
ten to the disk. The count registers specify the number of
times each 8-bit pattern is to be written. In loading these
registers, several things need to be kept in mind:
Provides protection against speed varia-
tion. In soft sectored mode, its length is
determined by the Gap Byte Count regis-
ter. In hard sectored mode, this gap will
continue until the next sector pulse.
Format operations always start with an index pulse, and end
with the next index pulse, thus making one track. The DDC
has three approaches for formating disks:
If any byte count register is loaded with zero, that field
will be excluded, and no pattern for the corresponding
pattern register need be loaded.
#
Internal Sequential
FIFO Table
At least two header bytes must be used, with no more
#
than two consecutive unused header bytes. This also
applies to all the fields in the format, where no more
than two consecutive fields may be deleted. The one
exception is the internal header ECC and external head-
er ECC field. At least one of these fields must be pres-
ent.
Interlock Type
INTERNAL SEQUENTIAL
This mode is used where the sector number is incremented
for each physically adjacent sector, that is, for an interleave
of one. This mode may be used on a multi-sector operation
to format a whole track of sequential sectors. The header
bytes other than the sector number, such as cylinder num-
ber and head number, are loaded. The Sector Counter (SC)
is loaded with the first sector number desired on the track
If the disk is hard sectored, no gap byte count needs to
be loaded. See Hard Vs. Soft Sector Operation in the
FORMAT, READ AND WRITE Section.
#
The sector format options that are provided with the DDC
are shown in Figure 8. The fields common to the ID and
data fields, such as the preamble, Synch, CRC/ECC and
postamble fields, perform similar functions, and are briefly
discussed below.
e
and the HC register with SSC 1. The Number of Sector
Operations (NSO) counter is loaded with the number of sec-
tors per track. Finally, the FMT bit is set in the DC register
in addition to bits for a Write Header/Write Data, multi-
sector operation. Formatting begins upon loading the DC
register. The last sector number written will therefore be
PREAMBLE:
Allows the PLL in the data separator to
achieve phase lock.
a
b
]
NSO 1.
[
]
[
SC
Ý
Ý
SYNCH 1 and 2: Synch 1 contains the missing clock ad-
dress mark for use with soft sectored
FIFO TABLE
disks. Generally, this field is not used in
Ý
This approach is ideal for sector interleaving and offers the
minimum of microprocessor intervention during the format
operation. The microprocessor sets up the header bytes of
each sector, contiguously in memory. The local DMA chan-
nel or external DMA is used to transfer the header byte sets
into the FIFO. Each set transferred is used once for each
header field. The local DMA transfers a new set for each
sector. The number of sectors transferred is determined by
the NSO register.
hard sectored disks. The synch 1 field
can be used to extend the preamble or
the synch fields in hard sectored mode.
Ý
Ý
Synch 1 and 2 fields allow for byte
alignment of the DDC.
HEADER BYTES: Used to uniquely identify each sector.
Examples are sector number, cylinder
number, track number, etc.
The format operation follows the sequence below:
DATA:
Information to be stored.
(1) Before the format operation, a full track of header byte
sets is loaded into a memory area accessible to the
local DMA channel. Each header byte set must contain
an even number of bytes. If it contains an odd number
of bytes, an extra ‘‘dummy’’ byte must be inserted so
that each header byte set will be contained in an even
byte boundary.
CRC/ECC:
This field is generated and checked in-
ternally.
EXT.ECC:
Used with external ECC circuitry. Pro-
vides space for externally generated
ECC bytes.
(2) The DMA address is loaded with the location of the first
byte of the first header byte set.
ID FIELD
Ý
Ý
2
0–31 Bytes
ID PREAMBLE ID SYNCH 1 (AM) ID SYNCH
0–31 Bytes
HEADER BYTES ID CRC/ECC*
ID EXT ECC* ID POSTAMBLE
0–31 Bytes
2–6 Bytes
0, 2, 4 or 6 Bytes 0–31 Bytes
0–31 Bytes
DATA FIELD
DATA
DATA
Ý
DATA
DATA
DATA
CRC/ECC
0, 2, 4 or 6 Bytes 0–31 Bytes 0–31 Bytes 0–255 Bytes
DATA
EXT ECC POSTAMBLE
DATA
GAP 3
Ý
PREAMBLE SYNCH 1 (AM) SYNCH 2 FORMAT PATTERN
0–31 Bytes 0–31 Bytes 0–31 Bytes 1–64k Bytes
Note 1: The ID CRC/ECC field and the ID EXT ECC field must not be set to zero simultaneously.
Note 2: The ID and DATA preamble fields need to be at least 3 bytes for proper operation.
FIGURE 8. Sector Format Fields
16
5.0 Format, Read & Write (Continued)
(3) The Header Byte Count (HBC) is loaded with the num-
ber of header bytes in each sector (2–6 bytes).
WRITE
A similar process occurs in reverse for a write operation.
The DMA fills the FIFO, and when the correct sector is
found, this data begins to be written to disk. When the data
in the FIFO falls by an amount equal to the burst length, a
transfer request is issued on LRQ. When LACK is granted,
the DMA either fills the FIFO or transfers the exact number
of bytes specified in the burst length. This process contin-
ues until a number of bytes specified by the Sector Byte
Count register has been written to the disk.
(4) The Disk Format (DF) register is loaded with the FTF bit
set.
(5) The Drive Command (DC) register is loaded for a Write
Header/Write Data, multi-sector, format operation.
INTERLOCK TYPE
This approach offers the most versatility, but requires fast
microprocessor intervention. It may be used to format a
whole track of interleaved sectors. It can also be used for
creating files of varying sector length, but this can be very
tricky. The DDC can format sectors with data lengths from 1
to 64k bytes with single byte resolution.
Multi-sector operations follow the same procedure, but the
operation is repeated on the number of sectors specified in
the Number of Sector Operations (NSO) counter, with an
interrupt being generated on completion of the last sector.
Interlock type formatting uses the interlock mode and the
header complete interrupt to enable the microprocessor to
directly update any format parameter bytes. The Operation
Command (OC) register is loaded wth IR (Interlock Mode),
EHI and EI bits set. The Disk Format (DF) register should be
loaded with the FTF bit reset. The header byte pattern for
each selected header byte must be loaded into the relevant
register. The NSO register is loaded with the number of sec-
tors to be formatted. The DC register is then loaded for a
Write Header/Write Data, multi-sector, format operation.
5.3 HARD SECTOR vs. SOFT SECTOR
OPERATION
The choice between hard and soft sectored operation is
made through the use of the HSS bit in the Drive Format
register. This bit, in conjunction with other control bits can
set the DDC to perform a number of functions depending on
whether a read, write or format operation is to be enacted.
e
e
HSS
HSS
0 sets the DDC for soft sectored operation, and
1 sets the DDC for hard sectored operation.
After the header field is written in the first sector, the DDC
issues the header complete interrupt. With interlock mode
set, the controlling microprocessor has the block of time
until the preamble field of the next sector to read status,
load the next sector’s header bytes into the DDC registers
and confirm this had been accomplished by writing to the
Interlock (HBC) register. This must be done after the HMC
interrupt for every sector, including the last sector of the
operation. If this is not done, a Late Interlock error will occur
when a subsequent command is loaded in the DC register.
FORMAT
In hard sectored operation, the DDC assumes that sector
pulses are present, and will ignore the gap count. Gap bytes
will be written until a pulse is detected on the SECTOR pin.
In soft sectored operation, the gap count will be used for
every sector except the last. The Gap Byte Count register
determines the Gap 3 length. For the last sector, gap bytes
will be written until an index pulse is received.
READ
When reading, the need for the AMF input pulse is deter-
mined by the HSS bit. For soft sectoring, the AMF input is
In a non-format operation, the user has only until the end of
the data field to write to the HBC register (see Data Recov-
ery Using The Interlock Feature in ADDITIONAL FEA-
TURES). This operation is repeated until the NSO register
decrements to zero. An interrupt will then be issued indicat-
ing that the operation has completed.
Ý
required for at least one bit time within the Synch 1 fields
in both the ID and Data sections of the sector. For hard
sectoring, the AMF input is not required.
The HSS bit in the DF register, and the SAIS command in
the DC register define when RGATE is asserted for various
sector formats. This is outlined below.
5.2 READ AND WRITE
For initiating Read/Write operations, the necessary format
registers need to be loaded with the appropriate information
to enable the DDC to identify the desired sector. Multi-sec-
tor operations will also require the Number of Sector Opera-
tions (NSO) counter and the Sector Counter (SC). Algo-
rithms outlining the read/write operations are shown in Fig-
ures 10 and 11. For each of these, it is assumed that the
parameters for the desired sector(s) have been loaded, and
that the head is positioned over the proper track.
HSS
SAIS
RGATE ASSERTED:
0
0
1
1
0
1
0
1
On index pulse
On receipt of instruction
On index pulse
On index or sector pulse
WRITE
The HSS, MFM and SAM bits in the DF register determine
the use of the address mark and the AME pin as follows:
READ
HSS MFM SAM
FUNCTION
During a read operation, header data passing under the disk
head is compared to the header bytes in the DDC parame-
ter RAM. If a match is found after a read command is is-
sued, the data field of the identified sector will start filling
the FIFO. Once the selected threshold data level (burst
length) is reached, the Local DMA Request (LRQ) pin will be
asserted, signaling that a transfer is required. When the
LACK pin grants the bus, either the exact burst length or the
entire FIFO contents are transferred to memory. The FIFO
continues filling, and this process repeats until the entire
data field has been transferred to memory.
0
0
0
AME pin activated during ID and data
Ý
synch 1 fields.
X
0
0
1
1
AME pin activated during ID preamble.
X
Missing clocks inserted in ID and data
Ý
synch 1 fields.
AME pin indicates LPRE (if enabled).
1
1
0
1
0
AME pin disabled.
Ý
Synch 1 fields written without
missing clock pulse.
X
17
5.0 Format, Read & Write (Continued)
TL/F/5282–7
FIGURE 9. Format Track Algorithm
18
5.0 Format, Read & Write (Continued)
TL/F/5282–8
FIGURE 10. Simple Read Operation
19
5.0 Format, Read & Write (Continued)
TL/F/5282–9
FIGURE 11. Simple Write Operation
20
5.0 Format, Read & Write (Continued)
5.4 MFM ENCODED DATA
MFM encoding of write data is controlled by the MFM bit in
5.5 ADDRESS MARK PATTERNS, MISSING
CLOCK
During writing and formatting a sector with MFM encoding
enabled, a clock violation, or missing clock pulse, will be
Ý
inserted in the synch 1 field. This indicates the address
mark. For an example of this, refer to Figure 13.
e
0 sets the DDC to write NRZ data to the
the DF register MFM
e
1 sets the DDC to write MFM data
to the disk. MFM
disk.
PRECOMPENSATION OF MFM ENCODED DATA
When writing MFM encoded data with precompensation en-
abled, only the following hex values are allowed to be load-
Ý
ed into the synch 1 pattern registers:
When the MFM bit in the DF register and the EP bit in the
OC register are set, precompensation will be indicated on
the EPRE and LPRE pins. Precompensation is issued for
the middle bit of a 5-bit field. In the DP8466B, early and late
precompensation will be enacted for all of the combinations
as shown below. All other patterns will not require precom-
pensation. Precompensation can be disabled by setting the
EP bit in the OC register inactive low.
A1, C2, C3, E1, 84, 85, 86, 87
With no precompensation, any pattern containing 100001 is
valid.
During a soft sectored read operation, an AMF pulse will be
expected on the AMF/EPRE pin during each byte of the
Ý
synch 1 field.
EPRE NRZ PATTERNS
00 0 10
LPRE NRZ PATTERNS
00 1 10
00 0 11
00 1 11
01 1 00
10 0 00
01 1 01
10 0 01
11 1 00
10 1 10
11 1 01
10 1 11
Precompensation outputs are aligned to provide symmetri-
cal set-up and hold times relative to the rising edge of the
WDATA outputs. This gives a half period of RCLK set-up
time on precompensation outputs. This is shown in Figure
12. Two bits of zero precede the preamble fields at the lead-
ing edge of the write gate when writing MFM data due to
MFM encoded delays.
TL/F/5282–10
FIGURE 12. Example of EPRE and LRPE Outputs
TL/F/5282–11
FIGURE 13. Missing Clock Example
21
6.0 CRC/ECC
PROGRAMMING PRESET PATTERN
6.1 PROGRAMMING CRC
To program the preset pattern that the shift registers will be
preset to, PPB0–PPB5 must be initialized. As in the polyno-
The DDC is set for internal CRC by programming the disk
Format (DF) and ECC/CRC Control (EC) registers. The
CRC-CCITT polynomial used by the DDC for the CRC code
is given below:
48 32
0
mial taps, x , x , and x are implied. The assignment of
the bits for 48 and 32 bit modes is shown in the tables on
the following pages.
16
12
5
x
e
a
a
a
1
P(x)
x
x
The value programmed into each register will be the preset
pattern for the eight bits of the corresponding shift register.
For typical operation, these will be programmed to all 1’s.
All unused presets must be set to 0. In 32-bit mode, PPB2
and PPB3 must be set to all 0’s. Failure to do so will result in
improper operation.
The DDC uses the pattern preset to all 1’s for the CRC
calculation. Note: If no CRC/ECC is used for the ID fields,
an external ECC must be used.
6.2 PROGRAMMING ECC
There are two sets of six registers used to program the
ECC. One set of six is used to program the polynomial taps,
while the other set is used to establish a preset pattern
(typically all 1’s). Bits contained in the ECC Control (EC)
register are used to control the correction span. The DF
register contains bits for choosing the desired type of ap-
pendage: Either 32 or 48-bit programmable ECC polynomi-
als, or the 16-bit CCITT CRC polynomial is possible. A 48-bit
computer generated polynomial is also available from Na-
tional Semiconductor free of charge.
Preset Bit Assignment 48-Bit Mode
BIT NUMBER
Ý
REG ADDR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
7
6
5
4
3
2
1
9
0
8
PPB0
PPB1
PPB2
PPB3
PPB4
PPB5
02
03
04
05
06
07
x
x
x
x
x
x
x
x
x
x
15
23
31
39
47
14
22
30
38
46
13
21
29
37
45
12
20
28
36
44
11
19
27
35
43
10
18
26
34
42
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
17
25
33
41
16
24
32
40
x
x
x
x
x
x
x
x
PROGRAMMING POLYNOMIAL TAPS
To program a polynomial into the shift register, each tap
position used in the code must be set to 0, and all unused
taps should be set to 1. The bit assignment for these regis-
ters in 48 and 32-bit modes is shown in the tables that fol-
low. It is important that for 32-bit codes, PTB2 and PTB3 all
be set to 1’s. Failure to do so will result in improper opera-
Preset Bit Assignment 32-Bit Mode
BIT NUMBER
Ý
REG ADDR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
48
32
tion. Also, x
always contain the x term and a 48-bit ECC will always
and x
are implied, i.e., a 32-bit ECC will
7
6
5
4
3
2
1
9
0
8
PPB0
PPB1
PPB2
PPB3
PPB4
PPB5
02
03
04
05
06
07
x
x
x
x
x
x
x
x
x
x
32
15
14
13
12
11
10
x
x
x
x
x
x
48
0
contain the x term. For both ECC’s, the term x (or 1) is
also implied, even though this bit is accessible.
0
0
0
0
0
0
0
0
0
23
0
22
0
21
0
20
0
19
0
18
0
17
0
16
Tap Assignment 48-Bit Mode
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
31
30
29
28
27
26
25
24
BIT NUMBER
Ý
REG ADDR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
RECOMMENDED POLYNOMIAL AS AN EXAMPLE
7
6
5
4
3
2
1
9
0
8
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
08
09
0A
0B
0C
0D
x
x
x
x
x
x
x
x
x
x
To program the 32-bit polynomial of the form:
15
23
31
39
47
14
22
30
38
46
13
21
29
37
45
12
20
28
36
44
11
19
27
35
43
10
18
26
34
42
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
32
28
26
19
17
10
6
2
x
a
a
a
a
a
a
a
a
1
x
x
x
x
x
x
x
17
25
33
41
16
24
32
40
x
x
x
x
x
x
x
x
with a preset of all 1’s, a correction span of 5-bits with no
header/data encapsulation, the following registers would be
programmed as shown. Note that PTB2 and PTB3 must be
all 1’s and PPB2 and PPB3 must be all 0’s in 32-bit mode.
Tap Assignment 32-Bit Mode
BIT NUMBER
Ý
REG ADDR
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
7
6
5
4
3
2
1
9
0
8
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
08
09
0A
0B
0C
0D
x
x
x
x
x
x
x
x
x
x
15
14
13
12
11
10
x
x
x
x
x
x
1
1
1
1
1
1
1
1
1
23
1
22
1
21
1
20
1
19
1
18
1
17
1
16
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
31
30
29
28
27
26
25
24
22
6.0 CRC/ECC (Continued)
The DDC will issue an interrupt after the correction cycle is
complete. Other activities (such as completion of remote
DMA) may issue interrupts before this happens. These inter-
rupts should be serviced to allow the Correction Cycle Com-
plete interrupt to be issued. The CCA bit in the Status regis-
ter will be high during the entire correction cycle. It will be
reset when the cycle has completed. The ED bit in the
Status register will remain active throughout the correction
cycle.
Polynomial Taps
BIT NUMBER
Ý
REG
7
6
5
4
3
2
1
0
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
0
1
0
0
1
1
1
0
1
1
1
1
0
1
0
1
1
1
1
1
If after an interrupt, the Status register is read and the CCA
bit is low, the Error register is read to see if the correction
was successful. If the CF bit is set, this signifies that the
error was non-correctable. This usually means that two er-
rors have occurred with extremities exceeding the selected
correction span. Failure to correct an error is serious and
the system should be notified that the data from that sector
is erroneous.
Preset Pattern
BIT NUMBER
Ý
REG
7
6
5
4
3
2
1
0
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
If the CF bit was not set, the error was corrected. The micro-
processor then computes the address of the first byte in the
[
data field that contains the error. That address is: current
a
]
Sector Length
]
[
value of DMA Address Bytes 0 & 1
b
]
-
[
Data Byte Count L & H
1.
Errors are corrected by XOR’ing syndrome bytes (ECC SR
Out 0–5) with the bytes in the data record in memory that
contain the error. The Data Byte Count can be used to de-
termine whether the error is in the ECC or data field. If the
Data Byte Count is greater than the maximum sector length,
the error is in the ECC field and no correction should be
attempted. If the Data Byte Count is less than the sector
length, the error is in the data field (or it may straddle the
data and ECC fields) and may be corrected.
ECC Control Register
Ý
BIT
7
6
5
4
3
2
1
0
SET
1
0
0
1
0
1
0
1
6.3 OPERATION DURING CORRECTION
The DDC can be set to correct an error any time one has
been detected and before another operation has begun.
The user decides when to initiate the correction. The sector
in question can be re-read several times to insure that the
error is repeatable. If so, the error can be considered a hard
error on the disk and a correction can be attempted. Since
the DDC does not contain drive control circuitry, it is the
user’s responsibility to provide the programming for the exe-
cution of any re-read operations and the associated deci-
sion making.
For performing a correction with 32-bit ECC, the following
shift registers should be read sequentially to obtain the syn-
drome byte pattern:
ECC SR Out 1, ECC SR Out 4, ECC SR Out 5
ECC SR Out 2 and 3 are not used in 32-bit mode and will
contain 0’s if read. ECC SR Out 0 will contain all 0’s if the
error is correctable, and may contain some set bits if it is
not.
ECC SR Out 1 will always contain the first bits in error. The
succeeding bits will be contained in ECC SR Out 4 and 5. If
the maximum span of 15 bits is used, all three registers may
be needed, depending on where the first bit occurs.
The syndrome bytes in the ECC shift register will contain the
bit error information. The bytes in error will already have
been transferred to memory. Once initiated, the correction
is performed internal to the DDC, leaving the bus free for
other operations. An interrupt will be issued within the time it
takes to read a sector, indicating whether the error was cor-
rected or not. During this time, the erroneous sector in
memory will remain unchanged.
To correct the error, the syndrome bits in these registers are
XOR’ed with the data bits contained in buffer memory. The
corrected data is then written back to the buffer memory,
replacing the data in error. The address of the first byte in
error is computed by the microprocessor as described
above.
Error correction time is determined by the error’s location in
the sector. The nearer to the start of the sector, the longer
the DDC takes to locate the error. This time can be deter-
mined using the formula shown at right. It should be noted
that this is internal correction time only; more time is re-
quired for the microprocessor to perform additional opera-
tions.
Before initiating a correction operation, the DDC needs to
be reset, and re-enabled (see Operating Modes in DDC OP-
ERATION). The Sector Byte Count registers must be initial-
TL/F/5282–12
e
b
(l x)/f
Approximate Correction Time
e
l
Entire length of data field and ECC appendage (in bits)
Distance from least significant bit to first error location (in bits)
read clock frequency (in hertz)
a
[
]
[
ized to sector length
4 for 32-bit mode or sector
6 for 48-bit mode. The correction command
should be issued when the counter has been updated.
e
x
f
a
]
length
e
FIGURE 14. Calculating Correction Time
23
6.0 CRC/ECC (Continued)
DATA BYTES
FROM
CORRECTED
DATA BYTES
BUFFER MEMORY
v
SYNDROME
BYTES
RETURNED TO
BUFFER MEMORY
BYTE 27
BYTE 28
BYTE 29
BYTE 30
BYTE 31
v
Z
Z
Z
1st Data Byte with Error
2nd Data Byte with Error
3rd Data Byte with Error
x
x
x
x
x
x
x
x
x
ECC SR OUT 1
ECC SR OUT 4
ECC SR OUT 5
x
x
x
BYTE 28
BYTE 29
BYTE 30
FIGURE 15. 32-Bit ECC Correction Process
To perform a 48-bit ECC correction, the following registers
should be read sequentially:
EXAMPLE OF A 32-BIT CORRECTION
Shown in Figure 17, is a record with several bits read in
error from disk. Bits D4, D11, D13 and D14, now located in
memory, were incorrectly and need to be corrected. As can
be seen, the correction pattern provided in ECC SR Out 1
and 2 can be used to correct bits D4, D11, D13 and D14.
The CPU reads the Data Byte Count and computes that it
points to the first byte read from disk. This byte is XOR’ed
with ECC SR Out 1 and is written back to memory. The
second byte read from the disk is XOR’ed with ECC SR Out
4 and then written back. ECC SR Out 5 need not be used
since it contains all 0’s.
ECC SR Out 1, ECC SR Out 2, ECC SR Out 3
ECC SR Out 0, 4 and 5 are not used for outputting syn-
drome bits for correction in 48-bit mode and will contain 0’s
for a correctable error. If the error is non-correctable, these
registers may contain some set bits. Syndrome bit location
and error correction is performed as in 32-bit mode.
DATA BYTES
FROM
CORRECTED
DATA BYTES
BUFFER MEMORY
v
BYTE 13
SYNDROME
RETURNED TO
BYTES
BUFFER MEMORY
Z
Z
Z
1st Data Byte with Error
2nd Data Byte with Error
3rd Data Byte with Error
x
x
x
BYTE 14
BYTE 15
BYTE 16
BYTE 17
v
x
x
x
x
x
x
ECC SR OUT 1
ECC SR OUT 2
ECC SR OUT 3
x
x
x
BYTE 14
BYTE 15
BYTE 16
FIGURE 16. 48-Bit ECC Correction Process
Syndrome Pattern
BIT NUMBER
Buffer Memory
CORRESPONDING
REGISTER
7
6
5
4
3
2
1
0
BUFFER DATA BIT PATTERN
ECC SR OUT 1
ECC SR OUT 4
ECC SR OUT 5
0
0
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
D7
D6
*
D5
*
*
D12
D3
*
D2
D1
D0
0
0
1
0
D15
D23
D10
D18
D9
D8
D22
D21
D20
D19
D17
D16
e
*
location of bits in error
FIGURE 17. Example of a 32-Bit Correction
24
6.0 CRC/ECC (Continued)
TL/F/5282–13
FIGURE 18. Correction Cycle Algorithm
THIS CYCLE CAN ONLY BE
INITIATED AFTER A READ
DATA OPERATION HAS
BEEN COMPLETED
25
6.0 CRC/ECC (Continued)
A note of caution: If the DDC is in the tracking DMA mode
when a data error occurs, the remote DMA channel will
transfer the sector in error to its destination in the system.
The DDC will still interrupt to indicate that it has detected an
error. It is then up to the system to get the DDC to correct
the error in buffer memory and retransfer the corrected data
to the system.
At the end of a sector or an operation, the local burst coun-
ter does not reset. This means that the first burst of a sub-
sequent sector will not be what was programmed in the LTR
if the burst length was not an exact multiple of the data
length. The data length is equal to the sector length times
the number of sectors. The DDC would have to be reset
between operations if resetting the local burst counter is
desired. It is not recommended to count bursts in order to
monitor the amount of data transferred.
6.4 ECC CHECK USING LONG READ AND
LONG WRITE
8-BIT/16-BIT WIDE TRANSFERS
During a normal read or write operation, the size of the data
field is specified by the Sector Byte Count register pair. If
the data field is extended during a readback, the ECC ap-
pendage can be read in as data and analyzed outside the
DDC. This is what is known as a long read.
Byte or word wide data transfer can be selected for both
local and remote DMA channels. Word wide tranfers with
local DMA use the AD0–15 pins, and byte wide use the
AD0–7 pins. Both the local and the remote DMA addresses
are incremented by 2 for word wide transfers, and 1 for byte
wide transfers. Commands and DDC parameter registers
are loaded and read only 8-bits at a time, using AD0–7.
REVERSE BYTE ORDER
TL/F/5282–14
This option is only valid for 16-bit wide transfers using the
local DMA channel. This should not be used for 8 bit wide
transfers. It enables the two bytes being transferred to be
mapped with the high order byte to AD0–7 and the low
order byte to AD8–15, or vice-versa.
*Read length defined by Sector Byte Count register pair.
FIGURE 19. Example of a Long Read
Likewise, an externally generated ECC appendage can be
added to the data and written to the disk as data with or
without the onboard CRC/ECC generator enabled. This is
known as a long write.
The DDC has provisions to accommodate five DMA modes.
These are as follows:
By using long reads and long writes in conjunction with ex-
ternal software used to produce data fields and external
CRC/ECC appendages, various diagnostic programs can
be devised to test the DDC’s internal correction functions
and ECC generation circuitry. These tests could be incorpo-
rated in the initialization algorithm to test the chip each time
it is powered up.
EXTERNAL DMA:
1. Slave Mode
INTERNAL DMA, Single Bus: 2. 16-Bit Local Mode
3. 32-Bit Local Mode
Multiple Bus: 4. Non-Tracking Mode
5. Tracking Mode
All five modes accommodate the three configurations just
described. All DMA modes, except external slave, use an
incrementing address. Local channel transfers always have
priority over remote channel transfers unless externally re-
prioritized. If the local channel is used, its transfer length is
always automatically loaded from the Sector Byte Count
register pair.
7.0 Data Transfer
7.1 DIRECT MEMORY ACCESS (DMA)
The DDC is designed to work efficiently in two major system
configurations:
(1) A single system bus with shared data buffer/system
memory (see Figure 20).
7.2 EXTERNAL DMA
SLAVE MODE
(2) A dual bus environment with a local microprocessor,
buffer memory and DP8466B on a local bus interfacing
the host system bus through an I/O port (seeFigure 21).
In this mode, no on-chip DMA control is used. LRQ and
LACK pins are connected to an external DMA controller.
After LACK has been granted, I/O RD and I/O WR from the
DMA controller are used to strobe data between the internal
FIFO and the DDC I/O port. 8-bit and 16-bit wide data trans-
fers are possible. Throughout this data sheet, reference has
been made to the use of on-chip DMA for the transfer of
data. It is important to note here that external DMA can be
used in place of this if so desired.
All DMA activity is supported by the following three features:
PROGRAMMABLE BURST LENGTH (THRESHOLD)
Here, the transfer of data between the 32-byte FIFO on the
DDC and the external memory (local or main) involves the
use of internal or external local DMA channel. While writing
to the disk, the DDC will initiate a transfer when the FIFO
has been depleted by the burst length. It will also initiate a
transfer while reading from the disk when the FIFO fills to
the burst length. This length is selectable from 2, 8, 16 or 24
bytes, allowing for the variations in bus latency time encoun-
tered in most systems.
7.3 INTERNAL DMA
The following four modes all use on-chip DMA control with
at least the local channel serving as bus master for data
transfers between the internal FIFO and memory.
At the start of a write operation, the FIFO will be filled up in
a series of bursts of the programmed length.
SINGLE BUS SYSTEMS
The following two modes support a single bus and a single
shared buffer/system memory. Bus access should be guar-
anteed before the FIFO overflows or empties during a disk
transfer operation. A FIFO Data Lost error (FDL bit in Error
register) will be flagged and the operation aborted if this fails
If the exact burst option is not selected, the FIFO will be
completely filled (if writing to disk) or emptied (if reading
from disk) in one DMA operation. The burst length is always
the threshold at which the transfer will be requested and is
independent of the DMA mode, including slave.
26
7.0 Data Transfer (Continued)
TL/F/5282–16
FIGURE 20. Single System Bus, 32-Bit Address DMA
TL/F/5282–15
FIGURE 21. Dual System Bus, 16-Bit Address DMA
27
7.0 Data Transfer (Continued)
to happen. Different system latency times can be accommo-
dated by the selectable burst length.
the remote channel manages to transfer a sector before the
local channel has completed the next sector, the DSC regis-
ter will decrement to zero. Further remote transfers are in-
hibited until the local channel completes another sector and
increments the DSC. In other words, each time a local sec-
tor has been transferred, the DSC is incremented and each
time a remote sector completes, the DSC is decremented.
Therefore, the DDC prevents further buffer memory con-
tents that have not been previously loaded with valid data
by the local DMA from being transferred to the host system.
The remote channel continues operation until the last byte
from the buffer memory has been transferred. An interrupt is
issued upon completion of the operation.
16-BIT LOCAL MODE
SLD bit is set and LA bit is reset in the LT register. Only the
16-bit local DMA channel is enabled. 64k bytes are directly
addressable by the DDC. Address data is presented on
AD0–15 and latched with ADS0. Transfers always take 4
BCLK cycles if no wait states are issued.
32-BIT LOCAL MODE
SLD bit and LA bit are both set in the LT register. SRD bit in
the RT register must be reset. The local DMA channel is
now set to issue 32-bit addresses using the remote DMA
channel as the upper 16-bit address register. 4 G bytes are
addressable by the DDC. During the first DMA cycle of a
newly programmed address, or after a roll-over of the lower
16-bit address counter occurs, ADS1 strobes a new high
order word (A16-31) into the external address latches. Each
time this happens, the DMA cycle is 5 BCLK periods long.
When a new high order address is not needed, the DMA
cycle is 4 BCLK periods long. ADS0 is used as an output to
latch the low order word (A0–15) from the AD0–15 pins into
the address latch.
NON-TRACKING MODE
SLD bit set and LA bit reset in the LT register. SRD bit set
and TM bit reset in the RT register. The remote and local
channel addresses are completely independent. The con-
trolling microprocessor must insure that the data to be
transferred by the remote channel is not over-written by the
local channel and vice-versa. DMA address and count regis-
ters are set up independently. Remote start address (DMA
Address Bytes 2 and 3) and Remote Data Byte Count regis-
ters must be loaded before SRI or SRO bits are set in the
OC register. Local or remote transfers may already be in
progress when the other channel is started. The local chan-
nel has priority over the remote channel. Local bus utiliza-
tion is then interleaved between the local channel, the re-
mote channel and the controlling microprocessor.
MULTIPLE BUS SYSTEMS
The following two modes support a dual bus environment,
where a local microprocessor, buffer memory and the
DP8466B interface to the host through an I/O port. The
difference between tracking and non-tracking mode is
whether the DDC or the controlling microprocessor ensures
that an attempt to read data from buffer memory does not
occur before data has been written there. Basic algorithms
for both are shown in Figures 22 and 23.
By setting both SRI and SRO simultaneously, any non-track-
ing remote DMA operation will stop. The present remote
address and remote data byte count will be retained and the
local DMA will be unaffected. Loading the original OC in-
struction (input or output) will restart the original instruction
from the last remote DMA address.
TRACKING MODE
SLD bit set and LA bit reset in the LT register. SRD bit and
TM bit set in the RT register. The DDC ensures that data is
not overwritten by data transferred from the FIFO.
DMA Mode Select Table
LT Register
SLD
RT Register
SRD
DMA Mode
SLAVE
This mode effectively turns the buffer memory into a large
FIFO. This is accomplished through the use of the DMA
Sector Counter (DSC), which keeps track of the difference
between sectors read/written to the disk and the sectors
transferred to/from the host system. Each time the source
transfers a sector of data into buffer memory (length deter-
mined by the Sector Byte Count register pair), the DSC reg-
ister is incremented. It is decremented each time the desti-
nation has transferred a sector of data. Whenever the DSC
register contents become zero, destination transfers are in-
hibited. This mode facilitates multi-sector operations.
LA
TM
0
1
1
1
1
0
0
0
0
1
1
0
16-BIT LOCAL
32-BIT LOCAL
TRACKING
0
0
1
0
0
1
NON-TRACKING
0
0
NOTE: In either tracking or non-tracking mode, if either
channel is loaded with an odd byte transfer count, the DDC
will transfer the next higher even number of bytes. For ex-
ample, if 511 was loaded into the Remote Data Byte Count
registers, 512 bytes would be transferred, with valid data
only in the first 511 bytes.
Example: Tracking Mode, Disk Read
Source is local DMA
#
Destination is remote DMA
#
DMA WAIT STATES
INTERNAL
DSC register is reset automatically upon start of opera-
tion
#
Local and remote start address, SC, NSO, OC and final-
ly DC registers are loaded. Other registers may need to
be updated, but this is a minimum set.
#
Both DMA channels can independently be set to lengthen
the RD and WR strobes by one clock cycle (LSRW bit in the
LT register and RSRW bit in the RT register). This lengthens
each transfer from 4 cycles to 5 cycles of the BCLK.
A sector is read from the disk and is transferred in bursts
from the FIFO to the buffer memory by local DMA. The DSC
register then increments and the remote channel can begin
transferring the first sector from the buffer memory to the
host system. Burst transfers can be interleaved with local
DMA, remote DMA and microprocessor all sharing the bus.
The local channel bursts have priority over remote bursts. If
EXTERNAL
By enabling the external wait states (in the RT register), the
EXT STAT pin is configured to insert wait states in each RD
and WR pulse as long as this input is high. This is valid for
both the local and remote DMA channels.
28
7.0 Data Transfer (Continued)
29
8.0 Interrupts
Interrupts can only occur if the EI bit in the OC register is
set. If it is not set, the INT pin is always de-asserted high. 16
RCLK periods (3.2 ms at 5 Mbit/sec data rate) must pass
before servicing an interrupt (i.e. reading Status). Failure to
do this will result in servicing the same interrupt twice. There
are four general conditions that may cause an interrupt to
occur:
CLEARING INTERRUPTS
The INT pin will be forced inactive high any time the Status
register is being read. If an interrupt condition arises during
a status read, this condition will assert INT as soon as the
status read is finished.
Interrupts can also be cleared by setting the internal RES
bit, or by asserting the external RESET pin.
Operation Complete
Header Complete
Error
9.0 Additional Features
Correction Cycle Complete
9.1 DATA RECOVERY USING THE INTER-
LOCK FEATURE
OPERATION COMPLETE
This interrupt indicates that the current DDC operation has
completed and the DDC is ready to execute a new com-
mand. Commands can be loaded sooner by setting EHI bit
in the OC register. The Next Disk Command (NDC) bit in the
Status register is set coincident with the Header Complete
interrupt. New disk commands can be loaded before DMA
operation is finished if NDC is set. If the command is a multi-
sector operation, the end of operation interrupt will occur
only after the operation is completed in the last sector of
operation. The INT pin is asserted low when:
The potential use of the interlock feature is in recovering
data from a sector with an unreadable header field. It is
assumed that the number of the sector physically preceding
the bad sector on the disk is known. A single-sector opera-
tion will be performed on these sectors, and the Drive Com-
mand register will be changed in between them. The follow-
ing steps will recover the data:
The header bytes of the physical sector preceding the
desired sector are loaded into the relevant byte pattern
registers.
#
Disk operation is completed for any command that is not
a disk read operation.
#
The OC register must be loaded with the EI, EHI and IR
bits set. This enables the Header Complete interrupt as
well as the interlock feature.
#
A read operation in the tracking DMA mode after the
remote transfer is complete.
#
The DC register is loaded for a single-sector, Compare
Header/Check Data operation.
#
A read operation in the non-tracking DMA mode after the
local transfer is complete.
#
After the Header Complete interrupt, the DC register
#
A non-tracking mode remote DMA transfer is completed.
This is independent of the disk operation or the local
DMA.
#
must be loaded with an Ignore Header/Read Data oper-
ation, and the Interlock (HBC) register written to. If the
controlling microprocessor fails to write to the HBC regis-
ter before the end of the data field of the first sector, a
Late Interlock error (LI bit in Error register) will be
flagged, and the operation will be terminated with an in-
terrupt.
HEADER COMPLETE:
If the EHI and EI bits are set in the OC register, an interrupt
will occur when any header operation is complete. Multi-
sector operations will generate an interrupt after each head-
er in each sector has been operated on. It is asserted two
bit times into the ID postamble. This function allows the
changing of header bytes (and parameter RAM in general)
on the fly. The Header Complete interrupt can be used in
conjunction with the Interlock Required (IR) bit in the OC
register set to insure that changes have been completed
before the next sector is encountered (see Interlock Type
formatting). Another normal mode of use would be to notify
the controlling microprocessor when the next disk com-
mand can be loaded. This interrupt is coincident with the
Next Disk Command (NDC) bit being set in the Status regis-
ter.
When the HMC interrupt occurs on the second sector,
the Interlock (HBC) register must be written to again in
order to avoid LI error.
#
The operation will terminate normally when the data from
the badly labeled sector has been read.
#
9.2 HFASM FUNCTION
The Header Failed Although Sector number Matched
(HFASM) function on the DDC can be used to perform
maintainance and diagnostic functions, both of which will be
briefly outlined here.
The HFASM function is enabled by setting the EHF bit in at
least one of the Header Control registers, with a Compare
Header command loaded into the DC register. More than
one header byte may have its EHF bit set. If any one of the
header byte(s) with it’s EHF bit set matched, but any other
header byte(s) (regardless of the state of their EHF bit)
don’t match, an HFASM error will occur.
ERROR
Any bit set in the Error register sets the ED bit in the Status
register and causes an interrupt.
CORRECTION CYCLE COMPLETE
An interrupt will occur at the end of an internal correction
cycle, regardless of whether the error was corrected or not.
If the error was non-correctable, the CF bit will be set in the
Error register. This will not generate two interrupts.
30
9.0 Additional Features (Continued)
TL/F/5282–19
FIGURE 24. Data Recovery Algorithm
31
9.0 Additional Features (Continued)
In this way, the HFASM function performs a maintenance
type function, and can often indicate that the head is posi-
tioned over the wrong track. It is independent of whether or
not a CRC failure has occurred. An HFASM failure will not
stop operation until the header CRC bytes have been com-
pared and the CRC check is completed.
This process can only be enabled for one disk command.
The Compare Header/Check Data command will enable
this function. Any other command will disable it.
10.0 Typical System Configurations
10.1 LOW COST SYSTEM
To perform a diagnostic function, the header can be read
and analyzed. This can be done only during a Compare
Header/Check Data operation with HFASM enabled. This
causes the header patterns coming from the disk to be writ-
ten into the FIFO. We must assume that the FIFO is empty
(or has been reset before the operation) in order for this
operation not to interfere with data transfers. If an HFASM
error occurs during a Header Compare, the FIFO will be left
intact and the header with the error can be read out of the
FIFO from the Header Diagnostic Readback (HDR) register.
(Note: LWDT of the local transfer register must be set to
match the bus width of the accessing MP for this function.)
In a single bus system, the DDC can directly address 4G
bytes of main memory. The 16-bit I/O port (AD0–15) is ex-
ternally demultiplexed and buffered with the octal latches
and drivers. The main microprocessor, through a separate
disk drive control I/O block, is responsible for commands
like Head Select, Seek, TRK 000, Drive select, etc. Bus ac-
cess must be guaranteed before the FIFO overflows or
empties. A short burst length (LT and RT registers) accom-
modates longer bus latency times and helps to insure this.
The burst capability allows for other bus operations to be
interleaved while the FIFO is filling (during a read) or empty-
ing (during a write). If long, important CPU operations are
required, the next configuration must be used.
If an HFASM error did not occur, the FIFO will be cleared
and the header patterns that were stored there will be lost.
FIGURE 25. Low Cost System Configuration
TL/F/5282–20
32
10.0 Typical System Configuration (Continued)
a cache for track or file buffering and command lists can be
down-loaded for execution by the microprocessor. The two
DMA channels can both directly address 64k bytes of buffer
memory. The local DMA channel transfers data between
the buffer memory and the internal FIFO. The remote DMA
channel transfers data between the buffer memory and the
host I/O port. With the addition of a bi-directional buffer
isolating the DDC from the microprocessor, simultaneous
drive operations can be accomplished. While the DDC is
transferring data via DMA with the buffer memory, the local
microprocessor can issue drive control commands.
10.2 HIGH PERFORMANCE SYSTEM
This configuration provides a local bus for the DDC to share
with the local microprocessor and a buffer memory. Here,
whole blocks of data can be transferred between the DDC
and buffer memory without interfering with the system bus.
This leaves the main CPU to perform important operations
and to allow data transfers when it is ready. This configura-
tion is also used in intelligent drives or systems that comply
to SCSI or IPI specifications. A local bus, dedicated micro-
processor and buffer memory are main characteristics of an
intelligent disk interface. The buffer memory can be used as
TL/F/5282–21
FIGURE 26. High Performance System
33
INDEX
11.0 ABSOLUTE MAXIMUM RATINGS
13.17 Read Data Timing
13.18 RGATE Assertion from Index or Sector Pulse Input
13.19 Write Data Timing for NRZ Type Data
13.20 WGATE Assertion from Index or Sector Pulse Input
13.21 Write Data Timing for MFM Type Data
13.22 Positional Timing for SDV and EEF
13.23 Field Envelope Timing
12.0 DC ELECTRICAL CHARACTERISTICS
13.0 AC ELECTRICAL CHARACTERISTICS & TIMING
DIAGRAMS
13.1 Register Read (Latched Register Select:
ADS0 Active)
13.2 Register Read (Non-Latched Register Select:
e
13.24 EXT STAT Timing When Used as External Byte
Synch
ADS0
1)
13.3 Register Write (Latched Register Select:
ADS0 Active)
13.25 EXT STAT Timing When Using External ECC
13.4 Register Write (Non-Latched Register Select:
e
14.0 AC TIMING TEST CONDITIONS
ADS0
1)
15.0 MISCELLANEOUS TIMING INFORMATION
15.1 Status Register Timing
15.2 Error Register Timing
15.3 General Timing for Read Gate
15.4 Write Gate Timing
13.5 LRQ Timing with External DMA
13.6A Reading FIFO Data in DMA Slave Mode
13.6B Writing FIFO Data in DMA Slave Mode
13.7 Additional Slave Mode DMA Timing
13.8 Local and Remote DMA Acknowledge
13.9 DMA Address Generation
15.5 Normal Interrupts
15.6 Derating Factor
13.10 DMA Memory Write
16.0 DP8466B Functional Status
17.0 Helpful Design Hints
18.0 Appendix
13.11 DMA Memory Read
13.12 DMA with Internal Wait States
13.13 DMA with External Wait States
13.14 DMA Control Signals
13.15 Local and Remote DMA Interleaving
13.16 RRQ Assertion after Writing to OC Register for a
Remote Transfer
11.0 Absolute Maximum Ratings*
b
a
150 C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Storage Temperature Range (TSTG)
Power Dissipation (PD)
65 C to
§
§
500 mW
Lead Temperature (TL) (Soldering 10 sec.)
260 C
§
2000V
b
a
a
a
Supply Voltage (V
)
CC
0.5 to
7.0V
0.5V
0.5V
e
e
ESD Tolerance: C
R
100 pF
1500X
ZAP
ZAP
b
b
DC Input Voltage (V
)
0.5 to V
IN
CC
CC
DC Output Voltage (V
)
0.5 to V
*Absolute Maximum Ratings are those values beyond which damage to the
device may occur.
OUT
e
e a
0 C to 70 C
g
5V 10%, unless otherwise specified) T
12.0 DC Electrical Characteristics (V
Symbol
§
§
CC
A
Parameter
Conditions
Typ
Limit
2.0
Units
V
V
V
V
Minimum High Level Input Voltage
Maximum Low Level Input Voltage
(Note 1)
(Note 1)
V
V
V
V
IH
0.8
IL
e
b
0.1
Minimum High Level
Output Voltage
(Note 2)
I
20 mA
V
CC
OH1
OH2
l
OUT
l
ADS0, ADS1 I
e
4.0 mA
3.5
l
OUT
For All Other Outputs I
l
e
2.0 mA
2.0 mA
l
OUT
l
e
V
V
Maximum Low Level
Output Voltage
(Note 2)
I
20 mA
0.1
0.4
V
V
OL1
l
ADS0, ADS1 I
OUT
l
e
4.0 mA
OL2
l
OUT
For All Other Outputs I
l
e
l
OUT
l
e
g
I
Maximum Input Current
V
IN
V or GND
CC
1
mA
IN
34
12.0 DC Electrical Characteristics
(V
e
e
A
a
0 C to 70 C (Continued)
g
5V 10%, unless otherwise specified) T
§
§
CC
Symbol
Parameter
Conditions
Typ
Limit
Units
e
I
I
Maximum TRI-STATE Output
Leakage Current
V
V
or GND
OZ
CC
OUT
CC
or GND
CC
g
10
mA
e
Average Supply Current
DP8466BN-12
(Note 3)
V
IN
BCLK
V
e
e
RCLK
12 MHz
12
20
25
30
mA
mA
mA
e
I
0 mA
OUT
e
V
CC
e
e
Average Supply Current
DP8466BN-20
(Note 3)
V
IN
or GND
RCLK
BCLK
20 MHz
16 MHz, I
40
45
e
0 mA
OUT
or GND
e
V
CC
e
e
Average Supply Current
DP8466BN-25
(Note 3)
V
IN
BCLK
RCLK
20 MHz
25 MHz
e
I
0 mA
OUT
Note 1: Limited functional test patterns are performed at these levels. The majority of functional test patterns are performed with input levels of 0V and 3V for AC
Timing Verification.
Note 2: Outputs are ‘‘conditioned’’ for Tested States by normal functional test patterns. Device clocks are disabled and a purely static measurement is performed.
Note 3: Device is in normal operating mode and is measured with bypass capacitor of 0.1 mF between V
and Ground.
CC
13.0 AC Electrical Characteristics & Timing Diagrams
NATIONAL SEMICONDUCTOR PRELIMINARY TIMING FOR THE DP8466B
Note: Refer to 11.4 for AC Timing Test Conditions.
Refer to 11.5.6 for derating factor.
13.1 REGISTER READ (Latched Register Select: ADS0 Active)
TL/F/5282–22
DP8466B-25/20
Min Max
DP8466B-12
Symbol
Parameter
Units
Min
15
Max
rss
Register Select Setup to ADS0 Low
Register Select Hold to ADS0 Low
Address Strobe Width In
10
10
20
ns
ns
ns
ns
ns
ns
ms
ns
ns
ns
rsh
15
aswi
asdv
csdv
rdv
30
Address Strobe to Data Valid (Note 1)
Chip Select to Data Valid
150
125
125
10
200
150
150
10
Read Strobe to Data Valid
rw
Read Strobe Width
csdz
rdz
Chip Select to Data TRI-STATE (Note 2)
Read Strobe for Data to TRI-STATE (Note 2)
Data Hold from ADS0 (Note 1)
20
20
20
80
20
20
20
90
80
90
asdh
Note 1: asdv and asdh timing is referenced to the leading edge of ADS0 or the leading edge of valid address, whichever comes last.
Note 2: TRI-STATE note: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to
drive this line with no contention.
35
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
e
13.2 REGISTER READ (Non-Latched Register Select: ADS0
1)
TL/F/5282–23
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
Min
Max
200
150
150
10
e
rsdv
csdv
rdv
Register Select to Data Valid (ADS0
Chip Select to Data Valid
Read Strobe to Data Valid
Read Strobe Width
1) (Note 1)
150
125
125
10
ns
ns
ns
ms
ns
ns
ns
rw
csdz
rdz
Chip Select to Data TRI-STATE (Note 2)
20
20
20
80
20
20
20
90
Read Strobe for Data to TRI-STATE (Note 2)
Data Hold from Register Select Change (Note 1)
80
90
rsdh
Note 1: rsdv and rsdh timing assumes that ADS0 is true when RS0–5 changes.
Note 2: TRI-STATE note: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to
drive this line with no contention.
13.3 REGISTER WRITE (Latched Register Select: ADS0 Active)
TL/F/5282–24
DP8466B-25/20
DP8466B-12
Min Max
Symbol
Parameter
Units
Min
15
50
7
Max
asws
csws
csdh
rwds
rwdh
ww
Address Strobe to Write Setup (Note 1)
Chip Select to Write Setup
20
70
10
50
5
ns
ns
ns
ns
ns
ns
ns
Chip Select Data Hold (Note 2)
Register Write Data Setup
40
3
Register Write Data Hold (Note 2)
Write Strobe Width
50
10
70
15
aswh
ADS0 Hold from Write (Note 1)
Note 1: asws and aswh timing is referenced to the leading edge of ADS0 or the leading edge of valid address, whichever comes last.
Note 2: Minimum data hold time for a register write is referenced to CS or WR, whichever goes inactive high first.
36
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
e
13.4 REGISTER WRITE (Non-Latched Register Select: ADS0
1)
TL/F/5282–25
DP8466B-25/20
DP8466B-12
Min Max
Symbol
Parameter
Units
Min
10
50
7
Max
rsws
csws
csdh
rwds
rwdh
ww
Register Select to Write Setup (Note 1)
Chip Select to Write Setup
15
70
10
50
5
ns
ns
ns
ns
ns
ns
ns
Chip Select to Data Hold (Note 2)
Register Write Data Setup
40
3
Register Write Data Hold (Note 2)
Write Strobe Width
50
15
70
20
rswh
Register Select Hold from Write (Note 1)
Note 1: rsws and rswh assume that ADS0 is true when RS0–5 changes.
Note 2: Minimum data hold time for a register write is referenced to CS or WR, whichever goes inactive high first.
13.5 LRQ TIMING WITH EXTERNAL DMA
TL/F/5282–26
DP8466B-25/20
DP8466BN-12
Symbol
Parameter
Units
Min
Max
75
Min
Max
bchrqh
bchrql
BCLK High to LRQ High
BCLK High to LRQ Low
100
100
ns
ns
75
Note 1: The ‘‘ON’’ condition for the slave mode DMA, once the LRQ is active, is when both LACK and the RD or WR strobes are active. The LRQ is then removed
after the next BCLK as shown. The ‘‘OFF’’ condition for the slave mode DMA is determined by the RD or WR strobe becoming inactive and the LRQ could be
deasserted from the next BCLK rising edge. Lack does not play a role in determining the ‘‘OFF’’ condition.
Note 2: National recommends to use the same clock that generates the external RD & WR strobes for BCLK.
37
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.6A READING FIFO DATA IN DMA SLAVE MODE
TL/F/5282–27
DP8466B-25/20
DP8466B-12
Symbol
Parameter
LACK to Data Valid
Units
Min
Max
80
Min
Max
90
lackdv
srdv
ns
ns
ns
Slave Read Strobe to Data Valid
60
70
srdz
Slave Read Strobe to Data TRI-STATE (Note 3)
20
80
20
90
Conditions: Disk read operation, DMA disabled, LRQ output true.
Note 3: TRI-STATE Note: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to
drive this with no contention.
13.6B WRITING FIFO DATA IN DMA SLAVE MODE
TL/F/5282–28
DP8466B-25/20
Min Max
DP8466B-12
Min Max
Symbol
Parameter
Units
swds
swdh
Slave Write Data Setup
Slave Write Data Hold
5
10
28
ns
ns
20
Conditions: Disk write operation, DMA disabled, LRQ output true.
13.7 ADDITIONAL SLAVE MODE DMA TIMING
TL/F/5282–78
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
40
50
10
35
10
20
Max
Min
50
60
15
40
15
25
Max
smsw
lacks
lackh
lkbcs
stbch
stbcs
Slave Mode Strobe Width
Lack to Strobe Setup
(Note 2)
(Note 2)
ns
ns
ns
ns
ns
ns
Strobe to Lack Hold
Lack to Bus Clock Setup
Strobe from Bus Clock Hold
Strobe to Bus Clock Setup
Conditions: Disk read or disk write operation, internal DMA disabled, and LRQ output active.
Note 1: The Read or Write Cycle begins when Lack and (WR or RD) are true. From this point Lack must be held true for lackh and WR or RD must remain true for
smsw.
Note 2: Disk Read or Write Byte Transfer Rate cannot exceed DMA Byte Transfer Rate. The inactive RD/WR pulse width must be at least 2 BCLK cycles.
38
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.8 LOCAL AND REMOTE DMA ACKNOWLEDGE
TL/F/5282–29
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
Min
Max
crq
Bus Clock to Request (Notes 5, 6)
Acknowledge Setup to Clock
Bus Clock to Remote Status
85
100
ns
ns
ns
caks
cakh
20
10
25
15
Note 1: The Local and Remote Acknowledges are sampled at the beginning of bus cycles t4 and t1.
Note 2: Local Acknowledge has internal priority over Remote Acknowledge.
Note 3: Local and Remote Acknowledge are ignored if their respective Request output line is false.
Note 4: Above timing is for 16 bit address updates. For 32 bit Local address mode, cycle t0 occurs on the first transfer of an operation or when the lower 16 bits of
the address rollover.
Note 5: crq is implied to be the same for both assertion and deassertion of LRQ or RRQ.
Note 6: LRQ will deassert on t2 for the final deassertion.
13.9 DMA ADDRESS GENERATION
TL/F/5282–30
DP8466B-25/20
DP8466B-12
Min
Symbol
Parameter
Units
Min
Max
Max
10,000
10,000
10,000
55
bcyc
bch
Bus Clock Cycle Time (Notes 2, 3)
Bus Clock High Time (Note 3)
Bus Clock Low Time (Note 3)
Bus Clock to Address Strobe High
Bus Clock to Address Strobe Low
Address Strobe Width Out
40/60
10,000
10,000
10,000
45
80
32
32
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
22.5/28
22.5/28
bcl
bcash
bcasl
aswo
bcadv
bcadz
ads
50
60
bch
20
bch
20
Bus Clock to Address Valid
60
80
70
90
Bus Clock to Address TRI-STATE (Note 4)
Address Setup to ADS0/1 Low
Address Hold from ADS0/1 Low
b
bch 17
b
bch 22
b
bcl 10
b
bcl 10
adh
Note 1: Cycle t0 occurs only on the first transfer of an operation or when the lower 16 bits of the address rolls over.
Note 2: The rate of bus clock must be high enough that data will be transferred to and from the FIFO faster than the data being transferred to and from the disk.
Note 3: DP8466B-25 specification before the slash followed by the -20 specification after the slash.
Note 4: TRI-STATE note: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to
drive this line with no contention.
39
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.10 DMA MEMORY WRITE
TL/F/5282–31
DP8466B-25/20
Min Max
DP8466B-12
Min
Symbol
Parameter
Units
Max
bcw
Bus Clock to Write Strobe
50
60
ns
ns
ns
ns
b
2bcyc 35
b
2bcyc 45
wds
Data Setup to WR High (Note 1)
Data Hold from WR high (Note 1, 3)
Data Valid from t2 Clock (Note 1)
Address Strobe to Data Strobe (Note 2)
Address Strobe to Write Data Valid
wdh
8
50
75
a
8
60
90
bcwd
asds
aswd
a
a
bcl
bcl
10
40
bcl
bcl
20
60
ns
ns
a
Conditions: DMA write, Local or Remote transfer, internal DMA.
Note 1: Data is enabled on AD0–15 only in local DMA transfers.
Note 2: Data strobe is either RD or WR out.
Note 3: TRI-STATE Note: These limits include the RC delay inherent in our test method.
13.11 DMA MEMORY READ
TL/F/5282–32
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
Min
Max
bcr
Bus Clock to Read Strobe
50
60
ns
ns
ns
ns
ns
ds
Data Setup to Read Strobe High
Data Hold from Read Strobe High
DMA Data Strobe Width Out
30
0
35
0
dh
b
2bcyc 10
b
2bcyc 15
drw
dsada
b
bcyc 10
b
bcyc 10
DMA Data Strobe to Address Bus Active
Note 1: ds and dh timing are for Local transfers only.
40
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.12 DMA WITH INTERNAL WAIT STATES
TL/F/5282–33
Conditions: Local or Remote DMA transfer, read or write, internal DMA.
Note 1: Addition of an internal wait state will lengthen RD/WR strobes by an additional bus clock cycle.
Note 2: Internal wait states are enabled by setting the Slow Read/Write bits in the Local and Remote Transfer registers.
Note 3: If used, external wait states will be added between cycles t3 and t4.
13.13 DMA WITH EXTERNAL WAIT STATES
TL/F/5282–34
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
15
Max
Min
20
Max
ews
ewh
External Wait Setup to t3 Clock
External Wait Hold after tw Clock
ns
ns
10
15
Conditions: Read or write, internal DMA mode. Local or Remote transfer.
Note 1: Addition of external wait states will extend RD/WR strobes by an integral number of bus clock cycles.
Note 2: If enabled, an internal wait state is added between cycles t2 and t3.
Note 3: EXT STAT is sampled upon entering states t3 and tw, and adds wait states one bus clock cycle later.
41
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.14 DMA CONTROL SIGNALS
TL/F/5282–35
DP8466B-25/20
DP8466B-12
Min Max
70
70
Symbol
Parameter
Units
Min
Max
55
bccte
bcctr
Bus Clock to Control Enable (WR, RD, ADS0)
ns
ns
Bus Clock to Control Release (WR, RD, ADS0) (Note 1)
60
Note 1: TRI-STATE note: These limits include the RC delay inherent in our test method. These signals typically turn off within 15 ns, enabling other devices to
drive this line with no contention.
13.15 LOCAL AND REMOTE DMA INTERLEAVING
TL/F/5282–36
Note 1: Timing of the acknowledge pulses are used for illustration. Acknowledges need only to be set up with respect to t4 and t1 clock cycle.
Note 2: If both LACK and RACK are asserted with both LRQ and RRQ pending, a local DMA transfer will be performed.
42
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.16 RRQ ASSERTION AFTER WRITING TO OC REGISTER FOR REMOTE TRANSFER
TL/F/5282–37
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
Min
Max
wrqh
Write Strobe to Remote Request High
100
150
ns
Conditions: Non-tracking mode, writing ‘‘Start Remote Input/Output’’ to the Operation Command register.
13.17 READ DATA TIMING
TL/F/5282–38
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
10
Max
Min
15
Max
rds
rdh
Read Data/AMF Setup to Read Clock
Read Data/AMF Hold to Read Clock
ns
ns
10
15
13.18 RGATE ASSERTION FROM INDEX OR SECTOR PULSE INPUT
TL/F/5282–39
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
39/50
16/20
16/20
10
Max
Min
Max
rcyc
rch
rcl
Read Clock Cycle Time (Note 2)
Read Clock High Time (Note 2)
Read Clock Low Time (Note 2)
Index/Sector Setup to Read Clock
Index/Sector Pulse Hold
10,000
10,000
10,000
80
32
32
15
15
10,000
10,000
10,000
ns
ns
ns
ns
ns
ns
iss
ish
10
rcrg
Read Clock to Read Gate
55
70
Note 1: INDEX/SECTOR low must meet iss/ish timing for proper INDEX/SECTOR pulse detection.
Note 2: DP8466B-25 specification before the slash followed by the -20 specification after the slash.
43
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.19 WRITE DATA TIMING FOR NRZ TYPE DATA
TL/F/5282–40
DP8466B-25/20
Min Max
DP8466B-12
Min
Symbol
Parameter
Units
Max
40
40
7
rcwch
rcwcl
rcwcs
dwds
dwdh
wgs
Read Clock to Write Clock High Delay
Read Clock to Write Clock Low Delay
Absolute Value of (rcwcl Ð rcwch)
Drive Write Data Setup to Write Clock
Drive Write Data Hold to Write Clock
Write Gate Setup to Write Clock
30
30
6
ns
ns
ns
ns
ns
ns
ns
b
rcl 10
b
rcl 15
b
b
8
rch
5
rch
b
rcl 10
rch
b
rcl 15
rch
wgh
Write Gate Hold to Write Clock
Note 1: rcl and rch are described in Timing Diagram 13.18.
13.20 WGATE ASSERTION FROM INDEX OR SECTOR PULSE INPUT
TL/F/5282–41
DP8466B-25/20
DP8466B-12
Min Max
Symbol
Parameter
Units
Min
Max
40
rcwg
Read Clock to Write Gate
50
60
60
ns
ns
ns
rcepe
rcepz
Read Clock to Early Precomp Enabled
Read Clock to Early Precomp TRI-STATE
50
50
Note 1: Early Precompensation (EPRE) is used as an output only when writing MFM data.
44
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.21 WRITE DATA TIMING FOR MFM TYPE DATA
TL/F/5282–42
DP8466B-25/20
Min
DP8466B-12
Min
Symbol
Parameter
Units
Max
40
40
40
40
40
40
40
40
40
40
40
40
Max
50
50
50
50
50
50
50
50
50
50
50
50
rchmwh
rchmwl
rclmwh
rclmwl
rcheph
rchepl
rcleph
rclepl
RCLK High to MFM WDATA High
RCLK High to MFM WDATA Low
RCLK Low to MFM WDATA High
RCLK Low to MFM WDATA Low
RCLK High to EPRE High
RCLK High to EPRE Low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RCLK Low to EPRE High
RCLK Low to EPRE Low
rchlph
rchlpl
RCLK High to LPRE High
RCLK High to LPRE Low
rcllph
RCLK Low to LPRE High
rcllpl
RCLK Low to LPRE Low
45
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.22 POSITIONAL TIMING FOR SDV AND EEF
Read operation (Compare Header, Read Header, Compare Data or Read Data)
TL/F/5282–43
Note 1: Data should be delayed 2 bit times before entering external ECC circuitry in order for it to properly align correctly with SDC and EEF.
Note 2: Encapsulation is controlled by the HEN and DEN bits in the EC register, and causes the sync patterns to be included in the CRC/ECC calculation.
Write operation (Write Header, Write Data or Format Track)
TL/F/5282–44
Note 1: Write operation shown is for NRZ data. For MFM encoding, Write data is delayed two bit times relative to NRZ data.
Note 2: Encapsulation is controlled by the HEN and DEN bits in the EC register, and causes the sync patterns to be included in CRC/ECC calculation.
Write header operation (Start with Address Mark)
TL/F/5282–45
Note 1: Field names within parenthesis are the names of the fields on disk.
Note 2: Encapsulation is controlled by the HEN bit in the EC register, and causes the sync patterns to be included in CRC/ECC calculation.
46
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.23 FIELD ENVELOPE TIMING
TL/F/5282–46
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
35
Min
Max
50
rcsdv
rcee
Read Clock to Serial Data Valid
Read Clock to External ECC
ns
ns
35
50
Note 1: SDV is asserted after sync fields, and is deasserted at the start of the postamble field. If sync field encapsulation is enabled, SDV is asserted at the start of
the sync fields.
Note 2: EEF is asserted at the start of the external ECC field, and is deasserted at the start of the postamble field.
Note 3: When the DDC is receiving data from the disk, the SDV and EEF are delayed by two bit times from incoming read data due to internal delays.
Note 4: If the external ECC count is set to zero, no EEF output will be generated.
13.24 EXTERNAL STATUS TIMING WHEN USING EXTERNAL BYTE SYNC
TL/F/5282–47
DP8466B-25/20
DP8466B-12
Min Max
Symbol
Parameter
Units
Min
Max
esys
External Byte Sync Setup to Rising
Edge of Bit Clock 0 of Byte Sync
15
20
15
ns
ns
esyh
External Byte Sync Hold to Rising
Edge of Bit Clock 0 of Byte Sync
10
Note 1: The external sync feature can only be used if the Enable External Wait states (EEW) bit of the Remote Transfer (RT) register is not set.
Note 2: External circuitry is needed to feed the DDC with NRZ zeros until the external sync signal has been generated to prevent the DDC from trying to detect
sync.
Note 3: If External Sync and External Wait states are not being used, the EXT. STAT. pin must be false during preamble and sync fields.
47
13.0 AC Electrical Characteristics & Timing Diagrams (Continued)
13.25 EXTERNAL STATUS TIMING WHEN USED FOR EXTERNAL ECC
TL/F/5282–48
DP8466B-25/20
DP8466B-12
Symbol
Parameter
Units
Min
Max
Min
Max
eccs
External ECC Status Setup to Rising Edge of
Bit Clock 4 of Postamble
15
20
ns
ns
ecch
External ECC Status Hold to Rising Edge of
Bit Clock 2 of Postamble
10
15
Note 1: The external ECC error detection feature can only be used if the Enable External Wait states (EEW) bit of the Remote Transfer register (RT) is zero.
14.0 AC Timing Test Conditions
Input Pulse Levels
GND to 3.0V
5 ns
Input Rise and Fall Times
Input and Output Reference Levels
TRI-STATE Reference Levels
Output Load (See Figure 27)
1.3V
g
Float (DV) 0.5V
TL/F/5282–77
e
e
1MHz)
Capacitance (T
25 C, f
§
A
FIGURE 27
Parameter
Description
Typ
Max
Unit
e
e
e
Note 1: C
50 pF, includes scope and jig capacitance
Open for Push Pull Outputs
L
Note 2: S1
C
IN
Input
7
12
pF
S1
V
CC
for High Impedance to active low and active low to High
Capacitance
Impedance measurements.
e
High Impedance measurements.
S1
GND for High Impedance to active high and active high to
C
OUT
Output
7
12
pF
Capacitance
Note: This parameter is sampled and not 100% tested.
48
15.0 Miscellaneous Timing Information
15.1 STATUS REGISTER TIMING
FIFO DATA LOST: If a transfer between the disk and FIFO
causes the FIFO to underrun or overrun, this bit will be set
within the next byte time creating a write splice if write gate
was on. This is reflected as an ECC error and can be re-
moved if sector is rewritten.
HEADER FAULT: This bit is set at the start of the Header
Postamble field of a header with a CRC/ECC error. It is
reset at the start of the Header Postamble of the header
requested, or upon receipt of a new disk command. No in-
terrupt is generated.
CORRECTION FAILED: This bit is set at the end of the
correction cycle if the error is non-correctable.
NEXT DISK COMMAND: This bit is set at the start of the
Header Postamble of the last sector of an operation, and is
reset upon loading the Drive Command register. No inter-
rupt is generated.
LATE INTERLOCK: This bit is set at the start of Data Post-
amble field for Read operations and at the end of the post-
amble field for non-format Write operations. While format-
ting, this bit is set at the end of the Gap field.
HEADER MATCH COMPLETED: This bit is set at the start
of the Header Postamble field of the header of interest. This
bit is reset when the DDC begins the next header operation.
An interrupt is generated if enabled.
15.3 GENERAL TIMING FOR READ GATE
Whenever the DDC is reading, comparing, or in some cas-
es, ignoring information, RGATE is asserted. The use of
RGATE can be separated into three groups: Header search
(soft sectored mode), header examination, and data exami-
nation.
LOCAL REQUEST: This bit has the same timing as the Lo-
cal Request pin. When the FIFO requires servicing, this bit is
set. When service is no longer required, this bit is cleared.
No interrupt is generated.
SEARCHING FOR HEADERS
REMOTE COMMAND BUSY: In the tracking mode, this bit
is set 3–5 RCLK’s after receipt of a drive command. In the
non-tracking mode, this bit is set when either a Start Re-
mote Input or Start Remote Output command is received in
the Operation Command register. This bit is reset and inter-
rupt is generated upon completion of the initiating operation.
When the DDC is searching for a header in the soft-sec-
tored mode, RGATE is asserted in a somewhat random lo-
cation in the format. After being asserted, if the DDC does
not recognize the address mark pattern within eight bit
times of detecting a one, RGATE will be de-asserted in 18(/2
RCLK’s. RGATE will then remain low for 17(/2 RCLK’s be-
fore another search attempt is made.
LOCAL COMMAND BUSY: This bit is set 3–5 RCLK’s after
receipt of a drive command which requires the use of the
local channel. It is reset after the last transfer of the local
channel if in the non-tracking mode or writing the disk, or
after the last transfer of the remote channel if in the tracking
mode and reading disk. Interrupt is generated upon comple-
tion of the initiating operation.
In modes where the DDC starts a Read, Compare or Ignore
Header operation at an index or sector pulse, RGATE will
be asserted 3–4 RCLK cycles from detection of the index or
sector pulse.
DATA OPERATIONS
CORRECTION CYCLE ACTIVE: This bit is set upon receipt
of the Start Correction Cycle in the Operation Command
register, and is reset at the end of the correction operation.
An interrupt is generated at the end of the correction cycle.
After the header operation has completed, RGATE will be
removed two bits after the start of the Header Postamble. If
a Read or Check Data operation is to follow, RGATE will be
reasserted 11(/2 bits after the Header Postamble.
ERROR DETECTED: This bit is a logical OR function of all
the bits in the Error register. An interrupt is generated when
an error is detected.
At the end of the Data field, RGATE will be removed two
bits into the start of the Data Postamble.
15.4 WRITE GATE TIMING
15.2 ERROR REGISTER TIMING
Whenever the DDC is writing information, WGATE is assert-
ed. WGATE can be separated into three uses: Writing head-
er, writing data or track formatting.
HFASM ERROR: If while in the HFASM mode the sector
address matches and another header byte does not, this bit
will be set at the start of the Header Postamble field.
WRITING HEADERS
DATA FIELD ERROR: If the Data field contains a CRC/ECC
error, this bit will be set at the start of the Data Postamble
field.
When the DDC writes the header, the write operation does
not begin until the receipt of an index or sector pulse. After
the pulse is detected, WGATE will be asserted 2(/2–3(/2
RCLKs from the detection of the pulse. WGATE will stay
true until the end of the Header Postamble, unless the Data
field is to be written. If the Data field is to be written,
WGATE will not be de-asserted between the Header and
Data fields.
SECTOR NOT FOUND: If the header of the desired sector
is not located before two index pulses are received, this bit
will be set upon receipt of the second index pulse.
SECTOR OVERRUN: If an index or sector pulse is detected
while reading the Header or Data field, or while writing and
not in the Gap field, this bit will be set upon receipt of the
sector/index pulse.
WRITING DATA
After a header operation has properly completed, WGATE
will be asserted 3 bit times into the Data Preamble. The
WGATE will remain active until the end of the Data Postam-
ble. Because of internal delays within the DDC, the Write
Data operation is delayed three bit times from the header
patterns.
NO DATA SYNC: If an index or sector pulse is received
before data sync is detected, this bit is set upon receipt of
the sector/index pulse. If there is a data sync error after the
first sync byte has been detected, this bit will be set during
the byte following the byte in error.
49
1.0 Correction Cycle Failure
15.0 Miscellaneous Timing
Information (Continued)
FORMAT TRACK
If a correction cycle is attempted when an ECC/CRC error
occurs in a multisectored disk operation with the sync word
being encapsulated, then it will always fail because the ECC
shift register gets preset. In order to ensure proper correc-
tion, a single sector retry must be attempted on the errone-
ous sector before correction cycle is initiated.
In a format track operation, WGATE is asserted 2(/2–3(/2
RCLK’s from the detection of the index pulse. WGATE will
remain active until the next index pulse is detected, and will
then be removed.
2.0 Error-Correction Handling Feature in Tracking Mode
(Remote transfer of data conditional on Data ECC Er-
ror)
Note: Detection of an index or sector pulse is defined as the rising edge of
the RCLK where index/sector input has met the setup time.
During tracking-mode read data operation, data will be
transferred to local memory and then to a remote port. The
DMA should prevent a remote transfer of the data until the
DDC has checked for a data ECC error. Hence if correction
is to be attempted, then it can be done in the local memory
and then remote transfer can continue. However, the bad
data will be sent to remote system memory without regard
to its integrity and hence it’s the responsibility of the user to
correct the data in his system memory or send the correct
data block again.
15.5 NORMAL INTERRUPTS
Interrupts are generated by the DDC for a variety of rea-
sons, but they all fall into one of three categories: Either
they signal normal completion, a synchronization point, or
an error condition. If an interrupt is generated because of an
error, the interrupt will have timing as described in the Error
register timing section.
The Header Operation Complete interrupt is used for syn-
chronization, and is enabled with the Enable Header Inter-
rupt bit of the Operation Command register. This interrupt
will occur when the DDC finishes the header operation, and
starts the data operation. For Read, Compare, Write, or Ig-
nore Header operations, the interrupt will be generated at
the start of the Header Postamble field.
3.0 Odd Byte Remote DMA Transfer
Odd byte remote transfers are not allowed by the DMA
mode. Therefore if only one transfer is desired to the remote
port, it cannot be done. The only way to overcome this prob-
lem is to do a transfer of two bytes and ignore the second
byte by reloading the remote data byte counter, etc.
The normal Operation Complete interrupt is dependent on
the operation being performed. If the operation is to Check
Data, the interrupt is generated at the start of the Data Post-
amble field. For Write Data operations, an interrupt will be
generated at the end of the Data Postamble. When the DDC
is formatting, the interrupt will be delayed by the length of
the Header Preamble after the format has finished. The
fourth event is further defined by the DMA mode used. For
all local channel operations except for tracking mode disk
read, the interrupt will be generated during the last transfer
of data from the FIFO. In the configuration, tracking mode
disk read, the interrupt will be delayed until the last transfer
is made by the remote DMA. For all non-tracking remote
DMA operations, the interrupt will be generated during the
last transfer of the remote DMA.
4.0 Parameter RAM Registers Losing Contents
If at anytime the Read Clock input sees a glitch, then there
is a good probability for some of the registers in the parame-
Ý
Ý
2
ter RAM to lose their contents, e.g., ID sync 1, ID sync
etc. Whenever the Read Clock goes below the minimum
specifications of ‘rch’ (read clock high time) and ‘rcl’ (read
clock low time), it is considered as glitching the Read Clock.
Hence it is the users responsibility to ensure that there are
no glitches in the Read Clock input. In the future version,
redesign will be attempted to decrease or totally remove the
susceptibility of the chip to glitches on the Read Clk.
5.0 Remote DMA Interrupt Handling
When a correction operation is being performed, an inter-
rupt is generated at the end of the correction cycle, regard-
less of the outcome.
In the non-tracking-mode remote DMA operation the opera-
tion complete interrupt could be held off or remain asserted
despite servicing attempts whenever it happens while the
disk header search is being attempted simultaneously. This
will have to be taken care of in software. More details of this
situation are provided in Chapter 2.
15.6 DERATING FACTOR
Output timings are measured with a purely capacitive load
for 50 pF. The following correction factor can be used for
other loads:
6.0 AME/AMF Handshake for ESDI (Softsectored
Drives)
t
a
a
DP8466B-25/20 C
50 pF:
.13 ns/pF (ADS0, ADS1)
.20 ns/pF (all other out-
L
The DDC does not incorporate the handshake for ESDIsoft
sectored disk operation. The DDC generates the AME sig-
nal only during the format operation and not during the
read/write operation, when in the hardsectored, NRZ data
mode. In the ESDI spec. Address Mark Found, AMF, re-
sponds only after AME is asserted. If AME is not asserted
then AMF from the drive will not occur and the beginning of
the sector will not be determined. The external logic and
software methods needed to implement this handshake
protocol is discussed in the design guide application note
(AN413), in the MASS STORAGE data book.
puts)
t
a
a
DP8466B-12
C
50 pF:
.18 ns/pF (ADS0, ADS1)
.25 ns/pF (all other out-
L
puts)
16.0 DP8466B Functional Status
Introduction
This section is intended to provide some relevant informa-
tion on the functional status of the Disk Data Controller,
DP8466B. There are a few shortcomings of the DP8466B
which are outlined below for reference:
7.0 Post Index/Sector Gap Field
The DDC has no defined field to implement the post index
or post sector pulse gap. This can however be still imple-
50
Most Significant Bit of Sync Byte
16.0 DP8466B Functional Status
(Continued)
When the sync byte is included in the CRC/ECC calculation,
i.e., the encapsulated mode, controlled by the ECC Control
Register, then it is mandatory that the most significant bit
of the first sync byte be a 1. Hence, the most significant bit
of the sync byte must be a 1.
mented using a combination of software manipulation and
external circuitry, as outlined in the design guide application
note (AN413) in the MASS STORAGE handbook.
8.0 Write Clock with Respect to Write Gate
Proper Sequence for Reset and Renable
In the DDC, Write Clock is generated 0.5 bit times after
Write Gate is asserted. However in case of the SMD and
ESDI drives they expect write clock to be active 250 ns
(worst case) before write gate is asserted. This would have
to be accomplished using external circuitry if desired.
The proper reset sequence for the chip consists of holding
the RESET line active or the reset bit set in the OC register
for 32 RCLKS and 4 BCLKS. Then this is deactivated and
the RENABLE operation is initiated with a 01 in the DC reg-
ister. It is possible, although not necessary for the renable
operation to take as long as 260 RCLKS after which the
operation complete interrupt would be generated. In case
the status register is polled to detect operation completion,
then the status register should be polled for the NDC bit set.
Once set, it should be read after 30 RCLKS. If the NDC bit is
still set then it signals the proper completion of the RENA-
BLE operation.
17.0 Some Helpful Hints, When De-
signing a Disk Controller Subsys-
tem with National Semiconductor’s
DP8466B, Disk Data Controller
(DDC)
Read/Write Registers
The following section provides some useful hints/applica-
tion information for designing with the DP8466B. The sug-
gestions given in this document are the results of situations
encountered while debugging the designs at National and
also from the feedback provided by the numerous beta site
designs during their debug stages. This is an unending list
and users are welcome to add their experiences, for they
may save someone else a lot of trouble in the process. It
should be understood that some of the situations outlined
may be dependent on that particular system design ap-
proach and may not necessarily present itself in a different
system environment. Hence National assumes no guaran-
tees regarding these situations. A lot of the suggestions are
explanations of inherent operational rules that may not be
very evident in the chips documentation. For a detailed
technical reference for design purposes, users are recom-
mended to consult the DP8466 design guide in the MASS
STORAGE handbook, while the DATA SHEET gives the
features and timing specifications of the chip.
In the DDC some of the registers are defined as read only,
while some are defined as write only. Care should be taken
that read only registers should not be written to and write
only registers should not be read from.
Write HeaderÐWrite Data Operation Variations
For the WRITE HEADER-WRITE DATA operation the DDC
will fetch the data for the ID and DATA fields from the on-
chip parameter RAM if the FMT bit is set in the DC register,
(this also constitutes a format operation). The same scener-
io with the FTF bit set in the DISK FORMAT register will
fetch the ID and DATA information from the local buffer
memory by the local DMA channel, and constitutes a full
format operation. If however, the FMT bit is reset then the
information is fetched from the local buffer memory by the
local DMA channel and the operation is a regular one.
Status Reads on Interrupts
The STATUS register is read when an interrupt occurs to
determine its cause and also serves to reset the interrupt
line. However, if the status is read before 16 RCLKS after
the interrupt, then the interrupt line will not be reset by the
status register read. If the STATUS register is being con-
stantly polled in the software, then it must not go faster then
once in 16 RCLKS.
Ý
Ý
Sync 1 and Sync 2 Pattern Restrictions
When the DDC is in the read mode, i.e., read/compare/ig-
nore header/or read/ check data, then it starts out looking
for the sync byte. The data separator usually sends out ze-
roes when it is attempting to lock and when it has, it sends
out the data coming off the disk. Hence the DDC is looking
for the first non-zero bit to initiate sync byte comparison. If
the DDC is programmed in the soft sectored mode then it
basically attempts to do a compare for eight clocks before it
asserts the abort address mark function internally and recy-
cles Read Gate. In the hard sectored mode it will essentially
be waiting for the sync match forever, till two revolutions of
the disk, after which it gives a SNF error. Therefore it is not
LCB Bit Behaviour
Whenever a disk operation is initiated, the LCB bit in the
status register is set until the operation is complete. Howev-
er if the operation is truncated due to any error condition in
the header or the data fields, the LCB bit will remain set in
the status register.
Ý
advisable to use a pattern of zeroes for the sync 1 or sync
2 bytes as that would result in an immediate sync byte
Resetting the DDC
Ý
After a normal reset of the DDC, none of the registers in the
parameter RAM are affected. The STATUS and ERROR
registers are cleared. The internal counters are reset and
the FIFO pointers point to the beginning of the FIFO. There
are, however, two other conditions that need to be taken
into account.
alignment when read gate is asserted, as the serializer has
been cleared to all zeroes. However, when writing informa-
Ý
Ý
tion on the disk the sync 1 and sync 2 fields could be
used to write a pattern of zeroes. This would probably be
the case when some software manipulation is being at-
tempted with the various fields of the DDC to implement
some additional function like the post index gap, etc. Hence,
If the DDC is reset while it is reading, writing, or formatting,
the entire format RAM is potentially corrupted. For this rea-
son, hex addresses 14–33, 38, 39, 3B–3F need to be re-
loaded after such a reset.
Ý
a pattern of zeroes is not recommended for sync 1 and
Ý
sync 2 fields during a READ operation.
51
17.0 Some Helpful Hints, When Designing a Disk Controller Subsystem with
National Semiconductor’s DP8466B, Disk Data Controller (DDC) (Continued)
There is a certain relationship between BCLK and WR that
can cause the DDC to be fooled into thinking it is in a DMA
cycle for 2 BCLKs following a software reset (setting the
reset bit in the Operation Command Register). This is also
true if BCLK and RST have a certain relationship. The impli-
cations of this are that ADS0 will be asserted on the first
BCLK and WR will be asserted on the second. Both will be
cleared by the third. Internally, the following registers may
change:
register. In a similar context it should be noted that even if
the interrupts are not enabled in the OC register, the inter-
rupt condition is generated internally when it happens. This
EN bit in the OC register essentially controls the physical
availability of the interrupt on the pin to the outside world.
Correction Cycle Initiation Sequence
When a CRC/ECC error occurs in a disk operation, the DDC
has to be reset before a correction cycle can be attempted.
On completion of the correction cycle the chip needs to be
reset only if the correction cycle failed and hence an error
condition resulted. In general, the DDC should be reset fol-
lowing any operation terminating in an error condition.
HA
Register
0F
13
1A
1B
1C
1D
1E
1F
38
39
Header Byte Count
NSO Counter
Remote Data Byte Count (L)
Remote Data Byte Count (H)
DMA Address Byte 0
DMA Address Byte 1
DMA Address Byte 2
DMA Address Byte 3
Sector Byte Count (L)
Sector Byte Count (H)
DFE (Data Field Error) Exceptions
Usually the Data Field Error condition in the DDC is terminal
and the operation is aborted with an interrupt. However
there is one exception to the rule. This is if the operation is a
multisector check data operation in the interlock mode, then
the DFE error will set the bit in the ERROR register but will
not generate an interrupt and hence will not terminate the
operation.
Read HeaderÐCheck Data Operation Exception
For this reason all of the above registers should be reloaded
after a reset if it is not known that the timing relationship is
such that the problem will not occur. Additionally, if CS is
active at the time of the false WR, then the register selected
by the RS0–5 signals will be altered. In order to avoid a
problem here, putting a zero on these lines will cause the
write to go to the Status Register which cannot be written
to, so no destructive write will occur.
Normally the operation complete interrupt comes at the end
of the data field for the disk operation. It is usually signified
by the LCB bit reset in the STATUS register in case of non-
tracking mode or by the LCB and RCB bit reset in the track-
ing mode. However there is one exception to the rule. In the
case of a read header-check data operation, because local
DMA transfers only the header and there is no DMA activity
for the data field, the LCB bit is reset just after the header
and the operation complete interrupt is generated. There is
no interrupt at the end of the check data unless there is an
ECC error in which case the operation is terminated with the
error signalled through the STATUS and ERROR registers.
Queing Disk Commands
After header match is successfully accomplished in a disk
operation, also indicated by the header match complete in-
terrupt if enabled, the NDC bit is set in the status register,
indicating that the DDC is ready to accept the next disk
command. Hence the next disk operation could be queued
by a load of the DC register, however, it should be noted
that the operation will not commence until the previous one
has completed. Hence, care should be taken that registers
being used while the data segment of the previous opera-
tion is in progress should not be changed, e.g., the registers
associated with the DMA etc.
Header Fault Exceptional Behaviour
The HF (header fault) bit in the STATUS register is a pas-
sive error condition bit which is set if there is a CRC/ECC
error in the header. This does not generate an interrupt nor
terminate the operation normally. In a normal operation this
bit is set if there is a header fault in the header, while
searching for a sector and its gets reset, only if there is no
CRC/ECC error in the header of the sector being sought. It
should be noted that this behaviour is exhibited even when
the DDC is searching for headers. However there is one
exception to the rule. In case of a Read Header operation, if
there is a CRC/ECC error in the header, then an interrupt is
generated, the operation is terminated and the STATUS
register will have the ED bit and the HF bit set while the
ERROR register will read zeroes.
Assertion/Deassertion of LRQ/RRQ
In the burst DMA mode the request (LRQ/RRQ) is asserted
when the set threshold is reached in the FIFO/LOCAL
BUFFER MEMORY, and deasserted after the set burst is
transferred even if the threshold has been reached again for
the next transfer. The request is then reasserted for the next
transfer.
SC and NSO Counter Updates
Causes of Interrupts
The Number of Sector operations counter (NSO) in the DDC
should be handled with care. Although addressed as one
register, internally it is downloaded into two separate coun-
ters; one for the disk side and the other for the DMA logic.
Whenever a read is done of the NSO counter, the value
read back is the contents of the disk side NSO counter. The
disk side NSO counter is decremented just after the header
match complete interrupt, while the DMA side NSO counter
is decremented while the local DMA channel is transferring
There is only a single interrupt line on the DDC. There may
be more than one source for the interrupt at times. It is
hence recommended that every time an interrupt is serviced
all the possibilities be checked to safeguard against more
than one completion condition occurring at the same time.
HMC Bit in the Status Register
The HMC bit in the STATUS register is functional even if the
header match complete interrupt is not enabled in the OC
52
17.0 Some Helpful Hints, When Designing a Disk Controller Subsystem with
National Semiconductor’s DP8466B, Disk Data Controller (DDC) (Continued)
the last byte of the data field. If the SC and NSO counters
have to be read/written by the microprocessor for some
reason, care should be taken that they are not read/written
when the DDC is accessing them internally, otherwise they
might be zeroed. So it is recommended that they be read or
updated about 1 ms after the HMC bit is set in the STATUS
register. By the same token, this applies to other registers
like the Remote Data Byte Count registers, Sector Byte
Count registers, and DMA address registers. Also if the
NSO counter has to be updated before the operation is
completed to fool the DDC to go on some more without
reloading the command then certain precautions need to be
observed. Firstly the NSO register can be written to only
after the DMA side NSO has been decremented. Secondly,
the update cannot be done after the NSO on the DMA side
has decremented to a 1, in other words the update cannot
be done after the second to last sector, and hence has to
be done at the latest before two sectors remain for the com-
pletion of the current multisector operation.
tially cause a situation leading to the altering of some regis-
ter contents in the parameter RAM. Hence it is the design-
ers responsibility to ensure that there are no possibilities of
a glitch as defined by the specs on the RCLK line to the
DDC and if it does reach the DDC, he should be aware of
what to expect.
The DDC doesn’t tolerate glitches on the RCLK input.
Remote DMA Completion Interrupt
The DMA on board the DDC is controlled by a separate
sequencer. This DMA sequencer is responsible for generat-
ing the DMA completion interrupts and also controlling the
LCB & RCB bits in the STATUS register. It is oblivious to the
disk sequencer, in terms of the errors on the disk etc. How-
ever the interrupt generating mechanism for the remote
DMA uses a clock from the disk PLA for synchronization
purposes. This clock becomes inactive at certain times re-
ferred to as the freeze condition for the disk sequencer. This
happens whenever a command is loaded in the DC register
and the sequencer is waiting for a sync match in a disk read
operation. Hence in the non-tracking mode if the remote
DMA finishes at an instant when the disk sequencer is fro-
zen then the remote DMA completion interrupt is held off till
the next header comes along where the sequencer comes
out of the frozen state and the clock is available. So this is
more apt to happen when the remote DMA is under way
while the disk sequencer is off looking for a header match.
The other instances where the disk sequencer freezes is in
a multisector operation; 1) the time after the header CRC
and before the sync match for the data field occurs; 2) the
time after the data field and just before the sync match of
the header of the next field. Hence, if the remote DMA fin-
ishes around those instances then the completion interrupt
could be delayed. The more serious implication of this situa-
tion is if the remote happened to finish just before the disk
sequencer was entering the freeze mode, than the remote
DMA completion interrupt would be held active till the se-
quencer comes out of the freeze state. Until then all efforts
to service the interrupt by doing a status read will not deacti-
vate the interrupt.
LT and RT Register Loading Restrictions
It is mandatory that the LT (RT) register must be loaded
before the Sector Byte Count (Remote Data Byte) register
pairs for any of the following situations.
a) If any internal DMA is being used or b) if the Remote Data
Byte Count registers are going to be read by the processor,
or c) if one needs to rewrite the LT or RT registers at any-
time, (like when one wants to shift from tracking to non-
tracking mode etc).
DMA Burst Mode Behaviour
One of the features of the DDC is that it can be programmed
to do DMA transfers in the burst mode. The size of the burst
is selectable through the LT & RT registers. Internally the
burst value is downloaded to the burst counter which will
reload itself only when the terminal count is reached or if the
DDC is reset. The size of the DMA transfer is the length of
the sector in case of a single sector transfer while in case of
a multisector operation the DDC looks at it like one big
transfer of length equal to the sector length times the num-
ber of sectors requested for the operation. This value is
divided by the burst length which determines the number of
bursts in the total transfer. If the total transfer length were
not an even multiple of the burst length, then the very last
burst would be less than the burst length selected. Control
logic in the FIFO ensures that the remainder bytes are
transferred even though it is less than the burst threshold.
However, the internal burst counter remains at that lesser
number and does not get reinitialized to the original burst
value at the end of the operation. Hence the length of the
first burst transfer of the next DMA operation may not be the
same as that specified in the LT & RT registers.
Hence the recommendation would be to initiate a remote
operation only after a header match has occurred and to
wait for the remote DMA completion before issuing another
disk command. The other alternative would be to accommo-
date in software to look for such a situation and work
around it. Software polling could be used to determine re-
mote DMA completion and the interrupts from it ignored.
LRQ/RRQ Synchronization and Hold Off
In the DDC, the acknowledge signal in response to a re-
quest is sampled at the T4 state of the DMA transfer cycle.
The chip does not require cycling of the acknowledge signal
with the request from the chip. Also the initial assertion of
the LRQ/RRQ signals is not synchronous to the BCLK.
Glitches on the Read Clock Input
The DDC has a minimum specification for the RCLK high
time (rch) and the RCLK low time (rcl). Any RCLK not within
these specifications is taken as a clock with the glitch. If
such a situation is presented to the DDC then a number of
things happen. This glitch results in throwing the Disk Se-
quencer in an unknown state, away from the standby state.
Hence, in order for the DDC to be able to accept commands
the chip has to be reset and reenabled in order to bring the
sequencer to standby. A glitch on the RCLK can also poten-
Read Gate Algorithm for Harmonic Lock
If the read head was turned on over a write splice, the data
separator may go into harmonic lock, which will prevent it
from detecting the preamble pattern it is looking for. This
forces zeroes data out of the data separator to the DDC and
hence the DDC allows read gate to remain asserted, indefi-
nitely. This is a lock up situation which must be avoided
using external hardware.
53
17.0 Some Helpful Hints, When Designing a Disk Controller Subsystem with
National Semiconductor’s DP8466B, Disk Data Controller (DDC) (Continued)
Write Splice During a Disk Write
Restrictions for the 2 Byte Exact Burst DMA Transfer
Mode
If a genuine FDL error occurs during a disk write function,
the write gate will be deasserted as soon as the FIFO gets
over-read. If this happens in the middle of a sector, it will
result in a write splice to occur.
The two byte exact burst mode was intended to be used for
systems with very fast BCLKS relative to the RCLKS, such
as when using the DDC to write a floppy as back up. The 2
byte exact mode is not needed for quick bus access since
this can always be accomplished by the arbitration logic (in
any burst mode) by deasserting LACK and waiting a mini-
mum of 4 BCLKS. This is a better response than the 2 byte
exact burst mode when waiting for the LRQ to be deassert-
ed.
Read Gate Timing
Usually in most drives, when write gate is asserted, data
actually gets written after 8 RCLKS, because of write driver
delays etc. Hence the exists a write splice. In the DDC for a
write data operation, the write gate is asserted 3 bit times
into the data preamble. The read gate is asserted 8.5 bit
times after the write gate, which is just sufficient to ensure
assertion of read gate beyond the write splice associated
with the write gate assertion. However at the beginning of
the sector, both read and write gate are asserted 2–4 bit
times from the index or sector pulse, hence resulting in the
read gate being asserted in the write splice. External circuit-
ry must be implemented to prevent this from happening.
The performance degradation of the DDC when in the exact
burst mode is due to the following sequence of events.
1. A burst of data is transferred causing the LRQ to go inac-
tive.
2. Because the FIFO is still in a condition which requires
more data to be transferred, the LRQ must be reasserted.
3. This reassertion of LRQ is held off until both the FIFO
address counters match in parity; that is until both coun-
ters are either odd or even. This results in the LRQ being
held off until the disk strobe occurs which in some cases
(see table below) will allow the DMA to transfer only at
the same data rate as the disk.
FIFO Table Format
In the FIFO TABLE format mode the local DMA loads the
correct number of header bytes (given by the HBC register)
per sector into the FIFO from the local buffer memory. This
data is then substituted for the header bytes during a format
operation. It should be noted that each header byte set
must contain an even number of bytes. If it contains an odd
number of bytes, an extra dummy byte must be inserted so
that each header byte set starts at an even byte boundary.
The most exaggerated effect of this problem is when in the
2 byte exact burst mode when the data bus is in the byte
mode. In this mode the following ratios of BCLK to RCLK
must be observed for the corresponding DMA to disk trans-
fer rates.
Two Interrupts in a Read Disk Operation
Byte Mode
In a read disk operation, there is a potential for the control-
ler mP to see two interrupts from the DDC, if a DFE error
occurred during the operation. One of them is due to the
error condition reflecting the DFE error, while the other re-
flects the operation completion by the local DMA, i.e., when
the local DMA has finished transferring the data. Depending
on the local DMA speed and bus latency, this could occur
before or after the DFE interrupt, and they could be within
16 RCLKS or further apart. If the two interrupts are within 16
RCLKS of each other, the mP sees only one interrupts, while
if they occur more than 16 RCLKS apart, then there is a
potential of two interrupts being presented to the controller
mP. This situation should be kept in mind and handled in
firmware accordingly.
BCLK/RCLK
Ratio
Max DMA Transfer Rate
k
l
k
1/1.6 Will not be able to keep up with disk rate,
1/1.6 but will get FDL. Can only transfer at the disk
1/0.6
rate, therefore any bus sharing will result
in depleting the FIFO, with no ability to
refill it.
l
1/0.6
Can transfer at least at 2X the disk rate.
Can easily refill the FIFO if depleted.
Word Mode
k
1/1
Can transfer only at the disk rate.
Depleted FIFO cannot be refilled.
l
1/1
Can transfer at least at 2X the disk rate.
ADS0 Glitch During First DMA Transfer
The ADS0 line is a bidirectional line. Hence when the DMA
transfer is initiated, the ADS0 line changes from an input to
an output. It is released from the input mode into a tristate
condition. When released for the DMA operation, it tends to
touch the high level and goes low when the address needs
to be latched in the t1 cycle of the first DMA transfer. It has
been observed that just prior to that instant due to an inter-
nal race condition it is possible that the ADS0 may momen-
tarily go low in a glitch fashion. This does not really hurt the
system because it will go low at the appropriate time to latch
the correct address in the t1 cycle, however if the trailing
edge of the strobe is monitored to initiate some operation in
a system design, then this could pose a problem. This
needs to be kept in mind while designing.
Lost BCLK Cycles in DMA Burst Mode
During DMA burst mode operation, LRQ or RRQ is deas-
serted for two BCLK cycles between bursts of local or re-
mote DMA, i.e., When a remote burst is followed by another
remote burst, an extra BCLK cycle occurs between t4 of the
prior burst and the t1 of the subsequent burst. Likewise this
is true for a local burst followed by another local burst, with
the exception that here there is a possibility of two dummy
BCLK cycles being inserted between t4 and t1. However, if
a remote burst is followed by a local burst or vice versa, no
dummy BCLK cycles are introduced.
54
18.0 Appendix
18.1 DDC REGISTERS, INDEX BY HEX ADDRESS
The following is a repeat of what can be found in the DDC
INTERNAL REGISTERS Section. This listing is arranged nu-
merically by hex address, and is provided as a quick refer-
ence. The section numbers provided indicate where the
best description for the particular register can be located.
For an explanation of the information contained in the WR
and RD columns, refer to the key in the INTERNAL REGIS-
TERS Section.
COLUMN KEY:
B: Number of bits WR: Write RD: Read SC: Section
Ý
HA: Hex Address
Ý
Ý
B WR RD SC
HA
REGISTER
B WR RD SC
HA
REGISTER
00 Status Register (S)
8
NO
NO
NO
D
R
R
R
3.1
3.1
3.4
1D DMA Address Byte 1
1E DMA Address Byte 2
1F DMA Address Byte 3
20 Data Postamble Byte Count
21 ID Preamble Byte Count
8
C
C
C
D
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
F
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
3.2
3.2
3.2
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
01 Error Register (E)
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
8
8
8
8
8
8
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
02 ECC SR Out 0
02 Polynomial Preset Byte 0 (PPB0)
03 ECC SR Out 1
NO 3.4
3.4
NO 3.4
3.4
NO 3.4
3.4
NO 3.4
3.4
NO 3.4
3.4
NO 3.4
3.4
NO 3.4
3.4
NO
D
R
Ý
22 ID Sync 1 (AM) Byte Count
Ý
23 ID Sync Byte 2 Count
03 Polynomial Preset Byte 1 (PPB1)
04 ECC SR Out 2
NO
D
R
04 Polynomial Preset Byte 2 (PPB2)
05 ECC SR Out 3
24 Header Byte 0 Control
25 Header Byte 1 Control
26 Header Byte 2 Control
27 Header Byte 3 Control
28 Header Byte 4 Control
29 Header Byte 5 Control
2A Data External ECC Byte Count
2B ID External ECC Byte Count
2C ID Postamble Byte Count
2D Data Preamble Byte Count
NO
D
R
05 Polynomial Preset Byte 3 (PPB3)
06 ECC SR Out 4
NO
D
R
06 Polynomial Preset Byte 4 (PPB4)
07 ECC SR Out 5
NO
D
R
07 Polynomial Preset Byte 5 (PPB5)
08 Data Byte Count (0)
NO
D
R
08 Polynomial Tap Byte 0 (PTB0)
09 Data Byte Count (1)
NO
D
R
Ý
2E Data Sync 1 (AM) Byte Count
Ý
2F Data Sync 2 Byte Count
09 Polynomial Tap Byte 1 (PTB1)
0A Polynomial Tap Byte 2 (PTB2)
0B Polynomial Tap Byte 3 (PTB3)
0C Polynomial Tap Byte 4 (PTB4)
0D Polynomial Tap Byte 5 (PTB5)
0E ECC CONTROL (EC)
NO 3.4
NO 3.4
NO 3.4
NO 3.4
NO 3.4
NO 3.4
D
D
30 Data Postamble Pattern
31 ID Preamble Pattern
D
Ý
32 ID Sync 1 (AM) Pattern
Ý
33 ID Sync 2 Pattern
D
D
0F Header Byte Count (HBC)/Interlock
10 Drive Command Register (DC)
11 Operation Command Register (OC)
12 Sector Counter (SC)
F
R
3.1
34 Gap Byte Count
C
NO 3.1
NO 3.1
35 Disk Format Register (DF)
36 Header Diagnostic Readback (HDR)
36 Local Transfer Register
37 DMA Sector Counter (DSC)
37 Remote Transfer Register
38 Sector Byte Count 0
D
NO
I
NO 3.1
3.1
NO 3.2
3.2
NO 3.2
C
R
C
R
R
3.1
3.1
13 Number of Sector Operations
Counter (NSO)
C
NO
I
R
14 Header Byte 0 Pattern
15 Header Byte 1 Pattern
16 Header Byte 2 Pattern
17 Header Byte 3 Pattern
18 Header Byte 4 Pattern
19 Header Byte 5 Pattern
1A Remote Data Byte Byte Count (L)
1B Remote Data Byte Byte Count (H)
1C DMA Address Byte 0
8
8
8
8
8
8
8
8
8
C
C
C
C
C
C
C
C
C
R
R
R
R
R
R
R
R
R
3.3
3.3
3.3
3.3
3.3
3.3
3.2
3.2
3.2
D
D
F
R
R
R
R
R
R
R
R
3.2
3.2
3.3
3.3
3.3
3.3
3.3
3.3
39 Sector Byte Count 1
3A Gap Pattern
3B Data Format Pattern
3C ID Postamble Pattern
3D Data Preamble Pattern
F
D
D
D
D
Ý
3E Data Sync 1 (AM) Pattern
Ý
3F Data Sync 2 Pattern
55
18.0 Appendix (Continued)
LBL1, 2 Local Burst Length (bits in LT register)
3.2
3.1
3.1
2.0
18.2 ALPHABETICAL MNEMONIC
GLOSSARY AND INDEX
LCB
LI
LPRE
Local Command Busy (bit in Status register)
Late Interlock (bit in Error register)
Late Precompensation
Listed on the following pages are the majority of the abbre-
viations used within this data sheet as mnemonics to de-
scribe portions or functions of the DDC. The section num-
bers referenced indicate where the terms are first defined.
Mnemonics from the specifications section are not included
here.
(attached to AME, pin 13)
Local DMA Request (pin 36)
Local Request (bit in Status register)
LRQ
LRQ
2.0
3.1
3.2
3.2
LSRW Local Slow Read/Write (bit in LT register)
Local Transfer register
LT
LTEB
LWDT Local Word Data Transfer (bit in LT register)
Local Transfer Exact Burst (bit in LT register) 3.2
MNEMONIC DESCRIPTION SECTION
3.2
3.1
3.1
AD0–7 Address/Data 0–7 (pins 41–48)
AD8–15 Address/Data 8–15 (pins 1–8)
2.0
2.0
2.0
2.0
MFM
MSO
MFM Encode (bit in DF register)
Multi-Sector Operation
(command in DC register)
ADS0
ADS1
Address Strobe 0 (pin 9)
Address Strobe 1
NCP
NDC
NDS
NSO
OC
Not Compare (bit in HC0–5 registers)
Next Disk Command (bit in Status register)
No Data Synch (bit in Error register)
Number of Sector Operations counter
Operation Command register
3.3
3.1
3.1
3.1
3.1
3.4
3.4
2.0
3.2
3.2
(attached to RRQ, pin 37)
Address Mark Enable
(attached to LPRE, pin 13)
Address Mark Found
AME
AMF
2.0
2.0
(attached to EPRE, pin 16)
Bus Clock (pin 40)
Correction Cycle Active
(bit in Status register)
PPB0–5 Polynomial Preset Byte 0–5
PTB0–5 Polynomial Tap Byte 0–5
RACK Remote DMA Acknowledge (pin 38)
RBL1, 2 Remote Burst Length (bits in RT register)
BCLK
CCA
2.0
3.1
CF
CS
Correction Failed (bit in Error register)
Chip Select (pin 28)
3.1
2.0
3.4
RBO
RCB
RCLK
RD
Reverse Byte Order (bit in LT register)
Remote Command Busy (bit in Status register) 3.1
Read Clock (pin 25)
Read (pin 11)
CS0–3 Correction Span Selection
(bits in EC register)
2.0
2.0
2.0
3.1
3.2
2.0
DC
Drive Command register
3.1
3.4
3.2
3.1
3.1
RDATA Read Data (pin 15)
RED
RES
DNE
DF
DFE
Data Non-Encapsulation (bit in EC register)
Disk Format register
Data Field Error (bit in Error register)
Re-Enable DDC (command in DC register)
Reset DDC (bit OC register)
RGATE Read Gate (pin 19)
RRQ
RS0–5 Register Select 0–5 (pins 30–35)
RSRW Remote Slow Read/Write (bit in RT register) 3.2
D01, 2 Data Operation bits
(command in DC register)
Remote Request (attached to ADS1, pin 37) 2.0
2.0
DSC
E
EC
ED
EEF
EEW
EHF
DMA Sector Counter
Error register
ECC Control register
Error Detected (bit in Status register)
External ECC Field (pin 26)
Enable External Wait (bit in RT register)
Enable HFASM Function
3.2
3.1
3.4
3.1
2.0
3.2
3.3
RT
RTEB
Remote Transfer register
Remote Transfer Exact Burst
(bit in RT register)
3.2
3.2
RWDT Remote Word Data Transfer
(bit in RT register)
3.2
S
SAIS
Status register
Start At Index or Sector
(command in DC register)
3.1
3.1
(bit in HC0–5 registers)
Enable Header Interrupts
EHI
3.1
(command in OC register)
FIFO Table Format (bit in DF register)
Header Byte Active (bit in HC0–5 registers)
Header Byte Count register
SAM
SC
SCC
Start at Address Mark (bit in DF register)
Sector Counter
Start Correction Cycle
3.1
3.1
3.1
FTF
HBA
HBC
3.1
3.3
3.1
3.3
3.1
(command in OC register)
Serial Data Valid (pin 27)
Select Local DMA (bit in LT register)
Sector Not Found (bit in Error register)
Sector Overrun (bit in Error register)
Select Remote DMA (bit in RT register)
HC0–5 Header Byte 0–5 Control registers
SDV
SLD
SNF
SO
SRD
SRI
SRO
2.0
3.2
3.1
3.1
3.2
HDR
HNE
HF
Header Diagnostic Readback register
Header Non-Encapsulation (bit in EC register) 3.4
3.1
Header Fault (bit in Status register)
HFASM Header Failed Although Sector
number Matched (bit in Error register)
2.0
3.1
Start Remote Input (command in OC register) 3.1
Start Remote Output
HMC
Header Match Completed
(bit in Status register)
3.1
3.3
(command in OC register)
Substitute Sector Counter
(bit in HC0–5 registers)
H01, 2 Header Operation bits
(command in DC register)
3.1
SSC
HSS
ID1, 2
IDI
Hard or Soft Sectored (bit in DF register)
3.1
Internal Data Appendage (bits in DF register) 3.1
TM
Tracking Mode (bit in RT register)
3.2
2.0
2.0
2.0
2.0
WCLK Write Clock (pin 21)
WDATA Write Data (pin 18)
WGATE Write Gate (pin 20)
Invert Data In (bit in EC register)
Internal Header Appendage
(bits in DF register)
3.4
3.1
IH1, 2
WR
Write (pin 10)
INT
LA
LACK
Interrupt (pin 29)
Long Address (bit in LT register)
Local DMA Acknowledge (pin 39)
2.0
3.2
2.0
56
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Pkg (N)
Order Number DP8466BN
NS Package Number N48A
57
Ý
Lit. 103066
Physical Dimensions inches (millimeters) (Continued)
Plastic Chip Carrier (V)
Order Number DP8466BV
NS Package Number V68A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
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Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
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Email: cnjwge tevm2.nsc.com
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Fran3ais Tel:
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(
49) 0-180-530 85 85
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