DP84605R [ETC]
;
| 型号： | DP84605R |
| 厂家： | 
ETC |
| 描述： |
|
| 文件： | 总10页 (文件大小：132K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
April 1994
DP84600R/DP84605R
Thin-Film/MIG Head Read/Write Preamplifier
General Description
Features
Y
Low input capacitance: 12 pF typical
The DP84600R/DP84605R are 5V, high performance, four
channel, low power, read preamplifiers/write current drivers
designed for two-terminal recording head applications. An
idle mode is available which conserves power to a level of
0.5 mW (typically) when activated. Power supply fault pro-
tection is included to disable the write current generator
whenever the supply voltage is below 4V. Both parts incor-
porate 300X write damping.
Y
Y
Y
Y
Y
Y
Y
Y
Low input noise: 0.49 nV/ Hz typical
0
Low power: 100 mW typical in read mode
Very low idle power: 0.5 mW typical
Programmable write current source (1 mA–40 mA)
Low power supply protection in write mode
Head short to ground protection
Plug compatible to VTC VM7204/7104/7114
Single 5V power supply
The DP84600R has a read gain of 300 versus 200 for the
DP84605R.
Upon request, other options such as other read gains, PECL
inputs, no damping, and different packaging are available.
Block Diagram
TL/F/11990–1
FIGURE 1. Circuit Block Diagram
This Preliminary document contains information on a product under development. Specifications contained within are based
on design targets or a limited amount of data and are subject to change without notice. National Semiconductor reserves the
right to change or discontinue this product without notice.
C
1995 National Semiconductor Corporation
TL/F/11990
RRD-B30M105/Printed in U. S. A.
TABLE I. Pin Descriptions
Pin Function Description
Pin Name
Pin Type
Power Supply
Input (TTL)
g
Power supply Pin (5V 10%). These pins (10 and 13) are internally shorted.
V
CC
WDI
Each negative transition on WDI toggles the head current between the X and Y head
connections.
HS0, HS1
R/W
Input (TTL)
Input (TTL)
Logic levels are applied to these pins to select 1 of 4 heads (see Table II).
A logic high level selects the read mode while a low logic level selects the write mode. The CS pin
must be at a low logic level for this operation to be active (see Table III).
CS
Input (TTL)
Outputs
A high logic level disables the operation of the device and puts the read data outputs (RDX, RDY)
into a high impedance state.
H0X, H0Y
through
H3X, H3Y
X and Y connections to the read/write heads.
WUS
Output
A logic high level at this pin indicates that one of several conditions has been detected by internal
circuitry which makes writing unsafe.
RDX, RDY
WC
Output
Output
Differential read data outputs.
A resistor is connected from this pin to ground to control the magnitude of the write current (see
formula in Write Mode description).
GND
Ground
Device ground.
The selection of device mode (write, read or idle) is also
Connection Diagram
controlled by two pins, CHIP SELECT (CS) and READ/
WRITE (R/W). Table III defines the results of each combi-
nation of these two pins. These pins have internal pull-up
resistors so that the idle condition is selected if an open
condition exists on these pins.
TABLE III. Mode Selection
CS
0
R/W
Mode Selected
0
1
0
1
Write
Read
Idle
0
1
1
Idle
TL/F/11990–2
Write Mode
Order Number DP84600R or DP84605R
See NS Package Number M20B or MSA20
The write mode is entered by setting both CS and R/W to
logical low values. In the write mode, the device acts as a
current switch which toggles between the X and Y sides of
the selected head on each high-to-low logic level transition
of the WRITE DATA INPUT (WDI). When entering the write
mode from the read mode, the write data flip-flop is initial-
ized to pass current into the X side of the selected head.
The magnitude of the write current is set by an external
FIGURE 2. Connection Diagram
Basic Circuit Operation
The DP84600R/DP84605R can address up to four two-ter-
minal thin-film heads, providing the write current drive in the
write mode or read data amplification in the read mode.
resistor,
R
connected between the WC pin and
WRITE
Head selection is controlled by the logic states on two pins,
HEAD SELECT 0 (HS0) and HEAD SELECT 1 (HS1). Table
II defines the results of each combination of these two pins.
These pins have internal pull-down current so that head 0 is
selected if an open condition exists on these pins.
ground. The relationship between the write current and the
write resistor is:
V
WC
e
c
I
A
WC
WRITE
R
WRITE
TABLE II. Head Selection
where A
is the current gain (see Write Mode DC Electri-
WC
cal Characteristics Table).
HS1
HS0
Head Selected
0
0
1
1
0
1
0
1
0
1
2
3
2
Write Mode (Continued)
The portion of the write current that passes through the
head (I ) is defined as:
h
Read Mode
The read mode is entered by setting CS to a low logic level
and R/W to a high logic level. In this mode the write current
generator is disabled and a low noise differential amplifier is
enabled. The amplified head read-back signal is available at
the RDX and RDY pins. These outputs are differential emit-
ter-followers and should be AC coupled to the load.
I
WRITE
e
I
h
a
1
R /R
h d
e
e
where: R
the sum of the head and external wire resist-
ance
the damping resistance (if any).
h
During the write or idle modes, the read amplifier is disabled
and the RDX, RDY outputs are forced to a high impedance
state. This allows these outputs to be wire-ORed with out-
puts from other devices to support multiple read/write appli-
cations.
and R
d
d
e %
R
for no damping.
When entering the write mode, the write unsafe detector
circuitry is enabled. This circuit issues a high level output at
the WRITE UNSAFE (WUS) output when any of the follow-
ing conditions exist:
Idle Mode
1) Write data input frequency is too low.
2) The device is in the read mode.
3) The chip is disabled.
The idle mode is entered by applying a logical high level to
the CS pin. In this mode the RDX and RDY outputs are in a
high impedance state and the device is disabled. This will
reduce the power consumption to a mimmum value when
the device is not needed, which is particulariy important for
battery applications
4) No write current exists.
5) The head is an open circuit.
The WUS pin is an open-collector output and requires an
external pull-up resistor. After the fault condition has been
removed, two negative transitions of the WDI pin are re-
quired to clear the write unsafe circuitry.
A power supply fault detection circuit is provided on chip.
This circuit will disable the write current generator during
device power-up, power-down or when a power supply fault
occurs. This will prevent the possibility of writing bad data
onto the media.
3
Absolute Maximum Ratings Operation beyond these limits may permanently damage the device.
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Maximum Output Write Current
ESD Susceptibility (Note 1)
Storage Temperature Range
60 mA
2000V
b
a
65 C to 150 C
§
§
Supply Voltage (V
)
7V
0.3)V
0.3)V
CC
Note 1: Human body model is used. (120 pF through 1.5 kX)
b
b
a
a
Digital Input Voltage
Maximum Head Port Voltage
0.3V to (V
0.3V to (V
CC
Recommended Operating
Conditions
CC
b
Maximum Output Current (RDX, RDY)
10 mA
Min
4.5
Typ
5
Max
5.5
Units
V
Supply Voltage (V
)
CC
Operating Free Air
Temperature Range (T )
0
70
C
§
A
General DC Electrical Characteristics
Guaranteed over recommended operating free air temperature and supply voltage range unless otherwise specified.
Typ
Symbol
Parameter
Supply Current
(Read Mode)
Conditions
Min
Max
Units
mA
Test
(Note 1)
e
e
e
e
e
e
e
I
I
I
CS
CS
CS
CS
CS
CS
L, R/W
H
CCR
CCW
CCI
20
28
Note A
Note A
Note A
Note A
Note A
Note A
e
Supply Current
(Write Mode)
R/W
H
L
a
a
1.1 (1
20
1.1 (I
)
27
)
W
mA
W
Supply Current
(Idle Mode)
0.1
0.27
154
mA
e
e
PD
R
PD
W
PD
I
Power Dissipation
(Read Mode)
L, R/W
L, R/W
H
H
L
100
mW
mW
mW
Power Dissipation
(Write Mode)
a
a
6 (I
100
5.5 (I
)
W
150
)
W
Power Dissipation
(Idle Mode)
0.5
1.5
a
V
V
TTL Input High Voltage
TTL Input Low Voltage
TTL Input High Current
TTL Input Low Current
2
V
CC
0.3
V
V
Note A
Note A
Note A
Note A
IH(TTL)
IL(TTL)
IH(TTL)
IL(TTL)
b
0.3
100
100
0.8
100
100
b
b
I
I
mA
mA
Note 1: Typical values are specified at 25 C and 5V supply.
§
Note A: This parameter is guaranteed by outgoing testing.
4
DC and AC Electrical CharacteristicsÐRead Mode Guaranteed over recommended operating
k
e
conditions (see table) unless otherwise specified. Read characteristics: C
20 pF, R
1 kX
L(RDX, RDY)
L(RDX, RDY)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
Test
(Note 1)
@
e
IN
A
Differential Voltage Gain
(Note 2)
V
1 mV
PP
1 MHz
V
V
N
25
300
350
V/V
V/V
Note A
Note A
DP84600R Only
@
1 MHz
e
A
Differential Voltage Gain
V
1 mV
PP
IN
DP84605R Only
160
200
240
e
e
e
e
R 0
h
V
I
Input Noise Voltage
Input Noise Current
BW
15 MHz, L
0.49
3
0.65
nV/ Hz
0
Note B
Note B
h
pA/ Hz
0
N
e
5 MHz
C
Differential Input
Capacitance
V
IN
1 mV , f
PP
I
12
1250
6
17
pF
Note B
Note A
Note A
Note A
Note B
Note A
Note A
e
e
e
1 mV
PP
R
Differential Input Resistance
f
f
5 MHz, V
IN
720
4
X
I
V
Input Voltage Dynamic
Range
5 MHz, (Note 3)
IRANGE
mV
PP
b
V
Output Offset Voltage
150
150
40
mV
O(OFF)
e
R
Single Ended Output
Resistance
f
5 MHz
O(SE)
X
mA
V
I
Output Current
AC Coupled Load, RDX to RDY
1.5
2
2
OUT
V
O(CM)
Common Mode Output
Voltage at RDX, RDY Pins
b
V
2.4
3.5
CC
k
k
b
Voltage Bandwidth 1 dB
e
e
BW
BW
V
V
V
1 mV , Z
PP SOURCE
5X
5X
40
80
60
MHz
MHz
Note B
Note B
1dB
IN
b
Voltage Bandwidth 3 dB
1 mV , Z
PP SOURCE
100
90
3dB
IN
@
e
CMMR
PSRR
CSRR
Common Mode Rejection
Ratio
100 mV
,
5 MHz
CM
PP
60
dB
Note A
@
5 MHz
e
Power Supply Rejection
Ratio
DV
100 mV
,
CC
PP
60
50
90
60
dB
dB
Note A
Note A
Channel Separation
Unselected Channel 100 mV
PP
Note 1: Typical values are specified at 25 C and 5V supply.
§
Note 2: Various gain options exist from 160 to 300. See order information.
Note 3: The dynamic input voltage range limit is defined as the point where the gain falls to 90% of its small signal gain value.
Note A: This parameter is guaranteed by outgoing testing.
Note B: The limit values have been determined by characterization data. No outgoing tests are performed.
5
DC Electrical CharacteristicsÐWrite Mode Guaranteed over recommended operating conditions
e
e
e
1 mH, R 30X
h
(see table) unless otherwise specified. Write characteristics: I
20 mA, L
W
h
Typ
Symbol
Parameter
Conditions
Min
Max
Units
Test
(Note 1)
e
e
c
K
Write Current Constant
K
A
V
WC
46
50
54
V
Note A
Note A
W
W
WC
A
WC
I
to I
HEAD
Current Gain
R
H
40X
18.4
20
21.6
mA
WC
e
H
e
I
Write Current Matching
I
20 mA, R
40X
HM
H
b
a
10
2.3
10
2.7
%
V
Note A
(Note 2)
k
k
40 mA
V
V
Write Current Pin Voltage
Differential Head Voltage Swing
Unselected Head Current
Damping Resistance
1 mA
I
2.5
6.5
Note A
Note A
Note A
Note A
Note A
Note A
Note A
WC
W
e
Open Head, I
20 mA
5
V
PP
H
W
e
I
H
I
20 mA
100
mA
X
H(NS)
R
Write Only
300
DAMP
I
Head Write Current Range
1
40
4.2
0.5
mA
V
H
k
I
W
V
V
V
CC
Shut-Off Voltage
0.2 mA
3.6
CCF
e
I
OL
WUS Low Output Voltage
4 mA
V
OL(WUS)
LK(WUS)
e
V
CC
I
WUS High Level Output Leakage
Current
V
OH
100
15
mA
Note A
Note B
C
Differential Head Load
Capacitance
D
pF
e
f
t
t
WDI Transition Frequency
WDI Pulse Width (High)
WDI Pulse Width (Low)
For WUS
low
1
5
5
MHz
ns
Note A
Note B
Note B
W
PWH(WD)
PWL(WD)
ns
Note 1: Typical values are specified at 25 C and 5V supply.
§
Note 2: Write curent matching applies between any two heads.
Note A: This parameter is guaranteed by outgoing testing.
Note B: The limit values have been determined by characterization data. No outgoing tests are performed.
6
AC Electrical Characteristics
Guaranteed over recommended operating conditions (see table) unless otherwise specified. I
e
e
e
1 mH, R
h
20 mA, L
W
h
e
40X and f(data)
5 MHz unless otherwise specified.
Typ
(Note 1)
Symbol
Parameter
Conditions
Min
Max
Units
Test
td
td
td
td
Time Delay Switching from Read
to Write Modes
R/W Transition to 90% of Write
l
RW
0.35
2
ms
ms
ms
Note A
Note A
Note A
Current. I
5 mA
W
Time Delay Switching from Read
to Write Modes
R/W Transition to 90% I
k
5 mA
.
WRITE
RWL
WR
k
1 mA
I
W
Time Delay Switching from Write
to Read Modes
R/W Transition to 90% of
100 mV Read Signal Envelope
1
Time Delay Switching from Idle
to Either Read or Write Modes
CS Negative Transition to
SELECT
90% I or 90% of 100 mV,
WRITE
10 MHz Signal Envelope
0.6
ms
Note A
td
td
td
td
td
Time Delay Switching from Either
Read or Write to Idle Mode
IDLE
0.6
0.6
3.6
1
ms
ms
ms
ms
Note A
Note A
Note A
Note A
Time Delay Switching from One
Head to Another
HS0/HS1 to 90% of 100 mV,
10 MHz Read Signal Envelope
HEAD
UNSAFE
SAFE
HDI
Time Delay from a Write Safe to a
Write Unsafe Condition
WDI Negative Transition to
WUS Positive Transition
1
Time Delay from Write Unsafe to
Write Safe Condition
WDI Negative Transition to
WUS Negative Transition
Time Delay from WDI to a
Current Direction Change in a
Head Output
Measurements Made from 50%
e
40
e
Points. L
0, R
10
20
0.5
6
ns
ns
ns
Note A
Note B
Note B
h
h
e
0,
ASY
Head Current Asymmetry
WDI has 1 ns t Times. L
r/f
HD
h
e
R
40
h
t
Head Current Rise and Fall
Times
Measurements Made from 10%
e
r/f(HD)
to 90% Points. L
e
0,
h
R
40
h
t
Head Current Rise and Fall
Times
Measurements Made from 10%
r/f(loaded)
e
to 90% Points. L
1 mH,
e
20 mA
10
16
ns
Note B
h
e
R
40X, I
W
h
Note 1: Typical values are specified at 25 C and 5V supply.
§
Note A: This parameter is guaranteed by outgoing testing.
Note B: The limit values have been determined by characterization data. No outgoing tests are performed.
Ordering Information
DP 846 XY
R
ZW-
N
I
Manufacturer’s ID
Product Prefix
Mirror Image
Number of Channels
e
e
N
N
2
4
Preamplifier Part Number
e
e
e
e
e
X
X
X
X
Y
e
Y
0 5V Conventional Preamp.
3 3V–5V, Conventional Preamp.
4 3V–5V, Multi-Write Preamp.
5 5V, Multi-Write Preamp.
0 Read Gain of 300
Package Information
e
M
MS
Plastic Small Outline
Shrink Small Outline
e
e
e
R
Blank
Internal Damping Resistor
No Internal Damping Resistor
Y
0–3 Read Gain of 300
e
5 Read Gain of 200
7
8
Physical Dimensions inches (millimeters)
Order Number DP84600R or DP84605R
NS Package Number M20B
9
Physical Dimensions inches (millimeters) (Continued)
Order Number DP84600R or DP84605R
NS Package Number MSA20
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
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Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
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Tel: 1(800) 272-9959
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Fax:
(
49) 0-180-530 85 86
@
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a
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(
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