DP3S1MX32PY5-10CI [ETC]
x32 SRAM Module ; X32 SRAM模块\n
| 型号： | DP3S1MX32PY5-10CI |
| 厂家： | 
ETC |
| 描述： | x32 SRAM Module
|
| 文件： | 总6页 (文件大小：511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2Mx8/1Mx16/512Kx32, 12 - 20ns, Surface Mount
30A244-00
A
32 Megabit CMOS SRAM
DP3S1MX32PY5
ADVANCED INFORMATION
PIN-OUT DIAGRAM
DESCRIPTION:
The DP3S1MX32PY5 is a 1M x 32 SRAM module
that utilizes the new and innovative space saving
TSO P stacking technology. The module is
constructed of two 1M x 16 SRAM’s that are
configured as a 1M x 32.
The DP3S1MX32PY5 module features high speed
access times with common data inputs and outputs.
FEATURES:
•
•
•
•
Organizations Available: 1M x 32
Access Times: 10*, 12, 15, 20ns
3.3 ± 0.3** Volt Power Requirement
Fully Static Operation - No clock or refresh
required
•
•
TTL-compatible Inputs and Outputs
80-Pin Surface Mount LP-Stack ™
PIN NAMES
A0 - A19
I/O0 - I/O31
CS
Address Inputs
Data Input/Output
Stack Enable
WE
Write Enable
OE
Output Enable
FUNCTIONAL BLOCK DIAGRAM
BS0
Byte Select I/O0 - I/O7
Byte Select I/O8 - I/O15
Byte Select I/O16 - I/O23
Byte Select I/O24 - I/O31
Power (+ 3.3V)
BS1
BS2
BS3
VDD
VSS
Ground
NU.
Not Usable
* 0°-70° only.
** 5% for 10ns only.
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to
change or discontinue information on this product without prior notice.
30A244-00
REV. A
1
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Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED INFORMATION
RECOMMENDED OPERATING RANGE 4
Symbol
Characteristic
Min.
3.135
3.0
Typ.
3.3
3.3
Max.
3.465
3.6
Unit
V
10ns
12, 15, 20ns
VDD
Supply Voltage
V
V
IL
Input HIGH Voltage
Input LOW Voltage
2.0
VDD+ 0.33
0.8
V
V
IH
-0.32
0
C
CI
+ 25
+ 25
+ 70
+ 85
Operating Temperature
oC
TA
-40
5
AC TEST CONDITIONS
Input Pulse Levels
CAPACITANCE : TA = 25°C, F = 1.0MHz
0V to 3.0V
2ns
1.5V
Symbol
Parameter
Max. Unit Condition
Input Pulse Rise and Fall Times
Input and Output Timing Reference Levels
CADR Address Input
20
20
15
20
20
15
CCE
CBS
Chip Enable
Byte Select
pF
V
2 = 0V
IN
CWE Write Enable
COE
CI/O
Output Enable
Data Input/Output
OUTPUT LOAD
Load
CL
Parameters Measured
1
2
30pF
5pF
except tLZ, tHZ, tOHZ, tOLZ, and tWHZ
tLZ, tHZ, tOHZ, tOLZ, and tWHZ
DC OUTPUT CHARACTERISTICS
Symbol
VOH
VOL
Parameter
HIGH Voltage
LOW Voltage
Conditions Min. Max. Unit
IOH= -2mA 2.4
IOL= + 2mA
V
V
0.4
+ 3.3V
Figure 1. Output Load
** Including Probe and Jig Capacitance.
ABSOLUTE MAXIMUM RATINGS 4
1200W
780W
Symbol
TSTC
TBIAS
VDD
Parameter
Value
Unit
°C
°C
V
Storage Temperature
Temperature Under Bias
-55 to + 125
-55 to + 125
-0.5 to + 4.6
-0.5 to + 4.6
DOUT
CL**
1
Supply Voltage
1
VI/O
Input/Output Voltage
V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol
Characteristics
Test Conditions
Unit
Min.
Max.
Input
IIN
VIN = 0V to VDD, VDD = max.
-2
+ 2
mA
mA
Leakage Current
Output
Leakage Current
Dynamic
Operating Current
Full Standby Supply
Current (CMOS)
VI/O = 0V to VDD
,
IOUT
ICC
-1
+ 1
900
8
VDD = max., CE = V
IH
CE = V , VDD = max.
IL
mA
mA
IOUT = 0mA, f = f max.
f = 0, V ³ VDD -0.2V or
IN
ISB1
VIN £ VSS + 0.2V, CE ³ VDD -0.2V
ISB2
VOL
VOH
Standby Current (TTL)
Output Low Voltage
Output High Voltage
CE = V , f = f max.
IOUT = + 2.0mA
IOUT = -2.0mA
210
0.4
mA
V
V
IH
2.4
30A244-00
REV. A
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Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED INFORMATION
TRUTH TABLE
I/O0- I/O8- I/O16- I/O24- Supply
Mode
CS
OE
WE
BS0
BS1
BS2
BS3
I/O7
I/O15 I/O23 I/O31 Current
L
H
L
L
L
L
H
L
L
L
X
H
X
L
L
H
L
L
L
L
H
L
L
X
H
X
L
L
L
H
L
L
L
L
H
L
X
H
X
L
L
L
L
H
L
L
L
L
H
X
H
X
DOUT DOUT DOUT DOUT
High-Z DOUT DOUT DOUT
DOUT High-Z DOUT DOUT
DOUT DOUT High-Z DOUT
DOUT DOUT DOUT High-Z
Read
L
L
H
Active
DIN
High-Z
DIN
DIN
DIN
DIN
DIN
High-Z
DIN
DIN
DIN
DIN
DIN
High-Z
DIN
DIN
DIN
DIN
DIN
High-Z
Active
Active
Write
L
X
L
L
L
H
H
X
X
H
X
X
High-Z High-Z High-Z High-Z
High-Z High-Z High-Z High-Z
High-Z High-Z High-Z High-Z Standby
Output Data
Standby
H = HIGH
L = LOW
X = Don’t Care
Over operating ranges
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE:
10ns 12ns
15ns
20ns
No. Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
1
2
3
4
5
6
7
8
9
tRC
tAA
tCO
tOE
tBA
tLZ
tOLZ
tBLZ
tHZ
Read Cycle Time
Address Access Time
CE to Output Valid
Output Enable to Output Valid
Byte Enable Access Time
10
12
15
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
5
12
12
6
15
15
8
20
20
9
5
6
8
9
CE to Output in LOW-Z 5, 6
Output Enable to Output in LOW-Z 5, 6
Byte Enable to Output in LOW-Z
CE to Output in HIGH-Z 5, 6
Output Enable to Output in HIGH-Z 5, 6
Byte Enable to Output in HIGH-Z
Output Hold from Address Change
3
1
1
3
1
1
3
1
1
3
1
1
6
6
6
7
7
7
8
8
8
9
9
9
10 tOHZ
11
12
tBHZ
tOH
3
3
3
3
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 7, 8: Over operating ranges
10ns
12ns
15ns
20ns
No. Symbol
Parameter
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
13
14
15
16
17
18
19
20
21
22
23
tWC
tAW
tCW
tBW
tAS
Write Cycle Time
10
8.5
8.5
8.5
0
12
9
9
9
0
15
11
11
11
0
20
15
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Byte Enable to End of Write
Address Set-Up Time *
tWP
tWR
tWHZ
tDW
tDH
tOW
Write Pulse Width (OE High)
Write Recovery Time, CE, WE
Write Enable to Output in HIGH-Z 5, 6
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
7
0
8
0
10
0
12
0
6
7
8
10
6
0
1
7
0
1
8
0
1
10
0
1
* Valid for both Read and Write Cycles.
30A244-00
REV. A
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Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED INFORMATION
READ CYCLE
ADDRESS
CE
OE
BS0 - BS3
DATA OUT
WRITE CYCLE 1: WE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
30A244-00
REV. A
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Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED INFORMATION
WRITE CYCLE 2: CE Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
WRITE CYCLE 3: UB, LB Controlled.
ADDRESS
WE
CE
BS0 - BS3
DATA IN
DATA OUT
30A244-00
REV. A
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Dense-Pac Microsystems, Inc.
DP3S1MX32PY5
ADVANCED INFORMATION
ORDERING INFORMATION
NOTES:
1. All voltages are with respect to V .
5. This parameter is guaranteed and not 100% tested.
SS
2.
3.
6.
-1.5V min. (Pulse Width £ 4ns) for I £ 20mA.
IH (max.)= VDD+ 1.5Vdc (Pulse Width£ 4ns) for I£ 20mA.
Transition is measured at the point of ±500mV from steady
state voltage.
V
7. When OE and CE are LOW and WE is HIGH, I/O pins are in
the output state,and input signals of opposite phase to the
outputs must not be applied.
4. Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
7. The outputs are in a high impedance state when WE is
LOW.
9. Chip Enable and Write Enable can initiate and terminate
WRITE Cycle.
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way, Garden Grove, California 92841-1431
(800) 642-4477 FAX: (714) 897-1772 http://www.dense-pac.com
(714) 898-0007
u
u
u
30A244-00
REV. A
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