DO-DI-10GEMAC [ETC]
Controller Miscellaneous - Datasheet Reference ; 控制器杂项 - 数据表参考\n
| 型号： | DO-DI-10GEMAC |
| 厂家： | 
ETC |
| 描述： | Controller Miscellaneous - Datasheet Reference
|
| 文件： | 总44页 (文件大小：431K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
10-Gigabit Ethernet MAC
with XGMII or XAUI v2.1
0
0
DS201 (v2.1) June 24, 2002
Product Specification
LogiCORE™ Facts
Core Specifics
Features
Supported Families
Speed Grades
Virtex-II, Virtex-II Pro
•
Single-speed full-duplex 10-gigabits-per-second
Ethernet Media Access Controller
-5 speed grade on Virtex-II
(XGMII version only)
•
•
•
Designed to Draft D4.1 of IEEE P802.3ae specification
Choice of XGMII or XAUI interface to PHY layer
-7 speed grade on Virtex-II Pro
156.25 MHz internal clock;
Uses Virtex™-II DDR I/O primitives for the optional
Performance
XGMII interface
156.25MHz DDR on
XGMII interface;
•
•
•
•
•
•
•
•
•
Uses Virtex-II Pro™ Multi Gigabit Transceivers for the
optional XAUI interface
3.125Gbps per lane on XAUI
interface
Cut-through operation with minimum buffering for
maximum flexibility in 64-bit client bus interfacing
Configured and monitored through an independent
microprocessor-neutral interface
Size
3000-4400 slices
3
Global Clock Buffers
Special Features
Uses Virtex-II/Virtex-II Pro Digital Clock Management
to implement XGMII and XAUI interface timing
Digital Clock Management
integrated into core
Powerful statistics gathering to internal counters.
Statistics vectors are also output to the user.
Provided with Core
Configurable flow control through MAC Control pause
frames; symmetrically or asymmetrically enabled
Documentation
Product Specification
New-style Clause 45 MDIO interface to managed
objects in PHY layers
Design File Formats EDIF netlist
Constraints File .ucf
Supports LAN/WAN (OC-192c data rate) functionality
through open loop rate control
Design Tools Requirements
Xilinx Core Tools v4.2i SP2
Support
Configurable support of VLAN frames to specification
IEEE 802.3-2000
•
•
•
Configurable support of “jumbo frames” of any length
Support provided by Xilinx
Configurable interframe gap length adjustment
Remote Fault/Local Fault signalling at the
Reconciliation Sublayer
•
Available under terms of the SignOnce IP License
FIFO
I/F
TCP
IP
MAC
PCS
WIS
PMA
PMD
XIP2092
Figure 1: Typical 10-Gigabit Ethernet Architecture
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS201 (v2.1) June 24, 2002
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1
Product Specification
1-800-255-7778
R
10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The client interface has fully independent 64-bit interfaces
for both transmit and receive to support full duplex opera-
tion; control lines are associated with each port to delineate
data lanes within the 64 bits.
Overview
The 10-gigabit Ethernet MAC is part of the 10-gigabit Ether-
net architecture displayed in Figure 1. The part of this archi-
tecture from the MAC to the right is defined in Draft D4.1
specification of the IEEE P802.3ae Task Force, currently
under development and due to be ratified in May 2002.
The configuration block and the statistics block are both
accessed through the management interface, a 32-bit pro-
cessor-neutral data pathway that is independent of the
Ethernet data pathway. The MIIM port is also accessed
through this interface.
A block diagram of the MAC core can be seen in Figure 2.
This shows the major functional blocks of the MAC, which
are:
The RS either converts the internal data representation of
the MAC core to the 32-bit DDR data that the XGMII speci-
fication requires, or passes it to the XAUI block. It also con-
tains logic to handle local fault and remote fault signalling
across the link.
•
•
•
•
•
•
•
•
•
•
the client interface
the transmit engine
the flow control block
the receive engine
The optional XAUI interface is designed to clause 47 of the
IEEE P802.3ae D4.1 draft. It uses the Multi Gigabit Trans-
ceivers (MGTs) of the Virtex-II Pro family. It converts the
MAC data into 4 lanes of 3.125Gbps data for transmission
over current mode differential lines, and also receives four
lanes of data at the same rate and passes it to the MAC.
the Reconciliation Sublayer (RS)
the configuration block
the statistics block
the MII Management interface (MIIM)
the optional XGMII interface
the optional XAUI interface
TRANSMIT ENGINE
Client
Interface
FLOW CONTROL
RECEIVE ENGINE
Management
Interface
CONFIGURATION
STATISTICS
MIIM
XIP2093
Figure 2: Functional Block Diagram of the 10-Gigabit Ethernet MAC
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Interface Description
Client Interface Signals
Figure 3 shows the pinout for a MAC core with the optional XGMII interface.
TX_CLK Domain
TX_CLK
TX_DATA[63:0]
TX_DATA_VALID[7:0]
TX_START
GTX_CLK
TX_ACK
TX_UNDERRUN
XGMII_TXD[31:0]
XGMII_TXC[31:0]
XGMII_TX_CLK
TX_IFG_DELAY[7:0]
TX_STATISTICS_VECTOR[21:0]
TX_STATISTICS_VALID
PAUSE_REQ
PAUSE_VAL[15:0]
RX_CLK Domain
RX_CLK
RX_DATA[63:0]
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
XGMII_RX_CLK
XGMII_RXD[31:0]
XGMII_RXC[3:0]
RX_STATISTICS_VECTOR[24:0]
RX_STATISTICS_VALID
MDC
MDIO_IN
MDIO_OUT
MDIO_TRI
HOST_CLK Domain
HOST_CLK
HOST_OPCODE[1:0]
HOST_ADDR[9:0]
HOST_WR_DATA[31:0]
HOST_RD_DATA[31:0]
HOST_MIIM_SEL
HOST_REQ
HOST_MIIM_RDY
RESET
XIP2094
Figure 3: Core Pinout with XGMII Interface
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Product Specification
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Figure 4 shows the pinout of a MAC core with the optional XAUI interface.
TX_CLK/RX_CLK DomaTinX_CLK
TX_DATA[63:0]
TX_DATA_VALID[7:0]
TX_START
REFCLK
TX_ACK
TX_UNDERRUN
XAUI_TX_L0<P,N>
XAUI_RX_L0<P,N>
TX_IFG_DELAY[7:0]
TX_STATISTICS_VECTOR[21:0]
TX_STATISTICS_VALID
XAUI_TX_L1<P,N>
XAUI_RX_L1<P,N>
PAUSE_REQ
PAUSE_VAL[15:0]
XAUI_TX_L2<P,N>
XAUI_RX_L2<P,N>
RX_CLK
RX_DATA[63:0]
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
XAUI_TX_L3<P,N>
XAUI_RX_L3<P,N>
RX_STATISTICS_VECTOR[24:0]
RX_STATISTICS_VALID
SIGNAL_DETECT[3:0]
XAUI_TYPE_SEL
HOST_CLK Domain
HOST_CLK
HOST_OPCODE[1:0]
HOST_ADDR[9:0]
HOST_WR_DATA[31:0]
HOST_RD_DATA[31:0]
HOST_MIIM_SEL
HOST_REQ
XAUI_PRTAD[4:0]
MDC
MDIO_IN
MDIO_OUT
MDIO_TRI
HOST_MIIM_RDY
RESET
XIP2095
Figure 4: Core pinout with XAUI interface
Table 1 describes the client-side transmitter interface signals of the MAC core. These signals are used to transmit data from
the client to the MAC core.
Table 1: Transmit Client Interface Signal Pins
Signal
Direction
Output
Input
Description
TX_CLK
Clock for transmit client interface. 156.25 MHz nominal.
Frame data to be transmitted is supplied on this port.
TX_DATA[63:0]
TX_DATA_VALID[7:0]
Input
Control signals for TX_DATA port. Each asserted signal on
TX_DATA_VALID signifies which bytes of TX_DATA are valid; i.e., if
TX_DATA_VALID[0] is 1, the signal TX_DATA[7:0] is valid.
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Product Specification
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Description
Table 1: Transmit Client Interface Signal Pins (Continued)
Signal
Direction
TX_START
TX_ACK
Input
Handshaking signal. Asserted by the client to make data available for
transmission. See the timing diagrams in section "Transmitter" on page 8.
Output
Asserted when the current data on TX_DATA has been accepted. See
timing diagrams in section "Transmitter" on page 8.
TX_UNDERRUN
Input
Input
Asserted by client to force MAC to corrupt the current frame.
TX_IFG_DELAY[7:0]
Enables the user to select a minimum interframe gap size. See timing
diagrams in section "Transmitter" on page 8.
TX_STATISTICS_VECTOR[21:0]
Output
Output
This gives information on the last frame transmitted. The contents of the
vector are described in section "XGMII Interface" on page 29.
TX_STATISTICS_VALID
This is asserted when the data on the TX_STATISTICS_VECTOR is valid.
Notes:
1. All the above signals are synchronous to TX_CLK and Active High.
Table 2 describes the signals used by the host to request a flow control action from the transmit engine. Flow control frames
received by the MAC across the XGMII or XAUI are automatically handled (if the MAC is configured to do so).
Table 2: Flow Control Interface Signal Pinout
Signal
Direction
Input
Description
PAUSE_REQ
Pause request; sends a pause frame down the link.
PAUSE_VAL[15:0]
Input
Pause value; this value is inserted into the parameter field of the transmitted pause
frame.
Notes:
1. These signals are synchronous to TX_CLK and are Active High.
Table 3 describes the client-side receive signals. These signals are used by the MAC core to transfer data to the client.
Table 3: Receive Client Interface Signal Pins
Signal
Direction
Output
Description
RX_CLK
Clock for receiving client interface. 156.25 MHz nominal.
Frame data received is supplied on this port.
RX_DATA[63:0]
Output
RX_DATA_VALID[7:0]
Output
Control signals for the RX_DATA port. Each asserted signal on
RX_DATA_VALID signifies which bytes of RX_DATA are valid. E.g., if
RX_DATA_VALID[0] is 1, the signal RX_DATA[7:0] is valid.
RX_GOOD_FRAME
Output
Asserted at end of reception of compliant frame. See "Receiver" on page
16.
RX_BAD_FRAME
Output
Output
Asserted at end of noncompliant frame. See "Receiver" on page 16.
RX_STATISTICS_VECTOR[24:0]
Information on the last frame received. The contents of the vector are
described in section "XGMII Interface" on page 29.
RX_STATISTICS_VALID
Output
This is driven high when the RX_STATISTICS_VECTOR is valid.
Notes:
1. All signals above are synchronous to RX_CLK and Active High.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Table 4 describes the signals used by the host system to access the management features of the MAC core, including
configuration, status, statistics and MIIM access.
Table 4: Management Interface Signal Pinout
Signal
HOST_CLK
Direction
Description
Input
Clock for management interface. See "Management Interface" on page 22 for the
frequency range of this signal.
HOST_OPCODE[1:0]
HOST_ADDR[9:0]
Input
Input
Defines operation to be performed over management interface.
Address of register to be accessed.
Data to write to register.
HOST_WR_DATA[31:0]
HOST_RD_DATA[31:0]
HOST_MIIM_SEL
Input
Output
Input
Data read from register.
When asserted, the MIIM interface is accessed. When disasserted, the MAC
internal registers are accessed.
HOST_REQ
HOST_MIIM_RDY
RESET
Input
Output
Input
Used to signal a transaction on the MIIM interface and to read from the statistic
registers. See "Management Interface" on page 22.
When high, the MIIM interface has completed any pending transaction and is
ready for a new transaction.
Asynchronous reset for entire core. This must be asserted for a minimum of 500
ns for a valid reset to occur. The clocks must be running for the core to come out
of the reset state.
Notes:
1. All signals above except RESET are synchronous to HOST_CLK and are Active High.
Table 5 describes the XGMII signals of the MAC core. These signals are optional. These are typically attached to an off-chip
PHY module.
Table 5: XGMII Interface Signal Pinout
Signal
GTX_CLK
Direction
Description
Input
Clock signal at 156.25MHz. Other transmit clocks are derived from this using DCM.
Tolerance must be within that specified in the IEEE P802.3 Ethernet specification.
XGMII_TX_CLK
XGMII_TXD[31:0]
XGMII_TXC[3:0]
XGMII_RX_CLK
XGMII_RXD[31:0]
XGMII_RXC[3:0]
Output
Output
Output
Input
Clock to PHY; source centred with respect to transmit data.
Transmit data to PHY; double data rate (DDR) signalling.
Control lines to PHY.
Recovered clock from received data stream by PHY.
Received data from PHY; DDR signalling.
Control lines from PHY.
Input
Input
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Table 6 describes the XAUI signals of the MAC core. These signals are optional and are typically attached to a backplane or
PHY module.
Table 6: XAUI Interface Signal Pinout
Signal
REFCLK
Direction
Description
Input
Clock signal at 156.25 MHz. All other core clocks are derived from this using a
DCM. Must conform to MGT jitter and stability specifications. See Virtex-II Pro
databook.
XAUI_TX_L0_<P,N>
XAUI_TX_L1_<P,N>
XAUI_TX_L2_<P,N>
XAUI_TX_L3_<P,N>
XAUI_RX_L0_<P,N>
XAUI_RX_L1_<P,N>
XAUI_RX_L2_<P,N>
XAUI_RX_L3_<P,N>
SIGNAL_DETECT[3:0]
Output
Output
Output
Output
Input
Transmit Differential Pair, XAUI Lane 0
Transmit Differential Pair, XAUI Lane 1
Transmit Differential Pair, XAUI Lane 2
Transmit Differential Pair, XAUI Lane 3
Receive Differential Pair, XAUI Lane 0
Receive Differential Pair, XAUI Lane 1
Receive Differential Pair, XAUI Lane 2
Receive Differential Pair, XAUI Lane 3
Input
Input
Input
Input
Signals from an 10GBASE-LX4 optical module, when the XAUI block is used as
a 10GBASE-X PCS. When the XAUI block is used as an XGXS, these signals
have no effect.
XAUI_TYPE_SEL
Input
Selects which type of XAUI block is implemented.
When XAUI_TYPE_SEL = 0, the block behaves as a 10GBASE-X PCS.
When XAUI_TYPE_SEL = 1, the block behaves as a DTE XGXS.
XAUI_PRTAD[4:0]
Input
Sets the port address at which the XAUI block should appear on the MIIM bus.
Table 7 describes the MIIM interface signals of the MAC core. These signals are typically connected to the MIIM port of an
off-chip PHY.
Table 7: MIIM Interface Signal Pinout
Signal
MDC
Direction
Description
Output
Management Clock; derived from HOST_CLK on basis of supplied configuration data. See
"Management Interface" on page 22.
MDIO_IN
Input
Serial MDIO data signal from PHY.
Serial MDIO data signal to PHY
MDIO_OUT
MDIO_TRI
Output
Output
Tristate control for MDIO signals; “0” signals that the value on MDIO_OUT should be
asserted onto the MDIO bus.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Functional Description
Table 8: TX_DATA, RX_DATA Lanes
Client Interface
Lane
TX_DATA, RX_DATA bits
The client interface is designed for maximum flexibility in
matching to a client switching fabric or network processor
interface.
0
1
2
3
4
5
6
7
7:0
15:8
The data pathway is 64 bits wide in both the transmit and
receive directions, with each pathway synchronous to the
TX_CLK and RX_CLK respectively for completely indepen-
dent full duplex operation. There are 8 control lines associ-
ated with each interface to signal which byte lanes are
active in each clocked transfer (Table 8). For each of
TX_DATA and RX_DATA, the port is logically divided into
lane 0 to lane 7, with the corresponding bit of the control
word signifying valid data on the TX_DATA, RX_DATA port.
23:16
31:24
39:32
47:40
55:48
63:56
Transmitter
Normal frame transmission
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
TX_DATA_VALID[7:0]
TX_START
00
FF
FF
FF
FF
07
00
TX_ACK
TX_UNDERRUN
XIP2096
Figure 5: Normal Frame Transmission across Client Interface
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The timing of a normal outbound frame transfer is shown in
Figure 5. When the client wants to transmit a frame, it
asserts the TX_START signal, and on the next clock places
the first column of data and control onto the TX_DATA and
TX_DATA_VALID ports.
Table 9: Abbreviations Used in Timing Diagrams
Abbreviation
Definition
DA
SA
Destination Address
Source Address
When the MAC core has read this first column of data, it will
assert the TX_ACK signal; on the next and subsequent
clock edges, the client must provide the remainder of the
data for the frame.
L/T
FCS
Length/Type Field
Frame Check Sequence
In-band parameter encoding
The end of frame is signalled to the MAC core by having
TX_DATA_VALID not equal to hexadecimal “FF”; partially
full columns of data are not permitted within a frame. As an
example, in Figure 5, the value of TX_DATA_VALID of hexa-
decimal “07” signals to the MAC core that only the lower
three columns of data are valid on the transfer, and addition-
ally that the end of frame has been reached.
For maximum flexibility in switching applications, the Ether-
net frame parameters are encoded within the same data
stream that the frame payload is transferred upon, rather
than on separate ports.
The destination address must be supplied with the first byte
in lane 0 and so on. Similarly, the first byte of the Source
Address must be supplied in lane 6 of the first transfer.
Frame parameters (destination address, source address,
length/type and optionally FCS) must be supplied on the
data bus according to the timing diagram. The definitions of
the abbreviations are described in Table 9.
The length/type field is similarly encoded, with the first byte
placed into lane 4.
Client-supplied FCS passing
If the MAC core is configured to have the FCS field passed
by the client (see "Configuration Registers" on page 22), the
transmission timing is as shown in Figure 6. In this case, it is
the responsibility of the client to ensure that the frame
meets the Ethernet minimum frame length requirements;
the MAC core will not perform any padding of the payload.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
DA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DA
DA
DA
DA
DA
SA
SA
D
D
FCS
FCS
FCS
FCS
D
TX_DATA_VALID[7:0]
TX_START
00
FF
FF
FF
FF
7F
00
TX_ACK
TX_UNDERRUN
XIP2097
Figure 6: Frame Transmission with Client-supplied FCS
empties before a frame is completed. When the client
asserts TX_UNDERRUN during a frame transmission, the
MAC core will insert error codes into the XGMII data stream
in order to corrupt the current frame, then will fall back to
idle transmission. It is the responsibility of the client to
requeue the aborted frame for transmission.
Padding
When fewer than 46 bytes of data are supplied by the client
to the MAC core, the transmitter module will add padding up
to the minimum frame length, unless the MAC core is con-
figured for client-passed FCS. In the latter case, the client
must also supply the padding in order to maintain the mini-
mum frame length.
When an underrun occurs, TX_START may be asserted on
the clock cycle after the TX_UNDERRUN assertion to start
a new transmission.
Client Underrun
The timing of an aborted transfer can be seen in Figure 7.
This may happen, for instance, if a FIFO in the bus interface
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
TX_DATA_VALID[7:0]
TX_START
00
FF
FF
FF
FF
00
TX_ACK
TX_UNDERRUN
XIP2098
Figure 7: Frame Transmission with Underrun
Figure 8 shows the case where the MAC is immediately
ready to accept the next frame of data. In the column after
the last data is transferred for the first frame, the client
asserts TX_START to signal that another frame is ready for
transmission. The MAC core then asserts TX_ACK to allow
the client to begin the burst of frame parameters and data
that make up the frame.
Back-to-back transfers
Two situations can occur during back-to-back transfers; in
one, the MAC core is ready to accept data; in the other, the
MAC must defer to comply with inter-packet gap require-
ments, a user request to extend the interframe gap or flow
control requests.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
D
D
D
D
D
D
D
D
D
D
D
D
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
TX_DATA_VALID[7:0]
TX_START
FF
0F
00
FF
FF
FF
TX_ACK
TX_UNDERRUN
XIP2099
Figure 8: Back to Back Frame Transmission with no Back Pressure
Figure 9 shows a case where the MAC is exerting back
pressure on the client to delay the start of transmission. In
this case, the client has asserted TX_START to signal that
another frame is ready for transmission, but the MAC core
has delayed the assertion of TX_ACK to allow the data burst
to begin. Once this burst has begun, it continues in the
same manner as in the cases above. In both cases, as in
the case for normal frame transmission, the client must pro-
vide a whole frame of data in one burst; there is no mecha-
nism to stop and start transfer within a single frame.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
D
D
D
D
D
D
D
D
D
D
D
D
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
TX_DATA_VALID[7:0]
TX_START
FF
0F
00
FF
FF
FF
TX_ACK
TX_UNDERRUN
XIP2100
Figure 9: Back-to-Back Frame Transmission with Back Pressure
number of XGMII columns is controlled by the value on the
IFG_DELAY port. The minimum interframe gap of 3 XGMII
columns is always maintained. Figure 10 shows the MAC
operating in this mode.
Interframe gap adjustment
The user can elect to vary the length of the interframe gap.
If this function is selected (via a configuration bit, see "Con-
figuration Registers" on page 22), the MAC will exert back
pressure to delay the transmission of the next frame until
the requested number of XGMII columns has elapsed. The
If the core has a XAUI interface rather than a XAUI one, the
interframe gap will vary as if an XGMII interface existed.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
DA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
DA
DA
DA
DA
DA
SA
SA
D
TX_DATA_VALID[7:0]
TX_START
00
FF
FF
FF
FF
07
00
TX_ACK
TX_IFG_DELAY
IFG_DELAY_VAL
XIP2101
Figure 10: Interframe Gap Adjustment
VLAN Tagged Frames
Transmission of a VLAN tagged frame (if enabled) is shown in Figure 11. Note that the handshaking signals across the
interface do not change; however, the VLAN type tag 81-00 must be supplied by the client to signify that the frame is VLAN
tagged. The client also supplies the two bytes of Tag Control Information, V1 and V2, at the appropriate times in the data
stream. More information on the contents of these two bytes can be found in IEEE 802.3-2000.
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TX_CLK
TX_DATA[7:0]
TX_DATA[15:8]
TX_DATA[23:16]
TX_DATA[31:24]
TX_DATA[39:32]
TX_DATA[47:40]
TX_DATA[55:48]
TX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
81
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
00
D
V1
V2
D
D
TX_DATA_VALID[7:0]
TX_START
00
FF
FF
FF
FF
07
00
TX_ACK
TX_UNDERRUN
XIP2102
Figure 11: Transmission of a VLAN Tagged Frame.
Transmitter Statistics Vector
The statistics for the frame transmitted are contained within the TX_STATISTICS_VECTOR. The vector is synchronous to
the transmitter clock, TX_CLK and is driven following frame transmission. The bit field definition for the Vector is defined in
Table 10.
All bit fields, with the exception of BYTE_VALID, are valid only when the TX_STATISTICS_VALID is asserted. This is
illustrated in Figure 12. BYTE_VALID is significant on every TX_CLK cycle.
TX_CLK
TX_STATISTICS_VALID
TX_STATISTICS_VECTOR[21:0]
XIP2103
Figure 12: Transmitter statistics output timing.
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Table 10: TX_STATISTICS_VECTOR Description
TX Stats Vector
Bit
Name
Description
21
Pause Frame
Transmitted
The previous frame was a pause frame that was initiated by the MAC in
response to a pause request from the client.
20 to 17
Number of Bytes
The number of bytes transmitted on the last clock cycle. This can be
between 0 and 8. This is valid on every clock cycle, it is not validated by
TX_STATISTICS_VALID.
16
VLAN Frame
Length Count
High along with the valid signal when the previous frame was a VLAN frame.
15 to 5
The length of the previously transmitted frame. This does not take into
account the preamble or start bytes. The count will stick at 2047 for any
Jumbo frames larger than this value.
4
Control Frame
Indicates that the previous frame had the special control frame character in
the length/type field.
3
2
Underrun Frame
Multicast Frame
High if the previous frame contained an underrun error.
High if the destination address in the previous frame contained a multicast
address.
1
Broadcast Frame
Successful Frame
High if the destination address in the previous frame contained a broadcast
address.
0
High if the previous frame was transmitted successfully.
Receiver
Normal Frame Reception
The timing of a normal inbound frame transfer is represented in Figure 13. The client must be prepared to accept data at any
time; there is no buffering within the MAC to allow for latency in the receive client. Once frame reception begins, data is
transferred on consecutive clock cycles to the receive client until the frame is complete. The MAC asserts the
RX_GOOD_FRAME signal to signal successful frame reception to the client.
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RX_CLK
RX_DATA[7:0]
RX_DATA[15:8]
RX_DATA[23:16]
RX_DATA[31:24]
RX_DATA[39:32]
RX_DATA[47:40]
RX_DATA[55:48]
RX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
00
FF
FF
FF
FF
03
00
XIP2104
Figure 13: Normal Frame Reception
Frame parameters (destination address, source address, length/type and, optionally, FCS) are supplied on the data bus as
shown on the timing diagram. The abbreviations are described in Table 9.
If the Length/Type field in the frame has the Length interpretation, and this indicates that the inbound frame has been
padded to meet the Ethernet minimum frame size specification, this pad will not be passed to the client in the data payload.
An exception to this occurs when FCS passing is enabled. See "Client-Supplied FCS Passing" on page 19.
There is always at least one clock cycle with RX_DATA_VALID = 0x00 between frames; i.e., there’s no valid data for this
clock edge.
RX_GOOD_FRAME, RX_BAD_FRAME timing
Although the timing diagram in Figure 13 shows the RX_GOOD_FRAME signal asserted at the same time as the last valid
data on RX_DATA, this is not always the case. The RX_GOOD_FRAME and RX_BAD_FRAME signals can in fact be
asserted up to 7 clock cycles after the last valid data is presented; for example, this may result from padding at the end of
the Ethernet frame. This is represented in Figure 14. Note that although RX_GOOD_FRAME is illustrated, the same timing
applies to RX_BAD_FRAME.
Either the RX_GOOD_FRAME or RX_BAD_FRAME signal will, however, always be asserted before the next frame’s data
begins to appear on RX_DATA.
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RX_CLK
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
FF
7F
00
up to 7 CLOCKS
XIP2105
Figure 14: Late Arrival of RX_GOOD_FRAME
Frame Reception with Errors
The case of an unsuccessful frame reception (for example, a runt frame or a frame with an incorrect FCS) can be seen in
Figure 15. In this case, the RX_BAD_FRAME signal is asserted to the client at the end of the frame. It is then the
responsibility of the client to drop the data already transferred for this frame.
RX_CLK
RX_DATA[7:0]
RX_DATA[15:8]
RX_DATA[23:16]
RX_DATA[31:24]
RX_DATA[39:32]
RX_DATA[47:40]
RX_DATA[55:48]
RX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
00
FF
FF
FF
FF
03
00
XIP2106
Figure 15: Frame Reception with Error
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Client-Supplied FCS Passing
If the MAC core is configured to pass the FCS field to the client (see "Configuration Registers" on page 22), this is handled
as shown in Figure 16.
In this case, any padding inserted into the frame to meet Ethernet minimum frame length specifications will be left intact and
passed to the client.
Note that even though the FCS is passed up to the client, it is also verified by the MAC core, and RX_BAD_FRAME is
asserted if the FCS check fails.
RX_CLK
RX_DATA[7:0]
RX_DATA[15:8]
RX_DATA[23:16]
RX_DATA[31:24]
RX_DATA[39:32]
RX_DATA[47:40]
RX_DATA[55:48]
RX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
FCS
FCS
FCS
FCS
D
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
00
FF
FF
FF
FF
3F
00
XIP2107
Figure 16: Frame Reception with In-Band FCS Field
VLAN Tagged Frames
The reception of a VLAN tagged frame (if enabled) is represented in Figure 17. The VLAN frame is passed to the client so
that the frame can be identified as VLAN tagged; this is followed by the Tag Control Information bytes, V1 and V2. More
information on the interpretation of these bytes can be found in IEEE 802.3ac-1998.
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RX_CLK
RX_DATA[7:0]
RX_DATA[15:8]
RX_DATA[23:16]
RX_DATA[31:24]
RX_DATA[39:32]
RX_DATA[47:40]
RX_DATA[55:48]
RX_DATA[63:56]
DA
DA
DA
DA
DA
DA
SA
SA
SA
SA
SA
SA
81
L/T
L/T
D
D
D
D
D
D
D
D
D
D
D
D
D
00
D
V1
V2
D
D
RX_DATA_VALID[7:0]
RX_GOOD_FRAME
RX_BAD_FRAME
00
FF
FF
FF
FF
03
00
XIP2108
Figure 17: Reception of a VLAN Tagged Frame
Receive Statistics Vector
The statistics for the frame received are contained within the RX_STATISTICS_VECTOR. The vector is driven
synchronously by the receiver clock, RX_CLK, following frame reception. The bit field definition for the Vector is defined in
Table 11.
All bit fields, with the exception of BYTE_VALID, are valid only when RX_STATISTICS_VALID is asserted. This is illustrated
in Figure 18. BYTE_VALID is significant on every RX_CLK cycle.
RX_CLK
RX_STATISTICS_VALID
RX_STATISTICS_VECTOR[24:0]
XIP2109
Figure 18: Receiver Statistics Output Timing
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Description
Table 11: RX_STATISTICS_VECTOR Description
RX Stats Vector
Bit
Name
24
Bad Opcode
The previous frame received was a flow control frame but contained an
opcode that is not supported by the MAC.
23
Flow Control Frame The previous frame was a flow control frame with a supported opcode.
22 to 19
Number of Bytes
A binary representation of the number of bytes received on the last clock
cycle. This can range from 0 to 8. This is valid on every clock cycle, it is not
validated by RX_STATISTICS_VALID.
18
17
VLAN Frame
The last received frame contained a VLAN tag in the length/type field.
Out of Bounds
The previous frame exceeded the maximum length of a frame. This is only
valid when jumbo frames are disabled.
16
Control Frame
The last received frame contained the control frame identifier in the
length/type field.
15 to 5
Frame Length Count The length in bytes of the previous received frame. The count will stick at
2047 for any Jumbo frames larger than this value.
4
3
Multicast Frame
High if the destination address in the previous frame contained a multicast
address.
Broadcast Frame
High if the destination address in the previous frame contained a broadcast
address.
2
1
0
FCS Error
Bad Frame
Good Frame
This is high if the last frame that was received had an incorrect FCS value.
This is high when the last frame contained errors.
This is high if the last frame was error free.
If the MAC core is configured to support transmit flow con-
trol, this action causes the MAC core to transmit a PAUSE
Flow Control
The flow control block is designed to Clause 31 of the IEEE
P802.3 Ethernet standard. The MAC can be configured to
send pause frames and to act on their reception. These two
behaviors can be configured asymmetrically; see "Configu-
ration Registers" on page 22.
control frame on the link, with the PAUSE parameter set to
the value on PAUSE_VAL in the cycle when PAUSE_REQ
was asserted. This will not disrupt any frame transmission
in progress but will take priority over any pending frame
transmission.
Transmitting a PAUSE Control Frame
Receiving a Pause Control Frame
The client sends a flow control frame by asserting
PAUSE_REQ while the pause value is on the PAUSE_VAL
bus. These signals are synchronous with respect to
TX_CLK. The timing of this can be seen in Figure 19.
When a pause frame is received by the MAC core and the
MAC core is configured to act upon received pause frames,
the following checks are made:
•
The frame is checked to see whether it is well formed
(is a valid Ethernet frame). If not, the frame is dropped
TX_CLK
PAUSE_REQ
•
If the Destination Address does not match the MAC
Control Multicast address or the configured Source
Address for the MAC (see "Configuration Registers" on
page 22), the frame is passed to the client
•
•
If the Length/Type field does not match the MAC
Control Type code, the frame is passed up to the client
PAUSE_VAL[15:0]
If the opcode field contents do not match the PAUSE
opcode, the frame is passed up to the client
XIP2110
Figure 19: Pause Request Timing
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If the frame passes all of these checks, the pause value
parameter in the frame is then used to inhibit transmitter
operation for the time defined in the Ethernet specification.
This inhibit is implemented using the same back pressure
scheme shown in Figure 9. Since the received pause frame
has been acted upon, it is not passed up to the client by
marking it as a bad frame.
Table 12: Management Interface Transaction Types
Transaction
Configuration
Statistics
HOST_MIIM_SEL
HOST_ADDR[9]
0
0
1
1
0
MIIM Access
X
Management Interface
HOST_CLK Frequency
The management interface is a processor-independent
interface with standard address, data, and control signals. It
can be used as-is, or a wrapper (not supplied) can be
applied to interface to common bus architectures.
The management interface clock, HOST_CLK, is used to
derive the MIIM clock, MDC, and is therefore subject to
some frequency restrictions. This HOST_CLK must be:
This interface is used for:
•
•
≥ 10 MHz
•
•
configuring the MAC core
≤ 133 MHz
accessing statistics information for use by high layers,
Configuring the MAC core to derive the MDC signal from
this clock is detailed in MII Management Interface.
e.g., SNMP
•
•
accessing an internal MIIM interface through the
optional XAUI configuration and status registers
Configuration Registers
After power up or reset, the client can reconfigure some of
the core parameters from their defaults, such as flow control
support and WAN/LAN connections.
accessing the MIIM interface through the management
registers located in the PHY attached to the MAC core
The management interface is accessed differently, depend-
ing on the type of transaction; Table 12 is a truth table show-
ing which access method is required for each transaction
type. These access methods are described in the following
sections.
Configuration of the MAC core is performed through a reg-
ister bank accessed through the management interface.
The configuration registers available in the core are detailed
in Table 13. As can be seen, the address has some implicit
don’t-care bits; the configuration words appear at all loca-
tions in the ranges described.
Table 13: Configuration Registers
Address
Description
0x200
0x240
0x280
0x2C0
0x300
0x340
Receiver Configuration (Word 0).
Receiver Configuration (Word 1).
Transmitter Configuration.
Flow Control Configuration.
Reconciliation Sublayer Configuration.
Management Configuration.
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The register contents for the two receiver configuration words is shown in Table 14 and Table 15.
Table 14: Receiver Configuration Word 0
Bit
Default Value
Description
31-0
All “0s”
Pause frame MAC Address[31:0]. This address is used by the MAC to match
against the Destination Address of any incoming flow control frames. It is also
used by the flow control block as the Source Address (SA) for any outbound flow
control frames.
The address is ordered so the first byte transmitted/received is the lowest
positioned byte in the register; for example, a MAC address of
AA-BB-CC-DD-EE-FF would be stored in Address[47:0] as 0xFFEEDDCCBBAA.
Table 15: Receiver Configuration Word 1
Bit
15-0
26-16
27
Default Value
Description
Pause frame MAC Address[47:32]. See description in Table 14.
Reserved
All “0s”
N/A
0
VLAN Enable. When this bit is set to “1,” VLAN tagged frames will be accepted by
the receiver. The maximum payload length will increase by 4 bytes.
28
29
1
0
Receiver Enable. If set to “1,” the receiver block will be operational. If set to “0,”
the block will ignore activity on the XGMII RX port.
In-band CRC Enable. When this bit is “1,” the MAC receiver will pass the CRC up
to the client as described in "Client-Supplied FCS Passing" on page 19. When it
is “0,” the client will not be passed the FCS. In both cases, the FCS will be verified
on the frame.
30
31
0
0
Jumbo Frame Enable. When this bit is set to “1,” the MAC receiver will accept
frames of any length. When this bit is “0,” the MAC will only accept frames up to
the Ethernet legal maximum.
Reset. When this bit is set to “1,” the receiver will be reset. The bit will then
automatically revert to “0.” Note that this reset will also set all of the receiver
configuration registers to their default values.
The register contents for the Transmitter Configuration Word are described in Table 16.
Table 16: Transmitter Configuration Word
Bit
24-0
25
Default Value
Description
N/A
0
Reserved
Interframe gap stretch mode. If this bit is set to “1,” the core will maintain an
interframe gap of N cycles. N is set by the value appearing on the IFG_DELAY
port. This value should be set along with the START signal and kept on the port
until the DATA_ACK is received from the MAC. This bit has no effect when bit 26
(LAN/WAN mode) is set to “1.”
26
27
0
0
LAN/WAN Mode. When this bit is set to “1,” the transmitter will automatically insert
extra idles into the inter frame gap (IFG) to reduce the average data rate to that
of the OC-192 SONET payload rate (WAN mode). When this bit is set to 0, the
transmitter will use normal Ethernet inter-frame gaps (LAN mode).
VLAN Enable. When this bit is set to “1,” the transmitter will allow the transmission
of VLAN tagged frames.
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Table 16: Transmitter Configuration Word (Continued)
Bit
Default Value
Description
28
1
Transmit Enable. When this bit is “1,” the transmitter is operational. When it is “0,”
the transmitter is disabled.
29
0
In-band CRC Enable. When this bit is “1,” the MAC transmitter will expect the CRC
to be passed in by the client as described in "Client-supplied FCS passing" on
page 9. When this bit is “0,” the MAC transmitter will append padding as required,
compute the CRC and append it to the frame.
30
31
0
0
Jumbo Frame Enable. When this bit is set to “1,” the MAC transmitter will send
frames of any length. When this bit is “0,” the MAC will only send frames up to the
Ethernet legal maximum.
Reset. When this bit is set to “1,” the transmitter will be reset. The bit will then
automatically revert to “0.” Note that this reset will also set all of the transmitter
configuration registers to their default values.
The register contents for the Flow Control Configuration Word are described in Table 17.
Table 17: Flow Control Configuration Word
Bit
28-0
29
Default Value
Description
N/A
1
Reserved
Flow Control Enable (TX). When this bit is “1,” asserting the PAUSE_REQ signal
will send a flow control frame out from the transmitter. When this bit is “0,”
asserting the PAUSE_REQ signal has no effect.
30
31
1
0
Flow Control Enable (RX). When this bit is “1,” received flow control frames will
inhibit the transmitter operation as described in "Receiving a Pause Control
Frame" on page 21. When this bit is “0,” received flow control frames will be
passed up to the client.
Reset. When this bit is set to “1,” the flow control block will be reset. The bit will
then automatically revert to “0.” Note that this reset will also set all of the flow
control configuration registers to their default values.
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The register contents for the Reconciliation Sublayer Status Word are described in Table 18.
Table 18: Reconciliation Sublayer Status Word
Bits
27-0
28
Default Value
Description
N/A
N/A
Reserved
Local Fault. If this bit is “1,” the RS layer is receiving local fault sequence ordered
sets. Read-only.
29
30
N/A
N/A
Remote Fault. If this bit is “1,” the RS layer is receiving remote fault sequence
ordered sets. Read-only.
TXLOCK. If this bit is “1,” the Digital Clock Management (DCM) block for the
transmit-side clocks (GTX_CLK, XGMII_TX_CLK, TX_CLK) is locked. If this bit is
“0,” the DCM is not locked.
31
N/A
RXLOCK. If this bit is “1,” the Digital Clock Management (DCM) block for the
receive-side clocks (XGMII_RX_CLK, RX_CLK) is locked. If this bit is “0,” the
DCM is not locked.
The register contents for the Management Configuration Word are described in Table 19.
Table 19: Management Configuration Word
Bits
4-0
5
Default Value
Description
All “0s”
Clock Divide[4:0]. See "MII Management Interface" on page 28
0
MIIM Enable. When this bit is “1,” the MIIM interface can be used to access
attached PHY devices. When this bit is “0,” the MIIM interface is disabled and the
MDIO signal remains in a high impedance state.
31-6
N/A
Reserved.
Writing to the configuration registers through the management interface is depicted in Figure 20. When accessing the
configuration registers (i.e., when HOST_ADDR[9] = “1” and HOST_MIIM_SEL = “0”), the upper bit of HOST_OPCODE
functions as an Active Low write-enable signal. The lower HOST_OPCODE bit is a “don’t care.”
Reading from the configuration register words is similar, except that the upper HOST_OPCODE bit should be “1,” as shown
in Figure 21. In this case, the contents of the register appear on HOST_RD_DATA and the HOST_CLK edge after the
register address is asserted onto HOST_ADDR.
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HOST_CLK
HOST_MIIM_SEL
HOST_CLK
HOST_MIIM_SEL
HOST_OPCODE[1]
HOST_ADDR[8:0]
HOST_ADDR[9]
HOST_OPCODE[1]
HOST_ADDR[8:0]
HOST_ADDR[9]
HOST_RD_DATA[31:0]
HOST_WR_DATA[31:0]
XIP2112
XIP2111
Figure 21: Configuration Register Read Timing
Figure 20: Configuration Register Write Timing
Operational Statistics
During operation, the MAC core collects statistics on the success and failure of various operations, for processing by station
management entities (STA) further up the protocol stack. These statistics are accessed by the host through the
management interface.
A complete list of statistics supported is described in Table 20. Each of these statistic registers is 64 bits wide and therefore
must be read in a two-cycle transfer. The timing of this process is shown in Figure 22. Six clocks after the read transaction
is initiated, the least significant word (LSW) of the statistics counter appears on the HOST_RD_DATA bus, and a clock cycle
later the most significant word (MSW) appears. For accurate statistic values, 64 GTX_CLK ticks must elapse after the last
frame is sent or received through the MAC core.
Table 20: Statistics Registers
Address
0x000
0x001
0x002
0x003
0x004
0x005
0x006
0x007
0x008
0x009
0x00A
Description
Frames Received OK
Frame Check Sequence Errors
Broadcast Frames Received OK
Multicast Frames Received OK
64 byte Frames Received OK
65-127 byte Frames Received OK
128-255 byte Frames Received OK
256-511 byte Frames Received OK
512-1023 byte Frames Received OK
1024-1518 byte Frames Received OK
Control Frames Received OK (i.e., frames with Length/Type field matching the MAC
Control Type code and having the Destination Address match either the Source
Address in the configuration register or the MAC Control Multicast Address).
0x00B
0x00C
Length/Type Out of Range
VLAN Tagged Frames Received OK
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
Table 20: Statistics Registers (Continued)
Address
Description
0x00D
Pause Frames Received OK (i.e., Control Frames with an Opcode corresponding to
a pause request)
0x00E
0x00F
0x010
0x011
0x012
0x013
0x020
0x021
0x022
0x023
0x024
0x025
0x026
0x027
0x028
0x029
0x02A
0x02B
0x02C
0x02D
Control Frames Received with Unsupported Opcode
Oversize Frames Received OK
Undersized Frames Received (less than minimum frame size with valid FCS field)
Fragment Frames Received (less than minimum frame size with invalid FCS field)
Number of Bytes Received (bytes counted from DA to FCS field inclusive)
Number of Bytes Transmitted (bytes counted from DA to FCS field inclusive)
Frames Transmitted
Broadcast Frames Transmitted
Multicast Frames Transmitted
Underrun Errors. Note: this will not count underrun frames of length < 64 bytes.
Control Frames Transmitted OK
64 byte Frames Transmitted OK
65-127 byte Frames Transmitted OK
128-255 byte Frames Transmitted OK
256-511 byte Frames Transmitted OK
512-1023 byte Frames Transmitted OK
1024-1518 byte Frames Transmitted OK
VLAN Tagged Frames Transmitted OK
Pause Frames Transmitted OK
Oversize Frames Transmitted OK
In general, frames that are declared “received OK” are well formed Ethernet frames with valid CRCs. Frames that are
declared “transmitted OK” were sent out from the MAC with no errors introduced by the MAC.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
HOST_CLK
HOST_MIIM_SEL
HOST_REQ
HOST_ADDR[8:0]
HOST_ADDR[9]
6 CLOCKS
HOST_RD_DATA[31:0]
LSW MSW
XIP2113
Figure 22: Statistic Register Read Timing
The frequency of MDC given by this equation should not
exceed 2.5 MHz in order to comply with the IEEE specifica-
tion for this interface. To prevent MDC from being out of
specification, the Clock Divide[4:0] value powers up at
00000, and while this value is in the register, it is impossible
to enable the MII Management interface.
MII Management Interface
The management interface is also used to access the MII
Management interface of the MAC core; this interface is
used to access the Managed Information Block (MIB) of the
PHY components attached to the MAC core.
The MII Management interface supplies a clock to the exter-
nal devices, MDC. This clock is derived from the
HOST_CLK signal, using the value in the Clock Divide[4:0]
configuration register. The frequency of the MII Manage-
ment clock is given by the following equation:
For details of the register map of PHY layer devices and a
fuller description of the operation of the MII Management
interface itself, see IEEE draft specification P802.3ae D4.1.
Access to the MII Management interface through the man-
agement interface is depicted in the timing diagram in
Figure 23.
fHOST_CLK
fMDC = ----------------------------------------------------
Clock Divide[4:0] × 2
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
HOST_CLK
HOST_MIIM_SEL
HOST_REQ
HOST_OPCODE[1:0]
HOST_ADDR[9:0]
HOST_WR_DATA[15:0]
HOST_RDY
*
HOST_RD_DATA[15:0]
*
* If a read transaction is initiated, the HOST_RD_DATA bus is valid
at the point indicated. If a write transaction is initiated, the
HOST_WR_DATA bus must be valid at the indicated point.
Simultaneous read and write is not permitted.
XIP2114
Figure 23: MIIM Access Through Management Interface
For MII Management transactions, the following points
apply:
agement
interface
has
been
completed,
the
HOST_MIIM_RDY signal will be asserted by the MAC core;
if the transaction is a read, the data will also be available on
the HOST_RD_DATA[15:0] bus at this time.
•
HOST_OPCODE maps to the OP (opcode) field of the
MII Management frame
•
HOST_ADDR maps to the two address fields of the MII
Management frame; PHY_ADDR is HOST_ADD[9:5],
and REG_ADDR is HOST_ADD[4:0]
XGMII Interface
The optional XGMII interface is a 312Mbps DDR interface,
as defined in clause 46 of IEEE P802.3ae D4.1. It is imple-
mented using the Virtex-II DDR I/O buffer primitives and
uses DCM to adjust clock/data alignment.
•
•
HOST_WR_DATA[15:0] maps into the data field of the
MII Management frame when performing a write
operation
The data field of the MII Management frame maps into
HOST_RD_DATA[15:0]
Clock Management
Figure 24 shows how the clocks are used and derived
within the core when an XGMII interface is used.
The MAC core signals to the host that it is ready for an MII
Management transaction by asserting HOST_MIIM_RDY. A
read or write transaction on the MII Management is initiated
by a pulse on the HOST_REQ signal. This pulse is ignored
if the MII Management interface already has a transaction in
progress.
Note that the GTX_CLK signal must have an input buffer
IBUFG either instanced or inferred for correct operation of
the core as shown. A DCM is then used to source this clock
onto the global clock routing matrix.
Also note that the HOST_CLK signal does not have a BUFG
instanced within the core; this clock buffer must be
instanced or inferred by the core user.
The MAC core then disasserts the HOST_MIIM_RDY signal
while the transaction across the MII Management interface
is in progress. When the transaction across the MII Man-
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The XGMII_RX_CLK is received through an IBUFG. This clock is then routed onto a global clock network by connecting it
through a DCM to a BUFG: this global clock is used by all MAC receiver logic. The MAC Client can obtain this clock by
connecting to the RX_CLK signal output from the core.
GTX_CLK
IBUFG
MAC Core
DCM
BUFG
BUFG
CLKIN CLK0
FDDRRSE
FB
CLK90
XGMII_TX_CLK
TX_CLK
RX_CLK
BUFG
DCM
IBUFG
XGMII_RX_CLK
CLK0 CLKIN
FB
XIP2115
Figure 24: Clock Management in core with XGMII interface
recommended that these be separated into separate IO
Banks. Unused IOs in these banks, if tied to ground, will
help to reduce jitter by providing a low impedance path for
ground currents.
Pin Location Considerations
The MAC core allows for a flexible pinout of the XGMII and
the exact pin locations are left to the designer. In doing so,
codes of practice and device restrictions must be followed.
Every Virtex-II and Virtex-II Pro device has 8 separate IO
Banks. Each IO Bank has Output Drive Source Voltage
Pads (Vcco) that must be connected to the same external
voltage reference. For XGMII, this must be 1.5 volts. This
will force all IO pads within the bank to operate at this volt-
age level.
XAUI Interface
The optional XAUI interface is a 4-lane, 3.125Gbps-per-lane
current mode logic interface, as defined in clauses 47 and
48 of IEEE P802.3ae D4.1.
A diagram of the XAUI block is shown in Figure 25. The
main components of the XAUI block are:
IO standards, including HSTL, which use input differential
amplifiers, require voltage reference inputs (Vref). These
are automatically configured by the place and route tool
onto predefined pins (see the Virtex-II User Guide or Vir-
tex-II Pro User Guide for all devices and packages). Approx-
imately one of every 12 IO pins within an IO bank will be
configured as a Vref pin. For XGMII which uses HSTL_I, all
Vref pins must be connected externally to 0.75 volts.
•
•
•
•
the transmitter component
the receiver component
the management register component
the RocketIO Multi Gigabit Transceivers (MGTs)
The management registers of the XAUI block have an MIIM
interface which is accessed through the core host interface
as if it were an externally connected PHY.
IOs should be grouped in their own separate clock domains.
XGMII contains two of these: XGMII_RXD[31:0] and
XGMII_RXC[3:0], which are centered with respect to
XGMII_RX_CLK; XGMII_TXD[31:0] and XGMII_TXC[3:0],
which are centered with respect to XGMII_TX_CLK. It is
The RocketIO MGTs provide some of the XAUI functionality,
such as 8B10B encoding/decoding and the PMA serdes.
The synchronization and idle pattern generation logic are
generated as CLB logic.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
LANE 0
MGT
MGT
MGT
MGT
TRANSMIT ENGINE
LANE 1
LANE 2
To
MAC
RECEIVE ENGINE
MANAGEMENT
LANE 3
MDIO
Interface
XIP2116
Figure 25: Functional diagram of the XAUI block
Also note that the HOST_CLK signal does not have a BUFG
instanced within the core; this clock buffer must be
instanced or inferred by the core user.
Clock Management
Figure 26 shows how the clocks are used and derived
within the core when an XAUI interface is used.
In this configuration, the TX_CLK and RX_CLK signals are
actually the same net; the elastic buffer in the MGT is used
to cross into a common clock domain. If only the XAUI con-
figuration is to be used in the final application, some optimi-
zations to client logic can be made.
Note that the REF_CLK signal must have an input buffer
either instanced or inferred for correct operation of the core.
This REFCLK signal must be a High purity clock as speci-
fied for RocketIO reference clocks in the Virtex-II Pro User
Guide.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
REFCLK
IBUFG
MAC Core
BUFG
GT_XAUI_2
REFCLK_2
_2
_2
DCM
BUFG
TXUSRCLK
CLKIN CLK0
FB
TXUSRCLK2
K
RXUSRCLK
K2
K
RXUSRCLK2
TX_CLK
RX_CLK
K
K2
K
RXUSRCLK2
K
K2
RXUSRCLK2
K
RXUSRCLK2
XIP2117
Figure 26: Clock Management in core using XAUI interface
DTE XGXS Registers
Pin Location Considerations
The management registers for the DTE XGXS implementa-
tion of the XAUI block are shown in Table 21; the DTE
XGXS occupies device address 5.
The four MGTs of the XAUI block are channel bonded as
described in the Virtex-II Pro User’s Guide. The Lane 0
MGT is the channel bond master, Lanes 1 and 2 are 1-hop
slaves, and Lane 3 is a 2-hop slave.
Table 21: DTE XGXS Registers
It is therefore recommended that if the XAUI interface is to
be split across the top and bottom of the FPGA, lanes 0 and
1 are placed on one edge and lanes 2 and 3 on the opposite
edge, with lane 0 and lane 2 aligned vertically with each
other. This will allow the optimum routing for the time-critical
channel bonding signals.
Register
Address
Register Name
DTE XS Control 1
5.0
5.1
DTE XS Status 1
Device Identifier
5.2,3
XAUI Register Block
5.4
DTE XS Speed Ability
Devices in Package
Reserved
The XAUI core contains registers as defined in Clause 45 of
the IEEE P802.3ae D4.1 draft. If the XAUI_TYPE_SEL pin
is “1,” the register set is that of a DTE XGXS entity. If the
XAUI_TYPE_SEL pin is “0,” the register set is that of a
10GBASE-X PCS/PMA entity. Note that this pin is regis-
tered into the core at power-up and hard reset, and cannot
be changed after that time; it is intended to be a static flag.
These registers are accessed through the MIIM interface of
the MAC. The XAUI_PRTAD port designates the address of
the XAUI/PCS on the MIIM interface.
5.5,6
5.7
5.8
DTE XS Status 2
Reserved
5.9 to 5.13
5.14,15
5.16 to 5.23
5.24
Package Identifier
Reserved
10G DTE XGXS Lane Status
10G DTE XGXS Test Control
5.25
5.26 to 5.65 535 Reserved
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The DTE XS Control Register is described in Table 22.
Table 22: DTE XS Control Register 1 (Register 5.0)
Bit(s)
5.0.15
Name
Reset
Description
Attributes
Default Value
1 = block reset
R/W
0
0 = normal operation
Self-clearing
The XAUI block is reset when this bit is set to “1.” It returns
to “0” when the reset is complete.
5.0.14
5.0.13
Loopback
1 = enable loopback mode
0 = disable loopback mode
R/W
0
1
The XAUI block will loop the signal in the MGTs back into
the receiver.
Speed
The block always returns “1” for this bit and ignores writes.
R/O
selection
5.0.12
5.0.11
Reserved
The block always returns “0” for this bit and ignores writes.
R/O
R/W
0
0
Power down
1 = Power down mode
0 = Normal operation
When set to “1,” the MGTs are placed in a low power state.
This bit requires a reset (see bit 5.0.15) to clear.
5.0.10:7
5.0.6
Reserved
The block always returns “0s” for these bits and ignores
writes.
R/O
R/O
R/O
R/O
0
Speed
selection
The block always return “1” for this bit and ignores writes.
1
5.0.5:2
5.0.1:0
Speed
Selection
The block always returns “0s” for these bits and ignores
writes.
All “0s”
All “0s”
Reserved
The block always returns “0s” for these bits and ignores
writes.
The DTE XS Status Register is described in Table 23.
Table 23: DTE XS Status Register 1 (Register 5.1)
Bit(s)
Name
Description
Attributes
Default Value
5.1.15:8
Reserved
The block always returns “0s” for these bits and ignores
R/O
All “0s”
writes.
5.1.7
Local Fault
Reserved
1 = Local fault detected
R/O
R/O
-
0 = no local fault detected
This bit is set to “1” whenever either of the bits 5.8.11,
5.8.10 are set to “1.”
5.1.6:3
The block always returns “0s” for these bits and ignores
All “0s”
writes.
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Table 23: DTE XS Status Register 1 (Register 5.1) (Continued)
Bit(s)
5.1.2
Name
Description
Attributes
Default Value
DTE XS
Receive Link
Status
1 = the DTE XS receive link is up
R/O
0 = the DTE XS receive link is down
This is a latching low version of bit 5.24.12.
-
Self-setting
5.1.1
5.1.0
Power down
ability
The block always returns “1” for this bit.
R/O
R/O
1
0
Reserved
The block always returns “0” for this bit and ignores writes.
The DTE XS Identifier Register is described in Table 24.
Table 24: DTE XS Identifier (Registers 5.2 and 5.3)
Bit(s)
Name
Description
Attributes
Default Value
5.2.15:0
DTE XS
The block always returns “0” for these bits and ignores
R/O
All “0s”
Identifier
writes
5.3.15:0
DTE XS
Identifier
The block always returns “0” for these bits and ignores
writes
R/O
All “0s”
The DTE XS Speed Ability Register is described in Table 25.
Table 25: DTE XS Speed Ability Register (Register 5.4)
Bit(s)
Name
Description
Attribute
Default Value
5.4.15:1
Reserved
The block always returns “0” for these bits and ignores
R/O
All “0s”
writes
5.4.0
10G Capable The block always returns “1” for this bit and ignores
R/O
1
writes.
The Devices in Package Register is described in Table 26.
Table 26: Devices in Package (Register 5.5 and 5.6)
Bit(s)
5.6.15
Name
Description
Attributes
Default Value
Vendor-
The block always returns “0” for this bit.
R/O
0
specific device
present
5.6.14:0
5.6.15:6
5.5.5
Reserved
Reserved
The block always returns “0” for these bits.
The block always returns “0” for these bits.
The block always returns “1” for this bit.
R/O
R/O
R/O
All “0s”
All “0s”
All “0s”
DTE XS
Present
5.5.4
PHY XS
Present
The block always returns “0” for this bit.
R/O
0
5.5.3
5.5.2
5.5.1
PCS Present
WIS Present
The block always returns “0” for this bit.
The block always returns “0” for this bit.
The block always returns “0” for this bit.
R/O
R/O
R/O
0
0
0
PMA/PMD
Present
5.5.0
Clause 22
The block always returns “0” for this bit.
R/O
0
device present
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The DTE XS Status Register 2 is described in Table 27.
Table 27: DTE XS Status Register 2 (Register 5.8)
Bit(s)
5.8.15:14 Device present The block shall always return “10.”
5.8.13:12 Reserved The block always returns “0” for these bits.
Name
Description
Attributes
R/O
Default Value
“10”
All “0s”
-
R/O
5.8.11
5.8.10
5.8.9:0
Transmit Local 1 = Fault condition on transmit path
R/O
Fault
0 = No fault condition on transmit path
Latching high
Receive local
fault
1 = Fault condition on receive path
0 = No fault condition on receive path
R/O
-
Latching high
Reserved
The block always returns “0” for these bits.
R/O
All “0s”
The Package Identifier Register is described in Table 28
Table 28: Package Identifier (Registers 5.14 and 5.15)
Bit(s)
Name
Description
Attributes
Default Value
5.14.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
5.15.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
The DTE Lane Status Register is described in Table 29
Table 29: DTE XS Lane Status Register (Register 5.24)
Bit(s)
Name
Description
Attributes
R/O
Default Value
5.24.15:13 Reserved
The block always returns “0” for these bits.
All “0s”
5.24.12
5.24.11
DTE XGXS
Lane
Alignment
Status
1 = DTE XGXS receive lanes aligned;
0 = DTE XGXS receive lanes not aligned.
RO
-
Pattern testing The block always returns “1” for this bit.
R/O
1
ability
5.24.10:4
5.24.3
Reserved
The block always returns “0” for these bits.
R/O
R/O
All “0s”
Lane 3 Sync
1 = Lane 3 is synchronized;
-
0 = Lane 3 is not synchronized.
5.24.2
5.24.1
5.24.0
Lane 2 Sync
Lane 1 Sync
Lane 0 Sync
1 = Lane 2 is synchronized;
R/O
R/O
R/O
-
-
-
0 = Lane 2 is not synchronized.
1 = Lane 1 is synchronized;
0 = Lane 1 is not synchronized.
1 = Lane 0 is synchronized;
0 = Lane 0 is not synchronized.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The DTE XS Test Control Register is shown in Table 30.
Table 30: 10G DTE XS Test Control register (Register 5.25)
Bit(s)
5.25.15:3
5.25.2
Name
Description
Attributes
R/O
Default Value
Reserved
The block always returns “0” for these bits.
All “0s”
Transmit test
pattern enable
1 = Transmit test pattern enable
0 = Transmit test pattern disabled
R/W
0
5.25.1:0
Test pattern
select
11 = reserved
R/W
“00”
10 = mixed frequency test pattern
01 = low frequency test pattern
00 = high frequency test pattern
10GBASE-X PCS/PMA Registers
The management registers for the 10GBASE-X PCS/PMA implementation of the XAUI block are shown in Table 31. The
10GBASE-X PCS/PMA occupies device addresses 1 and 3.
Table 31: 10GBASE-X PCS/PMA Registers
Register Address
Register Name
PMA/PMD Control 1
1.0
1.1
PMA/PMD Status 1
Device Identifier
1.2,3
1.4
PMA/PMD Speed Ability
Devices in Package
10G PMA/PMD Control 2
10G PMA/PMD Status 2
Reserved
1.5,6
1.7
1.8
1.9
1.10
10G PMD Receive Signal OK
Reserved
1.11 to 1.13
1.14,15
1.16 to 1.65 535
3.0
Package Identifier
Reserved
PCS Control 1
3.1
PCS Status 1
3.2,3
Device Identifier
3.4
PCS Speed Ability
Devices in Package
10G PCS Control 2
10G PCS Status 2
Reserved
3.5,6
3.7
3.8
3.9 to 3.13
3.14,15
3.16 to 3.23
3.24
Package Identifier
Reserved
10GBASE-X PCS Status
10GBASE-X PCS Test Control
Reserved
3.25
3.26 to 3.65 535
The PMA/PMD Control Register 1 is described in Table 32.
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Table 32: PMA/PMD Control Register 1 (Register 1.0)
Bit(s)
1.0.15
Name
Reset
Description
Attributes
Default Value
1 = block reset
R/W
0
0 = normal operation
Self-clearing
The XAUI block is reset when this bit is set to “1.” It returns
to “0” when the reset is complete.
1.0.14
1.0.13
1.0.12
1.0.11
Reserved
The block always returns “0” for this bit and ignores
writes.
R/O
R/O
R/O
R/W
0
1
0
0
Speed
Selection
The block always returns “1” for this bit and ignores
writes.
Reserved
The block always returns “0” for this bit and ignores
writes.
Power down
1 = Power down mode
0 = Normal operation
When set to “1,” the MGTs are placed in a low power
state. This bit requires a reset (see bit 1.0.15) to clear.
1.0.10:7
1.0.6
Reserved
The block always returns “0” for these bits and ignores
writes.
R/O
R/O
R/O
All “0s”
1
Speed
selection
The block always return “1” for this bit and ignores writes.
1.0.5:2
Speed
The block always returns “0s” for these bits and ignores
All “0s”
Selection
writes.
1.0.1
1.0.0
Reserved
Loopback
The block always returns “0” for this bit and ignores writes
R/O
All “0s”
1 = enable loopback mode
0 = disable loopback mode
R/W
0
The XAUI block will loop the signal in the MGTs back into
the receiver.
The PMA/PMD Status Register 1 is described in Table 33.
Table 33: PMA/PMD Status Register 1 (Register 1.1)
Bit(s)
1.1.15:8
1.1.7
Name
Reserved
Local Fault
Description
Attributes
R/O
Default Value
The block always returns “0” for this bit.
0
-
1 = Local fault detected
R/O
0 = no local fault detected
This bit is set to “1” whenever either of the bits 1.8.11,
1.8.10 are set to “1.”
1.1.6:3
1.1.2
Reserved
The block always returns “0” for this bit.
The block always returns “1” for this bit.
R/O
R/O
0
1
Receive link
Status
1.1.1
1.1.0
Power down
ability
The block always returns “1” for this bit.
The block always returns “0” for this bit.
R/O
R/O
1
0
Reserved
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The Device Identifier Register is described in Table 34.
Table 34: Device Identifier (Registers 1.2 and 1.3)
Bit(s)
Name
Description
Attributes
Default Value
1.2.15:0
DTE XS
The block always returns “0” for these bits and ignores
R/O
All “0s”
Identifier
writes.
1.3.15:0
DTE XS
Identifier
The block always returns “0” for these bits and ignores
writes.
R/O
All “0s”
The PMA/PMS Speed Ability Register is shown in Table 35.
Table 35: PMA/PMD Speed Ability Register (Register 14)
Bit(s)
Name
Description
Attribute
Default Value
1.4.15:1
Reserved
The block always returns “0” for these bits and ignores
R/O
All “0s”
writes.
1.4.0
10G Capable The block always returns “1” for this bit and ignores
R/O
1
writes.
The Devices in Package Register is described in Table 36
Table 36: Devices in Package (Register 1.5 and 1.6)
Bit(s)
1.6.15
Name
Description
Attributes
Default Value
Vendor-
The block always returns “0” for this bit.
R/O
0
specific device
present
1.6.14:0
1.6.15:6
1.5.5
Reserved
Reserved
The block always returns “0” for these bits.
The block always returns “0” for these bits.
The block always returns “0” for this bit.
R/O
R/O
R/O
All “0s”
All “0s”
0
DTE XS
Present
1.5.4
PHY XS
Present
The block always returns “0” for this bit.
R/O
0
1.5.3
1.5.2
1.5.1
PCS Present
WIS Present
The block always returns “1” for this bit.
The block always returns “0” for this bit.
The block always returns “1” for this bit.
R/O
R/O
R/O
1
0
1
PMA/PMD
Present
1.5.0
Clause 22
The block always returns “0” for this bit.
R/O
0
device present
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The 10G PMA/PMD Control Register 2 is described in Table 37.
Table 37: 10G PMA/PMD Control Register 2 (Register 1.7)
Bit(s)
Name
Description
Attributes
Default Value
1.7.15:3
Reserved
The block always returns “0” for these bits and ignores
R/O
All “0s”
writes
1.7.2:0
PMA/PMD
The block always returns “100” for these bits and ignores
R/O
“100”
Type Selection writes. This corresponds to the 10GBASE-X PMA/PMD.
The 10G PMA/PMD Status Register 2 is described in Table 38
Table 38: 10G PMA/PMD Status Register 2 (Register 1.8)
Bit(s)
Name
Description
Attributes
R/O
Default Value
1.8.15:14 Device Present The block always returns “10” for these bits.
“10”
1.8.13
1.8.12
Transmit Local The block always returns “0” for this bit.
Fault Ability
R/O
0
Receive Local
Fault Ability
The block always returns “0” for this bit.
R/O
0
1.8.9
1.8.8
Reserved
The Block always returns “0” for this bit.
The block always returns “0” for this bit.
R/O
R/O
0
0
PMD Transmit
Disable Ability
1.8.7
1.8.6
1.8.5
1.8.4
1.8.3
1.8.2
1.8.1
1.8.0
10GBASE-SR
Ability
The block always returns “0” for this bit.
The block always returns “0” for this bit.
The block always returns “0” for this bit.
R/O
R/O
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
1
0
0
0
1
10GBASE-LR
Ability
10GBASE-ER
Ability
10GBASE-LX4 The block always returns “1” for this bit.
Ability
10GBASE-SW The block always returns “0” for this bit.
Ability
10GBASE-LW
Ability
The block always returns “0” for this bit.
10GBASE-EW The block always returns “0” for this bit.
Ability
PMA Loopback The block always returns “1” for this bit.
Ability
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The 10G PMD Signal Receive OK Register is described in Table 39.
Table 39: 10G PMD Signal Receive OK Register (Register 1.10)
Bit(s)
Name
Description
Attributes
R/O
Default Value
1.10.15:5 Reserved
The block always returns “0s” for these bits.
All “0s”
1.10.4
1.10.3
1.10.2
1.10.1
1.10.0
PMD receive
signal OK 3
1 = Signal OK on receive lane 3
R/O
-
0 = Signal not OK on receive lane 3
This is the value of the SIGNAL_DETECT[3] port.
PMD receive
signal OK 2
1 = Signal OK on receive lane 2
R/O
R/O
R/O
R/O
-
-
-
-
0 = Signal not OK on receive lane 2
This is the value of the SIGNAL_DETECT[2] port.
PMD receive
signal OK 1
1 = Signal OK on receive lane 1
0 = Signal not OK on receive lane 1
This is the value of the SIGNAL_DETECT[1] port.
PMD receive
signal OK 0
1 = Signal OK on receive lane 0
0 = Signal not OK on receive lane 0
This is the value of the SIGNAL_DETECT[0] port.
Global PMD
Receive
Signal OK
1 = Signal OK on all receive lanes
0 = signal not OK on all receive lanes
The Package Identifier Register is described in Table 40.
Table 40: Package Identifier (Registers 1.14 and 1.15)
Bit(s)
Name
Description
Attributes
Default Value
1.14.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
1.15.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
The PCS Control Register 1 is described in Table 41.
Table 41: PCS Control Register 1 (Register 3.0)
Bit(s)
3.0.15
Name
Reset
Description
Attributes
Default Value
1 = block reset
R/W
0
0 = normal operation
Self-clearing
The XAUI block is reset when this bit is set to “1.” It returns
to “0” when the reset is complete.
3.0.14
3.0.13
3.0.12
10GBASE-R
Loopback
The block always returns “0” for this bit and ignores
writes.
R/O
R/O
R/O
0
1
0
Speed
Selection
The block always returns “1” for this bit and ignores
writes.
Reserved
The block always returns “0” for this bit and ignores
writes.
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Table 41: PCS Control Register 1 (Register 3.0) (Continued)
Bit(s)
3.0.11
Name
Description
Attributes
Default Value
Power down
1 = Power down mode
0 = Normal operation
R/W
0
When set to “1,” the MGTs are placed in a low power
state. This bit requires a reset (see bit 3.0.15) to clear.
3.0.10:7
3.0.6
Reserved
The block always returns “0” for these bits and ignores
writes.
R/O
R/O
R/O
R/O
All “0s”
1
Speed
selection
The block always return “1” for this bit and ignores writes.
3.0.5:2
3.0.1:0
Speed
Selection
The block always returns “0s” for these bits and ignores
writes.
All “0s”
All “0s”
Reserved
The block always returns “0” for this bit and ignores writes
The PCS Status Register 1 is described in Table 42.
Table 42: PCS Status Register 1 (Register 3.1)
Bit(s)
Name
Description
Attributes
Default Value
3.1.15:8
Reserved
The block always returns “0”s for these bits and ignores
R/O
All “0s”
writes
3.1.7
Local Fault
1 = Local fault detected
R/O
R/O
-
0 = no local fault detected
This bit is set to “1” whenever either of the bits 3.8.11,
3.8.10 are set to “1.”
3.1.6:3
3.1.2
Reserved
The block always returns “0s” for these bits and ignores
writes
All “0s”
PCS Receive
Link Status
1 = the PCS receive link is up
R/O
-
0 = the PCS receive link is down
This is a latching low version of bit 3.24.12
Self-setting
3.1.1
3.1.0
Power down
ability
The block always returns “1” for this bit.
R/O
R/O
1
0
Reserved
The block always returns “0” for this bit and ignores writes
The Device Identifier Register is described in Table 43.
Table 43: Device Identifier (Registers 3.2 and 3.3)
Bit(s)
Name
Description
Attributes
Default Value
3.2.15:0
PCS Identifier The block always returns “0” for these bits and ignores
R/O
All “0s”
writes
3.3.15:0
PCS Identifier The block always returns “0” for these bits and ignores
R/O
All “0s”
writes
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The PCS Speed Ability Register is described in Table 44.
Table 44: PCS Speed Ability Register (Register 3.4)
Bit(s)
Name
Description
Attribute
Default Value
3.4.15:1
Reserved
The block always returns “0” for these bits and ignores
R/O
All “0s”
writes.
3.4.0
10G Capable The block always returns “1” for this bit and ignores
R/O
1
writes.
The Devices in Package Register is described in Table 45.
Table 45: Devices in Package (Register 3.5 and 3.6)
Bit(s)
3.6.15
Name
Description
Attributes
Default Value
Vendor
The block always returns “0” for this bit.
R/O
0
specific device
present
3.6.14:0
3.6.15:6
3.5.5
Reserved
Reserved
The block always returns “0” for these bits.
The block always returns “0” for these bits.
The block always returns “0” for this bit.
R/O
R/O
R/O
All “0s”
All “0s”
0
DTE XS
Present
3.5.4
PHY XS
Present
The block always returns “0” for this bit.
R/O
0
3.5.3
3.5.2
3.5.1
PCS Present
WIS Present
The block always returns “1” for this bit.
The block always returns “0” for this bit.
The block always returns “1” for this bit.
R/O
R/O
R/O
1
0
1
PMA/PMD
Present
3.5.0
Clause 22
The block always returns “0” for this bit.
R/O
0
device present
The 10G PCS Control Register 2 is described in Table 46.
Table 46: 10G PCS Control Register 2 (Register 3.7)
Bit(s)
Name
Description
Attributes
Default Value
3.7.15:2
Reserved
The block always returns “0” for these bits and ignores
R/O
All “0s”
writes.
3.7.1:0
PCS Type
Selection
The block always returns “01” for these bits and ignores
writes.
R/O
“01”
The 10G PCS Status Register 2 is described in Table 47.
Table 47: 10G PCS Status Register 2 (Register 3.8)
Bit(s)
3.8.15:14 Device present The block always returns “10.”
3.8.13:12 Reserved The block always returns “0” for these bits.
3.8.11 Transmit Local 1 = Fault condition on transmit path
Name
Description
Attributes
R/O
Default Value
“10”
All “0s”
-
R/O
R/O
Fault
0 = No fault condition on transmit path
Latching high
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Table 47: 10G PCS Status Register 2 (Register 3.8) (Continued)
Bit(s)
3.8.10
Name
Description
Attributes
Default Value
Receive local
fault
1 = Fault condition on receive path
0 = No fault condition on receive path
R/O
-
Latching high
3.8.9:3
3.8.2
Reserved
The block always returns “0” for these bits.
The block always returns “0” for this bit.
R/O
R/O
All “0s”
10GBASE-W
Capable
0
3.8.1
3.8.0
10GBASE-X
Capable
The block always returns “1” for this bit.
The block always returns “0” for this bit.
R/O
R/O
1
0
10GBASE-R
Capable
The Package Identifier register is described in Table 48.
Table 48: Package Identifier (Registers 3.14 and 3.15)
Bit(s)
Name
Description
Attributes
Default Value
3.14.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
3.15.15:0 Package
Identifier
The block always returns “0” for these bits.
R/O
All “0s”
The 10GBASE-X Status Register is described in Table 49.
Table 49: 10GBASE-X Status Register (Register 3.24)
Bit(s)
Name
Description
Attributes
R/O
Default Value
3.24.15:13 Reserved
The block always returns “0” for these bits.
All “0s”
3.24.12
3.24.11
10GBASE-X
Lane
Alignment
Status
1 = 10GBASE-X receive lanes aligned;
0 = 10GBASE-X receive lanes not aligned.
RO
-
Pattern testing The block always returns “1” for this bit.
R/O
1
ability
3.24.10:4
3.24.3
Reserved
The block always returns “0” for these bits.
R/O
R/O
All “0s”
Lane 3 Sync
1 = Lane 3 is synchronized;
-
0 = Lane 3 is not synchronized.
3.24.2
3.24.1
3.24.0
Lane 2 Sync
Lane 1 Sync
Lane 0 Sync
1 = Lane 2 is synchronized;
R/O
R/O
R/O
-
-
-
0 = Lane 2 is not synchronized
1 = Lane 1 is synchronized;
0 = Lane 1 is not synchronized.
1 = Lane 0 is synchronized;
0 = Lane 0 is not synchronized.
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10-Gigabit Ethernet MAC with XGMII or XAUI v2.1
The 10GBASE-X Test Control Register is described in Table 50.
Table 50: 10GBASE-X Test Control register (Register 5.25)
Bit(s)
3.25.15:3
3.25.2
Name
Description
Attributes
R/O
Default Value
Reserved
The block always returns “0” for these bits.
All “0s”
Transmit test
pattern enable
1 = Transmit test pattern enable
0 = Transmit test pattern disabled
R/W
0
3.25.1:0
Test pattern
select
11 = reserved
R/W
“00”
10 = mixed frequency test pattern
01 = low frequency test pattern
00 = high frequency test pattern
MDIO Interface
The MDIO interface pins (MDC, MDIO_IN, MDIO_OUT,
MDIO_TRI) are brought out of the core separately for maxi-
mum flexibility. They can be:
Table 51: Optional blocks - approximate resource
usage
Optional block
XGMII
XAUI
•
•
connected to an IOBUF to drive an external tristate bus
Statistics Included
3750 slices
3000 slices
4400 slices
3700 slices
connected through individual IBUFs and OBUFs to a
level shifter to create a fully compliant Clause 45 MDIO
interface
Statistics
Excluded
•
connected to an internal SoC management interface
Please contact Xilinx for more information on these configu-
rations.
References
•
•
•
•
IEEE P802.3ae D4.1 draft specification
Related Information
IEEE 802.3-2000
Xilinx products are not intended for use in life support appli-
ances, devices, or systems. Use of a Xilinx product in such
applications without the written consent of the appropriate
Xilinx officer is prohibited.
Virtex-II User Guide
Virtex-II Pro User Guide
Optional Blocks
Copyright 1991-2002 Xilinx, Inc. All rights reserved.
Xilinx can deliver instances of the core with the optional
functional blocks left out. This can significantly reduce logic
consumption in lightweight applications.
Ordering Information
This Xilinx LogiCORE product is provided under the
SignOnceIP Site License. A free evaluation version of the
product is available from the Xilinx IP Evaluation Lounge, at
http://www.xilinx.com/ipcenter/ipevaluation/index.htm.
The optional blocks are:
•
Statistical Counters included or excluded from the
netlist
•
XGMII or XAUI interface to the PHY
Please refer to the product page for this core on the Xilinx IP
Center, http://www.xilinx.com/ipcenter/index.htm, for part
number and pricing information. To purchase this core, con-
tact your local Xilinx sales representative. Information on
additional Xilinx LogiCORE modules is available on the Xil-
inx IP Center.
Table 51 provides some indication of the resource savings
that can be made. Note that these numbers are approxi-
mate and will depend to some extent on the customer
design.
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