CY7C68300-56LFC_技术文档

CY7C68300

EZ-USB AT2™

USB 2.0 to ATA/ATAPI Bridge

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-08011 Rev. *A

Revised August 30, 2002

CY7C68300

CONTENTS

1.0 INTRODUCTION ..............................................................................................................................4

1.1 Features ...........................................................................................................................................4

2.0 PIN ASSIGNMENTS ........................................................................................................................6

2.1 Pin Diagram .....................................................................................................................................6

2.2 Pin Descriptions .............................................................................................................................8

2.3 Additional Pin Descriptions .........................................................................................................10

3.0 APPLICATIONS .............................................................................................................................11

3.1 Additional Resources ...................................................................................................................11

4.0 FUNCTIONAL OVERVIEW ............................................................................................................11

4.1 USB Signaling Speed ...................................................................................................................11

4.2 ATA Interface ................................................................................................................................11

5.0 ENUMERATION .............................................................................................................................11

5.1 Board Manufacturing Test Mode .................................................................................................11

5.2 Normal Operation Mode ...............................................................................................................13

5.3 EEPROM Organization .................................................................................................................13

6.0 ABSOLUTE MAXIMUM RATINGS ................................................................................................22

7.0 OPERATING CONDITIONS^[3].........................................................................................................22

8.0 DC CHARACTERISTICS ...............................................................................................................22

9.0 AC ELECTRICAL CHARACTERISTICS .......................................................................................22

9.1 USB Transceiver ...........................................................................................................................22

9.2 ATA Timing ....................................................................................................................................22

10.0 ORDERING INFORMATION ........................................................................................................23

11.0 PACKAGE DIAGRAMS ...............................................................................................................23

12.0 PCB LAYOUT RECOMMENDATIONS^{[4] ......................................................................................................................................24}

13.0 QUAD FLAT PACKAGE NO LEADS (QFN) PACKAGE DESIGN NOTES ................................24

14.0 OTHER DESIGN CONSIDERATIONS .........................................................................................25

14.1 Proper Power-up Sequence .......................................................................................................25

14.2 IDE Removable Media Devices ..................................................................................................25

14.3 Devices With Small Buffers .......................................................................................................25

LIST OF FIGURES

Figure 1-1. Block Diagram .................................................................................................................... 5

Figure 2-1. 56-pin SSOP........................................................................................................................ 6

Figure 2-2. 56-pin QFN .......................................................................................................................... 7

Figure 2-3. XTALIN, XTALOUT Diagram ............................................................................................ 10

Figure 2-4. Typical Reset Circuit........................................................................................................ 10

Figure 11-1. 56-lead Shrunk Small Outline Package 056 .................................................................23

Figure 11-2. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56 ........................................................ 23

Figure 13-1. Cross-Section of the Area Underneath the QFN Package.......................................... 24

Figure 13-2. Plot of the Solder Mask (white area)............................................................................. 25

Figure 13-3. X-ray Image of the Assembly ........................................................................................ 25

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CY7C68300

LIST OF TABLES

Table 5-1. Command Block Wrapper ................................................................................................11

Table 5-2. Example CfgCB .................................................................................................................12

Table 5-3. Example MfgCB .................................................................................................................12

Table 5-4. Mfg_load Data Format ......................................................................................................12

Table 5-5. Mfg_read Data Format ......................................................................................................13

Table 5-6. EEPROM Organization ......................................................................................................14

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CY7C68300

1.0

Introduction

The EZ-USB AT2 implements a fixed function bridge between one USB port and one ATA- or ATAPI-based mass storage device

port. This bridge adheres to the Mass Storage Class Bulk-Only Transport specification and is intended for self-powered devices.

The USB port of the EZ-USB AT2 is connected to a host computer directly or via the downstream port of a USB hub. Host software

issues commands and data to the EZ-USB AT2 and receives status and data from the EZ-USB AT2 using standard USB protocol.

The ATA/ATAPI port of the EZ-USB AT2 is connected to a mass storage device. A 4Kbyte buffer maximizes ATA/ATAPI data

transfer rates by minimizing losses due to device seek times. The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra

DMA modes 2 and 4.

The device initialization process is configurable, enabling the EZ-USB AT2 to initialize ATA/ATAPI devices without software

intervention.

1.1

Features

• Complies with USB-IF specifications for USB 2.0, the USB Mass Storage Class, and the USB Mass Storage Class

Bulk-Only Transport

• Operates at high (480 Mbps) or full (12 Mbps) speed

• Complies with T13’s ATA/ATAPI-6 Draft Specification

• Supports 48-bit addressing for large hard drives

• Supports PIO modes 0, 3, 4, and UDMA modes 2, 4

• Uses one external serial EEPROM containing the USB device serial number, vendor and product identification data,

and device configuration data

• ATA interface IRQ signal support

• Support for ATA/ATAPI devices configured either as master or slave

• “ATA-Enable” input signal, which three-states all signals on the ATA interface in order to allow sharing of the bus

with another controller (e.g., an IEEE-1394 to ATA bridge chip)

• Support for board-level manufacturing test via USB interface

• 3.3V operation for self-powered devices

• 56-pin SSOP and 56-pin QFN packages

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CY7C68300

SCL

I2C-Compatible

BusController

SDA

24

MHz

PLL

XTAL

ATA_EN (ATA Interface 3-

state)

AT2 Internal Logic

ATA Interface

Control Signals

Control

ATA

Interface

Logic

16 Bit ATA Data

VBUS

D+

D-

CY Smart USB

FS/HSEngine

USB 2.0 XCVR

4kByte FIFO

Data

Figure 1-1. Block Diagram

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CY7C68300

2.0

2.1

Pin Assignments

Pin Diagram

1

2

3

4

5

6

DD13

DD14

56

DD12

DD11 55

54

DD15

GND

NC

DD10

53

52

51

DD9

DD8

Vcc

ATA_EN

Vcc

7

8

9

GND

IORDY

DMARQ

50

49

48

47

46

RESET#

GND

10 AVcc

11

12 XTALIN

ARESET#

VBUS_PWR_VALID

CS1#

XTALOUT

45

44

43

42

41

40

39

38

37

36

35

13

14

15

16

AGND

Vcc

CS0#

EZ-USB AT2

CY7C68300

DA2

DA1

DPLUS

DMINUS

DA0

17 GND

18 Vcc

INTRQ

Vcc

19

GND

DMACK#

DIOR#

DIOW#

GND

20 PU10K

21 RESERVED

22 SCL

23 SDA

24 Vcc

25 DD0

26 DD1

34

33

Vcc

GND

DD7 32

DD6 31

27

30

DD2

DD5

28 DD3

DD4 29

Figure 2-1. 56-pin SSOP

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CY7C68300

IORDY

DMARQ

AVCC

1

2

42

41

40

RESET#

GND

3

ARESET#

XTALOUT

XTALIN

AGND

VCC

4

39 VBUS_PWR_VALID

5

38

37

36

35

34

33

32

31

30

29

CS1#

CS0#

DA2

6

EZ-USB AT2

CY7C68300

56-pin QFN

7

DPLUS

DMINUS

GND

8

DA1

9

DA0

10

11

12

13

INTRQ

VCC

GND

DMACK#

DIOR#

DIOW#

PU10K

RESERVED 14

Figure 2-2. 56-pin QFN

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CY7C68300

2.2

Pin Descriptions

SSOP QFN

Default State at

Start-up

1

50

51

52

53

54

55

56

1

Pin Name

DD13

DD14

DD15

GND

Type

Pin Description

I/O^[1]

GND

Hi-Z

ATA Data bit 13.

ATA Data bit 14.

ATA Data bit 15.

Ground.

2

3

4

5

NC

Hi-Z

Reserved. This pin should remain a no-connect.

6

V_CC

PWR

GND

I^[1]

V_CC. Connect to 3.3V power source.

Ground.

7

GND

8

IORDY

DMARQ

AV_CC

I

ATA Control.

9

2

I^[1]

ATA Control.

10

3

PWR

Analog V_CC. Connect the V_CCthrough the shortest path

possible.

11

12

13

4

5

6

XTALOUT

XTALIN

AGND

Xtal

24-MHz Crystal Output (see subsection 2.3.3).

24-MHz Crystal Input (see subsection 2.3.3).

GND

Analog Ground. Connect to ground with as short a path as

possible.

14

15

7

8

V_CC

PWR

V_CC. Connect to 3.3V power source.

DPLUS

I/O Pulled high at Reset. USB D+ Signal (see subsection 2.3.1).

When the firmware

starts, the pullup is

controlled by pin

46(SSOP)/39(QFN).

When

VBUS_PWR_VALID

is high, the line is

pulled up.

VBUS_PWR_VALID

is polled at start-up

and then every

20ms.

16

17

18

19

20

21

22

23

9

DMINUS

GND

I/O

Hi-Z

USB D- Signal (see subsection 2.3.1).

Ground.

10

11

12

13

14

15

16

GND

PWR

GND

V_CC

V_CC. Connect to 3.3V power source.

Ground.

GND

PU10K

RESERVED

SCL

Tied to 10k ± 5% pull-up resistor.

Reserved. Tie to GND.

O

SCL/SDA will be ac- Clock signal for I²C-compatible interface (see 2.3.2).

tive for several ms at

start-up.Thendriven

high.

SDA

I/O

Data signal for I²C-compatible interface (see 2.3.2).

24

25

26

27

28

29

17

18

19

20

21

22

23

V_CC

DD0

DD1

DD2

DD3

DD4

DD5

PWR

I/O

V_CC. Connect to 3.3V power source.

Hi-Z

ATA Data bit 0.

ATA Data bit 1.

ATA Data bit 2.

ATA Data bit 3.

ATA Data bit 4.

ATA Data bit 5.

I/O

30

I/O

Notes:

1. ATA interface pins are not active when ATA_EN is not asserted.

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CY7C68300

2.2

Pin Descriptions (continued)

SSOP QFN

Default State at

Start-up

31

32

33

34

35

36

37

38

39

40

41

24

25

26

27

28

29

30

31

32

33

34

Pin Name

Type

Pin Description

DD6

I/O

Hi-Z

ATA Data bit 6.

ATA Data bit 7.

Ground.

DD7

I/O

GND

PWR

GND

V_CC

V_CC. Connect to 3.3V power source.

Ground.

GND

DIOW#^[2]

DIOR#

DMACK#

V_CC

O/Z^[1]Driven high (CMOS) ATA Control.

PWR

I^[1]

V_CC. Connect to 3.3V power source.

INTRQ

DA0

Input

IDE ATA Interrupt request.

ATA Address.

O/Z^[1]Driven high after

2ms delay

42

43

44

45

46

35

36

37

38

DA1

DA2

O/Z^[1]Driven high after

2ms delay

O/Z^[1]Driven high after

2ms delay

O/Z^[1]Driven high after

2ms delay

O/Z^[1]Driven high after

2ms delay

ATA Address.

CS0#

CS1#

ATA Chip Select.

39 VBUS_PWR_VALID

I

Input

VBUS detection. Indicates to the EZ-USB AT2 that VBUS

power is present.

47

48

49

40

41

42

ARESET#

GND

O/Z^[1]

GND

I

ATA Reset.

Ground.

RESET#

Active LOW Reset. Resets the entire chip. This pin is

normally tied to VCC through a 100K resistor, and to GND

through a 0.1-µF capacitor, supplying a 10-ms reset.

50

51

43

44

V_CC

PWR

I

V_CC. Connect to 3.3V power source.

ATA_EN

Input - If AT2 is not in Active HIGH. ATA interface enable. Allows ATA bus sharing

mfg mode, polled

every 20 ms after

start-up. If LOW,

with other host devices. Setting ATA_EN=1 enables the ATA

interface for normal operation. Disabling ATA_EN three-

states (High-Z) the ATA interface and halts the ATA interface

SSOP: pins 36-38, state machine logic.

41-45 and 47 are

three-stated.

QFN: pins 29-31,

34-38 and 40 are

three-stated.

52

53

54

55

45

46

47

48

49

DD8

DD9

I/O^[1]

Hi-Z

ATA Data bit 8.

ATA Data bit 9.

ATA Data bit 10.

ATA Data bit 11.

ATA Data bit 12.

DD10

DD11

DD12

56

Note:

2. A # sign after the signal name indicates it is an active LOW signal.

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CY7C68300

2.3

Additional Pin Descriptions

DPLUS, DMINUS

2.3.1

DPLUS and DMINUS are the USB signaling pins, and they should be tied to the D+ and D– pins of the USB connector. Because

they operate at high frequencies, the USB signals require special consideration when designing the layout of the PCB.

2.3.2

SCL, SDA

The clock and data pins for the I²C-compatible port should be connected to your configuration EEPROM and to V_CCthrough 2.2k

resistors.

2.3.3

XTALIN, XTALOUT

The EZ-USB AT2 requires a 24-MHz signal to derive internal timing. Typically a 24-MHz parallel-resonant fundamental mode

crystal is used, but a 24-MHz square wave from another source can also be used. If a crystal is used, connect the pins to XTALIN

and XTALOUT, and also through 20-pF capacitors to GND. If an alternate clock source is used, apply it to XTALIN and leave

XTALOUT open.

24MHz crystal

20pF

Figure 2-3. XTALIN, XTALOUT Diagram

2.3.4

ATA_EN

ATA_EN allows bus sharing with other host devices. Setting ATA_EN = 1 enables the ATA interface for normal operation. Setting

ATA_EN = 0 disables (High-Z) the ATA interface pins and removes the EZ-USB AT2 from the USB. The ATA_EN pin is sampled

at a rate of 60 times per second by the EZ-USB AT2 internal logic. This pin should be set to a HIGH at start-up. Upon a HIGH to

LOW transition all EZ-USB AT2 ATA signals are tri-stated, USB is disconnected, and the EZ-USB AT2 enters an idle state until

an active Reset is received, or the ATA_EN pin transitions back to a HIGH state. Upon sensing the LOW to HIGH transition the

EZ-USB AT2 will return to the post Reset operational state, and will reconnect to USB. Note that disabling the ATA bus with the

ATA_EN pin during the middle of a data transfer will result in data loss and can cause the operating system on the Host computer

to crash.

2.3.5

ATA Interface Pins

Design practices as outlined in the ATA/ATAPI -6 Specification for signal integrity should be followed with systems that utilize a

ribbon cable interconnect between the EZ-USB AT2’s ATA interface and the attached ATA/ATAPI device, especially if Ultra DMA

Mode is utilized.

2.3.6

VBUS_PWR_VALID

VBUS_PWR_VALID indicates to the EZ-USB AT2 that power is present on VBUS.

2.3.7

RESET#

Asserting RESET# for 10 ms will reset the entire chip. This pin is normally tied to V_CCthrough a 100k resistor, and to GND through

a 0.1-µF capacitor.

R

8

1 0 0 K

N

R E S E T

C

1

0 . 1 u F d

Figure 2-4. Typical Reset Circuit

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CY7C68300

3.0

Applications

The EZ-USB AT2 is a high-speed USB 2.0 peripheral device that connects ATA or ATAPI storage devices to a USB host using

the USB Mass Storage Class protocol.

3.1

Additional Resources

• CY4615 EZ-USB AT2 Reference Design Kit

• USB Specification version 2.0

• ATA Specification T13/1410D Rev 3B

• Universal Serial Bus Mass Storage Class Bulk Only Transport Specification, http://www.usb.org/devel-

opers/data/devclass/usbmassbulk_10.pdf.

4.0

4.1

Functional Overview

USB Signaling Speed

EZ-USB AT2 operates at two of the three rates defined in the Universal Serial Bus Specification Revision 2.0 dated April 27, 2000:

• Full speed, with a signaling bit rate of 12 Mbits/sec

• High speed, with a signaling bit rate of 480 Mbits/sec.

EZ-USB AT2 does not support the low-speed signaling rate of 1.5 Mbits/sec.

4.2

ATA Interface

The ATA/ATAPI port on the EZ-USB AT2 is compliant with the Information Technology AT Attachment with Packet Interface 6

(ATA/ATAPI-6) Specification, T13/1410D Rev 3B. The EZ-USB AT2 supports both ATAPI packet commands over USB. Addition-

ally, the EZ-USB AT2 translates ATAPI SFF-8070i commands to ATA commands for seamless integration of ATA devices with

generic Mass Storage Class BOT drivers.

5.0

Enumeration

During the power-up sequence, internal logic checks the I²C-compatible port for an EEPROM whose first two bytes are both

0x4D. If a valid signature is found, the EZ-USB AT2 uses the values stored in the EEPROM to configure the USB descriptors for

normal operation. If an invalid EEPROM signature is read, or if no EEPROM is detected, the EZ-USB AT2 defaults into Board

Manufacturing Test Mode. The two modes of operation are described in subsections 5.1 and 5.2, below.

5.1

Board Manufacturing Test Mode

In Board Manufacturing Test Mode, the chip behaves as a USB 2.0 device but the ATA/ATAPI interface is not active. The EZ-USB

AT2 allows for reading and writing an EEPROM and for board level testing through vendor specific ATAPI commands utilizing the

CBW Command Block as described in the USB Mass Storage Class Bulk Only Transport specification. There is a vendor-specific

ATAPI command for the EEPROM access (CfgCB) and one for the board level testing (MfgCB).

5.1.1

CfgCB

The cfg_load and cfg_read vendor-specific commands are passed down through the bulk pipe in the CBWCB portion of the CBW.

The format of this CfgCB is shown below. Byte 0 will be a vendor-specific command designator whose value is configurable and

set in the configuration data (EEPROM address 0x04). Byte 1 must be set to 0x26 to identify CfgCB. Byte 2 is reserved and must

be set to zero. Byte 3 is used to determine the memory source to write/read. For the EZ-USB AT2, this byte must be set to 0x02,

meaning the EEPROM. Bytes 4 and 5 will be used to determine the start address. For the EZ-USB AT2, this must always be

0x0000. Bytes 6 through 15 are reserved and should be set to zero.

The data transferred to the EEPROM must be in the format specified in Table 5-6 of this data sheet. Maximum data transfer size

is 255 bytes.

The data transfer length is determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTransfer-

Length) of the CBW. The type/direction of the command will be determined by the direction bit specified in byte 12, bit 7 (bmCB-

WFlags) of the CBW.

Table 5-1. Command Block Wrapper

7

6

5

4

3

2

1

0

0–3

4–7

DCBWSignature

dCBWTag

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CY7C68300

Table 5-1. Command Block Wrapper

7

6

5

4

3

2

1

0

8–11 (08h-0Bh)

12 (0Ch)

dCBWDataTransferLength

bwCBWFLAGS

Dir

Obsolete

Reserved (0)

13 (0Dh)

Reserved (0)

bCBWLUN

14 (0Eh)

bCBWCBLength

15-30 (0Fh1Eh)

Table 5-2. Example CfgCB

CBWCB (CfgCB or MfgCB)

CfgCB Byte Descriptions

Bits

7

0

6

0

5

1

0

4

0

3

0

2

1

0

1

0

1

0

1

0

0 bVSCBSignature (set in configuration bytes)

1 bVSCBSubCommand (must be 0x26)

2 Reserved (must be set to zero)

3 Data Source (must be set to 0x02)

4 Start Address (LSB) (must be set to zero)

5 Start Address (MSB) (must be set to zero)

6–15 Reserved (must be set to zero)

5.1.2

MfgCB

The mfg_load and mfg_read vendor-specific commands will be passed down through the bulk pipe in the CBWCB portion of the

CBW. The format of this MFGCB is shown below. Byte 0 is a vendor-specific command designator whose value is configurable

and set in the configuration data. Byte 1 must be 0x27 to identify MfgCB. Byte 2–15 are reserved and must be set to zero.

The data transfer length will be determined by the CBW Data Transfer Length specified in bytes 8 through 11 (dCBWDataTrans-

ferLength) of the CBW. The type/direction of the command is determined by the direction bit specified in byte 12, bit 7 (bmCBW-

Flags) of the CBW.

Table 5-3. Example MfgCB

MfgCB Byte Description

0 bVSCBSignature (set in configuration bytes)

1 bVSCBSubCommand (hardcoded 0x27)

2–15 Reserved (must be zero)

Bits

0

1

0

1

0

1

0

1

0

5.1.2.1 Mfg_load

During a mfg_load, the EZ-USB AT2 goes into Manufacturing Test Mode. Manufacturing Test Mode is provided as a means to

implement board or system level interconnect tests. During Manufacturing Test Mode operation, all outputs not directly associated

with USB operation are controllable. Normal control of the output pins are disabled. Control of the select EZ-USB AT2 IO pins

and their 3-state controls are mapped to the ATAPI data packet associated with this request. (See the following table for expla-

nation of the required mfg_load data format.) This requires a write of 7 bytes. To exit Manufacturing Test Mode, a hard reset

(#RESET) is required.

Table 5-4. Mfg_load Data Format

Byte

Bit(s)

Test/Tri-state Control Function

0

1

0

3:1

5:4

6

Reserved

DA[2:0]

CS#[1:0]

Reserved

ARESET#

NDIOW

7

0

1

NDIOR

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CY7C68300

Table 5-4. Mfg_load Data Format

Byte

Bit(s)

2

Test/Tri-state Control Function

1

2

3

4

5

6

NDMACK

Reserved

3:6

7

DD[15:0] Three-state (0 = three-state DD pins, 1 = enable DD pins).

7:0

DD[7:0]

DD[15:8]

Reserved

5.1.2.2 Mfg_read

This USB request returns a “snapshot in time” of select EZ-USB AT2 input pins. The input pin states are bit-wise mapped to the

ATAPI data associated with this request. EZ-USB AT2 input pins not directly associated with USB operation can be sampled at

any time during Manufacturing Test Mode operation. See the following table for an explanation of the mfg_read data format. The

data length shall always be 8 bytes.

Table 5-5. Mfg_read Data Format

Byte

0

Bit(s)

0

Test/Tri-state Control Function

INTRQ

0

5:1

6

Reserved. This data should be ignored.

VBUS_PWR_VALID

0

7

ARESET# (output value only)

Reserved. This data should be ignored.

IORDY

1

2:0

3

1

4

DMARQ

1

5

ATA_EN

1

6

Reserved. This data should be ignored.

DD[15:0] Tri-state

1

7

2

7:0

DD[7:0]

3

DD[15:8]

4

Reserved. This data should be ignored.

5

6

7

5.2

Normal Operation Mode

In Normal Operation Mode, the chip behaves as a USB 2.0 to ATA/ATAPI bridge. This includes all typical USB device states

(powered, configured, suspended, etc.). The USB descriptors are returned according to the values stored in the external EE-

PROM. An external EEPROM is required for Mass Storage Class Bulk-Only Transport Compliance, since a unique serial number

is required for each device. Also, Cypress requires customers to use their own Vendor and Product IDs for final products.

5.3

EEPROM Organization

The contents of the 256-byte (2048-bit) two-wire serial EEPROM are arranged as follows. The column labeled “Required Con-

tents” contains the values that must be used for proper operation of the EZ-USB AT2. The column labeled “Suggested Contents”

contains suggested values for the bytes that are defined by the manufacturer. Some values, such as the Vendor ID and device

and device serial number, must be customized to meet USB compliance. See subsection 5.1 for details on how to use vendor-

specific ATAPI commands to read and program the EEPROM. The serial EEPROM must be hard-wired to address 0x04. This

means that A0 and A1 of the serial EEPROM must be tied to ground and that A2 must be tied to 3.3V.

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CY7C68300

Table 5-6. EEPROM Organization

EEPROM

Required Suggested

Contents Contents

Address

Field Name

Field Description

Configuration

0x00

0x01

0x02

I²C-compatible memory

device signature (LSB)

I²C-compatible memory

device signature (MSB)

LSB I²C-compatible memory device signature byte.

MSB I²C-compatible memory device signature byte.

0x4D

0x00

APM Value

ATA Device Automatic Power Management Value. If an

attached ATA device supports APM and this field contains

other than 0x00, the EZ-USB AT2 will issue a

SET_FEATURES command to Enable APM with this value

during the drive initialization process. Setting APM Value to

0x00 disables this functionality. This value is ignored with

ATAPI devices.

0x03

0x04

ATA Initialization Timeout

ATA Command Designator

Time in 128-ms granularity before the EZ-USB AT2 stops

polling the ALT STAT register for reset complete and restarts

the reset process (0x80 = 16.4 seconds).

0x80

0x24

Value in the first byte of the CBW CB field that designates that

the CB is t o be decoded as vendor specific ATA commands

instead of the ATAPI command block. See section 4.0 for

more detail on how this byte is used.

0x05

Reserved

Bits(7:4) Set to 0

0x07

BUSY Bit Delay

Bit (3)

Enables a delay of up to 120ms at each read of the DRQ bit

where the device data length does not match the host data

length. This allows the EZ-USB AT2 to work with most

devices that incorrectly clear the BUSY bit before a valid

status is present.

Short Packet Before Stall

Bit (2)

Determines if a short packet is sent prior to the STALL of an

IN endpoint. The USB Mass Storage Class Bulk-Only Speci-

fication allows a device to send a short or zero-length IN

packet prior to returning a STALL handshake for certain

cases. Certain host controller drivers may require a short

packet prior to STALL.

1 = Force a short packet before STALL.

0 = Don’t force a short packet before STALL.

SRST Enable

Skip Pin Reset

Bit (1)

Determines if the EZ-USB AT2 is to do a SRST reset during

drive initialization. Note: At least one reset must be enabled.

Do not set SRST to 0 and Skip Pin Reset to 1at the same time.

1 = Perform SRST during initialization.

0 = Don’t perform SRST during initialization.

Bit (0)

Skip ATA_NRESET assertion. Note: SRST Enable must be

set in conjunction with Skip Pin Reset. Setting this bit causes

the EZ-USB AT2 to bypass ARESET# during initialization. All

reset events except a power-on reset utilize SRST as the

drive mechanism.

0 = Allow ARESET# assertion for all resets.

1 = Disable ARESET# assertion except for power-on reset

cycles.

Document #: 38-08011 Rev. *A

Page 14 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Address

Required Suggested

Contents Contents

Field Name

Field Description

0x06

ATA UDMA Enable

Bit (7)

0xD4

Enable Ultra DMA data transfer support for ATAPI devices. If

enabled, and if the ATAPI device reports UDMA support for

the indicated modes, the EZ-USB AT2 will utilize UDMA data

transfers at the highest negotiated rate possible.

0 = Disable ATA device UDMA support.

1 = Enable ATA device UDMA support.

ATAPI UDMA Enable

Bit (6)

Enable Ultra DMA data transfer support for ATAPI devices. If

enabled, and if the ATAPI device reports UDMA support for

the indicated modes, the EZ-USB AT2 will utilize UDMA data

transfers at the highest negotiated rate possible.

0 = Disable ATAPI device UDMA support.

1 = Enable ATAPI device UDMA support.

UDMA Modes

Bit (5:0)

These bits select which UDMA modes, if supported, are

enabled. Setting to 1 enables. Multiple bits may be set. The

EZ-USB AT2 will operate in the highest enabled UDMA mode

supported by the device. The EZ-USB AT2 supports UDMA

modes 2 and 4 only.

Bit Descriptions

5

4

3

2

1

0

Reserved. Must be set to 0.

Enable UDMA mode 4.

Reserved. Must be set to 0.

Enable UDMA mode 2.

Reserved. Must be set to 0.

0x07

Reserved

PIO Modes

Bits(7:2)

Bits(1:0)

0x03

These bits select which PIO modes, if supported, are

enabled. Setting to 1 enables. Multiple bits may be set. The

EZ-USB AT2 will operate in the highest enabled PIO mode

supported by the device. The EZ-USB AT2 supports PIO

modes 0, 3, and 4 only. PIO mode 0 is always enabled by

internal logic.

Bit Descriptions

1

0

Enable PIO mode 4.

Enable PIO mode 3.

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

Reserved

Must be set to 0x00.

0x00

Device Descriptor

0x10

0x11

0x12

0x13

0x14

0x15

bLength

Length of device descriptor in bytes.

Descriptor type.

0x12

0x01

0x00

0x02

0x00

bDescriptor Type

bcdUSB (LSB)

bcdUSB (MSB)

bDeviceClass

bDeviceSubClass

USB Specification release number in BCD.

Device class.

Device subclass.

Document #: 38-08011 Rev. *A

Page 15 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Required Suggested

Contents Contents

Address

Field Name

bDeviceProtocol

Field Description

0x16

Device protocol.

0x00

0x40

0xB4

0x04

0x30

0x68

0x01

0x17

bMaxPacketSize0

idVendor (LSB)

idVendor (MSB)

idProduct (LSB)

idProduct (MSB)

bcdDevice (LSB)

USB packet size supported for default pipe.

0x18

Vendor ID. Cypress’s Vendor ID may only be used for evalu-

ation purposes, and not in released products.

0x19

0x1A

0x1B

0x1C

Product ID.

Device release number in BCD LSB (product release

number).

0x1D

0x1E

bcdDevice (MSB)

iManufacturer

Device release number in BCD MSB (silicon release

number).

0x00

0x38

Index to manufacturer string. This entry must equal half of the

address valuewherethestringstarts or0x00ifthestringdoes

not exist.

0x1F

0x20

iProduct

Index to product string. This entry must equal half of the

address valuewherethestringstarts or0x00ifthestringdoes

not exist.

0x4E

0x64

iSerialNumber

Index to serial number string. This entry must equal half of

the address value where the string starts or 0x00 if the string

does not exist. The USB Mass Storage Class Bulk Only

Transport Specification requires a unique serial number (in

upper case, hexidecimal characters) for each device.

0x21

bNumConfigurations

Number of configurations supported.

0x01

Device Qualifier

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x29

0x2A

0x2B

bLength

Length of device descriptor in bytes.

Type Descriptor type.

0x0A

0x06

0x00

0x02

0x00

0x40

0x01

0x00

bDescriptor

bcdUSB (LSB)

bcdUSB (MSB)

bDeviceClass

USB Specification release number in BCD.

Device class.

bDeviceSubClass

bDeviceProtocol

bMaxPacketSize0

bNumConfigurations

bReserved

Device subclass.

Device protocol.

USB packet size supported for default pipe.

Number of configurations supported.

Reserved for future use. Must be set to zero.

High-speed Configuration Descriptor

0x2C

0x2D

0x2E

0x2F

bLength

Length of configuration descriptor in bytes.

Descriptor type.

0x09

0x02

0x20

0x00

bDescriptorType

bTotalLength (LSB)

bTotalLength (MSB)

Number of bytes returned in this configuration. This includes

the configuration descriptor plus all the interface and

endpoint descriptors.

0x30

0x31

bNumInterfaces

Number of interfaces supported.

0x01

bConfiguration Value

The value to use as an argument to Set Configuration to

select the configuration. This value must be set to 0x01.

0x32

iConfiguration

Index to the configuration string. This entry must equal half

of the address value where the string starts or 0x00 if the

string does not exist.

0x00

Document #: 38-08011 Rev. *A

Page 16 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Required Suggested

Contents Contents

Address

Field Name

bmAttributes

Field Description

0x33

Device attributes for this configuration.

Bit Descriptions

0xC0

7 Reserved. Must be set to 1.

6 Self-powered. Must be set to 1.

5 Remote wake-up. Must be set to 0.

4-0 Reserved. Must be set to 0.

0x34

bMaxPower

Maximum power consumption for this configuration. Units

used are mA*2(i.e., 0x31 = 98 mA, 0xF9 = 498 mA). 0x00

reported for self-powered devices.

0x00

High-speed Interface and Endpoint Descriptors

Interface Descriptor

0x35

0x36

0x37

0x38

0x39

0x3A

0x3B

0x3C

0x3D

bLength

Length of interface descriptor in bytes.

Descriptor type.

0x09

0x04

0x00

0x02

0x08

0x06

0x50

0x00

bDescriptorType

bInterfaceNumber

bAlternateSetting

bNumEndpoints

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

Interface number.

Alternate setting.

Number of endpoints.

Interface class.

Interface subclass.

Interface protocol.

Index to first interface string. This entry must equal half of the

address valuewherethestringstarts or0x00ifthestringdoes

not exist.

USB Bulk Out Endpoint

0x3E

0x3F

0x40

0x41

0x42

0x43

0x44

bLength

Length of this descriptor in bytes.

Endpoint descriptor type.

0x07

0x05

0x02

0x00

0x02

0x00

bDescriptorType

bEndpointAddress

bmAttributes

This is an Out endpoint, endpoint number 2.

This is a bulk endpoint.

wMaxPacketSize (LSB)

wMaxPacketSize (MSB)

bInterval

Max data transfer size.

HS interval for polling (max NAK rate).

USB Bulk In Endpoint

0x45

0x46

0x47

0x48

0x49

0x4A

0x4B

bLength

Length of this descriptor in bytes.

Endpoint descriptor type.

0x07

0x05

0x88

0x02

0x00

0x02

0x00

bDescriptorType

bEndpointAddress

bmAttributes

This is an In endpoint, endpoint number 8.

This is a bulk endpoint.

wMaxPacketSize (LSB)

wMaxPacketSize (MSB)

bInterval

Max data transfer size.

HS interval for polling (max NAK rate).

Full-speed Configuration Descriptor

0x4C

0x4D

0x4E

0x4F

bLength

Length of configuration descriptor in bytes.

Descriptor type.

0x09

0x02

0x20

0x00

bDescriptorType

bTotalLength (LSB)

bTotalLength (MSB)

Number of bytes returned in this configuration. This includes

the configuration descriptor plus all the interface and

endpoint descriptors.

0x50

0x51

bNumInterfaces

Number of interfaces supported.

0x01

bConfiguration Value

The value to use as an argument to Set Configuration to

select the configuration.

Document #: 38-08011 Rev. *A

Page 17 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Required Suggested

Contents Contents

Address

Field Name

iConfiguration

Field Description

0x52

Index to configuration string. This entry must equal half of the

address valuewherethestringstarts or0x00ifthestringdoes

not exist.

0x00

0x53

0x54

bmAttributes

Device attributes for this configuration.

Bit Descriptions

7 Reserved. Must be set to 1.

6 Self-powered. Must be set to 1.

5 Remote wake-up. Must be set to 0.

4–0 Reserved. Must be set to 0.

0xC0

bMaxPower

Maximum power consumption for the second configuration.

Units used are mA*2 (i.e. 0x31 = 98 mA, 0xF9 = 498 mA).

0x00

Full-speed Interface and Endpoint Descriptors

Interface Descriptor

0x55

0x56

0x57

0x58

0x59

0x5A

0x5B

0x5C

0x5D

bLength

Length of interface descriptor in bytes.

Descriptor type.

0x09

0x04

0x00

0x02

0x08

0x06

0x50

0x00

bDescriptorType

bInterfaceNumber

bAlternateSettings

bNumEndpoints

bInterfaceClass

bInterfaceSubClass

bInterfaceProtocol

iInterface

Interface number.

Alternate settings.

Number of endpoints.

Interface class.

Interface subclass.

Interface protocol.

Index to first interface string. This entry must equal half of the

address valuewherethestringstarts or0x00ifthestringdoes

not exist.

USB Bulk Out Endpoint

0x5E

0x5F

0x60

0x61

0x62

0x63

0x64

bLength

Length of this descriptor in bytes.

Endpoint descriptor type.

0x07

0x05

0x02

0x40

0x00

bDescriptorType

bEndpointAddress

bmAttributes

This is an Out endpoint, endpoint number 2.

This is a bulk endpoint.

wMaxPacketSize (LSB)

wMaxPacketSize (MSB)

bInterval

Max data transfer size.

Does not apply to FS bulk endpoints. Must be set to 0.

USB Bulk In Endpoint

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

bLength

Length of this descriptor in bytes.

Endpoint descriptor type.

0x07

0x05

0x88

0x02

0x40

0x00

bDescriptorType

bEndpointAddress

bmAttributes

This is an In endpoint, endpoint number 8.

This is a bulk endpoint.

wMaxPacketSize (LSB)

wMaxPacketSize (MSB)

bInterval

Max data transfer size.

Does not apply to FS bulk endpoints. Must be set to 0.

String Descriptor Examples (Note: The values in these strings are given as examples only and should not be used in final

products. Designers are encouraged to modify the string values to reflect the final product, since they are what users will see

with their operating systems.)

USB String Descriptor–Index 0 (LANGID)

0x6C

0x6D

bLength

LANGID string descriptor length in bytes.

Descriptor type.

0x04

0x03

bDescriptorType

Document #: 38-08011 Rev. *A

Page 18 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Required Suggested

Contents Contents

Address

Field Name

LANGID (LSB)

LANGID (MSB)

Field Description

0x6E

Language supported. Note: See http://www.usb.org for

LANGID documentation (the code for English is 0x0409).

0x09

0x04

0x6F

USB String Descriptor–Manufacturer

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

0x7C

0x7D

0x7E

0x7F

0x80

0x81

0x82

0x83

0x84

0x85

0x86

0x87

0x88

0x89

0x8A

0x8B

0x8C

0x8D

0x8E

0x8F

0x90

0x91

0x92

0x93

0x94

0x95

0x96

0x97

0x98

bLength

bDescriptorType

bString

String descriptor length in bytes (including bLength).

Descriptor type.

Unicode character.

(“NUL”)

0x2C

0x03

“C” 0x43

0x00

Unicode character.

(“NUL”)

“y” 0x79

0x00

Unicode character.

(“NUL”)

“p” 0x70

0x00

Unicode character.

(“NUL”)

“r” 0x72

0x00

Unicode character.

(“NUL”)

“e” 0x65

0x00

Unicode character.

(“NUL”)

“s” 0x73

0x00

Unicode character.

(“NUL”)

“s” 0x73

0x00

Unicode character.

(“NUL”)

“ ” 0x20

0x00

Unicode character.

(“NUL”)

“S” 0x53

0x00

Unicode character.

(“NUL”)

“e” 0x65

0x00

Unicode character.

(“NUL”)

“m” 0x6D

0x00

Unicode character.

(“NUL”)

“i” 0x69

0x00

Unicode character.

(“NUL”)

“c” 0x63

0x00

Unicode character.

(“NUL”)

“o” 0x6F

0x00

Unicode character.

(“NUL”)

“n” 0x6E

0x00

Unicode character.

(“NUL”)

“d” 0x64

0x00

Unicode character.

(“NUL”)

“u” 0x75

0x00

Unicode character.

(“NUL”)

“c” 0x63

0x00

Unicode character.

(“NUL”)

“t” 0x74

0x00

Unicode character.

“o” 0x6F

Document #: 38-08011 Rev. *A

Page 19 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Address

Required Suggested

Contents Contents

Field Name

Field Description

0x99

bString

(“NUL”)

0x00

“r” 0x72

0x00

0x9A

Unicode character.

(“NUL”)

0x9B

USB String Descriptor–Product

0x9C

0x9D

0x9E

0x9F

0xA0

0xA1

0xA2

0xA3

0xA4

0xA5

0xA6

0xA7

0xA8

0xA9

0xAA

0xAB

0xAC

0xAD

0xAE

0xAF

0xB0

0xB1

0xB2

0xB3

0xB4

0xB5

0xB6

0xB7

0xB8

0xB9

0xBA

0xBB

0xBC

0xBD

0xBE

0xBF

0xC0

0xC1

0xC2

bLength

bDescriptorType

bString

String descriptor length in bytes (including bLength).

Descriptor type.

Unicode character.

(“NUL”)

0x2C

0x03

“U” 0x55

0x00

Unicode character.

(“NUL”)

“S” 0x53

0x00

Unicode character.

(“NUL”)

“B” 0x42

0x00

Unicode character.

(“NUL”)

“2” 0x32

0x00

Unicode character.

(“NUL”)

“.” 0x2E

0x00

Unicode character.

(“NUL”)

“0” 0x30

0x00

Unicode character.

(“NUL”)

“ ” 0x20

0x00

Unicode character.

(“NUL”)

“S” 0x53

0x00

Unicode character.

(“NUL”)

“t” 0x74

0x00

Unicode character.

(“NUL”)

“o” 0x6F

0x00

Unicode character.

(“NUL”)

“r” 0x72

0x00

Unicode character.

(“NUL”)

“a” 0x61

0x00

Unicode character.

(“NUL”)

“g” 0x67

0x00

Unicode character.

(“NUL”)

“e” 0x65

0x00

Unicode character.

(“NUL”)

“ ” 0x20

0x00

Unicode character.

(“NUL”)

“D” 0x44

0x00

Unicode character.

(“NUL”)

“e” 0x65

0x00

Unicode character.

(“NUL”)

“v” 0x76

0x00

Unicode character.

“i” 0x69

Document #: 38-08011 Rev. *A

Page 20 of 26

CY7C68300

Table 5-6. EEPROM Organization (continued)

EEPROM

Address

Required Suggested

Contents Contents

Field Name

Field Description

0xC3

bString

(“NUL”)

0x00

“c” 0x63

0x00

0xC4

Unicode character.

(“NUL”)

0xC5

0xC6

Unicode character.

(“NUL”)

“e” 0x65

0x00

0xC7

USB String Descriptor–Serial Number (Note: The USB Mass Storage Class requires a unique serial number in each device.

Not providing a unique serial number will crash the operating system. The serial number must be at least a minimum size of 12

characters. Some hosts will only treat the last 12 characters of the serial number as unique.)

0xC8

0xC9

0xCA

0xCB

0xCC

0xCD

0xCE

0xCF

0xD0

0xD1

0xD2

0xD3

0xD4

0xD5

0xD6

0xD7

0xD8

0xD9

0xDA

0xDB

0xDC

0xDD

0xDE

0xDF

0xE0

0xE1

0xE2

0xE3

0xE4

0xE5

0xE6

0xE7

0xE8

0xE9

bLength

bDescriptor Type

bString

String descriptor length in bytes (including bLength).

0x22

Descriptor type.

0x03

Unicode character.

“1” 0x31

0x00

bString

(“NUL”)

bString

Unicode character.

“2” 0x32

0x00

bString

(“NUL”)

bString

Unicode character.

“3” 0x33

0x00

bString

(“NUL”)

bString

Unicode character.

“4” 0x34

0x00

bString

(“NUL”)

bString

Unicode character.

“5” 0x35

0x00

bString

(“NUL”)

bString

Unicode character.

“6” 0x36

0x00

bString

(“NUL”)

bString

Unicode character.

“7” 0x37

0x00

bString

(“NUL”)

bString

Unicode character.

“8” 0x38

0x00

bString

(“NUL”)

bString

Unicode character.

“9” 0x39

0x00

bString

(“NUL”)

bString

Unicode character.

“0” 0x30

0x00

bString

(“NUL”)

bString

Unicode character.

“A” 0x41

0x00

bString

(“NUL”)

bString

Unicode character.

“B” 0x42

0x00

bString

(“NUL”)

bString

Unicode character.

“C” 0x43

0x00

bString

(“NUL”)

bString

Unicode character.

“D” 0x44

0x00

bString

(“NUL”)

bString

Unicode character.

“E” 0x45

0x00

bString

(“NUL”)

bString

Unicode character.

“F” 0x46

0x00

bString

(“NUL”)

0xEA to

0xFF

Unused ROM Space

Amount of unused ROM space will vary depending on strings.

0xFF

Document #: 38-08011 Rev. *A

Page 21 of 26

CY7C68300

6.0

Absolute Maximum Ratings

Storage Temperature .......................................................................................................................................... –65°C to +150°C

Ambient Temperature with power supplied............................................................................................................0°C to +55.4°C

Supply Voltage to Ground Potential....................................................................................................................... –0.5V to +4.0V

DC Input Voltage to Any Input Pin ........................................................................................................................................5.25V

DC Voltage Applied to Outputs in High-Z State ..........................................................................................> –0.5V to V_CC+ 0.5V

Power Dissipation ..........................................................................................................................................................> 936 mW

Static Discharge Voltage......................................................................................................................................................2000V

Max Output Current per IO port ...........................................................................................................................................10 mA

7.0

Operating Conditions^[3]

T_A(Ambient Temperature Under Bias) ..................................................................................................................... 0°C to +70°C

Supply Voltage....................................................................................................................................................... +3.0V to +3.6V

Ground Voltage..........................................................................................................................................................................0V

F_osc(Oscillator or Crystal Frequency) .............................................................................................................24 MHz ± 100 ppm

...........................................................................................................................................................................Parallel Resonant

Note:

3. If an alternate clock source is input on XTALIN it must be supplied with standard 3.3V signaling characteristics and XTALOUT must be left floating.

8.0

DC Characteristics

Parameter

Description

Supply Voltage

Conditions

Min.

3.0

2

Typ.

Max.

3.6

Unit

V

V_CC

V_IH

V_IL

I_I

3.3

Input High Voltage

Input Low Voltage

5.25

0.8

V

–0.5

V

Input Leakage Current

Output Voltage High

Output Voltage Low

Output Current High

Output Current Low

Input Pin Capacitance

0 < V_IN< V_CC

+ 10

µA

V

V_OH

V_OL

I_OH

I_OL

C_IN

I_OUT= 4mA

2.4

I_OUT= –4mA

0.4

4

V

mA

pF

µA

mA

4

All but D+/D–

10

Only D+/D–

15

I_SUP

I_CC

Suspend Current

Supply Current

Including 1.5k integrated pull-up

USB High Speed

USB Full Speed

250

235

90

400

260

150

I_CC

9.0

9.1

AC Electrical Characteristics

USB Transceiver

Complies with the USB 2.0 specification.

9.2 ATA Timing

The ATA interface supports ATA PIO modes 0, 3, and 4, and Ultra DMA modes 2 and 4 per the ATA Specification T13/1410D

Rev. 3B.

Document #: 38-08011 Rev. *A

Page 22 of 26

CY7C68300

10.0

Ordering Information

Part Number

Package Type

CY7C68300

CY4615

56 SSOP

56 QFN

EZ-USB AT2 Reference Design Kit

11.0

Package Diagrams

Figure 11-1. 56-lead Shrunk Small Outline Package 056

56-Lead QFN (8 x 8 mm)

51-85062-*C

51-85144-*B

Figure 11-2. 56-lead Quad Flatpack No Lead (8 x 8 mm) LF56

Document #: 38-08011 Rev. *A

Page 23 of 26

CY7C68300

12.0

PCB Layout Recommendations^[4]

The following recommendations should be followed to ensure reliable high-performance operation.

• Four-layer impedance controlled boards are required to maintain signal quality.

• USB connector shell must be tied to ground near the connector.

• Bypass/flyback caps on VBus, near connector, are recommended.

• DPLUS and DMINUS trace lengths should be kept to within 2 mm of each other, with preferred length of 20-30 mm.

• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces.

• Do not place vias on the DPLUS or DMINUS trace routing.

• Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm.

13.0

Quad Flat Package No Leads (QFN) Package Design Notes

Electrical contact of the part to the Printed Circuit Board (PCB) is made by soldering the leads on the bottom surface of the

package to the PCB. Hence, special attention is required to the heat transfer area below the package to provide a good thermal

bond to the circuit board. A Copper (Cu) fill is to be designed into the PCB as a thermal pad under the package. Heat is transferred

from the AT2 through the device’s metal paddle on the bottom side of the package. Heat from here is conducted to the PCB at

the thermal pad. It is then conducted from the thermal pad to the PCB inner ground plane by a 5 x 5 array of Via. A Via is a plated

through-hole in the PCB with a finished diameter of 13 mil. The QFN’s metal die paddle must be soldered to the PCB’s thermal

pad. Solder mask is placed on the board top side over each Via to resist solder flow into the Via. The mask on the top side also

minimizes outgassing during the solder reflow process.

For further information on this package design please refer to the application note “Surface Mount Assembly of AMKOR’s

MicroLeadFrame (MLF) Technology.” This application note can be downloaded from AMKOR’s website from the following URL

http://www.amkor.com/products/notes_papers/MLF_AppNote_0301.pdf. The application note provides detailed information on

board mounting guidelines, soldering flow, rework process, etc.

Figure 13-1 below display a cross-sectional area underneath the package. The cross section is of only one via. The solder paste

template needs to be designed to allow at least 50% solder coverage. The thickness of the solder paste template should be 5 mil.

It is recommended that “No Clean”, type 3 solder paste is used for mounting the part. Nitrogen purge is recommended during

reflow.

0.017” dia

Solder Mask

Cu Fill

0.013” dia

PCB Material

Via hole for thermally connecting the

This figure only shows the top three layers of the

circuit board: Top Solder, PCB Dielectric, and

the Ground Plane

QFN to the circuit board ground plane.

Figure 13-1. Cross-Section of the Area Underneath the QFN Package

Figure 13-2 is a plot of the solder mask pattern and Figure 13-3 displays an X-Ray image of the assembly (darker areas indicate

solder.)

Note:

4. Source for recommendations: High Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.

Document #: 38-08011 Rev. *A

Page 24 of 26

CY7C68300

Figure 13-2. Plot of the Solder Mask (white area)

Figure 13-3. X-ray Image of the Assembly

14.0

Other Design Considerations

Certain design considerations must be followed to ensure proper operation of the EZ-USB AT2. The following items should be

taken into account when designing a USB device with the EZ-USB AT2.

14.1

Proper Power-up Sequence

Power must be applied to the EZ-USB AT2 before, or at the same time as the ATA/ATAPI device. If power is supplied to the drive

first, the EZ-USB AT2 will start up in an undefined state. Designs that utilize separate power supplies for the EZ-USB AT2 and

the ATA/ATAPI device are not recommended.

14.2

IDE Removable Media Devices

The EZ-USB AT2 does not fully support IDE removable media devices. Changes in media state are not reported to the operating

system so users will be unable to eject/reinsert media properly. This may result in lost or corrupted data.

14.3

Devices With Small Buffers

The size of the ATA/ATAPI device’s buffer can greatly affect the overall data transfer performance. Care should be taken to ensure

that devices have large enough buffers to handle the flow of data to/from the drive. The exact buffer size needed depends on a

number of variables, but a good rule of thumb is:

(aprox min buffer size) = (data rate) * (seek time + rotation time + other)

where (other) may include things like time to switch heads, power up a laser, etc. Devices with buffers that are too small to handle

the extra data may perform considerably slower than expected.

Purchase of I²C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips

I²C Patent Rights to use these components in an I²C system, provided that the system conforms to the I²C Standard Specification

as defined by Philips. EZ-USB AT2 is a trademark, and EZ-USB is a registered trademark, of Cypress Semiconductor. All product

and company names mentioned in this document are the trademarks of their respective holders.

Document #: 38-08011 Rev. *A

Page 25 of 26

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY7C68300

Description Title: CY7C68300 EZ-USB AT2™ USB 2.0 to ATA/ATAPI Bridge

Document Number: 38-08011

Issue

Date

Orig. of

Change

REV.

**

ECN NO.

111608

Description of Change

05/15/02

08/30/02

BHA

New Data Sheet

*A

116660

Added new 56 pin Quad Flatpack No Lead package and pinout. Revised

pin description table to reflect new package. Added typical reset diagram.

Removed Advance Information.

Document #: 38-08011 Rev. *A

Page 26 of 26


型号：	CY7C68300-56LFC
厂家：	ETC
描述：	Controller Miscellaneous - Datasheet Reference 控制器杂项 - 数据表参考\n 控制器
文件：	总26页 (文件大小：190K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY7C68300-56LFC [ETC]

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