CY7C346B-35RC [ETC]
UV-Erasable/OTP Complex PLD ; 紫外线可擦除/ OTP复杂可编程逻辑器件\n![CY7C346B-35RC](http://pdffile.icpdf.com/pdf1/p00001/img/icpdf/CY7C3_4379_icpdf.jpg)
型号: | CY7C346B-35RC |
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描述: | UV-Erasable/OTP Complex PLD
|
文件: | 总16页 (文件大小:287K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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46B
CY7C346B
128-Macrocell MAX® EPLD
The 128 macrocells in the CY7C346B are divided into 8 Logic
Array Blocks (LABs), 16 per LAB. There are 256 expander
product terms, 32 per LAB, to be used and shared by the mac-
rocells within each LAB.
Features
• 128 macrocells in 8 LABs
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
• Advanced 0.65-micron CMOS technology to increase
performance
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
The speed and density of the CY7C346B allow it to be used in
a wide range of applications, from replacement of large
amounts of 7400-series TTL logic, to complex controllers and
multifunction chips. With greater than 25 times the functional-
ity of 20-pin PLDs, the CY7C346B allows the replacement of
over 50 TTL devices. By replacing large amounts of logic, the
CY7C346B reduces board space, part count, and increases
system reliability.
Functional Description
The CY7C346B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
Logic Block Diagram
INPUT [59] (N4) . 36
INPUT [60] (M5) . 37
INPUT [61] (N5) . 38
INPUT [64] (N6) . 41
INPUT [65] (M7) . 42
INPUT [66] (L7) . 43
INPUT [67] (N7) . 44
INPUT [70] (L8) . 47
INPUT [71] (N9) . 48
INPUT [72] (M9) . 49
.
1 (C7) [16] INPUT/CLK
.
. 78 (A10) [9] .....
. 79 (B9) [10] .....
80 (A9) [11] .....
. 83 (A8) [14] .....
. 84 (B7) [15] .....
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
.
.
.
.
2
5
6
7
(A7) [17] .....
(C6) [20] .....
(A5) [21] .....
(B5) [22] .....
SYSTEM CLOCK
LAB A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
MACROCELL 121–128
MACROCELL 9–16
LAB B
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
MACROCELL 105–112
MACROCELL 25–32
P
I
LAB C
A
LAB F
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2)[40]
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 41–48
MACROCELL 86–96
LAB D
LAB E
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL 73– 80
MACROCELL 57– 64
() – PERTAIN TO 100-PIN PGA PACKAGE
[ ] –PERTAIN TO 100-PIN PQFP PACKAGE
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]
V
CC
C346B–1
GND
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-03037 Rev. **
Revised December 8, 1999
CY7C346B
Selection Guide
7C346B-25
7C346B-35
Maximum Access Time (ns)
25
35
Pin Configurations
PLCC/CLCC
Top View
PGA
BottomView
79 78 77 76
5 4 3 2 1 84 83 82 81 80
7
8
6
10
75
74
9
11
I/O I/O I/O INP INP INP INP
I/O I/O I/O I/O INP GND INP
V
INP I/O I/O I/O
INP I/O I/O I/O
I/O
I/O
N
CC
I/O
I/O
12
13
14
15
I/O
I/O
V
CC
M
73
72
71
70
69
68
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
GND INP INP
I/O
I/O
I/O
I/O
I/O
I/O
L
K
J
16
I/O
I/O
17
18
19
20
21
I/O
I/O
GND
GND
I/O
67
I/O
V
V
V
CC
I/O
GND GND I/O
I/O I/O I/O
I/O
H
G
F
E
CC
66
65
CC
V
CC
I/O I/O I/O
I/O GND GND
I/O
22
23
7C346B
I/O
64
63
62
61
60
59
V
CC
I/O
V
CC
V
CC
V
24
25
26
CC
GND
GND
I/O
7C346B
I/O
I/O
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
D
I/O
I/O
I/O
27
28
29
30
31
32
I/O
58
57
56
55
54
I/O
I/O
I/O
INP
/CLK
I/O I/O
INP
GND
I/O
I/O
I/O
C
B
I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
INP GND INP I/O I/O I/O
INP INP INP INP I/O I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
I/O
13
A
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
2
3
4
5
6
7
9
10 11
12
8
C346B–3
C346B–2
Document #: 38-03037 Rev. **
Page 2 of 16
CY7C346B
Pin Configurations (continued)
PQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
1
2
I/O
80
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
3
4
77
76
I/O
5
6
7
8
9
I/O
75
74
73
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
72
71
70
10
11
12
13
V
CC
GND
GND
69
68
V
CC
7C346B
INPUT
INPUT
INPUT
67
66
65
14
15
16
17
INPUT
INPUT/CLK
INPUT
INPUT
INPUT
64
63
62
V
CC
GND
18
19
20
21
V
CC
GND
INPUT
INPUT
INPUT
61
60
INPUT
INPUT
INPUT
59
58
22
23
I/O
I/O
I/O
I/O
I/O
I/O
57
56
55
54
24
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
53
52
29
30
I/O
I/O
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C346B–4
Document #: 38-03037 Rev. **
Page 3 of 16
CY7C346B
DC Output Current per Pin[1].................... –25 mA to+25 mA
DC Input Voltage[1] ........................................–2.0V to + 7.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Operating Range
Storage Temperature ................................. –65°C to+135°C
Ambient
Ambient Temperature with
Power Applied............................................. –65°C to+135°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
VCC
5V ± 5%
5V ± 10%
Maximum Junction Temperature
(under bias)..................................................................150°C
Supply Voltage to Ground Potential[1].............–2.0V to+7.0V
Electrical Characteristics Over the Operating Range
Parameter
Description
Supply voltage
Test Conditions
Maximum VCC rise time is 10 ms
IOH = –4 mA DC[2]
Min.
Max.
Unit
V
VCC
VOH
VOL
VIH
VIL
IIX
4.75(4.5) 5.25(5.5)
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
2.4
V
IOL = 8 mA DC[2]
0.45
V
2.0
–0.3
–10
–40
VCC +0.3
V
V
Input LOW Voltage
0.8
+10
+40
100
100
Input Current
VI = VCC or ground
VO = VCC or ground
µA
µA
ns
ns
IOZ
tR
Output Leakage Current
Recommended Input Rise Time
Recommended Input Fall Time
tF
Capacitance
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
VIN = 0V, f = 1.0 MHz
VOUT = 0V, f = 1.0 MHz
Max.
Unit
pF
CIN
10
20
COUT
pF
Notes:
1. Minimum DC input is –0.3V. During transactions, the inputs may undershoot to –2.0V or overshoot to 7.0V for input currents less then 100 mA and periods
shorter than 20 ns.
2. The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current.
AC Test Loads and Waveforms
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
90%
OUTPUT
OUTPUT
3.0V
GND
90%
10%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
≤ 6 ns
≤ 6 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
C346B–6
C346B–7
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT (commercial/military)
163Ω
OUTPUT
1.75V
Document #: 38-03037 Rev. **
Page 4 of 16
CY7C346B
Externally, the CY7C346B provides 20 dedicated inputs, one
of which may be used as a system clock. There are 64 I/O pins
that may be individually configured for input, output, or bidirec-
tional data flow.
Logic Array Blocks
There are 8 logic array blocks in the CY7C346B. Each LAB
consists of a macrocell array containing 16 macrocells, an ex-
pander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable in-
terconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROL DELAY
CLR
INPUT
t
LAC
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEM CLOCK DELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
IC
t
PIA
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
C346B–9
Figure 1. CY7C346B Internal Timing Model
Document #: 38-03037 Rev. **
Page 5 of 16
CY7C346B
Design Recommendations
Typical I vs. f
CC
MAX
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
data sheet is not implied. Exposure to absolute maximum rat-
ings conditions for extended periods of time may affect device
reliability. The CY7C346B contains circuitry to protect device
pins from high static voltages or electric fields, but normal pre-
cautions should be taken to avoid application of any voltage
higher than the maximum rated voltages.
400
300
V
= 5.0V
CC
Room Temp.
200
100
0
For proper operation, input and output pins must be con-
strained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level (ei-
ther VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply de-
coupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND direct-
ly at the device. Decoupling capacitors should have good
frequency response, such as monolithic ceramic types have.
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
C346B–10
Output Drive Current
Design Security
The CY7C346B contains a programmable design security fea-
ture that controls the access to the data programmed into the
device. If this programmable feature is used, a proprietary de-
sign implemented in the device cannot be copied or retrieved.
This enables a high level of design control to be obtained since
programmed data within EPROM cells is invisible. The bit that
controls this function, along with all other program data, may
be reset simply by erasing the entire device.
250
200
150
I
OL
V
= 5.0V
CC
Room Temp.
The CY7C346B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100% program-
ming yield.
100
50
I
OH
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsulat-
ed in non-windowed packages.
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
C346B–11
Document #: 38-03037 Rev. **
Page 6 of 16
CY7C346B
When expander logic is used in the data path, add the appro-
priate maximum expander delay, tEXP to tAS1. Determine
which of 1/(tAWH + tAWL), 1/tACO1, or 1/(tEXP + tAS1) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
pander delay tEXP to the overall delay. Similarly, there is an
additional tPIA delay for an input from an I/O pin when com-
pared to a signal from straight input pin.
The parameter tOH indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchro-
nous clock. If tOH is greater than the minimum required input
hold time of the subsequent synchronous logic, then the de-
vices are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
When calculating synchronous frequencies, use tSU if all in-
puts are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, tEXP to tSU. Determine which of 1/(tWH + tWL), 1/tCO1
,
or 1/(tEXP + tSU) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the syn-
chronous configuration.
When calculating external asynchronous frequencies, use
tAS1 if all inputs are on the dedicated input pins.
Commercial and Industrial External Synchronous Switching Characteristics Over Operating Range
7C346B-25
7C346B-35
Parameter
tPD1
tPD2
tSU
tCO1
tH
tWH
tWL
Description
Min.
Max.
Min.
Max.
Unit
ns
Dedicated Input to Combinatorial Output Delay[3]
I/O Input to Combinatorial Output Delay[3]
Global Clock Set-Up Time
Synchronous Clock Input to Output Delay[3]
Input Hold Time from Synchronous Clock Input
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
Maximum Register Toggle Frequency[4]
Minimum Global Clock Period
25
40
35
55
ns
15
25
ns
14
20
20
30
ns
0
8
0
ns
12.5
12.5
40
ns
8
ns
fMAX
tCNT
tODH
fCNT
62.5
MHz
ns
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency[5]
2
2
ns
50
33.3
MHz
Commercial and Industrial External Asynchronous Switching Characteristics Over Operating Range
7C346B–25
Min. Max.
7C346B–35
Min. Max.
Parameter
tACO1
Description
Asynchronous Clock Input to Output Delay[3]
Unit
ns
25
35
tAS1
Dedicated Input or Feedback Set-Up Time to
Asynchronous Clock Input
5
10
ns
tAH
Input Hold Time from Asynchronous Clock Input
Asynchronous Clock Input HIGH Time[6]
Asynchronous Clock Input LOW Time[6]
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency[5]
6
11
9
10
16
14
ns
ns
tAWH
tAWL
tACNT
fACNT
ns
20
30
ns
50
33.3
MHz
Notes:
3. C1 = 35 pF.
4. The fMAX values represent the highest frequency for pipeline data.
5. This parameter is measured with a 16-bit counter programmed into each LAB.
6. This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the tACH and tACL parameter must be swapped.
Document #: 38-03037 Rev. **
Page 7 of 16
CY7C346B
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346B-25
7C346B-35
Parameter
Description
Dedicated Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Expander Array Delay
Min.
Max.
Min.
Max.
11
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
tIN
tIO
5
6
11
tEXP
tLAD
tLAC
tOD
12
12
10
5
20
14
13
6
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay[3]
Output Buffer Enable Delay[3]
Output Buffer Disable Delay[7]
tZX
10
10
13
13
tXZ
tRSU
RegisterSet-UpTimeRelativetoClockSignal
at Register
6
4
12
8
tRH
Register Hold Time Relative to Clock Signal
at Register
ns
tLATCH
tRD
tCOMB
tIC
Flow Through Latch Delay
Register Delay
3
1
4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
Transparent Mode Delay
3
4
Asynchronous Clock Logic Delay
Synchronous Clock Delay
14
3
16
1
tICS
tFD
Feedback Delay
1
2
tPRE
tCLR
tPIA
Asynchronous Register Preset Time
Asynchronous Register Clear Time
ProgrammableInterconnectArrayDelayTime
5
7
5
7
14
20
Note:
7. C1 = 5 pF.
Document #: 38-03037 Rev. **
Page 8 of 16
CY7C346B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
t
/t
PD1 PD2
COMBINATORIAL
OUTPUT
C346B-12
External Synchronous
tWH
tWL
SYNCHRONOUS
CLOCK PIN
SYNCHRONOUS
CLOCK AT REGISTER
tSU
tH
DATA FROM
LOGIC ARRAY
tCO1
REGISTERED
OUTPUTS
C346B-13
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
C346B-14
Internal Combinatorial
t
IN
INPUT PIN
t
IO
I/O PIN
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
tCOMB
tOD
OUTPUT
PIN
C346B-15
Document #: 38-03037 Rev. **
Page 9 of 16
CY7C346B
Switching Waveforms (continued)
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
C346B-16
Internal Synchronous
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
C346B-17
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
OD
t
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
C346B-18
Document #: 38-03037 Rev. **
Page 10 of 16
CY7C346B
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C346B-25HC/HI
CY7C346B-25JC/JI
CY7C346B-25NC/NI
CY7C346B-25RC/RI
CY7C346B-35HC/HI
CY7C346B-35JC/JI
CY7C346B-35NC/NI
CY7C346B-35RC/RI
Package Type
25
H84
J83
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
Commercial/Industrial
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
35
Commercial/Industrial
J83
N100
R100
100-Pin Windowed Ceramic Pin Grid Array
MAX is a registered trademark of Altera Corporation.
Document #: 38-03037 Rev. **
Page 11 of 16
CY7C346B
Package Diagrams
84-Leaded Windowed Leaded Chip Carrier H84
51-80081
Document #: 38-03037 Rev. **
Page 12 of 16
CY7C346B
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
51-85006-A
Document #: 38-03037 Rev. **
Page 13 of 16
CY7C346B
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
51-85052-A
Document #: 38-03037 Rev. **
Page 14 of 16
CY7C346B
Package Diagrams (continued)
100-Pin Windowed Ceramic Pin Grid Array R100
51-80010-B
Document #: 38-03037 Rev. **
Page 15 of 16
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C346B
Document Title: CY7C346B 128-Macrocell Max® EPLD
Document Number: 38-03037
Issue
ECN NO. Date
Orig. of
Change
REV.
Description of Change
**
106460
07/11/01
SZV
Change from Spec Number: 38-00861 to 38-03037
Document #: 38-03037 Rev. **
Page 16 of 16
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