CY7C346B-15JC [ETC]
UV-Erasable/OTP Complex PLD ; 紫外线可擦除/ OTP复杂可编程逻辑器件\n
| 型号： | CY7C346B-15JC |
| 厂家： | 
ETC |
| 描述： | UV-Erasable/OTP Complex PLD
|
| 文件： | 总22页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1CY7C346B
fax id: 6104
CY7C346
CY7C346B
128-Macrocell MAX® EPLDs
ture is 100% user configurable, allowing the devices to accom-
modate a variety of independent logic functions.
Features
• 128 macrocells in 8 LABs
• 20 dedicated inputs, up to 64 bidirectional I/O pins
• Programmable interconnect array
• 0.8-micron double-metal CMOS EPROM technology
(CY7C346)
• Advanced 0.65-micron CMOS technology to increase
performance (CY7C346B)
The 128 macrocells in the CY7C346/CY7C346B are divided
into 8 Logic Array Blocks (LABs), 16 per LAB. There are 256
expander product terms, 32 per LAB, to be used and shared
by the macrocells within each LAB.
Each LAB is interconnected through the programmable inter-
connect array, allowing all signals to be routed throughout the
chip.
• Available in 84-pin CLCC, PLCC, and 100-pin PGA,
PQFP
The speed and density of the CY7C346/CY7C346B allow it to
be used in a wide range of applications, from replacement of
large amounts of 7400-series TTL logic, to complex controllers
and multifunction chips. With greater than 25 times the func-
tionality of 20-pin PLDs, the CY7C346/CY7C346B allows the
replacement of over 50 TTL devices. By replacing large
amounts of logic, the CY7C346/CY7C346B reduces board
space, part count, and increases system reliability.
Functional Description
The CY7C346/CY7C346B is an Erasable Programmable Log-
ic Device (EPLD) in which CMOS EPROM cells are used to
configure logic functions within the device. The MAX architec-
Logic Block Diagram
INPUT [59] (N4)
INPUT [60] (M5)
INPUT [61] (N5)
INPUT [64] (N6)
INPUT [65] (M7)
INPUT [66] (L7)
INPUT [67] (N7)
INPUT [70] (L8)
INPUT [71] (N9)
INPUT [72] (M9)
.
.
.
.
.
.
.
.
.
.
36
37
38
41
42
43
44
47
48
49
.
1 (C7) [16] INPUT/CLK
..
.
78 (A10) [9] .....
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
.
79 (B9) [10] .....
80 (A9) [11] .....
83 (A8) [14] .....
84 (B7) [15] .....
.
.
..
..
..
..
2
5
6
7
(A7) [17] .....
(C6) [20] .....
(A5) [21] .....
(B5) [22] .....
SYSTEM CLOCK
LAB A
LAB H
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
MACROCELL
1
2
3
4
5
6
7
8
[100] (C13) NC
[99] (D12) NC
[98] (D13) 77
[97] (E12) 76
[96] (E13) 75
[95] (F11) 74
[92] (G13) 73
[91] (G11) 72
8 (B13) [1]
9 (C12) [2]
10 (A13) [3]
11 (B12) [4]
12 (A12) [5]
13 (11) [6]
NC (A11) [7]
NC (B10) [8]
MACROCELL 121–128
MACROCELL 9–16
LAB
B
LAB G
MACROCELL 104
MACROCELL 103
MACROCELL 102
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
14 (A4) [23]
15 (B4) [24]
16 (A3) [25]
17 (A2) [26]
18 (B3) [27]
21 (A1) [28]
NC (B2) [29]
NC (B1) [30]
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 22
MACROCELL 23
MACROCELL 24
[90] (G12) NC
[89] (H13) NC
[86] (J13) 71
[85] (J12) 70
[84] (K13) 69
[83] (K12) 68
[82] (L13) 67
[81] (L12) 64
MACROCELL 105–112
MACROCELL 25–32
P
I
LAB C
A
LAB F
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 38
MACROCELL 39
MACROCELL 40
22 (C2) [31]
25 (C1) [32]
26 (D2) [33]
27 (D1) [34]
28 (E2) [35]
29 (E1) [36]
NC (F1) [39]
NC (G2)[40]
[80] (M13) NC
[79] (M12) NC
[78] (N13) 63
[77] (M11) 60
[76] (N12) 59
[75] (N11) 58
[74] (M10) 57
[73] (N10) 56
MACROCELL 88
MACROCELL 87
MACROCELL 86
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 41–48
MACROCELL 86–96
LAB D
LAB E
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
[58] (M4) NC
[57] (N3) NC
[56] (M3) 55
[55] (N2) 54
[54] (M2) 53
[53] (N1) 52
[52] (L2) 51
[51] (M1) 50
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
30 (G3) [41]
31 (G1) [42]
32 (H3) [45]
33 (J1) [46]
34 (J2) [47]
35 (K1) [48]
NC (K2) [49]
NC (L1) [50]
MACROCELL 73– 80
MACROCELL 57– 64
() – PERTAIN TO 100–PIN PGA PACKAGE
] –PERTAIN TO 100–PIN PQFP PACKAGE
3, 20, 37, 54 (A6,B6,F12,F13,H1,H2,M8,N8) [18, 19, 43, 44, 68, 69, 93, 94]
16, 33, 50, 67 (B8,C8,F2,F3,H11,H12,L6,M6) [12, 13, 37, 38, 62, 63, 87, 88]
V
CC
[
C346–1
GND
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
October 1989 – Revised March 31, 1997
CY7C346
CY7C346B
Selection Guide
7C346–25
7C346–30
7C346–35
7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35
Maximum Access Time (ns)
15
20
25
30
35
Maximum Operating
Current (mA)
Commercial
Military
250
250
320
320
225
275
275
250
325
320
225
275
275
250
320
320
225
275
275
250
320
320
225
275
275
Industrial
Commercial
Military
320
225
Maximum Standby
Current (mA)
Industrial
275
Shaded area contains preliminary information.
Pin Configurations
PLCC/CLCC
Top View
PGA
BottomView
79 78 77 76
5 4 3 2 1 84 83 82 81 80
7
8
6
10
75
9
11
I/O I/O I/O INP INP INP INP
I/O I/O I/O I/O INP GND INP
V
INP I/O I/O I/O
I/O
I/O
N
CC
I/O
I/O
12
13
14
15
I/O
I/O
74
73
72
71
70
69
68
V
CC
INP I/O I/O I/O
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O I/O
GND INP INP
I/O
I/O
I/O
I/O
I/O
I/O
L
K
J
16
I/O
I/O
17
18
19
20
21
I/O
I/O
GND
GND
I/O
67
I/O
V
V
V
CC
I/O
GND GND I/O
I/O I/O I/O
I/O
H
G
F
E
CC
66
65
CC
V
7C346
7C346B
CC
I/O I/O I/O
I/O GND GND
I/O
22
23
I/O
64
63
62
61
60
59
V
CC
I/O
V
CC
V
CC
7C346
7C346B
V
24
25
26
CC
GND
GND
I/O
I/O
I/O
I/O I/O
I/O I/O
I/O
I/O
I/O
I/O
D
I/O
I/O
I/O
27
28
29
30
31
32
I/O
58
57
56
55
54
I/O
I/O
I/O
INP
/CLK
I/O I/O
INP
GND
I/O
I/O
I/O
C
B
I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
INP GND INP I/O I/O I/O
INP INP INP INP I/O I/O
I/O
I/O
I/O I/O I/O I/O INP
V
CC
I/O
13
A
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
1
2
3
4
5
6
7
9
10 11
12
8
C346–3
C346–2
2
CY7C346
CY7C346B
Pin Configurations (continued)
PQFP
Top View
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/O
1
2
I/O
80
79
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
78
3
4
77
76
I/O
5
6
7
8
9
I/O
75
74
73
I/O
I/O
I/O
I/O
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
72
71
70
10
11
12
13
V
CC
GND
GND
69
68
7C346
7C346B
V
CC
INPUT
INPUT
INPUT
67
66
65
14
15
16
17
18
19
20
21
INPUT
INPUT/CLK
INPUT
INPUT
INPUT
64
63
62
V
CC
GND
V
CC
GND
INPUT
INPUT
INPUT
61
60
INPUT
INPUT
INPUT
59
58
22
23
24
I/O
I/O
I/O
I/O
I/O
I/O
57
56
55
54
I/O
25
26
27
28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
53
52
29
30
I/O
I/O
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
C346–4
3
CY7C346
CY7C346B
[1]
DC Input Voltage ........................................–3.0V to + 7.0V
DC Program Voltage .................................................... 13.0V
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Static Discharge Voltage ........................................... >1100V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................–65°C to+150°C
Ambient Temperature with
Power Applied..............................................–55°C to+125°C
Operating Range
Ambient
Maximum Junction Temperature
(under bias).................................................................. 150°C
Range
Commercial
Industrial
Military
Temperature
V
CC
0°C to +70°C
5V ± 5%
5V ± 10%
5V ± 10%
Supply Voltage to Ground Potential................–2.0V to+7.0V
Maximum Power Dissipation...................................2500 mW
–40°C to +85°C
–55°C to +125°C (Case)
DC V or GND Current............................................500 mA
CC
DC Output Current per Pin........................ –25 mA to+25 mA
[2]
Electrical Characteristics Over the Operating Range
Parameter
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Test Conditions
= Min., I = –4.0 mA
OH
Min.
Max.
Unit
V
V
V
V
2.4
OH
OL
IH
CC
CC
V
V
V
= Min., I = 8.0 mA
0.45
+0.3
V
OL
2.2
–0.3
–10
–40
–30
V
V
CC
0.8
+10
+40
–90
225
275
250
320
100
100
V
IL
I
I
I
I
Input Current
GND < V < V
CC
µA
µA
mA
mA
IX
IN
Output Leakage Current
Output Short Circuit Current
V
V
= V or GND
CC
OZ
O
[3, 4]
= Max., V = 0.5V
OUT
OS
CC
Power Supply Current (Stand- V = GND (No Load)
by)
Com’l
Mil/Ind
Com’l
Mil/Ind
CC1
I
[5]
I
Power Supply Current
V = V or GND (No Load)
mA
CC2
I
CC
[4]
f = 1.0 MHz
t
t
Recommended Input Rise Time
Recommended Input Fall Time
ns
ns
R
F
Capacitance[6]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
C
C
V
V
= 2V, f = 1.0 MHz
10
20
pF
pF
IN
IN
= 2V, f = 1.0 MHz
OUT
OUT
Notes:
1. Minimum DC input is –0.3V. During transitions, the inputs may undershoot to –3.0V for periods less than 20 ns.
2. Typical values are for TA = 25°C and VCC = 5V.
3. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. VOUT = 0.5V has been chosen to avoid
test problems caused by tester ground degradation.
4. Guaranteed by design but not 100% tested.
5. This parameter is measured with device programmed as a 16-bit counter in each LAB.
6. Part (a) in AC Test Load and Waveforms is used for all parameters except tER and tXZ, which is used for part (b) in AC Test Load and Waveforms. All external
timing parameters are measured referenced to external pins of the device.
4
CY7C346
CY7C346B
AC Test Loads and Waveforms[6]
R1 464Ω
R1 464Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
R2
250Ω
R2
250Ω
50 pF
5 pF
≤ 6 ns
≤ 6 ns
INCLUDING
JIGAND
INCLUDING
JIGAND
C346–5
SCOPE
SCOPE
C346–6
(a)
(b)
Equivalent to:
THÉVENIN EQUIVALENT(commercial/military)
163Ω
OUTPUT
1.75V
Externally, the CY7C346/CY7C346B provides 20 dedicated
inputs, one of which may be used as a system clock. There
are 64 I/O pins that may be individually configured for input,
output, or bidirectional data flow.
Logic Array Blocks
There are 8 logic array blocks in the CY7C346/CY7C346B.
Each LAB consists of a macrocell array containing 16 macro-
cells, an expander product term array containing 32 expand-
ers, and an I/O block. The LAB is fed by the programmable
interconnect array and the dedicated input bus. All macrocell
feedbacks go to the macrocell array, the expander array, and
the programmable interconnect array. Expanders feed them-
selves and the macrocell array. All I/O feedbacks go to the
programmable interconnect array so that they may be access-
ed by macrocells in other LABs as well as the macrocells in
the LAB in which they are situated.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves intercon-
nect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
EXPANDER
DELAY
t
EXP
REGISTER
LOGIC ARRAY
OUTPUT
DELAY
t
t
CONTROL DELAY
CLR
INPUT
t
LAC
PRE
OUTPUT
t
OD
XZ
ZX
INPUT
DELAY
t
LOGIC ARRAY
DELAY
t
t
RD
t
RSU
t
t
COMB
LATCH
t
t
IN
RH
t
LAD
SYSTEMCLOCKDELAY t
ICS
CLOCK
DELAY
PIA
DELAY
t
IC
t
PIA
FEEDBACK
DELAY
t
FD
I/O DELAY
t
IO
C346–7
Figure 1. CY7C346/CY7C346B Internal Timing Model
5
CY7C346
CY7C346B
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsulat-
ed in non-windowed packages.
Timing Delays
Timing delays within the CY7C346/CY7C346B may be easily
determined using Warp2 or Warp3 software or by the mod-
el shown in or Figure 1. The CY7C346 /CY7C346B has fixed
internal delays, allowing the user to determine the worst case
timing delays for any design. For complete timing information,
Warp3 software provides a timing simulator.
Typical I vs. f
CC
MAX
400
Design Recommendations
Operation of the devices described herein with conditions
above those listed under “Maximum Ratings” may cause per-
manent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this
datasheet is not implied. Exposure to absolute maximum rat-
ings conditions for extended periods of time may affect device
reliability. The CY7C346/CY7C346B contains circuitry to pro-
tect device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
300
200
V
=5.0V
CC
RoomTemp.
100
For proper operation, input and output pins must be con-
strained to the range GND ≤ (VIN or VOUT) ≤ VCC. Unused
inputs must always be tied to an appropriate logic level (ei-
ther VCC or GND). Each set of VCC and GND pins must be
connected together directly at the device. Power supply de-
coupling capacitors of at least 0.2 µF must be connected
between VCC and GND. For the most effective decoupling,
each VCC pin should be separately decoupled to GND di-
rectly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
0
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz 50 MHz
MAXIMUM FREQUENCY
C346–8
Output Drive Current
100
80
I
OL
Design Security
The CY7C346/CY7C346B contains a programmable design
security feature that controls the access to the data pro-
grammed into the device. If this programmable feature is used,
a proprietary design implemented in the device cannot be cop-
ied or retrieved. This enables a high level of design control to
be obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire de-
vice.
V
=5.0V
CC
60
RoomTemp.
40
20
I
OH
The CY7C346/CY7C346B is fully functionally tested and guar-
anteed through complete testing of each programmable
EPROM bit and all internal logic elements thus ensuring 100%
programming yield.
0.45
0
1
2
3
4
5
V
O
OUTPUTVOLTAGE (V)
C346–9
6
CY7C346
CY7C346B
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum ex-
The parameter t
indicates the system compatibility of this
OH
pander delay t
to the overall delay. Similarly, there is an
EXP
device when driving other synchronous logic with positive
input hold times, which is controlled by the same synchro-
additional t
delay for an input from an I/O pin when com-
PIA
pared to a signal from straight input pin.
nous clock. If t is greater than the minimum required input
OH
When calculating synchronous frequencies, use t if all in-
hold time of the subsequent synchronous logic, then the de-
vices are guaranteed to function properly with a common
synchronous clock under worst-case environmental and
supply voltage conditions.
S1
puts are on dedicated input pins. The parameter t should
S2
be used if data is applied at an I/O pin. If t is greater than
S2
t
, 1/t becomes the limiting frequency in the data path
CO1
S2
mode unless 1/(t
+ t ) is less than 1/t
.
S2
WH
WL
The parameter t
indicates the system compatibility of this
AOH
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t to t . Determine which
device when driving subsequent registered logic with a pos-
itive hold time and using the same asynchronous clock as
the CY7C346/CY7C346B.
EXP
S1
of 1/(t
+ t ), 1/t
, or 1/(t
+ t ) is the lowest fre-
WH
WL
CO1
EXP S1
quency. The lowest of these frequencies is the maximum
data path frequency for the synchronous configuration.
In general, if t
is greater than the minimum required input
AOH
hold time of the subsequent logic (synchronous or asynchro-
nous) then the devices are guaranteed to function properly
under worst-case environmental and supply voltage condi-
tions, provided the clock signal source is the same. This also
applies if expander logic is used in the clock signal path of
the driving device, but not for the driven device. This is due
to the expander logic in the second device’s clock signal path
When calculating external asynchronous frequencies, use
t
if all inputs are on the dedicated input pins. If any data
AS1
is applied to an I/O pin, t
must be used as the required
AS2
set-up time. If (t
+ t ) is greater than t
, 1/(t
+ t
)
AS2
AH
ACO1
AS2
AH
becomes the limiting frequency in the data path mode unless
1/(t + t ) is less than 1/(t + t ).
AWH
AWL
AS2
AH
adding an additional delay (t
from the preceding device to change prior to the arrival of
the clock signal at the following device’s register.
) causing the output data
EXP
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t to t . Determine
EXP
AS1
which of 1/(t
+ t
), 1/t
, or 1/(t
+ t
) is the
AWH
AWL
ACO1
EXP
AS1
7
CY7C346
CY7C346B
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
7C346–25
7C346–30
7C346–35
7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
Dedicated Input to Combinatorial
Output Delay
15
25
23
20
32
30
25
40
37
30
45
44
35
55
55
ns
ns
ns
PD1
PD2
PD3
[7]
t
t
I/O Input to Combinatorial
[8]
Output Delay
Dedicated Input to Combinatorial
Output Delay with
[9]
Expander Delay
t
I/O Input to Combinatorial
Output Delay with
Expander Delay
33
42
52
59
75
ns
PD4
[4,10]
[4,7]
t
t
t
Input to Output Enable Delay
15
15
7
20
20
8
25
25
14
30
30
16
35
35
20
ns
ns
ns
EA
[4,7]
Input to Output Disable Delay
ER
Synchronous Clock Input to
Output Delay
CO1
t
t
Synchronous Clock to Local
Feedback to Combinatorial
Output
17
20
30
35
42
ns
ns
CO2
S1
[4,11]
Dedicated Input or Feedback
Set-Up Time to
10
13
15
20
25
[7,12]
Synchronous Clock Input
t
t
t
t
I/O Input Set-Up Time to
Synchronous Clock Input
20
0
24
0
30
0
36
0
45
0
ns
ns
ns
ns
S2
H
[7]
Input Hold Time from
Synchronous Clock Input
[7]
Synchronous Clock Input
HIGH Time
5
7
8
10
10
12.5
12.5
WH
WL
Synchronous Clock Input
LOW Time
5
7
8
[4,7]
t
t
Asynchronous Clear Width
16
16
22
22
25
25
30
30
35
35
ns
ns
RW
RR
Asynchronous Clear Recovery
[4,7]
Time
t
Asynchronous Clear to Regis-
tered
Output Delay
15
20
25
30
35
ns
RO
[7]
[4,7]
t
t
Asynchronous Preset Width
15
15
20
20
25
25
30
30
35
35
ns
ns
PW
PR
Asynchronous Preset Recovery
[4,7]
Time
t
Asynchronous Preset to Regis-
tered
Output Delay
15
3
20
3
25
3
30
3
35
6
ns
PO
[7]
t
t
f
f
Synchronous Clock to Local
ns
ns
CF
[4,13]
Feedback Input
External Synchronous Clock
12
15
16
20
25
P
[4]
Period (1/(f
))
MAX3
External Feedback Maximum
58.8
76.9
47.6
62.5
34.5
55.5
27.7
43.4
22.2
32.2
MHz
MHz
MAX1
MAX2
[4,14]
Frequency (1/(t
+ t ))
CO1
S1
Internal Local Feedback
Maximum Frequency, lesser of
[4,15]
(1/(t + t )) or (1/t )
S1
CF
CO1
Shaded area contains preliminary information.
8
CY7C346
CY7C346B
Commercial and Industrial External Synchronous Switching Characteristics[6] Over Operating Range
7C346–25
7C346–30
7C346–35
7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
f
Data Path Maximum Frequency,
100
71.4
62.5
50
40
MHz
MAX3
lesser of (1/(t
+ t )),
WL
WH
[4,16]
(1/(t + t )) or (1/t )
S1
H
CO1
f
t
Maximum Register Toggle
100
3
71.4
3
62.5
3
50
3
40
3
MHz
ns
MAX4
OH
[4,17]
Frequency (1/(t
+ t ))
WL
WH
Output Data Stable Time from
[4,18]
Synchronous Clock Input
Shaded area contains preliminary information.
Notes:
7. This specification is a measure of the delay from input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 66, or 68) to combinatorial
output on any output pin. This delay assumes no expander terms are used to form the logic function.
When this note is applied to any parameter specification it indicates that the signal (data, asynchronous clock, asynchronous clear, and/or asynchronous
preset) is applied to a dedicated input only and no signal path (either clock or data) employs expander logic.
If an input signal is applied to an I/O pin an additional delay equal to tPIA should be added to the comparable delay for a dedicated input. If expanders are
used, add the maximum expander delay tEXP to the overall delay for the comparable delay without expanders.
8. This specification is a measure of the delay from input signal applied to an I/O macrocell pin to any output. This delay assumes no expander terms are used
to form the logic function.
9. This specification is a measure of the delay from an input signal applied to a dedicated input (68-pin PLCC input pin 1, 2, 32, 34, 35, 36, 66, or 68) to
combinatorial output on any output pin. This delay assumes expander terms are used to form the logic function and includes the worst-case expander logic
delay for one pass through the expander logic.
10. This specification is a measure of the delay from an input signal applied to an I/O macrocell pin to any output. This delay assumes expander terms are used
to form the logic function and includes the worst-case expander logic delay for one pass through the expander logic. This parameter is tested periodically by
sampling production material.
11. This specification is a measure of the delay from synchronous register clock to internal feedback of the register output signal to the input of the LAB logic array
and then to a combinatorial output. This delay assumes no expanders are used, register is synchronously clocked and all feedback is within the same LAB.
This parameter is tested periodically by sampling production material.
12. If data is applied to an I/O input for capture by a macrocell register, the I/O pin input set-up time minimums should be observed. These parameters are tS2 for
synchronous operation and tAS2 for asynchronous operation.
13. This specification is a measure of the delay associated with the internal register feedback path. This is the delay from synchronous clock to LAB logic array
input. This delay plus the register set-up time, tS1, is the minimum internal period for an internal synchronous state machine configuration. This delay is
for feedback within the same LAB. This parameter is tested periodically by sampling production material.
14. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which a state machine configuration with external feedback can
operate. It is assumed that all data inputs and external feedback signals are applied to dedicated inputs.
15. This specification indicates the guaranteed maximum frequency at which a state machine with internal-only feedback can operate. If register output states
must also control external points, this frequency can still be observed as long as this frequency is less than 1/tCO1. All feedback is assumed to be local
originating within the same LAB.
16. This frequency indicates the maximum frequency at which the device may operate in data path mode (dedicated input pin to output pin). This assumes data
input signals are applied to dedicated input pins and no expander logic is used. If any of the data inputs are I/O pins, tS2 is the appropriate tS for calculation.
17. This specification indicates the guaranteed maximum frequency, in synchronous mode, at which an individual output or buried register can be cycled by a
clock signal applied to the dedicated clock input pin.
18. This parameter indicates the minimum time after a synchronous register clock input that the previous register output data is maintained on the output pin.
9
CY7C346
CY7C346B
Commercial and Industrial External Asynchronous Switching Characteristics[6] Over Operating Range
7C346–25
7C346–30
7C346–35
7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
Asynchronous Clock Input to
Output Delay
15
25
20
32
25
39
30
46
35
55
ns
ns
ACO1
[7]
t
t
Asynchronous Clock Input to
ACO2
Local Feedback to Combinatorial
[19]
Output
Dedicated Input or Feedback
Set-Up Time to Asynchronous
5
5
5
6
8
ns
AS1
[7]
Clock Input
t
t
t
t
t
t
f
I/O Input Set-Up Time to
Asynchronous Clock Input
14.5
17
6
19
6
22
8
28
10
16
14
ns
ns
AS2
AH
[7]
Input Hold Time from
Asynchronous Clock Input
5
9
7
[7]
Asynchronous Clock Input
10
8
11
9
14
11
ns
AWH
AWL
ACF
AP
[7]
HIGH Time
Asynchronous Clock Input
ns
[7, 20]
LOW Time
Asynchronous Clock to Local
11
13
15
18
22
ns
[4,21]
Feedback Input
External Asynchronous Clock
16
50
18
40
20
25
30
ns
[4]
Period (1/(f
))
MAXA4
External Feedback Maximum
33.3
27.7
23.2
MHz
MAXA1
Frequency in Asynchronous
[4,22]
Mode (1/(t
+ t
))
ACO1
AS1
f
f
f
Maximum Internal Asynchronous
Frequency
62.5
66.6
62.5
55.5
50
50
40
50
40
33.3
40
33.3
28.5
33.3
MHz
MHz
MHz
MAXA2
MAXA3
MAXA4
[4,23]
Data Path Maximum Frequency
[4,24]
in Asynchronous Mode
Maximum Asynchronous
55.5
Register Toggle Frequency
[4,25]
1/(t
+ t
)
AWH
AWL
t
Output Data Stable Time from
Asynchronous Clock Input
12
12
15
15
15
ns
AOH
[4,26]
Shaded area contains preliminary information.
Notes:
19. This specification is a measure of the delay from an asynchronous register clock input to internal feedback of the register output signal to the input of the LAB
logic array and then to a combinatorial output. This delay assumes no expanders are used in the logic of combinatorial output or the asynchronous clock input.
The clock signal is applied to the dedicated clock input pin and all feedback is within a single LAB. This parameter is tested periodically by sampling production
material.
20. This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the tAWH and tAWL parameters must be swapped.
If a given input is used to clock multiple registers with both positive and negative polarity, tAWH should be used for both tAWH and tAWL
.
21. This specification is a measure of the delay associated with the internal register feedback path for an asynchronous clock to LAB logic array input. This delay
plus the asynchronous register set-up time, tAS1, is the minimum internal period for an internal asynchronously clocked state machine configuration. This
delay is for feedback within the same LAB, assumes no expander logic in the clock path, and assumes that the clock input signal is applied to a dedicated
input pin. This parameter is tested periodically by sampling production material.
22. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine configuration with external feedback can
operate. It is assumed that all data inputs, clock inputs, and feedback signals are applied to dedicated inputs and that no expander logic is employed in the
clock signal path or data path.
23. This specification indicates the guaranteed maximum frequency at which an asynchronously clocked state machine with internal-only feedback can operate.
This parameter is determined by the lesser of (1/(tACF + tAS1)) or (1/(tAWH + tAWL)). If register output states must also control external points, this frequency
can still be observed as long as this frequency is less than 1/tACO1
.
This specification assumes no expander logic is utilized, all data inputs and clock inputs are applied to dedicated inputs, and all state feedback is within a
single LAB. This parameter is tested periodically by sampling production material.
24. This frequency is the maximum frequency at which the device may operate in the asynchronously clocked data path mode. This specification is determined
by the lesser of 1/(tAWH + tAWL), 1/(tAS1 + tAH) or 1/tACO1. It assumes data and clock input signals are applied to dedicated input pins and no expander
logic is used.
25. This specification indicates the guaranteed maximum frequency at which an individual output or buried register can be cycled in asynchronously clocked mode
by a clock signal applied to an external dedicated input pin.
26. This parameter indicates the minimum time that the previous register output data is maintained on the output after an asynchronous register clock input applied
to an external dedicated input pin.
10
CY7C346
CY7C346B
Commercial and Industrial Internal Switching Characteristics Over Operating Range
7C346–25
7C346–30
7C346–35
7C346B–15 7C346B–20 7C346B–25 7C346B–30 7C346B–35
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
Dedicated Input Pad and
Buffer Delay
3
3
4
4
5
6
7
6
9
9
ns
ns
IN
t
I/O Input Pad and Buffer De-
lay
IO
t
t
t
t
t
Expander Array Delay
8
8
5
3
5
10
10
7
12
12
10
5
14
14
12
5
20
16
13
6
ns
ns
ns
ns
ns
EXP
LAD
LAC
OD
Logic Array Data Delay
Logic Array Control Delay
Output Buffer and Pad Delay
Output Buffer Enable De-
3
5
10
11
13
ZX
[27]
lay
t
t
Output Buffer Disable Delay
5
5
10
11
13
ns
ns
XZ
Register Set-Up Time
Relative to Clock Signal
at Register
4
4
5
5
6
6
8
8
10
10
RSU
t
Register Hold Time Relative
to Clock Signal at Register
ns
RH
t
t
t
t
t
t
Flow Through Latch Delay
Register Delay
1
1
1
2
1
2
3
1
3
4
2
4
4
2
4
ns
ns
ns
ns
ns
ns
LATCH
RD
[28]
Transparent Mode Delay
COMB
CH
Clock HIGH Time
Clock LOW Time
4
4
6
6
8
8
10
10
12.5
12.5
CL
Asynchronous Clock Logic
Delay
6
8
14
16
18
IC
t
t
t
Synchronous Clock Delay
Feedback Delay
0.5
1
0.5
1
1
1
5
1
1
6
1
2
7
ns
ns
ns
ICS
FD
Asynchronous Register
Preset Time
3
3
PRE
t
t
t
t
Asynchronous Register
Clear Time
3
3
5
6
7
ns
ns
ns
ns
CLR
PCW
PCR
PIA
Asynchronous Preset and
Clear Pulse Width
3
3
4
4
5
5
6
6
7
7
Asynchronous Preset and
Clear Recovery Time
Programmable Interconnect
Array Delay Time
10
12
14
16
20
Shaded area contains preliminary information.
Notes:
27. Sample tested only for an output change of 500 mV.
28. This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combi-
natorial operation.
11
CY7C346
CY7C346B
Military External Synchronous Switching Characteristics[6] Over Operating Range
7C346–30
7C346B–30
7C346–35
7C346B–35
7C346B–20
7C346B–25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
Dedicated Input to Combinatorial
Output Delay
20
25
30
35
ns
PD1
PD2
PD3
PD4
[7]
t
t
t
I/O Input to Combinatorial
32
30
42
39
37
51
45
44
59
55
55
75
ns
ns
ns
[8]
Output Delay
Dedicated Input to Combinatorial
Output Delay with Expander Delay
[9]
I/O Input to Combinatorial
Output Delay with
[4,10]
Expander Delay
[4,7]
t
t
t
Input to Output Enable Delay
20
20
8
25
25
14
30
30
16
35
35
20
ns
ns
ns
EA
[4,7]
Input to Output Disable Delay
ER
Synchronous Clock Input to
Output Delay
CO1
t
t
Synchronous Clock to Local
Feedback to Combinatorial
Output
20
30
35
42
ns
ns
CO2
S1
[4,11]
Dedicated Input or Feedback
Set-Up Time to
13
15
20
25
[7,12]
Synchronous Clock Input
t
t
t
I/O Input Set-Up Time to
Synchronous Clock Input
24
0
29
0
36
0
45
0
ns
ns
S2
H
[7]
Input Hold Time from
Synchronous Clock Input
[7]
Synchronous Clock Input HIGH Time
Synchronous Clock Input LOW Time
7
7
8
8
10
10
30
30
12.5
12.5
35
ns
ns
ns
ns
WH
t
WL
[4,7]
t
t
Asynchronous Clear Width
20
20
25
25
RW
RR
Asynchronous Clear Recovery
35
[4,7]
Time
t
Asynchronous Clear to Registered
Output Delay
20
25
30
35
ns
RO
[7]
[4,7]
t
t
Asynchronous Preset Width
20
20
25
25
30
30
35
35
ns
ns
PW
PR
Asynchronous Preset Recovery
[4,7]
Time
t
t
t
f
Asynchronous Preset to Registered
Output Delay
20
3
25
3
30
3
35
6
ns
ns
PO
CF
[7]
Synchronous Clock to Local
[4,13]
Feedback Input
External Synchronous Clock
14
16
20
25
ns
P
[4]
Period (1/(f
))
MAX3
External Feedback Maximum
47.6
34.5
27.7
22.2
MHz
MAX1
[4,14]
Frequency (1/(t
+ t ))
CO1
Shaded area contains preliminary information.
S1
12
CY7C346
CY7C346B
Military External Synchronous Switching Characteristics[6] Over Operating Range (continued)
7C346–30
7C346B–30
7C346–35
7C346B–35
7C346B–20
7C346B–25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
Internal Local Feedback
62.5
55.5
43.4
32.2
MHz
MAX2
Maximum Frequency, lesser of
[4,15]
(1/(t + t )) or (1/t )
S1
CF
CO1
f
Data Path Maximum Frequency,
lesser of (1/(t + t )),
71.4
62.5
50
40
MHz
MAX3
WL
WH
[4,16]
(1/(t + t )) or (1/t )
S1
H
CO1
f
t
Maximum Register Toggle
71.4
3
62.5
3
50
3
40
3
MHz
ns
MAX4
OH
[4,17]
Frequency (1/(t
+ t ))
WL
WH
Output Data Stable Time from
[4,18]
Synchronous Clock Input
Shaded area contains preliminary information.
Military External Asynchronous Switching Characteristics[6] Over Operating Range
7C346–30
7C346B–30
7C346–35
7C346B–35
7C346B–20
7C346B–25
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
Asynchronous Clock Input to
Output Delay
20
25
30
35
ns
ACO1
[7]
t
t
Asynchronous Clock Input to
32
39
46
55
ns
ns
ACO2
Local Feedback to Combinatorial
[19]
Output
Dedicated Input or Feedback
Set-Up Time to Asynchronous
6
5
6
8
AS1
[7]
Clock Input
t
t
t
t
t
t
f
I/O Input Set-Up Time to
Asynchronous Clock Input
17
6
19
6
22
8
28
10
16
14
ns
ns
AS2
AH
[7]
Input Hold Time from
Asynchronous Clock Input
[7]
Asynchronous Clock Input
10
8
11
9
14
11
ns
AWH
AWL
ACF
AP
[7]
HIGH Time
Asynchronous Clock Input
ns
[7, 20]
LOW Time
Asynchronous Clock to Local
13
15
18
22
ns
[4,21]
Feedback Input
External Asynchronous Clock
18
40
20
25
30
ns
[4]
Period (1/(f
))
MAXA4
External Feedback Maximum
33.3
27.7
23.2
MHz
MAXA1
Frequency in Asynchronous
[4,22]
Mode (1/(t
+ t
))
ACO1
AS1
f
f
f
Maximum Internal Asynchronous
Frequency
55.5
50
50
40
50
40
33.3
40
33.3
28.5
33.3
MHz
MHz
MHz
MAXA2
MAXA3
MAXA4
[4,23]
Data Path Maximum Frequency
[4,24]
in Asynchronous Mode
Maximum Asynchronous
55.5
Register Toggle Frequency
[4,25]
1/(t
+ t
)
AWH
AWL
t
Output Data Stable Time from
Asynchronous Clock Input
12
15
15
15
ns
AOH
[4,26]
Shaded area contains preliminary information.
13
CY7C346
CY7C346B
Military Typical Internal Switching Characteristics Over Operating Range
7C346–30
7C346B–30
7C346–35
7C346B–35
7C346B–20
7C346B–25
Parameter
Description
Min.
Max. Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
Dedicated Input Pad and
Buffer Delay
4
5
7
9
ns
IN
t
t
t
t
t
t
t
t
I/O Input Pad and Buffer Delay
Expander Array Delay
4
10
10
7
6
6
9
ns
ns
ns
ns
ns
ns
ns
ns
IO
12
14
14
12
5
20
16
13
6
EXP
LAD
LAC
OD
ZX
Logic Array Data Delay
12
Logic Array Control Delay
Output Buffer and Pad Delay
10
3
5
[27]
Output Buffer Enable Delay
5
10
11
11
13
13
Output Buffer Disable Delay
5
10
XZ
Register Set-Up Time Relative
to Clock Signal at Register
5
5
6
8
8
10
10
RSU
t
Register Hold Time Relative
to Clock Signal at Register
6
ns
RH
t
t
t
t
t
t
t
t
t
t
t
Flow Through Latch Delay
Register Delay
2
1
2
3
4
2
4
4
2
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LATCH
RD
1
[28]
Transparent Mode Delay
3
COMB
CH
Clock HIGH Time
6
6
8
10
10
12.5
12.5
Clock LOW Time
8
CL
Asynchronous Clock Logic Delay
Synchronous Clock Delay
Feedback Delay
8
0.5
1
14
2
16
2
18
3
IC
ICS
1
1
2
FD
Asynchronous Register Preset Time
Asynchronous Register Clear Time
3
5
6
7
PRE
CLR
PCW
3
5
6
7
Asynchronous Preset and
Clear Pulse Width
4
4
5
6
6
7
7
t
t
Asynchronous Preset and
Clear Recovery Time
5
ns
ns
PCR
PIA
Programmable Interconnect
Array Delay Time
12
14
16
20
Shaded area contains preliminary information.
14
CY7C346
CY7C346B
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
[7]
PD1
[8]
t
/t
PD2
COMBINATORIAL
OUTPUT
[7]
ER
t
HIGH-IMPEDANCE
THREE-STATE
COMBINATORIAL OR
REGISTERED OUTPUT
[7]
t
EA
HIGH-IMPEDANCE
THREE-STATE
VALID OUTPUT
C346–10
External Synchronous
DEDICATED INPUTS OR
REGISTERED
[7]
FEEDBACK
t
S1
t
H
t
t
WL
WH
SYNCHRONOUS
CLOCK
t
t
/t
t /t
RR PR
CO1
RW PW
ASYNCHRONOUS
CLEAR/PRESET
t
OH
[7]
t
/t
RO PO
REGISTERED
OUTPUTS
t
CO2
COMBINATORIAL OUTPUT FROM
[7]
REGISTERED FEEDBACK
C346–11
External Asynchronous
DEDICATED INPUTS OR
REGISTERED FEEDBACK
t
t
t
AWL
t
AH
AWH
AS1
ASYNCHRONOUS
CLOCK INPUT
t
ACO1
t
/t
t
/t
RW PW
RR PR
ASYNCHRONOUS
CLEAR/PRESET
t
AOH
t
/t
RO PO
ASYNCHRONOUS REGISTERED
OUTPUTS
t
ACO2
COMBINATORIAL OUTPUT FROM
ASYNCHRONOUS REGISTERED
FEEDBACK
C346–12
15
CY7C346
CY7C346B
Switching Waveforms (continued)
Internal Combinatorial
t
IN
INPUT PIN
I/O PIN
t
PIA
t
IO
t
EXP
EXPANDER
ARRAY DELAY
t
, t
LAC LAD
LOGIC ARRAY
INPUT
LOGIC ARRAY
OUTPUT
C346–13
Internal Asynchronous
t
t
AWL
AWH
t
R
t
F
CLOCK PIN
t
IN
CLOCK INTO
LOGIC ARRAY
t
IC
CLOCK FROM
LOGIC ARRAY
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
t
,t
t
FD
t
,t
t
FD
RD LATCH
CLR PRE
REGISTER OUTPUT
TO LOCAL LAB
LOGIC ARRAY
t
PIA
REGISTER OUTPUT
TO ANOTHER LAB
C346–14
Internal Synchronous
t
t
CL
CH
SYSTEM CLOCK PIN
t
IN
t
ICS
SYSTEM CLOCK
AT REGISTER
t
t
RH
RSU
DATA FROM
LOGIC ARRAY
C346–15
16
CY7C346
CY7C346B
Switching Waveforms (continued)
Internal Synchronous
CLOCK FROM
LOGIC ARRAY
t
t
OD
RD
DATA FROM
LOGIC ARRAY
t
XZ
t
ZX
HIGH IMPEDANCE
STATE
OUTPUT PIN
C346–16
Ordering Information
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
CY7C346B–15HC/HI
CY7C346B–15JC/JI
CY7C346B–15NC/NI
CY7C346B–15RC/RI
CY7C346B–20HC/HI
CY7C346B–20JC/JI
CY7C346B–20NC/NI
CY7C346B–20RC/RI
CY7C346B–20HMB
CY7C346B–20RMB
CY7C346–25HC/HI
CY7C346–25JC/JI
CY7C346–25NC/NI
CY7C346–25RC/RI
CY7C346B–25HC/HI
CY7C346B–25JC/JI
CY7C346B–25NC/NI
CY7C346B–25RC/RI
CY7C346B–25HMB
CY7C346B–25RMB
CY7C346–30HC/HI
CY7C346–30JC/JI
CY7C346–30NC/NI
CY7C346B–30HC/HI
CY7C346B–30JC/JI
CY7C346B–30NC/NI
CY7C346B–30RC/RI
CY7C346–30HMB
CY7C346–30RMB
CY7C346B–30HMB
CY7C346B–30RMB
Package Type
15
H84
J83
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
Commercial/Industrial
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
20
25
Commercial/Industrial
J83
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
Military
R100
H84
Commercial/Industrial
J83
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
J83
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
Military
R100
H84
30
Commercial/Industrial
J83
N100
H84
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
J83
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
Military
R100
H84
R100
Shaded area contains preliminary information.
17
CY7C346
CY7C346B
Ordering Information (continued)
Speed
(ns)
Package
Operating
Range
Ordering Code
CY7C346–35JC/JI
CY7C346–35NC/NI
CY7C346–35RC/RI
CY7C346B–35HC/HI
CY7C346B–35JC/JI
CY7C346B–35NC/NI
CY7C346B–35RC/RI
CY7C346–35HMB
CY7C346–35RMB
CY7C346B–35HMB
CY7C346B–35RMB
Name
Package Type
35
J83
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
Commercial/Industrial
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
84-Lead Plastic Leaded Chip Carrier
100-Lead Plastic Quad Flatpack
J83
N100
R100
H84
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
84-Pin Windowed Leaded Chip Carrier
100-Pin Windowed Ceramic Pin Grid Array
Military
R100
H84
R100
Shaded area contains preliminary information.
MILITARY SPECIFICATIONS
Group A Subgroup Testing
DC Characteristics
Switching Characteristics
Parameter
Subgroups
1, 2, 3
Parameter
Subgroups
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
7, 8, 9, 10, 11
V
V
V
V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
OH
PD1
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
OL
IH
IL
PD2
PD3
CO1
S1
I
I
I
IX
OZ
S2
CC1
H
WH
WL
RO
PO
ACO1
ACO2
AS1
AH
AWH
AWL
Document #: 38–00244–D
MAX is a registered trademark of Altera Corporation.
Warp2 and Warp3 are registered trademarks of Cypress Semiconductor Corporation.
18
CY7C346
CY7C346B
Package Diagrams
84-Lead Windowed Leaded Chip Carrier H84
19
CY7C346
CY7C346B
Package Diagrams (continued)
84-Lead Plastic Leaded Chip Carrier J83
20
CY7C346
CY7C346B
Package Diagrams (continued)
100-Lead Plastic Quad Flatpack N100
21
CY7C346
CY7C346B
Package Diagrams (continued)
100-Pin Windowed Ceramic Pin Grid Array R100
© Cypress Semiconductor Corporation, 1997. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of anycircuitry other than circuitry embodied in a CypressSemiconductor product. Nor does it conveyor imply any license under patent or other rights. CypressSemiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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