CY7C017A-15JI [ETC]
x9 Dual-Port SRAM ; X9双端口SRAM\n
| 型号： | CY7C017A-15JI |
| 厂家： | 
ETC |
| 描述： | x9 Dual-Port SRAM
|
| 文件： | 总20页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
1
CY7C006A, CY7C007A
CY7C016A, CY7C017A
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
• Automatic power-down
Features
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
[1]
• High-speed access: 12 /15/20 ns
• Low operating power
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
• Pin-compatible and functionally equivalent to IDT7006
and IDT7007
— Active: I = 180 mA (typical)
CC
— Standby: I
= 0.05 mA (typical)
SB3
• Fully asynchronous operation
Logic Block Diagram
R/W
R/W
CE
L
R
R
R
CE
L
OE
OE
L
[2]
[2]
8/9
8/9
I/O –I/O
I/O –I/O
0R 7/8R
0L
7/8L
I/O
I/O
Control
Control
14/15
14/15
[4]
13/14R
Address
Decode
Address
Decode
True Dual-Ported
[4]
A
A
–A
A
A
–A
–A
0L
0L
13/14L
0R
RAM Array
14/15
14/15
[4]
13/14R
[4]
13/14L
–A
0R
CE
CE
Interrupt
Semaphore
Arbitration
L
R
OE
OE
L
R
R/W
SEM
R/W
SEM
L
R
R
L
[3]
L
[3]
BUSY
INT
BUSY
INT
R
R
L
M/S
Notes:
1. See page 7 for Load Conditions.
2. I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A0–A13 for 16K; A0–A14 for 32K devices.
For the most recent information, visit the Cypress web site at www.cypress.com
ypress Semiconductor Corporation
C
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
January 10, 2001
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY sig-
nals that the port is trying to access the same location currently
being accessed by the other port. The Interrupt flag (INT) per-
mits communication between ports or systems by means of a
mail box. The semaphores are used to pass a flag, or token,
from one port to the other to indicate that a shared resource is
in use. The semaphore logic is comprised of eight shared
latches. Only one side can control the latch (semaphore) at
any time. Control of a semaphore indicates that a shared re-
source is in use. An automatic power-down feature is con-
trolled independently on each port by a Chip Select (CE) pin.
Functional Description
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
low-power CMOS 32K x 8/9 and 16K x 8/9 dual-port static
RAMs. Various arbitration schemes are included on the devic-
es to handle situations when multiple processors access the
same piece of data. Two ports are provided, permitting inde-
pendent, asynchronous access for reads and writes to any
location in memory. The devices can be utilized as standalone
8/9-bit dual-port static RAMs or multiple devices can be com-
bined in order to function as a 16/18-bit or wider master/slave
dual-port static RAM. An M/S pin is provided for implementing
16/18-bit or wider memory applications without the need for
separate master and slave devices or additional discrete logic.
Application areas include interprocessor/multiprocessor de-
signs, communications status buffering, and dual-port vid-
eo/graphics memory.
The CY7C006A, CY7C007A, and CY7C017A are available in
68-pin PLCC packages, the CY7C006A is also available in
64-pin TQFP, and the CY7C007A and CY7C016A are also
available in 80-pin TQFP packages.
2
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Pin Configurations
68-Pin PLCC
Top View
60
59
A
10
11
12
13
I/O
5L
2L
I/O
I/O
A
4L
3L
58
57
4L
A
A
A
3L
I/O
5L
2L
56
55
GND
1L
14
15
A
0L
I/O
6L
54
53
52
INT
I/O
7L
L
16
17
CY7C006A (16K x 8)
CY7C007A (32K x 8)
CY7C017A (32K x 9)
BUSY
V
CC
L
GND
M/S
GND
18
19
20
21
I/O
0R
51
50
I/O
1R
BUSY
R
I/O
2R
INT
R
49
48
V
CC
A
0R
22
23
A
1R
I/O
3R
47
I/O
4R
24
25
26
A
A
46
45
2R
I/O
5R
3R
4R
I/O6
R
A
44
80-Pin TQFP
Top View
NC
1
2
NC
60
I/O
2L
A
5L
59
I/O
I/O
I/O
A
4L
3
4
3L
4L
58
57
A
A
3L
2L
5
6
7
8
5L
56
55
54
53
A
1L
A
0L
GND
I/O
6L
I/O
7L
INT
L
BUSY
V
L
9
10
CC
52
51
GND
M/S
NC
CY7C007A (32K x 8)
CY7C016A (16K X 9)
GND
I/O
11
12
13
14
50
49
48
47
0R
BUSY
R
I/O
1R
INT
R
I/O
2R
CC
3R
4R
5R
6R
A
0R
A
1R
A
2R
A
3R
V
15
16
46
45
I/O
I/O
I/O
I/O
17
44
A
4R
18
19
20
43
42
41
NC
NC
NC
Notes:
5. This pin is I/O for CY7C017A only.
6. 14 is a no connect pin for 16K devices.
A
3
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Pin Configurations
64-Pin TQFP
Top View
I/O
2L
A
48
47
1
2
4L
A
3L
I/O
3L
A
I/O
4L
2L
46
45
3
4
A
1L
I/O
5L
A
GND
44
43
42
41
5
6
0L
I/O
6L
INT
L
I/O
7L
BUSY
L
7
GND
M/S
V
CC
8
CY7C006A (16K x 8)
GND
40
39
9
BUSY
R
I/O
0R
10
11
12
I/O
1R
38
37
36
INT
R
I/O
2R
A
0R
A
1R
V
CC
13
A
I/O
3R
35
34
2R
14
15
A
3R
I/O
4R
I/O
5R
33
A
4R
16
C006-3
Selection Guide
CY7C006A
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-15
CY7C006A
CY7C007A
CY7C016A
CY7C017A
-20
CY7C007A
CY7C016A
CY7C017A
[1]
-12
Maximum Access Time (ns)
12
195
55
15
190
50
20
180
45
Typical Operating Current (mA)
Typical Standby Current for I
(mA) (Both Ports TTL Level)
(mA) (Both Ports CMOS Level)
SB1
SB3
Typical Standby Current for I
0.05
0.05
0.05
4
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Pin Definitions
Left Port
Right Port
Description
CE
CE
Chip Enable
Read/Write Enable
Output Enable
Address
L
R
R/W
R/W
R
L
OE
OE
R
L
A
–A
A
–A
0R 14R
0L
14L
I/O –I/O
I/O –I/O
Data Bus Input/Output (I/O –I/O for x8 devices and I/O –I/O for x9)
0 7 0 8
0L
8L
0R
8R
SEM
SEM
Semaphore Enable
Interrupt Flag
Busy Flag
L
R
INT
INT
R
L
BUSY
M/S
BUSY
R
L
Master or Slave Select
Power
V
CC
GND
NC
Ground
No Connect
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
Latch-Up Current.................................................... >200 mA
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................–65°C to +150°C
Operating Range
Ambient Temperature with
Ambient
Power Applied.............................................–55°C to +125°C
Range
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
CC
Supply Voltage to Ground Potential............... –0.3V to +7.0V
5V ± 10%
5V ± 10%
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
[7]
DC Input Voltage ........................................ –0.5V to +7.0V
5
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Over the Operating Range
Electrical Characteristics
CY7C006A
CY7C007A
CY7C016A
CY7C017A
[1]
-12
-15
-20
Parameter
Description
Output HIGH Voltage
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
V
2.4
2.4
2.4
V
OH
(V = Min., I = –4.0 mA)
CC
OH
V
Output LOW Voltage
(V = Min., I = +4.0 mA)
0.4
0.4
0.4
V
OL
CC
OH
V
V
Input HIGH Voltage
Input LOW Voltage
Output Leakage Current
Operating Current
2.2
2.2
2.2
V
V
IH
IL
0.8
10
0.8
10
0.8
10
I
I
–10
–10
–10
µA
mA
mA
OZ
Com’l.
195
55
325
190
215
280
305
180
45
275
CC
(V = Max., I
= 0 mA)
CC
OUT
Ind.
Outputs Disabled
I
I
I
Standby Current
(Both Ports TTL Level)
Com’l.
75
205
0.5
50
65
70
95
65
160
0.5
mA
mA
SB1
SB2
SB3
Ind.
CE & CE ≥ V , f = f
L
R
IH
MAX
Standby Current
(One Port TTL Level)
Com’l.
125
0.05
120
135
180
205
110
0.05
mA
mA
Ind.
CE | CE ≥ V , f = f
L
R
IH
MAX
Standby Current
(Both Ports CMOS Level)
Com’l.
0.05
0.05
0.5
0.5
mA
mA
Ind.
CE & CE ≥ V − 0.2V,
L
R
CC
f = 0
I
Standby Current
(One PortCMOS Level) CE
Com’l.
115
185
110
125
160
175
100
140
mA
mA
SB4
L
Ind.
[7]
| CE ≥ V , f = f
R
IH
MAX
Capacitance[9]
Parameter
Description
Test Conditions
T = 25°C, f = 1 MHz,
Max.
Unit
pF
C
Input Capacitance
Output Capacitance
10
10
IN
A
V
= 5.0V
CC
C
pF
OUT
Notes:
7. Pulse width < 20 ns.
8. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3
.
9. Tested initially and after any design or process changes that may affect these parameters.
6
CY7C006A, CY7C007A
CY7C016A, CY7C017A
AC Test Loads and Waveforms
5V
5V
R
TH
= 250
Ω
R1 = 893
R2 = 347
Ω
OUTPUT
C = 30 pF
OUTPUT
C = 30 pF
R1 = 893
Ω
OUTPUT
C = 5 pF
Ω
R2 = 347
Ω
V
TH
= 1.4V
(a) Normal Load (Load 1)
(c)Three-State Delay(Load 2)
(b) Thévenin Equivalent (Load 1)
(Used for t , t , t
, & t
LZWE
LZ HZ HZWE
including scope and jig)
AC Test Loads (Applicable to -12 only)[10]
ALL INPUTPULSES
Z0 = 50
Ω
R = 50
Ω
OUTPUT
3.0V
GND
90%
10%
90%
10%
3 ns
C
3 ns
≤
V
= 1.4V
≤
TH
(a) Load 1 (-12 only)
1 .00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.1 0
0.00
1 0
1 5
20
25
30
35
Capacitance (pF)
(b) Load Derating Curve
Note:
10. Test Conditions: C = 10 pF.
7
CY7C006A, CY7C007A
CY7C016A, CY7C017A
[11]
Over the Operating Range
Switching Characteristics
CY7C006A
CY7C007A
CY7C016A
CY7C017A
[1]
–12
Min.
–15
–20
Parameter
Description
Max.
Min.
Max.
Min.
20
3
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
Address to Data Valid
Output Hold From Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
12
15
20
AA
OHA
[12]
12
8
15
10
20
12
ACE
DOE
LZOE
[13, 14, 15]
[13, 14, 15]
3
3
0
3
3
0
3
3
0
OE HIGH to High Z
10
10
12
10
10
15
12
12
20
HZOE
[13, 14, 15]
CE LOW to Low Z
LZCE
[13, 14, 15]
CE HIGH to High Z
HZCE
[15]
[15]
CE LOW to Power-Up
CE HIGH to Power-Down
PU
PD
WRITE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
12
10
10
0
15
12
12
0
20
15
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
SCE
AW
HA
[12]
CE LOW to Write End
Address Valid to Write End
Address Hold From Write End
Address Set-Up to Write Start
Write Pulse Width
[12]
0
0
0
SA
10
10
0
12
10
0
15
15
0
PWE
SD
Data Set-Up to Write End
Data Hold From Write End
R/W LOW to High Z
[18]
HD
[14, 15]
10
10
12
HZWE
[14, 15]
R/W HIGH to Low Z
3
3
3
LZWE
[16]
WDD
[16]
DDD
Write Pulse to Data Delay
25
20
30
25
45
30
Write Data Valid to Read Data Valid
[17]
BUSY TIMING
t
t
t
t
t
BUSY LOW from Address Match
BUSY HIGH from Address Mismatch
BUSY LOW from CE LOW
12
12
12
12
15
15
15
15
20
20
20
17
ns
ns
ns
ns
ns
BLA
BHA
BLC
BHC
PS
BUSY HIGH from CE HIGH
Port Set-Up for Priority
5
5
5
Notes:
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
OI/IOH and 30-pF load capacitance.
12. To access RAM, CE = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time.
I
13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE
.
14. Test conditions used are Load 3.
15. This parameter is guaranteed but not tested.
16. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform.
17. Test conditions used are Load 2.
18. For 15 ns industrial parts tHD Min. is 0.5 ns.
8
CY7C006A, CY7C007A
CY7C016A, CY7C017A
[11]
Over the Operating Range (continued)
Switching Characteristics
CY7C006A
CY7C007A
CY7C016A
CY7C017A
[1]
–12
Min.
–15
–20
Parameter
Description
Max.
Min.
Max.
Min.
0
Max.
Unit
ns
t
t
t
R/W HIGH after BUSY (Slave)
0
0
WB
R/W HIGH after BUSY HIGH (Slave)
11
13
15
ns
WH
[19]
BUSY HIGH to Data Valid
12
15
20
ns
BDD
[17]
INTERRUPT TIMING
t
t
INT Set Time
12
12
15
15
20
20
ns
ns
INS
INR
INT Reset Time
SEMAPHORE TIMING
t
t
t
t
SEM Flag Update Pulse (OE or SEM)
SEM Flag Write to Read Time
SEM Flag Contention Window
SEM Address Access Time
10
5
10
5
10
5
ns
ns
ns
ns
SOP
SWRD
SPS
5
5
5
12
15
20
SAA
Timing
Data Retention Mode
Data Retention Mode
4.5V
The CY7C006A, CY7C007A, CY7C016A, and CY7C017A are
designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The fol-
lowing rules ensure data retention:
V
CC
4.5V
V
CC
2.0V
>
t
RC
1. Chip Enable (CE) must be held HIGH during data retention,
V
CC
to V – 0.2V
CC
V
within V
to V
– 0.2V.
IH
CE
CC
CC
2. CE must be kept between V
– 0.2V and 70% of V
CC
CC
during the power-up and power-down transitions.
[20]
3. The RAM can begin operation >t after V reaches the
minimum operating voltage (4.5 volts).
Parameter
ICC
Test Conditions
@ VCC = 2V
Max.
Unit
RC
CC
1.5
mA
DR1
DR
Switching Waveforms
[21, 22, 23]
Read Cycle No. 1 (Either Port Address Access)
t
RC
ADDRESS
t
AA
t
t
OHA
OHA
DATA OUT
PREVIOUS DATAVALID
DATA VALID
Notes:
19.
tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual).
20. CE = VCC, Vin = GND to VCC, TA = 25°C. This parameter is guaranteed but not tested.
21. R/W is HIGH for read cycles.
22. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads.
23. OE = VIL
.
9
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
[21, 24, 25]
Read Cycle No. 2 (Either Port CE/OE Access)
t
ACE
CE
OE
t
HZCE
t
DOE
t
HZOE
t
LZOE
DATA VALID
DATA OUT
t
LZCE
t
PU
t
PD
I
CC
CURRENT
I
SB
[21, 23, 24, 25]
Read Cycle No. 3 (Either Port)
t
RC
ADDRESS
t
AA
t
OHA
t
LZCE
t
ABE
CE
t
HZCE
t
ACE
t
LZCE
DATA OUT
Notes:
24. Address valid prior to or coincident with CE transition LOW.
25. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = V .
IL
10
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
[26, 27, 28, 29]
Write Cycle No. 1: R/W Controlled Timing
t
WC
ADDRESS
OE
[31]
t
HZOE
t
AW
[30]
CE
[29]
PWE
t
SA
t
t
HA
R/W
DATAOUT
DATA IN
[31]
t
HZWE
t
LZWE
NOTE 32
NOTE 32
t
t
HD
SD
[26, 27, 28, 33]
Write Cycle No. 2: CE Controlled Timing
t
WC
ADDRESS
t
AW
[30]
CE
t
SA
t
t
HA
SCE
R/W
t
t
HD
SD
DATA IN
Notes:
26. R/W or CE must be HIGH during all address transitions.
27. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM.
28. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle.
29. If OEis LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on
the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE
30. To access RAM, CE = VIL, SEM = VIH
.
.
31. Transition is measured ±500 mV from steady state with a 5-pF load (including scope and jig). This parameter is sampled and not 100% tested.
32. During this period, the I/O pins are in the output state, and input signals must not be applied.
33. If the CEor SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
11
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
[34]
Semaphore Read After Write Timing, Either Side
t
AA
t
OHA
A –A
0
VALID ADRESS
VALID ADRESS
2
t
AW
t
ACE
t
HA
SEM
t
t
SOP
SCE
t
SD
I/O
0
DATA VALID
DATA
VALID
IN
OUT
t
HD
t
SA
t
PWE
R/W
OE
t
t
DOE
SWRD
t
SOP
WRITE CYCLE
[35, 36, 37]
READ CYCLE
Timing Diagram of Semaphore Contention
A
0L
–A
2L
MATCH
R/W
L
SEM
L
t
SPS
A
–A
2R
0R
MATCH
R/W
R
SEM
R
Notes:
34. CE = HIGH for the duration of the above timing (both write and read cycle).
35. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.
36. Semaphores are reset (available to both ports) at cycle start.
37. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable.
12
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
[38]
Timing Diagram of Read with BUSY (M/S=HIGH)
t
WC
ADDRESS
R
MATCH
t
PWE
R/W
R
t
t
HD
SD
DATA IN
VALID
R
t
PS
ADDRESS
L
MATCH
t
BLA
t
BHA
BUSY
L
t
BDD
t
DDD
DATA
VALID
OUTL
t
WDD
Write Timing with Busy Input (M/S=LOW)
t
PWE
R/W
t
t
WH
WB
BUSY
Note:
38. CEL = CER = LOW.
13
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
[39]
Busy Timing Diagram No. 1 (CE Arbitration)
CE Valid First:
L
ADDRESS
L,R
ADDRESS MATCH
CE
L
t
PS
CE
R
t
t
BHC
BLC
BUSY
R
CE ValidFirst:
R
ADDRESS
L,R
ADDRESS MATCH
CE
R
t
PS
CE
L
L
t
t
BHC
BLC
BUSY
[39]
Busy Timing Diagram No. 2 (Address Arbitration)
Left Address Valid First:
t
or t
WC
RC
ADDRESS
L
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
R
t
t
BHA
BLA
BUSY
R
Right Address Valid First:
t
or t
WC
RC
ADDRESS
R
ADDRESS MATCH
ADDRESS MISMATCH
t
PS
ADDRESS
L
t
t
BHA
BLA
BUSY
L
Note:
39. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
14
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Switching Waveforms
Interrupt Timing Diagrams
Left Side Sets INT :
R
t
WC
ADDRESS
L
WRITE 7FFF
[40]
t
HA
CE
L
R/W
INT
L
R
[41]
t
INS
Right Side Clears INT :
R
t
RC
READ 7FFF
ADDRESS
R
CE
R
[41]
INR
t
R/W
R
OE
R
INT
R
:
Right SideSets INT
L
t
WC
ADDRESS
R
WRITE 7FFE
[40]
HA
t
CE
R
R
R/W
INT
L
[41]
INS
t
Left Side Clears INT :
L
t
RC
ADDRESS
R
READ 7FFE
CE
L
L
[41]
INR
t
R/W
OE
L
L
INT
Notes:
40. tHA depends on which enable pin (CEL or R/WL) is deasserted first.
41. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last.
15
CY7C006A, CY7C007A
CY7C016A, CY7C017A
address match occurs within t of each other, the busy logic will
Architecture
PS
determine which port has access. If t is violated, one port will defi-
PS
The CY7C006A, CY7C007A, CY7C016A and CY7C017A
consist of an array of 32K/16K words of 8 bits and 32K words
of 9 bits each of dual-port RAM cells, I/O and address lines,
and control signals (CE, OE, R/W). These control pins permit inde-
pendent access for reads or writes to any location in memory. To
handle simultaneous writes/reads to the same location, a BUSY pin
is provided on each port. Two Interrupt (INT) pins can be utilized for
port-to-port communication. Two Semaphore (SEM) control pins are
used for allocating shared resources. With the M/S pin, the devices
can function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The devices also have an automatic pow-
er-down feature controlled by CE. Each port is provided with its own
Output Enable control (OE), which allows data to be read from the
device.
nitely gain permission to the location, but it is not predictable which
port will get that permission. BUSY will be asserted t
after an ad-
BLA
dress match or t
after CE is taken LOW.
BLC
Master/Slave
A M/S pin is provided in order to expand the word width by configur-
ing the device as either a master or a slave. The BUSY output of the
master is connected to the BUSY input of the slave. This will allow the
device to interface to a master device with no external components.
Writing to slave devices must be delayed until after the BUSY input
has settled (t
or t
), otherwise, the slave chip may begin a write
BLC
BLA
cycle during a contention situation. When tied HIGH, the M/S pin al-
lows the device to be used as a master and, therefore, the BUSY line
is an output. BUSY can then be used to send the arbitration outcome
to a slave.
Functional Description
Semaphore Operation
Write Operation
The CY7C006A, CY7C007A, CY7C016A and CY7C017A pro-
vide eight semaphore latches, which are separate from the
dual-port memory locations. Semaphores are used to reserve
resources that are shared between the two ports. The state of
the semaphore indicates that a resource is in use. For exam-
ple, if the left port wants to request a given resource, it sets a
latch by writing a zero to a semaphore location. The left port
then verifies its success in setting the latch by reading it. After
Data must be set up for a duration of t before the rising edge
SD
of R/W in order to guarantee a valid write. A write operation is con-
trolled by either the R/W pin (see Write Cycle No. 1 waveform) or the
CE pin (see Write Cycle No. 2 waveform). Required inputs for
non-contention operations are summarized in Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output; other-
wise the data read is not deterministic. Data will be valid on the
writing to the semaphore, SEMor OE must bedeasserted fort
SOP
before attempting to read the semaphore. The semaphore value will
be available t + t after the rising edge of the semaphore
port t
after the data is presented on the other port.
SWRD
DOE
DDD
write. If the left port was successful (reads a zero), it assumes control
of the shared resource, otherwise (reads a one) it assumes the right
port has control and continues to poll the semaphore. When the right
side has relinquished control of the semaphore (by writing a one), the
left side will succeed in gaining control of the semaphore. If the left
side no longer requires the semaphore, a one is written to cancel its
request.
Read Operation
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
asserted. If the user wishes to access a semaphore flag, then the
SEM pin must be asserted instead of the CE pin, and OE must also
be asserted.
after CE or t
after OE is
ACE
DOE
Semaphores are accessed by asserting SEM LOW. The SEM
pin functions as a chip select for the semaphore latches (CE must
Interrupts
remain HIGH during SEM LOW). A
represents the semaphore
The upper two memory locations may be used for message
passing. The highest memory location (7FFF) is the mailbox
for the right port and the second-highest memory location
(7FFE) is the mailbox for the left port. When one port writes to
the other port’s mailbox, an interrupt is generated to the owner.
The interrupt is reset when the owner reads the contents of the
mailbox. The message is user defined.
0–2
address. OE and R/W are used in the same manner as a normal
memory access. When writing or reading a semaphore, the other
address pins have no effect.
When writing to the semaphore, only I/O is used. If a zero is
0
written to the left port of an available semaphore, a one will appear at
the same semaphore address on the right port. That semaphore can
now only be modified by the side showing zero (the left port in this
case). If the left port now relinquishes control by writing a one to the
semaphore, the semaphore will be set to one for both sides. Howev-
er, if the right port had requested thesemaphore (written a zero) while
the left port had control, the right port would immediately own the
semaphore as soon as theleft port released it. Table 3 shows sample
semaphore operations.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
prevents the port from setting the interrupt to the winning port.
Also, an active busy to a port prevents that port from reading
its own mailbox and, thus, resetting the interrupt to it.
If an application does not require message passing, do not
connect the interrupt pin to the processor’s interrupt request
input pin.
When reading a semaphore, all data lines output the sema-
phore value. The read value is latched in an output register to
prevent the semaphore from changing state during a write
from the other port. If both ports attempt to access the sema-
The operation of the interrupts and their interaction with Busy
are summarized in Table 2.
phore within t
of each other, the semaphore will definitely be
SPS
Busy
obtained by one side or the other, but there is no guarantee which
side will control the semaphore.
The CY7C006A, CY7C007A, CY7C016A and CY7C017A pro-
vide on-chip arbitration to resolve simultaneous memory loca-
tion access (contention). If both ports’ CEs are asserted and an
16
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Table 1. Non-Contending Read/Write
Inputs
Outputs
–
CE
H
H
X
R/W
X
OE
X
SEM
H
I/O I/O
Operation
0
8
High Z
Deselected: Power-Down
H
L
L
Data Out
High Z
Read Data in Semaphore Flag
I/O Lines Disabled
Write into Semaphore Flag
Read
X
H
X
X
H
L
L
Data In
Data Out
Data In
H
L
L
H
L
X
H
Write
L
X
X
L
Not Allowed
Table 2. Interrupt Operation Example (assumes BUSY =BUSY =HIGH)
L
R
Left Port
Right Port
Function
Set Right INT Flag
R/W
CE
L
OE
X
A
INT
X
R/W
CE
X
OE
X
A
INT
L
L
L
L
L
L
0 –14
R
R
R
0R–14R
R
[43]
L
X
X
X
7FFF
X
X
L
X
L
R
[42]
Reset Right INT Flag
X
X
X
X
X
L
L
7FFF
7FFE
X
H
R
[42]
Set Left INT Flag
X
X
L
L
X
X
X
L
[43]
Reset Left INT Flag
L
L
7FFE
H
X
X
X
L
Table 3. Semaphore Operation Example
–
–
Function
I/O I/O Left I/O I/O Right
Status
0
8
0
8
No action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port has semaphore token
Left port writes 0 to semaphore
Right port writes 0 to semaphore
Left port writes 1 to semaphore
Left port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 1 to semaphore
Right port writes 0 to semaphore
Right port writes 1 to semaphore
Left port writes 0 to semaphore
Left port writes 1 to semaphore
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
Notes:
42. If BUSYR = L, then no change.
43. If BUSYL= L, then no change.
17
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Ordering Information
16K x8 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
(ns)
Ordering Code
CY7C006A-12AC
Package Type
Range
Commercial
Commercial
Commercial
Industrial
[1]
12
A65
J81
A65
A65
J81
J81
A65
J81
64-Pin Thin Quad Flat Pack
CY7C006A-12JC
CY7C006A-15AC
CY7C006A-15AI
CY7C006A-15JC
CY7C006A-15JI
CY7C006A-20AC
CY7C006A-20JC
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
15
20
64-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
64-Pin Thin Quad Flat Pack
Commercial
Industrial
Commercial
Commercial
68-Pin Plastic Leaded Chip CarrieR
32K x8 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
80-Pin Thin Quad Flat Pack
[1]
12
CY7C007A-12AC
A80
J81
A80
A80
J81
J81
A80
J81
Commercial
Commercial
Commercial
Industrial
CY7C007A-12JC
CY7C007A-15AC
CY7C007A-15AI
CY7C007A-15JC
CY7C007A-15JI
CY7C007A-20AC
CY7C007A-20JC
68-Pin Plastic Leaded Chip Carrier
80-Pin Thin Quad Flat Pack
15
20
80-Pin Thin Quad Flat Pack
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
80-Pin Thin Quad Flat Pack
Commercial
Industrial
Commercial
Commercial
68-Pin Plastic Leaded Chip CarrieR
16K x9 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
80-Pin Plastic Leaded Chip Carrier
80-Pin Plastic Leaded Chip Carrier
80-Pin Plastic Leaded Chip Carrier
80-Pin Plastic Leaded Chip Carrier
[1]
12
CY7C016A-12AC
A80
A80
A80
A80
Commercial
Commercial
Industrial
15
CY7C016A-15AC
CY7C016A-15IC
CY7C016A-20AC
20
Commercial
32K x9 Asynchronous Dual-Port SRAM
Speed
Package
Name
Operating
Range
(ns)
Ordering Code
Package Type
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
68-Pin Plastic Leaded Chip Carrier
[1]
12
CY7C017A-12JC
J81
J81
J81
J81
Commercial
Commercial
Industrial
15
20
CY7C017A-15JC
CY7C017A-15JI
CY7C017A-20JC
Commercial
Document #: 38-00831-*C
18
CY7C006A, CY7C007A
CY7C016A, CY7C017A
Package Diagrams
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
19
CY7C006A, CY7C007A
CY7C016A, CY7C017A
(continued)
Package Diagrams
80-Pin Thin Plastic Quad Flat Pack A80
51-85065-B
68-Lead Plastic Leaded Chip Carrier J81
51-85005-A
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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