CY62148BLL-55ZRC [ETC]
x8 SRAM ; X8 SRAM\n
| 型号： | CY62148BLL-55ZRC |
| 厂家： | 
ETC |
| 描述： | x8 SRAM
|
| 文件： | 总11页 (文件大小：195K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY62148B
512K x 8 Static RAM
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Features
• 4.5V–5.5V operation
• CMOS for optimum speed/power
• Low active power
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O0 through I/O7) is then written into the location speci-
fied on the address pins (A0 through A18).
— 165 mW (max.)
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH for read. Under these conditions, the con-
tents of the memory location specified by the address pins will
appear on the I/O pins.
• Low standby power (L version)
— 110 µW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options
The eight input/output pins (I/O0 through I/O7) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
Functional Description
The CY62148 is a high-performance CMOS static RAM orga-
nized as 524,288 words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
The CY62148 is available in a standard 32-pin 450-mil-wide
body width SOIC and 32-pin TSOP II packages.
Logic Block Diagram
Pin
Configuration
Top View
SOIC
TSOP II
VCC
A15
A18
A17
A16
32
31
30
1
2
3
4
5
6
7
A14
A12
A7
A6
29
28
27
26
WE
A13
A8
A5
A9
I/O
25
24
23
22
21
A4
A3
A2
0
8
9
10
11
12
13
A11
INPUT BUFFER
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
I/O
I/O
1
2
A
0
A1
A
1
A0
I/O0
A
4
20
19
A
5
6
I/O1
I/O2
GND
14
15
16
A
I/O
I/O
I/O
18
17
3
4
5
512 x 256 x 8
ARRAY
A
7
A
12
A
14
Top View
Reverse
TSOP II
A
16
A
17
I/O3
GND
I/O2
I/O1
17
18
19
20
21
22
16
15
14
13
12
11
10
9
8
7
6
5
I/O
6
7
I/O4
I/O5
POWER
DOWN
COLUMN
DECODER
CE
I/O0
I/O6
I/O7
CE
I/O
WE
A0
A1
A2
A3
A4
A5
A6
A7
A12
OE
23 A10
24
OE
A11
A9
A8
A13
25
26
27
28
29
30
4
3
2
1
WE
A18
A15
Vcc
A14
A16
A17
31
32
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05039 Rev. *A
Revised June 19, 2001
CY62148B
Selection Guide
CY62148BLL-55
CY62148BLL-70
Unit
ns
Max Access Time
55
30
30
20
20
70
20
20
20
20
Max Operating Current (Icc)
Commercial
Industrial
LL
LL
mA
mA
µA
Max CMOS Standby Current (ISB2)
Commercial
Industrial
µA
Current into Outputs (LOW) ........................................ 20 mA
Maximum Ratings
Static Discharge Voltage...............................................2001V
(per MIL-STD-883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied.............................................–55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND ....... –0.5V to +7.0V
Ambient
Temperature[2]
0°C to +70°C
VCC
DC Voltage Applied to Outputs
Range
Commercial
Industrial
in High Z State[1] .....................................–0.5V to VCC +0.5V
4.5V–5.5V
DC Input Voltage[1]..................................–0.5V to VCC +0.5V
–40°C to +85°C
Notes:
1.
VIL (min.) = –2.0V for pulse durations of less than 20 ns.
2. TA is the “Instant On” case temperature.
Document #: 38-05039 Rev. *A
Page 2 of 11
CY62148B
Electrical Characteristics Over the Operating Range
CY62148B-55
CY62148B-70
Parameter
VOH
Description
Test Conditions
Min. Typ.[3] Max. Min. Typ.(3) Max Unit
Output HIGH Voltage VCC = Min., IOH = – 1 mA
Output LOW Voltage VCC = Min., IOL = 2.1 mA
Input HIGH Voltage
2.4
2.2
2.4
2.2
V
V
V
VOL
0.4
0.4
VIH
VCC
+
VCC
+
0.3
0.3
VIL
IIX
Input LOW Voltage[1]
–0.3
–1
0.8
+1
+1
–0.3
–1
0.8
+1
+1
V
Input Load Current
GND ≤ VI ≤ VCC
µA
µA
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output Disabled
–1
–1
ICC
VCC Operating
Supply Current
VCC = Max.,
IOUT =0 mA,
f = fMAX = 1/tRC
Ind’l
Ind’l
LL
LL
30
20
mA
mA
ISB1
Automatic CE
Max. VCC
,
2.5
1.5
Power-Down Current CE ≥ VIH
—TTL Inputs
V
IN ≥ VIH or
VIN ≤ VIL, f = fMAX
ISB2
Automatic CE
Power-Down Current CE ≥ VCC – 0.3V,
Max. VCC
,
Ind’l
LL
4
20
4
20
µA
—CMOS Inputs
VIN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f =
0
ICC
VCC Operating
Supply Current
VCC = Max.,
Com
Com
LL
LL
30
20
mA
mA
I
OUT =0 mA,
f = fMAX = 1/tRC
ISB1
Automatic CE
Max. VCC
,
2.5
1.5
Power-Down Current CE ≥ VIH
—TTL Inputs
V
IN ≥ VIH or
VIN ≤ VIL, f = fMA
ISB2
Automatic CE
Max. VCC
,
Com
LL
4
20
4
20
µA
Power-Down Current CE ≥ VCC – 0.3V,
—CMOS Inputs IN ≥ VCC – 0.3V,
or VIN ≤ 0.3V, f=0
V
Capacitance[4]
Parameter
Description
Test Conditions
Max.
Unit
CIN
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 5.0V
6
8
pF
pF
COUT
Note:
3. Typical values are measured at VCC = 5V, TA = 25°C, and are included for reference only and are not tested or guaranteed.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05039 Rev. *A
Page 3 of 11
CY62148B
AC Test Loads and Waveforms
R1 1800Ω
R1 1800 Ω
5V
ALL INPUT PULSES
5V
5.0V
GND
OUTPUT
OUTPUT
R2
990Ω
90%
10%
90%
10%
R2
990Ω
100 pF
5 pF
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
≤ 3 ns
≤ 3 ns
(b)
(a)
Equivalent to:
THEVENIN EQUIVALENT
639Ω
1.77V
OUTPUT
Switching Characteristics[5] Over the Operating Range
CY62148BLL-55
62148BLL–70
Parameter
Description
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
55
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
55
70
tOHA
10
10
tACE
55
25
70
35
tDOE
tLZOE
5
10
0
5
10
0
tHZOE
20
20
55
25
25
70
tLZCE
tHZCE
tPU
tPD
WRITE CYCLE[8]
tWC
tSCE
tAW
tHA
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tSA
0
0
tPWE
tSD
45
30
0
55
30
0
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
tHD
tLZWE
5
5
tHZWE
WE LOW to High Z[6, 7]
20
25
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified IOL/IOH and 100-pF load capacitance.
6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE1 LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05039 Rev. *A
Page 4 of 11
CY62148B
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions
Min.
Typ.[2]
Max.
Unit
V
2.0
Com’l LL
Ind’l LL
No input may exceed
VCC + 0.3V
VCC = VDR = 3.0V
CE > VCC – 0.3V
VIN > VCC – 0.3V or
VIN < 0.3V
20
20
µA
µA
ns
[4]
tCDR
tR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
3.0V
3.0V
V
DR
> 2V
V
CC
t
t
R
CDR
CE
Switching Waveforms
Read Cycle No.1[9, 10]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[10, 11]
ADDRESS
CE
t
RC
t
ACE
OE
t
HZOE
t
DOE
t
HZCE
t
LZOE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PD
t
PU
V
CC
50%
50%
SUPPLY
I
CURRENT
SB
Notes:
9. Device is continuously selected. OE, CE = VIL.
10. WE is HIGH for read cycle.
11. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05039 Rev. *A
Page 5 of 11
CY62148B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[12]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[12, 13]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
OE
t
t
SD
HD
DATA VALID
DATA I/O
IN
NOTE 14
t
HZOE
Notes:
12. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
13. Data I/O is high-impedance if OE = VIH
.
14. During this period the I/Os are in the output state and input signals should not be applied.
Document #: 38-05039 Rev. *A
Page 6 of 11
CY62148B
Switching Waveforms (continued)
Write Cycle No.3 (WE Controlled, OE LOW)[12, 13]
t
WC
ADDRESS
CE
t
SCE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
NOTE 14
DATAI/O
DATA VALID
t
t
LZWE
HZWE
Truth Table
CE
H
L
OE
WE
I/O0 – I/O7
High Z
Mode
Power
X
L
X
H
L
Power-Down
Read
Standby (ISB
Standby (ICC
Active (ICC
Active (ICC
)
Data Out
Data In
High Z
)
L
X
H
Write
)
L
H
Selected, Outputs Disabled
)
Ordering Information
Speed
Package
Operating
Range
(ns)
Ordering Code
CY62148BLL-70SC
CY62148BLL-70ZC
CY62148BLL-70ZRC
CY62148BLL-70SI
CY62148BLL-70ZI
CY62148BLL-70ZRI
CY62148BLL-55SC
CY62148BLL-55ZC
CY62148BLL-55ZRC
CY62148BLL-55SI
CY62148BLL-55ZI
CY62148BLL-55ZRI
Name
Package Type
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
70
S34
Commercial
ZS32
ZU32
S34
32-Lead RTSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
Industrial
ZS32
ZU32
S34
32-Lead RTSOP II
55
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
Commercial
Industrial
ZS32
ZU3s
S34
32-Lead RTSOP II
32-Lead (450-Mil) Molded SOIC
32-Lead TSOP II
ZS32
ZU32
32-Lead RTSOP II
Document #: 38-05039 Rev. *A
Page 7 of 11
CY62148B
Package Diagrams
32-Lead (450 MIL) Molded SOIC S34
51-85081-A
Document #: 38-05039 Rev. *A
Page 8 of 11
CY62148B
Package Diagrams (continued)
32-Lead
TSOP II ZS32
51-85095
Document #: 38-05039 Rev. *A
Page 9 of 11
CY62148B
Package Diagrams (continued)
32-Lead Reverse Thin Small Outline Package Type II ZU32
-85138-**
Document #: 38-05039 Rev. *A
Page 10 of 11
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62148B
Document Title: CY62148B 512K x 8 Static RAM
Document Number: 38-05039
REV.
**
ECN NO.
106833
106970
Issue Date
05/01/01
07/16/01
Orig. of Change
Description of Change
SZV
GAV
Change from Spec number 38-01104 to 38-05039
*A
Modified annotations on Pin Configurations; tSD = 30 ns
Document #: 38-05039 Rev. *A
Page 11 of 11
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