CY62137VLL-70BAI [ETC]
x16 SRAM ; X16 SRAM
| 型号： | CY62137VLL-70BAI |
| 厂家： | 
ETC |
| 描述： | x16 SRAM
|
| 文件： | 总11页 (文件大小：304K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1*CY62137V18
MoBL2™
CY62137V MoBL™
128K x 16 Static RAM
high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), BHE and BLE are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW, and WE
LOW).
Features
• Low voltage range:
— CY62137V: 2.7V–3.6V
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is
written into the location specified on the address pins (A0
through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
Functional Description
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O8 to I/O15. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62137V is a high-performance CMOS static RAM or-
ganized as 131,072 words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL™) in portable
applications such as cellular telephones. The device also has
an automatic power-down feature that reduces power con-
sumption by 99% when addresses are not toggling. The device
can also be put into standby mode when deselected (CE
HIGH) or when CE is LOW and both BLE and BHE are HIGH.
The input/output pins (I/O0 through I/O15) are placed in a
The CY62137V is available in 48-ball FBGA and standard
44-pin TSOP Type II (forward pinout) packaging.
Logic Block Diagram
Pin
Configurations
TSOP II (Forward)
Top View
DATA IN DRIVERS
44
1
A
4
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
A
2
7
9
OE
A
A
1
8
BHE
BLE
I/O
I/O
14
I/O
A
0
A
7
6
5
CE
A
A
A
A
128K x 16
RAM Array
I/O
7
0
15
37
36
35
34
33
I/O –I/O
I/O
I/O
8
0
7
1
2
4
9
13
3
2
I/O –I/O
10
11
12
13
I/O
V
SS
I/O
12
8
15
3
CC
A
V
SS
A
V
V
1
0
CC
32
31
30
29
28
27
I/O
I/O
A
4
5
6
7
11
I/O
10
I/O
I/O
8
I/O
I/O
I/O
14
15
16
9
COLUMN DECODER
WE 17
NC
18
A
A
8
16
19
26
25
A
A
15
14
9
10
11
A
20
21
22
A
A
BHE
A
12
24
23
WE
CE
OE
13
A
NC
BLE
CE
Power Down
Circuit
BHE
BLE
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
February 2, 2001
CY62137V MoBL™
Pin Configurations (continued)
48-Ball FBGA
Top View
1
2
4
3
5
6
A
A
A
2
NC
I/O
OE
BLE
0
1
A
B
C
A
A
4
I/O BHE
8
CE
I/O
3
0
A
A
6
I/O I/O
I/O
2
5
9
10
1
A
V
V
I/O
I/O
3
NC
NC
CC
D
E
F
SS
7
11
A
V
CC
V
SS
I/O
I/O
16
12
4
A
A
15
I/O
I/O
I/O
I/O
6
14
13
5
14
A
A
G
H
I/O
I/O
NC
WE
13
12
15
7
A
A
9
A
A
NC
NC
10
11
8
DC Voltage Applied to Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
in High Z State[1]–0.5V to VCC + 0.5V
DC Input Voltage[1]–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)20 mA
Storage Temperature –65°C to +150°C
Static Discharge Voltage >2001V
(per MIL-STD-883, Method 3015)
Ambient Temperature with
Power Applied−55°C to +125°C
Latch-Up Current >200 mA
Supply Voltage to Ground Potential–0.5V to +4.6V
Operating Range
Device
CY62137V
Range
Ambient Temperature
VCC
2.7V to 3.6V
Industrial
–40°C to +85°C
Product Portfolio
Power Dissipation (Industrial)
Operating (ICC Standby (ISB2)
VCC Range
)
VCC
(max.)
2]
Product
VCC(min.) VCC(typ.)
Power
Typ.[2]
Max.
15 mA
Typ.[2]
Max.
CY62137V
2.7V
3.0V
3.6V
LL
7 mA
1 µA
15 µA
Notes:
1. VIL(min.) = –2.0V for pulse durations less than 20 ns.
2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC Typ., TA = 25°C.
2
CY62137V MoBL™
Electrical Characteristics Over the Operating Range
CY62137V
Parameter
VOH
VOL
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage Current
Test Conditions
Min.
Typ.[2]
Max.
Unit
V
IOH = –1.0 mA
VCC = 2.7V
VCC = 2.7V
VCC = 3.6V
VCC = 2.7V
2.4
IOL = 2.1 mA
0.4
VCC + 0.5V
0.8
V
VIH
2.2
–0.5
–1
V
VIL
V
IIX
GND < VI < VCC
+1
+1
7
+1
µA
µA
mA
IOZ
GND < VO < VCC, Output Disabled
–1
+1
ICC
VCC Operating Supply
Current
IOUT = 0 mA, VCC = 3.6V
15
f = fMAX = 1/tRC
,
CMOS Levels
IOUT =0mA,f=1MHz,
CMOS Levels
1
2
mA
ISB1
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V, f = fMAX
VCC = 3.6V
100
µA
ISB2
Automatic CE
Power-Down Current—
CMOS Inputs
CE > VCC – 0.3V
VIN > VCC – 0.3V
or VIN < 0.3V, f = 0
VCC
3.6V
=
LL
1
15
µA
9
Capacitance[3]
Parameter
Description
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = VCC(typ)
Max.
Unit
CIN
Input Capacitance
Output Capacitance
6
8
pF
pF
COUT
Thermal Resistance
Description
Test Conditions
Symbol
BGA
TSOPII
Unit
Thermal Resistance
Still Air, soldered on a 4.25 x 1.125 inch, 4-layer
printed circuit board
ΘJA
55
60
°C/W
(Junction to Ambient)[3]
Thermal Resistance
(Junction to Case)[3]
ΘJC
16
22
°C/W
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
3
CY62137V MoBL™
AC Test Loads and Waveforms
R1
R1
ALL INPUT PULSES
V
V
CC
CC
V
Typ
CC
90%
90%
OUTPUT
OUTPUT
10%
10%
R2
GND
5 pF
R2
30 pF
INCLUDING
JIG AND
SCOPE
Fall Time:
1 V/ns
Rise Time:
1 V/ns
INCLUDING
JIG AND
SCOPE
(a)
(b)
(c)
Equivalent to:
THÉVENIN EQUIVALENT
R
TH
OUTPUT
V
Parameters
3.0V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
1105
1550
645
RTH
VTH
1.75V
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
ICCDR
Description
VCC for Data Retention
Data Retention Current
Conditions[4]
Min.
Typ.[2]
Max.
3.6
Unit
V
1.0
VCC = 1.0V
LL
0.5
7.5
µA
CE > VCC – 0.3V,
VIN > VCC – 0.3V or
VIN < 0.3V
No input may exceed
VCC+0.3V
[3]
tCDR
Chip Deselect to Data
Retention Time
0
ns
ns
tR
Operation Recovery Time
70
Data Retention Waveform
DATA RETENTION MODE
> 1.0 V
VCC(min.)
VCC(min.)
V
V
DR
CC
t
t
R
CDR
CE
Note:
4. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified
IOL/IOH and 30 pF load capacitance.
4
CY62137V MoBL™
Switching Characteristics Over the Operating Range[4]
55 ns
70 ns
Parameter
Description
Min.
55
Max.
Min.
70
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
55
70
tOHA
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[5]
OE HIGH to High Z[5, 6]
CE LOW to Low Z[5]
10
10
tACE
55
25
70
35
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
5
10
0
5
10
0
25
25
25
25
CE HIGH to High Z[5, 6]
CE LOW to Power-Up
tPD
CE HIGH to Power-Down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low Z
BHE / BLE HIGH to High Z
55
55
70
70
tDBE
(7)
tLZBE
5
5
tHZBE
25
25
WRITE CYCLE[8, 9]
tWC
tSCE
tAW
Write Cycle Time
55
45
45
0
70
60
60
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
tHA
tSA
0
0
tPWE
tSD
40
25
0
50
30
0
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z[5, 6]
WE HIGH to Low Z[5]
tHD
tHZWE
tLZWE
20
25
5
10
60
tBW
BHE / BLE LOW to End of Write
50
Notes:
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
7. If both byte enables are toggled together this value is 10 ns.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
5
CY62137V MoBL™
Switching Waveforms
Read Cycle No. 1[10, 11]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 [11, 12]
t
RC
CE
t
PD
HZCE
t
t
ACE
OE
t
HZOE
t
DOE
BHE/BLE
t
LZOE
t
HZBE
t
DBE
t
LZBE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
LZCE
t
PU
V
I
CC
CC
SUPPLY
CURRENT
50%
50%
I
SB
Notes:
10. Device is continuously selected. OE, CE=VIL
11. WE is HIGH for read cycle.
.
12. Address valid prior to or coincident with CE transition LOW.
6
CY62137V MoBL™
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
t
AW
HA
t
SA
t
PWE
WE
t
BW
BHE/BLE
OE
t
SD
t
HD
DATA I/O
DATA VALID
IN
NOTE15
t
HZOE
Write Cycle No. 2 (CE Controlled)[8, 13, 14]
t
WC
ADDRESS
CE
t
SCE
t
SA
t
t
HA
AW
t
BW
BHE/BLE
t
PWE
WE
t
t
HD
SD
DATA I/O
DATA VALID
IN
Notes:
13. Data I/O is high-impedance if OE = VIH
.
14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
15. During this period, the I/Os are in output state and input signals should not be applied.
7
CY62137V MoBL™
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 14]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 15
IN
t
t
LZWE
HZWE
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[15]
t
WC
ADDRESS
CE
t
t
HA
AW
t
BW
BHE/BLE
WE
t
SA
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 15
IN
t
t
LZWE
HZWE
8
CY62137V MoBL™
Typical DC and AC Characteristics
Normalized Operating Current
vs. Supply Voltage
Standby Current vs. Supply Voltage
35
1.4
1.2
MoBL
30
MoBL
25
20
15
1.0
0.8
0.6
10
0.4
5
0
0.2
0.0
2.7
1.0
3.7
2.8
1.9
1.7
2.2
2.7
3.2
3.7
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
80
70
MoBL
60
50
40
30
20
10
1.0
3.7
2.8
1.9
2.7
SUPPLY VOLTAGE (V)
Truth Table
CE
H
L
WE
X
OE
BHE
BLE
X
Inputs/Outputs
Mode
Power
Standby (ISB
Standby (ISB
Active (ICC
Active (ICC
X
X
L
L
X
H
L
High Z
High Z
Deselect/Power-Down
Deselect/Power-Down
Read
)
X
H
)
L
H
L
Data Out (I/OO–I/O15
)
)
L
H
H
L
Data Out (I/OO–I/O7);
I/O8–I/O15 in High Z
Read
)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High Z
Read
Active (ICC)
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High Z
High Z
High Z
Deselect/Output Disabled
Deselect/Output Disabled
Deselect/Output Disabled
Write
Active (ICC
Active (ICC
Active (ICC
Active (ICC
Active (ICC
)
)
)
L
Data In (I/OO–I/O15
)
)
L
H
Data In (I/OO–I/O7);
I/O8–I/O15 in High Z
Write
)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0 –I/O7 in High Z
Write
Active (ICC)
9
CY62137V MoBL™
Ordering Information
Speed
(ns)
Package
Name
Operating
Range
Ordering Code
Package Type
55
CY62137VLL-55ZI
CY62137VLL-55BAI
CY62137VLL-70ZI
CY62137VLL-70BAI
Z44
BA48
Z44
44-Pin TSOP II
Industrial
48-Ball Fine Pitch BGA
44-Pin TSOP II
70
Industrial
BA48
48-Ball Fine Pitch BGA
Document #: 38-00738-*D
Package Diagrams
48-Ball (7.00 mm x 7.00 mm) FBGA BA48
51-85096-D
10
CY62137V MoBL™
Package Diagrams (continued)
44-Pin TSOP II Z44
51-85087-A
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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