CXL1008M/P [ETC]
CMOS-CCD Signal Processor for Skew Compensation ; CMOS ， CCD信号处理器，用于补偿倾斜\n
| 型号： | CXL1008M/P |
| 厂家： | 
ETC |
| 描述： | CMOS-CCD Signal Processor for Skew Compensation
|
| 文件： | 总13页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXL1008M/P
CMOS-CCD Signal Processor for Skew Compensation
For the availability of this product, please contact the sales office.
Description
CXL1008M
CXL1008P
CXL1008M/P are CMOS-CCD signal processors
developed for the variable-speed video signal processor
for home-use 8mm VCRs.
28 pin SOP (Plastic)
28 pin DIP (Plastic)
Features
• Low power consumption 105mW (Typ.)
• Built-in peripheral circuit
• Adjustment is necessary for one part.
Structure
CMOS-CCD
Functions
• 1/2H 359-bit, direct 20-bit CCD register
• Clock driver
• Timing oscillation circuit
• Automatic bias circuit
• Sync tip clamp circuit
• Dummy VD insert circuit
• Sample/hold circuit
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD
VCL
11
6
V
V
• Operating temperature Topr
• Storage temperature Tstg
• Allowable power dissipaiton
–10 to +60
–55 to +150
°C
°C
PD CXL1008M 500 mW
CXL1008P 1000 mW
Recommended Operating Conditions
Supply voltage
VDD
VCL
9V ± 5
5V ± 5
%
%
Recommended Clock Conditions
• Clock input amplitude VCLK 0.15 to 1.0 (0.3 Typ.) Vp-p
• Clock frequency 10.738635 MHz
fCLK
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E60248-PS
CXL1008M/P
Block Diagram
13
19
24
25 23 21 12
AUTOBIAS
CIRCUIT
1/2H
OUTPUT
CIRCUIT
SIG IN1 11
D
50mV
28
27
T10
T9
50mV
REFERENCE
10
MUTE IN
OUTPUT
CONTROL
26
SKEW IN
SKEW
17 JOG IN
16 EXT VD
15 T8
φ1
φ2
DRIVER
TIMING
T1
T2
2
DUTY
9
T7
CONTROL GENERATOR
3
4
5
6
1
18 14 20
7
22
8
Pin Configuration (Top View)
T8 15
14 VCL
13
EXT VD 16
JOG IN 17
AUTO
12 SIG IN2
11 SIG IN1
18
19
VSS
SIG OUT
10
9
8
7
6
5
4
3
2
1
MUTE IN
T7
VDD 20
SIG DELAY 21
REC/PB 22
T6
CLK IN
T5
23
CCD OUT
FEED OUT 24
FEED IN 25
T4
T3
26
27
28
SKEW IN
T9
T2
T1
T10
VSS
– 2 –
CXL1008M/P
Pin Description
Pin
No.
Supply
voltage
Impedance
Symbol
I/O
Description
(Ω)
1
VSS
GND
7
CLK IN
I
I
0.3Vp-p
Input the sine wave of 3fsc (10.738635MHz)
> 50k
5V when
muting,
The video signal mute is generated at High level.
See the Logic Table of Signal Output Selection
10
MUTE IN
> 100k
normally 0V State (Table 1).
1.1Vp-p or
less
Signal input pin of CCD DL.
Input composite video signal.
11
12
SIG IN1
SIG IN2
I
> 100k
2.2Vp-p or
less
Signal input pin of the through side.
Input composite video signal.
I
> 100k
10k
13
14
AUTO
O
The DC level of automatic bias is output.
Power supply 1
VCL
+5V
5V when VD Use this pin when VD is inserted to the video signal
16
EXT VD
JOG IN
I
I
> 100k
> 100k
is inserted
with the extrenal dummy VD signal input.
JOG mode
5V
PB/REC
mode 0V
JOG/NORMAL PB selection pin.
See the Logic Table of Signal Output Selection
State (Table 1).
17
18
19
20
VSS
GND
SIG OUT
VDD
O
Final output
Power supply 2
0.6 to 1.5k
+9V
After the output from Pin 23 CCD OUT passes through
LPF, input it to the same pin and insert clamp and VD.
21
22
SIG DELAY
REC/PB
I
I
> 100k
> 100k
5V when PB Operate the clock at High when PB.
0V when REC Stop the clock at Low when REC.
23
24
CCD OUT
O
O
Direct output from CCD DL
Feedback DC output
0.6 to 1.5k
10k
FEED OUT
Smoothing capacitor connection pin of the bias
commutation loop on the output circuit
25
FEED IN
SKEW IN
I
> 100k
Select Direct DL and 1/2H DL signals when High
and Low, respectively.
See the Logic Table of CCD DL Mode Selection
(Table 2).
26
I
> 100k
Note) T1 through T10 test pins must be connected as shown in the application circuit because of the IC
internal circuit.
Notes on Handling
Countermeasures for electrostatics are necessary because some pins have low electrostatic strength
(particularly Pin 26: SKEW IN).
– 3 –
CXL1008M/P
– 4 –
CXL1008M/P
– 5 –
CXL1008M/P
[ d B ]
[ d B ]
– 6 –
CXL1008M/P
Notes)
1) Current value when the clock is in operation in the PB or JOG mode.
In the REC mode, the clock is stopped (Pin 22 is at low) to save power.
2) With the signal input pin voltage value, the video signal sync tip is clamped.
3) Vdo1 is a CCD OUT output voltage when the SIG IN1 input voltage is Vdi1.
Vdo2 is a SIG OUT output voltage when the SIG IN2 input voltage is Vdi2.
Vdo1 and Vdo2 represent outputs for the sync tip clamp level when a white level signal is input as shown
in the diagram.
Output signal
Vdo
40%
100%
1.0Vp-p
Vdi Input signal
4) ∆Dab denotes an output voltage difference of CCD OUT when the direct DL and 1/2H DL are switched.
5) IGCCD is a CCD OUT gain when a 1.1Vp-p 100kHz sine wave is input to SIG IN1.
Output amplitude (Vp-p)
IGCCD = 20 log
1.1Vp-p
It is measured by giving a Vdi1 + 0.6 bias with VBias.
IGin2 and IGDL are SIG OUT gains when 2.2Vp-p 100kHz sine wave is input to each of SIG IN2 and SIG
DELAY pins.
Output amplitude (Vp-p)
IGin2 = 20 log
2.2Vp-p
It is measured by giving a Vdi2 + 1.1V bias with VBias.
– 7 –
CXL1008M/P
6) ∆Gab is a gain difference between the direct DL and 1/2H DL.
7) It represents a loss at 3.58MHz compared with 100kHz.
It is measured by raising the SIG IN1 input pin by 0.6V higher than the sync tip clamp level (Vdi1) with VBias.
3.85MHz 300mVp-p sine wave
100kHz 300mVp-p sine wave
VBias = Vdi1 + 0.6V
SIG IN1 DC
V3.58MHz output
FCCD = 20 log
V100kHz output
8) It represents a loss at 10MHz compared with 100kHz.
It is measured by raising the SIG IN2 or SIG DELAY input pin by 1.1V higher than the sync tip clamp level
(Vdi2 or Vdi3) with VBias.
9) ∆Fab is a frequency response difference between the direct DL and 1/2H DL.
10)
Chroma 40 IRE
1.1Vp-p at DGCCD
2.2Vp-p at DGin2 or DGDL
140 IRE
40 IRE
1H 63.5µs
DG is measured with a vectorscope in each mode of the 5-stage waves.
11) Measure S/N of the BPF 100kHz to 4.2MHz in the subcarrier trap mode with a video noise meter.
12)
SIG DELAY
Input waveform
EXT VD input
SIG OUT
Output waveform
2Vp-p
VVD
Set a voltage value at VVD when inserting EXT VD to the 2Vp-p signal output waveform sync tip of SIG OUT.
– 8 –
CXL1008M/P
CLOCK
3fsc (10.738635MHz) Sine wave
0.15 to 1.0Vp-p
Function Outline
Output signal selection
SIG IN2
(PB)
SIG DELAY
(JOG)
SIG OUT
50mV
REF
The video output signal is selected by selecting the output switch for three signals: Pin 10 (MUTE IN), Pin 17
(JOG IN) and Pin 16 (EXT VD).
Table 1. Logic Table of Signal Output Selection State
Input control signal state
Video signal output selection state
JOG IN
MUTE IN
EXT VD
PB
O
O
×
JOG
×
VD insert
MUTE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
O
O
×
×
×
×
×
O
×
×
×
O
×
×
×
×
O
O
×
×
O
Note 1) Figures "0" and "1" of the input control signal state are equivalent to "Low" and "High" of logic.
Note 2) Items marked with the symbol "O" in the video signal output selection state are selected.
Note 3) PB = JOG IN · MUTE IN
JOG = JOG IN · MUTE IN · EXT VD
VD insert = JOG IN · EXT VD
MUTE = MUTE IN
– 9 –
CXL1008M/P
CCD selection
Table 2. Logic Table of CCD DL Mode
Selection
1/2H (359bit)
D (20bit)
SIG
IN1
Control signal
CCD DL mode
CCD OUT
SKEW IN
D
×
1/2H
O
0
1
SKEW IN
O
×
Application Circuit
9V
390
390
8.2k
1.8k
1k
2.2k 4.7k
1.5k
560
120 10µH
220
SIGNAL OUTPUT
10µ
10µ
2k
18k
220p 270p
10k
0.022µ
220k
JOG EXT
10µ
1000p
18
REC/PB
47µ
IN
VD
SKEW IN
22µ
1M
10k
25
220k
28
27
26
24
23
22
21
20
19
10
17
16
15
1
2
3
4
5
6
7
8
9
11
12
13
14
47µ 1000p
10µ
2M
2M
5V
100k
0.01µF
3fsc
0.047µ
MUTE
IN
0.047µ
0.3Vp-p
SINE WAVE
SIGNAL
INPUT
Transistor to be used
PNP: 2SA1175
510
510
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Frequency characteristics (Ta = 25°C)
0
–1
–2
10k
100k
1M
f – Frequency [Hz]
– 10 –
CXL1008M/P
Supply voltage (VCL) vs.
Insert gain (IGCCD)
Supply voltage (VCL) vs.
Frequency characteristics (fCCD)
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
4.75
5.00
5.25
5.25
9.5
4.75
5.00
5.25
5.25
9.5
VCL – Supply voltage [V]
VCL – Supply voltage [V]
Supply voltage (VCL) vs.
Differential gain (DGCCD)
Supply voltage (VCL) vs.
Output pin voltage (Vdo1)
5
4
3
2
1
0
2.5
2.0
1.5
4.75
5.00
4.75
5.00
VCL – Supply voltage [V]
VCL – Supply voltage [V]
Supply voltage (VDD) vs.
Insert gain (IGCCD)
Supply voltage (VDD) vs.
Frequency characteristics (fCCD)
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
8.5
9.0
8.5
9.0
VDD – Supply voltage [V]
VDD – Supply voltage [V]
– 11 –
CXL1008M/P
Supply voltage (VDD) vs.
Differential gain (DGCCD)
Supply voltage (VDD) vs.
Output pin voltage (Vdo1)
5
4
3
2
1
0
2.5
2.0
1.5
8.5
9.0
9.5
8.5
9.0
9.5
VDD – Supply voltage [V]
VDD – Supply voltage [V]
Ambient temperature (Ta) vs.
Insert gain (IGCCD)
Ambient temperature (Ta) vs.
Frequency characteristics (fCCD)
2
1
1
0
0
–1
–2
–3
–4
–1
–2
–3
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Ambient temperature (Ta) vs.
Differential gain (DGCCD)
Ambient temperature (Ta) vs.
Output pin voltage (Vdo1)
5
4
3
2
1
0
2.5
2.0
1.5
0
20
40
60
0
20
40
60
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
– 12 –
CXL1008M/P
Package Outline
CXL1008M
Unit: mm
28PIN SOP (PLASTIC)
+ 0.4
18.8 – 0.1
+ 0.4
2.3 – 0.15
28
15
0.15
+ 0.2
0.1 – 0.05
1
14
+ 0.1
0.15 – 0.05
1.27
0.45 ± 0.1
M
0.24
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
SONY CODE
SOP-28P-L02
SOP028-P-0375
EIAJ CODE
PACKAGE MASS
JEDEC CODE
0.6g
CXL1008P
28PIN DIP (PLASTIC)
+ 0.4
37.8 – 0.1
28
15
0° to 15°
1
14
2.54
0.5 ± 0.1
1.2 ± 0.15
Two kinds of package surface:
1.All mat surface type.
2.Center part is mirror surface.
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
DIP-28P-03
EIAJ CODE
DIP028-P-0600
COPPER ALLOY
4.2g
JEDEC CODE
PACKAGE MASS
– 13 –
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