CAT93HC46P-1.8 [ETC]
Microwire Serial EEPROM ; Microwire串行EEPROM\n型号: | CAT93HC46P-1.8 |
厂家: | ETC |
描述: | Microwire Serial EEPROM
|
文件: | 总10页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT93HC46
1K-Bit High Speed Microwire Serial EEPROM
FEATURES
ꢀ High speed operation:
ꢀ Hardware and software write protection
ꢀ Power-up inadvertent write protection
ꢀ 1,000,000 program/erase cycles
ꢀ 100 year data retention
– 93HC46: 3MHz
ꢀ Low power CMOS technology
ꢀ 1.8 to 6.0 volt operation
ꢀ Selectable x8 or x16 memory organization
ꢀꢀ Self-timed write cycle with auto-clear
ꢀ Sequential Read
ꢀ Commercial, industrial and automotive
temperature ranges
DESCRIPTION
technology. Thedeviceisdesignedtoendure1,000,000
program/erase cycles and has a data retention of 100
years. The CAT93HC46 is available in 8-pin DIP, 8-pin
SOIC or 8-pin TSSOP packages.
The CAT93HC46 is a 1K-bit Serial EEPROM memory
devices which is configured as either registers of 16 bits
(ORG pin at VCC) or 8 bits (ORG pin at GND). Each
register can be written (or read) serially by using the DI
(or DO) pin. The CAT93HC46 is manufactured using
Catalyst’s advanced CMOS EEPROM floating gate
PIN CONFIGURATION
TSSOP Package (U)
SOIC Package (J)
SOIC Package (S)
DIP Package (P)
1
2
3
4
8
7
6
5
CS
SK
DI
V
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CC
CS
SK
DI
V
ORG
GND
DO
CS
SK
DI
V
CC
NC
CC
NC
NC
V
NC
ORG
GND
CC
CS
ORG
GND
ORG
GND
DO
DO
SK
DI
DO
PIN FUNCTIONS
BLOCK DIAGRAM
Pin Name
CS
Function
V
GND
CC
Chip Select
SK
Clock Input
ADDRESS
DECODER
DI
Serial Data Input
Serial Data Output
MEMORY ARRAY
ORGANIZATION
ORG
DO
VCC
GND
ORG
NC
+1.8 to 6.0V Power Supply
Ground
DATA
REGISTER
OUTPUT
BUFFER
Memory Organization
No Connection
DI
MODE DECODE
LOGIC
CS
PE*
PE*
Program Enable
Note: When the ORG pin is connected to VCC, the X16
organization is selected. When it is connected to ground,
the X8 pin is selected. If the ORG pin is left unconnected,
then an internal pullup device will select the X16
organization.
CLOCK
GENERATOR
DO
SK
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1008,Rev. A
1
CAT93HC46
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
V
CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
3
mA
fSK = 3MHz
VCC = 5.0V
ICC2
ISB1
Power Supply Current
(Operating Read)
500
10
0
µA
µA
µA
µA
fSK = 3MHz
VCC = 5.0V
Power Supply Current
(Standby) (x8 Mode)
CS = 0V
ORG=GND
(5)
ISB2
Power Supply Current
(Standby) (x16Mode)
CS=0V
ORG=Float or VCC
ILI
Input Leakage Current
(Including ORG pin)
1
VIN = 0V to VCC
ILO
Output Leakage Current
(Including ORG pin)
1
µA
VOUT = 0V to VCC
,
CS = 0V
VIL1
VIH1
VIL2
VIH2
VOL1
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.1
0.8
VCC+1
VCCX0.2
VCC+1
0.4
4.5V≤VCC<5.5V
4.5V≤VCC<5.5V
1.8V≤VCC<4.5V
1.8V≤VCC<4.5V
V
V
V
V
V
2
0
VCCX0.7
4.5V≤VCC<5.5V,
IOL=2.1mA
VOH1
Output High Voltage
2.4
V
4.5V≤VCC<5.5V,
IOH = -400mA
V
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
1.8V≤VCC<4.5V, IOL=1mA
VCC-0.2
1.8V≤VCC<4.5V,
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (ISB )=0µA (<900nA).
2
Doc. No. 1008, Rev. A
2
CAT93HC46
RECOMMENDED OPERATING CONDITIONS
Device
Supply Voltage Range
Temperature Minimum
Maximum
+70˚C
CAT93HC46
CAT93HC46-1.8
2.5V to 6.0V
1.8V to 6.0V
Commercial
Industrial
0˚C
-40˚C
-40˚C
-40˚C
+85˚C
Automotive
Extended
+105˚C
+125˚C
PIN CAPACITANCE
Symbol
Test
Max.
Units
Conditions
(1)
COUT
OUTPUT CAPACITANCE (DO)
5
pF
VOUT=0V, tA=25˚C,
fSK=1MHz
(1)
CIN
INPUT CAPACITANCE (CS, SK, DI, ORG)
5
pF
VIN=0V, tA=25˚C, fSK=1MHz
INSTRUCTION SET
Start
Address
x16
Data
Instruction
Bit Opcode x8
x8
x16 Comments
Read Address AN–A0
READ
1
1
1
1
1
1
1
10
11
01
00
00
00
00
A6-A0 A5-A0
A6-A0 A5-A0
A6-A0 A5-A0
ERASE
WRITE
EWEN
EWDS
ERAL
Clear Address AN–A0
D15-D0 Write Address AN–A0
Write Enable
D7-D0
11XXXXX
00XXXXX
10XXXXX
01XXXXX
11XXXX
00XXXX
10XXXX
01XXXX
Write Disable
Clear All Addresses
WRAL
D7-D0
D15-D0 Write All Addresses
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1008, Rev. A
3
CAT93HC46
(1)(2)
POWER-UP TIMING
SYMBOL
tPUR
PARAMETER
Max
1
Units
ms
Power-up to Read Operation
Power-up to Write Operation
tPUW
1
ms
A.C. CHARACTERISTICS
Limits
VCC
2.5V-6V
VCC
1.8V-6V*
=
=
VCC
4.5V-5.5V
=
SYMBOL PARAMETER
Min.
200
0
Max.
Min.
Max.
Min.
50
0
Max. UNITS
ns
tCSS
tCSH
tDIS
CS Setup Time
150
0
CS Hold Time
ns
ns
ns
µs
µs
ns
ms
µs
µs
µs
µs
DI Setup Time
400
400
250
250
50
50
tDIH
tPD1
tPD0
DI Hold Time
CL = 100pF
Output Delay to 1
1
1
0.5
0.5
200
5
0.1
0.1
100
5
(3)
Output Delay to 0
(1)
tHZ
Output Delay to High-Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
400
5
tEW
tCSMIN
tSKHI
tSKLOW
tSV
1
1
1
0.5
0.5
0.5
0.1
0.1
0.1
1
0.5
0.1
SKMAX
DC
250
DC
1000
DC
3000 KHZ
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
(3) The input levels and timing reference points are shown in “AC Test Conditions” table.
A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
≤ 50ns
0.4V to 2.4V
4.5V ≤ VCC ≤ 5.5V
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ VCC ≤ 4.5V
1.8V ≤ VCC ≤ 4.5V
Timing Reference Voltages
Input Pulse Voltages
0.8V, 2.0V
0.3VCC to 0.7VCC
0.5VCC
Timing Reference Voltages
Doc. No. 1008, Rev. A
4
CAT93HC46
DEVICE OPERATION
The ready/busy status can be determined after the start
ofawriteoperationbyselectingthedevice(CShigh)and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that
the device is ready for the next instruction. If necessary,
the DO pin may be placed back into a high impedance
state during chip select by shifting a dummy “1” into the
DIpin. TheDOpinwillenterthehighimpedancestateon
the falling edge of the clock (SK). Placing the DO pin into
thehighimpedancestateisrecommendedinapplications
where the DI pin and the DO pin are to be tied together
to form a common DI/O pin.
The CAT93HC46 is a 1024-bit nonvolatile memory
intendedforusewithindustrystandardmicroprocessors.
TheCAT93HC46canbeorganizedaseitherregistersof
16 bits or 8 bits. When organized as X16, seven 9-bit
instructions control the reading, writing and erase
operations of the device. When organized as X8, seven
10-bit instructions control the reading, writing and erase
operations of the device. The CAT93HC46 operates on
a single power supply and will generate on chip, the high
voltage required during any write operation.
Instructions, addresses, and write data are clocked into
the DI pin on the rising edge of the clock (SK). The DO
pin is normally in a high impedance state except when
reading data from the device, or when checking the
ready/busy status after a write operation.
Figure 1. Sychronous Data Timing
t
t
t
SKLOW
SKHI
CSH
SK
t
t
DIS
DIH
VALID
VALID
DI
t
CSS
CS
t
t
t
t
DIS
PD0, PD1
CSMIN
DO
DATA VALID
Figure 2a. Read Instruction Timing
SK
CS
t
CSMIN
STANDBY
A
A
A
0
N
N—1
DI
1
1
0
t
HZ
t
HIGH-Z
HIGH-Z
PD0
DO
0
D
D
D
D
0
N
N—1
1
Doc. No. 1008, Rev. A
5
CAT93HC46
The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit byte/
word address (an additional bit when organized X8) and
for write operations a 16-bit data field (8-bit for X8
organizations).
back to address 0. In the sequential READ mode, only
the initial data word is preceeded by a dummy zero bit.
All subsequent data words will follow without a dummy
zero bit.
Write
Read
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93HC46 can be determined by selecting the
deviceandpollingtheDOpin. Sincethisdevicefeatures
Auto-Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93HC46
will come out of the high impedance state and, after
sending an initial dummy zero bit, will begin shifting out
the data addressed (MSB first). The output data bits will
toggle on the rising edge of the SK clock and are stable
after the specified time delay (tPD0 or tPD1
)
After the initial data word has been shifted out and CS
remains asserted with the SK clock continuing to toggle,
the CAT93HC46 will automatically increment to the next
address and shift out the next data word in a sequential
READ mode. As long as CS is continuously asserted
and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
oftCSMIN.ThefallingedgeofCSwillstarttheselfclocking
Figure 2b. Sequential Read Instruction Timing
SK
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CS
DI
Don't Care
A
A
A
0
N
N–1
1
1
0
HIGH-Z
DO
Dummy 0
D
D
Address + 1 Address + 2 Address + n
15 . . .
0
or
D
D
D
D
D
15 . . .
0
15 . . .
or
D
0
15 . . .
D
D
0
or
or
7 . . .
D
D
D
D
7 . . .
7 . . .
0
7 . . .
0
Figure 3. Write Instruction Timing
SK
t
CS MIN
STANDBY
STATUS
VERIFY
CS
A
A
A
0
D
D
0
N
N-1
N
DI
1
0
1
t
t
SV
HZ
BUSY
HIGH-Z
DO
READY
HIGH-Z
t
EW
93C46/56/57/66/86 F05
Doc. No. 1008, Rev. A
6
CAT93HC46
of all memory locations in the device. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. (Note 1.) The ready/busy status of
the CAT93HC46 can be determined by selecting the
deviceandpollingtheDOpin.Oncecleared,thecontents
of all memory bits return to a logical “1” state.
clearcycleoftheselectedmemorylocation.Theclocking
of the SK pin is not necessary after the device has
entered the self clocking mode. (Note 1.) The ready/
busy status of the CAT93HC46 can be determined by
selecting the device and polling the DO pin. Once
cleared, the content of a cleared location returns to a
logical “1” state.
Write All
Erase/Write Enable and Disable
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
data write to all memory locations in the device. The
clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy
statusoftheCAT93HC46 canbedeterminedbyselecting
the device and polling the DO pin. It is not necessary for
all memory locations to be cleared before the WRAL
command is executed.
The CAT93HC46 powers up in the write disable state.
Any writing after power-up or after an EWDS (write
disable) instruction must first be preceded by the EWEN
(write enable) instruction. Once the write instruction is
enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93HC46 write
and clear instructions, and will prevent any accidental
writing or clearing of the device. Data can be read
normally from the device regardless of the write enable/
disable status.
Note 1: After the last data bit has been sampled, Chip
Select (CS) must be brought Low before the next rising
edgeoftheclock(SK)inordertostarttheself-timedhigh
voltage cycle. This is important because if the CS is
brought low before or after this specific frame window,
theaddressedlocationwillnotbeprogrammedorerased.
Erase All
UponreceivinganERALcommand,theCS(ChipSelect)
pin must be deselected for a minimum of tCSMIN. The
falling edge of CS will start the self clocking clear cycle
Figure 4. Erase Instruction Timing
SK
CS
STANDBY
STATUS VERIFY
CS MIN
t
A
A
0
A
N
N-1
DI
1
1
1
t
t
HZ
SV
HIGH-Z
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1008, Rev. A
7
CAT93HC46
Figure 5. EWEN/EWDS Instruction Timing
SK
CS
STANDBY
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 6. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
t
CS MIN
DI
1
0
0
1
0
t
t
SV
HZ
HIGH-Z
HIGH-Z
DO
BUSY
READY
t
EW
Figure 7. WRAL Instruction Timing
SK
CS
STATUS VERIFY
CS MIN
STANDBY
t
D
D
0
DI
1
0
0
0
1
N
t
t
SV
HZ
DO
BUSY
READY
HIGH-Z
t
EW
Doc. No. 1008, Rev. A
8
CAT93HC46
ORDERING INFORMATION
Prefix
Device #
93HC46
Suffix
-1.8
CAT
TE13
I
S
Optional
Company ID
Temperature Range
Tape & Reel
TE13: 2000/Reel
Product
Blank = Commercial (0°C to +70°C)
I = Industrial (-40°C to +85°C)
A = Automotive (-40°C to +105°C)
Number
93HC46: 1K
E = Extended (-40˚C to +125˚C)
Package
P = PDIP
S = SOIC (JEDEC)
J = SOIC (JEDEC)
U = TSSOP
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
Notes:
(1) The device used in the above example is a 93HC46SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc. No. 1008, Rev. A
9
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1008
Revison:
Issue date:
Type:
A
10/16/01
Final
相关型号:
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