BUS-61570-320Y
更新时间:2024-09-18 08:18:35
品牌:ETC
描述:MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HYer)
BUS-61570-320Y 概述
MIL-STD-1553B NOTICE 2 ADVANCED INTEGRATED MUX HYBRIDS WITH ENHANCED RT FEATURES (AIM-HYer) MIL- STD- 1553B注意2先进的集成MUX具有增强RT杂种特点( AIM- HYER )
BUS-61570-320Y 数据手册
通过下载BUS-61570-320Y数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载BUS -6 1 5 5 9 S ERIES
MIL-S TD-1 5 5 3 B NOTICE 2
ADVANCED INTEGRATED MUX HYBRIDS
WITH ENHANCED RT FEATURES (AIM-HY’e r)
DESCRIPTION
FEATURES
DDC’s BUS-61559 series of Advanced buffers to provide a direct interface to
Integrated Mux Hybrids with enhanced a host processor bus. Alternatively,
RT Features (AIM-HY’er) comprise a the buffers may be operated in a fully
complete interface between a micro- transparent mode in order to interface
• Complete Integrated 1553B
Notice 2 Interface Terminal
processor and
a MIL-STD-1553B to up to 64K words of external shared
• Functlonal Superset of BUS-
61553 AlM-HYSeries
Notice bus, implementing Bus RAM and/or connect directly to a com-
2
Controller (BC), Remote Terminal (RX, ponent set supporting the 20 MHz
and Monitor Terminal (MT) modes. STANAG-3910 bus.
• Internal Address and Data
Buffers for Dlrect Interface to
Processor Bus
Packaged in a single 78-pin DIP or
The memory management scheme
82-pin flat package the BUS-61559
for RT mode prevails an option for
series contains dual low-power trans-
separation of broadcast data, in com-
ceivers and encoder/decoders, com-
pliance with 1553B Notice 2. A circu-
plete BC/RT/MT protocol logic, memory
lar buffer option for RT message data
management and interrupt logic, 8K x 16
blocks offloads the host processor for
of shared static RAM, and a direct,
bulk data transfer applications.
• RT Subaddress Circular Buffers
to Support Bulk Data Transfers
buffered interface to a host processor bus.
• Optlonal Separatlon of
RT Broadcast Data
Another feature besides those listed
to the right, is a transmitter inhibit con-
trol for the individual bus channels.
The BUS-61559 includes a number of
advanced features in support of
MIL-STD-1553B Notice 2 and STANAG
• Internal Interrupt Status and
Time Tag Registers
3838. Other salient features of the
BUS-61559 serve to provide the bene-
fits of reduced board space require-
ments enhanced software flexibility,
and reduced host processor overhead
The BUS-61559 series hybrids oper-
ate over the full military temperature
range of -55 to +125”C and MIL-PRF-
38534 processing is available. The
hybrids are ideal for demanding mili-
tary and industrial microprocessor-to-
1553 applications
• Internal ST Command
Illegalization
The BUS-61559 contains internal
address latches and bidirectional data
• MIL-PRF-38534 Processing
Available
(ILLEGALIZATION
ILLENA
ILLEGALLIZATION
LOGIC
ENABLE)
8K x 16
DUAL
PORT
RAM
CLK IN (16MHz)
BUS-25679
8
7
5
4
1
LOW-POWER
TRANSCEIVER
A
2
3
DUAL
TX_INH_A
ENCODER/
DECODER
BC/RT/MT
PROTOCOL
DATA
BUFFERS*
(PROCESSOR
DATA)
MEMORY DATA
D15-D
BUS-25679
8
7
5
4
1
(PROCESSOR
ADDRESS)
LOW-POWER
TRANSCEIVER
A
A15-A
2
ADDRESS
LATCHES/
BUFFERS*
MEMORY ADDRESS
3
(ADDRESS
LATCH
CONTROL)
ADDR_LAT
TX_INH_A
TRANSPARENT/BUFFERED, MSTCLR,
STRBD, SELECT, MEM/REG, RD/WR
RTAD 4- , RTADP
BRO_ENA
RTFAIL
(RT ADDRESS)
(PROCESSOR
CONTROL)
MEMORY
MANAGEMENT,
SHARED
IOEN, READYD
INT
(BROADCAST
ENABLE)
(INTERRUPT
REQUEST)
RAM/
MEMEN-OUT,MEMWR, MEMOE
MEMENA-IN
(MEMORY
CONTROL)
PROCESSOR
INTERFACE,
INTERRUPT
LOGIC
(RTFAIL,
RTFLAG)
RTFLAG
(SUBSYSTEM
FLAG)
SSFLAG
(BROADCAST,
MESSAGE
TIMING, DATA
(TIME TAG
CLOCK)
TAGCLK
BCSTRCV, CMD_STR, TXDTA_STR
RXDTA_STR, MSG_ERR, INCMD
STROBE AND ERROR
INDICATORS)
BU-61559 BLOCK DIAGRAM
© 1990, 1999 Data Device Corporation
ORDERING INFORMATION
BUS-615XX- XX0X*
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See page xiii.)
1 = MIL-PRF-38534 Compliant
2 = B**
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B** with PIND Testing
7 = B** with Solder Dip
8 = B** with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See page xiii.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply and Packaging
59 = +5 V/-15 V DDIP
60 = +5 V/-12 V DIP
69 = +5 V/-15 V Flat Pack
70 = +5 V/-12 V Flat Pack
71 = +5 V Flat Pack
*-601 version also available = MIL-STD-1760 compatible with fully compliant
MIL-PRF-38534 Processing Available
2
NOTES
3
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2482
For Technical Support - 1-800-DDC-5757 ext. 7257 or 7381
Headquarters - Tel: (631) 567-5600 ext. 7257 or 7381, Fax: (631) 567-7358
Southeast - Tel: (703) 450-7900, Fax: (703) 450-6610
West Coast - Tel: (714) 895-9777, Fax: (714) 895-4988
Europe - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
Asia/Pacific - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
ILC DATA DEVICE CORPORATION
REGISTERED TO ISO 9001
FILE NO. A5976
PRINTED IN THE U.S.A.
K-ABR
4
BUS-61570-320Y 相关器件
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