BC419143B-DS-001PE [ETC]
BlueCoyreTM4-Flash plug-n-GoTM Data sheet; BlueCoyreTM4 - Flash插件正GoTM数据表
| 型号： | BC419143B-DS-001PE |
| 厂家： | 
ETC |
| 描述： | BlueCoyreTM4-Flash plug-n-GoTM Data sheet |
| 文件： | 总97页 (文件大小：2939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Device Features
_äìÉ`çêÉ»QJcä~ëÜ=mäìÖJåJdç»
®
Fully Qualified Bluetooth v2.0+EDR
Single Chip Bluetooth
Full Speed Bluetooth Operation with Full Piconet
Support
v2.0 + EDR System
Advance Information Data Sheet For
BC419143B
Scatternet Support
Low Power 1.8V operation
10 x 10mm 96-ball LFBGA Package
Minimum External Components
Integrated 1.8V Regulator
Dual UART Ports
April 2006
RF Plug-n-Go Package
50Ω Matched Connection to Antenna
RoHS Compliant
General Description
Applications
The _äìÉ`çêÉ»QJcä~ëÜ=mäìÖJåJdç» is a single
chip radio and baseband IC for Bluetooth 2.4GHz
systems. It is implemented in 0.18µm CMOS
technology.
Automotive
BC419143B contains 8Mbit of internal Flash memory.
When used with CSR Bluetooth stack, it provides a
fully compliant Bluetooth system to v2.0 + EDR of the
specification for data and voice.
BlueCore4-Flash Plug-n-Go has the same pinout and
electrical characteristics as available in
BlueCore4-ROM Plug-n-Go to enable development of
custom code before committing to ROM. It also has
the same pinout as BlueCore2-ROM Plug-n-Go and
BlueCore2-Flash Plug-n-Go to keep compatibility.
BlueCore4-Flash Plug-n-Go has been designed to
reduce the number of external components required
which ensures production costs are minimised. The
0.8mm pitch BlueCore4-Flash Plug-n-Go can be
used on either two or four layer PCB construction.
The device incorporates auto-calibration and built-in
self-test (BIST) routines to simplify development, type
approval and production test. All hardware and
device firmware is fully compliant with the Bluetooth
v2.0 + EDR specification.
SPI
RAM
UART/ USB
Flash
RF IN
RF
OUT
2.4
GHz
Radio
I/O
PIO
Baseband
DSP
MCU
PCM
XTAL
System Architecture
Data Sheet
Advance InformationCSR PLC2006
e2006BC419143B-ds-001P© 2006 CSR plc
Advance Information
© CSR plc 2006
BC419143B-ds-001Pe
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Contents
1
2
3
Status Information .......................................................................................................................................... 7
Key Features .................................................................................................................................................... 8
Package Information ....................................................................................................................................... 9
3.1 BC419143B Pinout Diagram ................................................................................................................... 9
3.2 BC419143B-ANN-E4 Device Terminal Functions ................................................................................. 10
Electrical Characteristics ............................................................................................................................. 14
4.1 Power Consumption .............................................................................................................................. 19
Radio Characteristics - Basic Data Rate ..................................................................................................... 20
5.1 Temperature +20°C ............................................................................................................................... 20
5.1.1 Transmitter ................................................................................................................................ 20
5.1.2 Receiver .................................................................................................................................... 22
5.2 Temperature -40°C ................................................................................................................................ 24
5.2.1 Transmitter ................................................................................................................................ 24
5.2.2 Receiver .................................................................................................................................... 24
5.3 Temperature -25°C ................................................................................................................................ 25
5.3.1 Transmitter ................................................................................................................................ 25
5.3.2 Receiver .................................................................................................................................... 25
5.4 Temperature +85°C ............................................................................................................................... 26
5.4.1 Transmitter ................................................................................................................................ 26
5.4.2 Receiver .................................................................................................................................... 26
Radio Characteristics - Enhanced Data Rate ............................................................................................. 27
6.1 Temperature +20°C ............................................................................................................................... 27
6.1.1 Transmitter ................................................................................................................................ 27
6.1.2 Receiver .................................................................................................................................... 28
6.2 Temperature -40°C ................................................................................................................................ 29
6.2.1 Transmitter ................................................................................................................................ 29
6.2.2 Receiver .................................................................................................................................... 29
6.3 Temperature -25°C ................................................................................................................................ 30
6.3.1 Transmitter ................................................................................................................................ 30
6.3.2 Receiver .................................................................................................................................... 30
6.4 Temperature +85°C ............................................................................................................................... 31
6.4.1 Transmitter ................................................................................................................................ 31
6.4.2 Receiver .................................................................................................................................... 31
Device Diagram ............................................................................................................................................ 32
Description of Functional Blocks ................................................................................................................ 33
8.1 RF Receiver ........................................................................................................................................... 33
8.1.1 Low Noise Amplifier .................................................................................................................. 33
8.1.2 Analogue to Digital Converter ................................................................................................... 33
8.2 RF Transmitter ....................................................................................................................................... 33
8.2.1 IQ Modulator ............................................................................................................................. 33
8.2.2 Power Amplifier ......................................................................................................................... 33
8.2.3 Auxiliary DAC ............................................................................................................................ 33
8.3 Balun and Filter ..................................................................................................................................... 33
8.4 RF Synthesiser ...................................................................................................................................... 33
8.5 Clock Input and Generation ................................................................................................................... 33
8.6 Baseband and Logic .............................................................................................................................. 33
8.6.1 Memory Management Unit ....................................................................................................... 33
8.6.2 Burst Mode Controller ............................................................................................................... 34
8.6.3 Physical Layer Hardware Engine DSP ..................................................................................... 34
4
5
6
7
8
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8.6.4 System RAM ............................................................................................................................. 34
8.6.5 Flash Memory (8Mbit) ............................................................................................................... 34
8.6.6 USB .......................................................................................................................................... 34
8.6.7 Synchronous Serial Interface .................................................................................................... 34
8.6.8 UART ........................................................................................................................................ 34
8.7 Microcontroller ....................................................................................................................................... 34
8.7.1 Programmable I/O .................................................................................................................... 34
8.7.2 802.11 Co-Existence Interface ................................................................................................. 35
CSR Bluetooth Software Stacks .................................................................................................................. 36
9.1 BlueCore HCI Stack ............................................................................................................................. 36
9.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ........................................... 37
9.1.2 Key Features of the HCI Stack: Extra Functionality .................................................................. 38
9.2 BlueCore RFCOMM Stack .................................................................................................................... 39
9.2.1 Key Features of the RFCOMM Stack ....................................................................................... 40
9.3 BlueCore Virtual Machine Stack ............................................................................................................ 41
9.4 BlueCore HID Stack .............................................................................................................................. 42
9.5 Host-Side Software ................................................................................................................................ 43
9.6 Device Firmware Upgrade ..................................................................................................................... 43
9.7 BCHS Software ..................................................................................................................................... 43
9.8 Additional Software for Other Embedded Applications .......................................................................... 43
9.9 CSR Development Systems .................................................................................................................. 43
9
10 Enhanced Data Rate ..................................................................................................................................... 44
10.1 Enhanced Data Rate Baseband ............................................................................................................ 44
10.2 Enhanced Data Rate π/4 DQPSK .......................................................................................................... 44
10.3 Enhanced Data Rate 8DPSK ................................................................................................................ 45
11 Device Terminal Descriptions ...................................................................................................................... 47
11.1 RF Ports ................................................................................................................................................ 47
11.1.1 RF Plug-n-Go ............................................................................................................................ 47
11.1.2 Single-Ended Input (RF_IN) ..................................................................................................... 48
11.2 External Reference Clock Input (XTAL_IN) ........................................................................................... 49
11.2.1 External Mode ........................................................................................................................... 49
11.2.2 XTAL_IN Impedance in External Mode .................................................................................... 49
11.2.3 Clock Timing Accuracy ............................................................................................................. 49
11.2.4 Clock Start-Up Delay ................................................................................................................ 50
11.2.5 Input Frequencies and PS Key Settings ................................................................................... 51
11.3 Crystal Oscillator (XTAL_IN, XTAL_OUT) ............................................................................................. 52
11.3.1 XTAL Mode ............................................................................................................................... 52
11.3.2 Load Capacitance ..................................................................................................................... 53
11.3.3 Frequency Trim ......................................................................................................................... 54
11.3.4 Transconductance Driver Model ............................................................................................... 55
11.3.5 Negative Resistance Model ...................................................................................................... 55
11.3.6 Crystal PS Key Settings ............................................................................................................ 56
11.3.7 Crystal Oscillator Characteristics .............................................................................................. 56
11.4 UART Interface ...................................................................................................................................... 59
11.4.1 UART Bypass ........................................................................................................................... 61
11.4.2 UART Configuration While RESET is Active ............................................................................ 61
11.4.3 UART Bypass Mode ................................................................................................................. 61
11.4.4 Current Consumption in UART Bypass Mode .......................................................................... 61
11.5 USB Interface ........................................................................................................................................ 62
11.5.1 USB Data Connections ............................................................................................................. 62
11.5.2 USB Pull-Up Resistor ............................................................................................................... 62
11.5.3 USB Power Supply ................................................................................................................... 62
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11.5.4 Self-Powered Mode .................................................................................................................. 63
11.5.5 Bus-Powered Mode .................................................................................................................. 63
11.5.6 Suspend Current ....................................................................................................................... 64
11.5.7 Detach and Wake_Up Signalling .............................................................................................. 64
11.5.8 USB Driver ................................................................................................................................ 65
11.5.9 USB 1.1 Compliance ................................................................................................................ 65
11.5.10 USB 2.0 Compatibility ............................................................................................................... 65
11.6 Serial Peripheral Interface ..................................................................................................................... 66
11.6.1 Instruction Cycle ....................................................................................................................... 66
11.6.2 Writing to the Device ................................................................................................................. 67
11.6.3 Reading from the Device .......................................................................................................... 67
11.6.4 Multi-Slave Operation ............................................................................................................... 67
11.7 PCM CODEC Interface .......................................................................................................................... 68
11.7.1 PCM Interface Master/Slave ..................................................................................................... 68
11.7.2 Long Frame Sync ..................................................................................................................... 69
11.7.3 Short Frame Sync ..................................................................................................................... 69
11.7.4 Multi-slot Operation ................................................................................................................... 70
11.7.5 GCI Interface ............................................................................................................................ 70
11.7.6 Slots and Sample Formats ....................................................................................................... 71
11.7.7 Additional Features ................................................................................................................... 72
11.7.8 PCM Timing Information ........................................................................................................... 73
11.7.9 PCM Configuration ................................................................................................................... 76
11.8 I/O Parallel Ports ................................................................................................................................... 80
11.8.1 PIO Defaults ............................................................................................................................. 80
11.9 TCXO Enable OR Function ................................................................................................................... 82
11.10RESET and RESETB ............................................................................................................................ 83
11.10.1 Pin States on Reset .................................................................................................................. 84
11.10.2 Status after Reset ..................................................................................................................... 84
11.11Power Supply ........................................................................................................................................ 85
11.11.1 Voltage Regulator (Plug-n-Go) ................................................................................................. 85
11.11.2 Sequencing ............................................................................................................................... 85
11.11.3 Sensitivity to Disturbances ........................................................................................................ 85
11.11.4 VREG_EN Pin .......................................................................................................................... 85
12 Product Reliability Tests .............................................................................................................................. 86
13 Product Reliability Tests for BlueCore4-Flash Plug-n-Go Automotive .................................................... 87
13.1 AEC-Q100 ............................................................................................................................................. 87
14 Application Schematic .................................................................................................................................. 88
15 Package Dimensions .................................................................................................................................... 89
15.1 10 x 10 LFBGA 96-Ball 1.6mm Package .............................................................................................. 89
16 RoHS Statement with a List of Banned Materials ...................................................................................... 90
16.1 RoHS Statement .................................................................................................................................... 90
16.1.1 List of Banned Materials ........................................................................................................... 90
17 Ordering Information .................................................................................................................................... 91
17.1 BlueCore4-Flash Plug-n-Go .................................................................................................................. 91
18 Contact Information ...................................................................................................................................... 92
19 Document References .................................................................................................................................. 93
20 Terms and Definitions .................................................................................................................................. 94
21 Document History ......................................................................................................................................... 97
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List of Figures
Figure 3.1
BlueCore4-Flash Plug-n-Go 10 x 10mm LFBGA Package........................................................... 9
BlueCore4-Flash Plug-n-Go Device Diagram............................................................................. 32
BlueCore HCI Stack.................................................................................................................... 36
BlueCore RFCOMM Stack.......................................................................................................... 39
Virtual Machine ........................................................................................................................... 41
HID Stack.................................................................................................................................... 42
Basic Rate and Enhanced Data Rate Packet Structure.............................................................. 44
π/4 DQPSK Constellation Pattern............................................................................................... 45
8DPSK Constellation Pattern...................................................................................................... 46
Circuit for RF_CONNECT........................................................................................................... 47
Circuit RF_IN .............................................................................................................................. 48
TCXO Clock Accuracy ................................................................................................................ 49
Crystal Driver Circuit................................................................................................................... 52
Crystal Equivalent Circuit............................................................................................................ 52
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency...................... 56
Crystal Driver Transconductance vs. Driver Level Register Setting ........................................... 57
Crystal Driver Negative Resistance as a Function of Drive Level Setting .................................. 58
Universal Asynchronous Receiver.............................................................................................. 59
Break Signal................................................................................................................................ 60
UART Bypass Architecture ......................................................................................................... 61
USB Connections for Self-Powered Mode.................................................................................. 63
USB Connections for Bus-Powered Mode.................................................................................. 64
USB_DETACH and USB_WAKE_UP Signal.............................................................................. 65
SPI Write Operation.................................................................................................................... 67
SPI Read Operation.................................................................................................................... 67
BlueCore4-Flash Plug-n-Go as PCM Interface Master............................................................... 68
BlueCore4-Flash Plug-n-Go as PCM Interface Slave................................................................. 69
Long Frame Sync (Shown with 8-bit Companded Sample)........................................................ 69
Short Frame Sync (Shown with 16-bit Sample).......................................................................... 70
Multi-slot Operation with Two Slots and 8-bit Companded Samples.......................................... 70
GCI Interface............................................................................................................................... 71
16-Bit Slot Length and Sample Formats..................................................................................... 72
PCM Master Timing Long Frame Sync....................................................................................... 74
PCM Master Timing Short Frame Sync ...................................................................................... 74
PCM Slave Timing Long Frame Sync......................................................................................... 75
PCM Slave Timing Short Frame Sync ........................................................................................ 76
Example TCXO Enable OR Function.......................................................................................... 82
Application Circuit for Radio Characteristics Specification ......................................................... 88
BlueCore4-Flash Plug-n-Go 96-Ball LFBGA 1.6mm Package Dimensions................................ 89
Figure 7.1
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Figure 10.1
Figure 10.2
Figure 10.3
Figure 11.1
Figure 11.2
Figure 11.3
Figure 11.4
Figure 11.5
Figure 11.6
Figure 11.7
Figure 11.8
Figure 11.9
Figure 11.10
Figure 11.11
Figure 11.12
Figure 11.13
Figure 11.14
Figure 11.15
Figure 11.16
Figure 11.17
Figure 11.18
Figure 11.19
Figure 11.20
Figure 11.21
Figure 11.22
Figure 11.23
Figure 11.24
Figure 11.25
Figure 11.26
Figure 11.27
Figure 11.28
Figure 14.1
Figure 15.1
List of Tables
Table 10.1
Table 10.2
Table 10.3
Table 11.1
Table 11.2
Table 11.3
Table 11.4
Table 11.5
Data Rate Schemes.................................................................................................................... 44
2-Bits Determine Phase Shift Between Consecutive Symbols ................................................... 45
3-Bits Determine Phase Shift Between Consecutive Symbols ................................................... 46
External Clock Specifications...................................................................................................... 49
PS Key Values for CDMA/3G Phone TCXO Frequencies .......................................................... 51
Crystal Specification ................................................................................................................... 53
Possible UART Settings.............................................................................................................. 59
Standard Baud Rates.................................................................................................................. 60
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Table 11.6
Table 11.7
Table 11.8
Table 11.9
Table 11.10
Table 11.11
Table 11.12
USB Interface Component Values.............................................................................................. 63
Instruction Cycle for an SPI Transaction..................................................................................... 66
PCM Master Timing .................................................................................................................... 73
PCM Slave Timing ...................................................................................................................... 75
PSKEY_PCM_CONFIG32 Description....................................................................................... 78
PSKEY_PCM_LOW_JITTER_CONFIG Description................................................................... 79
Pin States of BlueCore4-Flash Plug-n-Go on Reset................................................................... 84
List of Equations
Equation 11.1
Equation 11.2
Equation 11.3
Equation 11.4
Equation 11.5
Equation 11.6
Equation 11.7
Equation 11.8
Equation 11.9
Load Capacitance....................................................................................................................... 53
Trim Capacitance........................................................................................................................ 54
Frequency Trim........................................................................................................................... 54
Pullability..................................................................................................................................... 54
Transconductance Required for Oscillation................................................................................ 55
Equivalent Negative Resistance ................................................................................................. 55
Baud Rate................................................................................................................................... 60
PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock....................... 76
PCM_SYNC Frequency Relative to PCM_CLK.......................................................................... 76
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Status Information
1 Status Information
The status of this Data Sheet is Advance Information.
CSR Product Data Sheets progress according to the following format:
Advance Information
Information for designers concerning CSR product in development. All values specified are the target values of the
design. Minimum and maximum values specified are only given as guidance to the final specification limits and must
not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-Production Information
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
All electrical specifications may be changed by CSR without notice.
Production Information
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Life Support Policy and Use in Safety-Critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done
at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.
RoHS Compliance
BlueCore4-Flash Plug-n-Go devices meet the requirements of Directive 2002/95/EC of the European Parliament and
of the Council on the Restriction of Hazardous Substance (RoHS).
Trademarks, Patents and Licenses
Unless otherwise stated, words and logos marked with ™ or ® are trademarks registered or owned by CSR plc or its
affiliates. Bluetooth® and the Bluetooth logos are trademarks owned by Bluetooth SIG, Inc. and licensed to CSR. Other
products, services and names used in this document may have been trademarked by their respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned
by CSR plc.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept
responsibility for any errors.
Advance Information
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Key Features
2 Key Features
Radio
Baseband and Software
Direct 50Ω connection to a common TX/RX antenna
Internal programmed 8Mbit flash for complete
system solution
Bluetooth v2.0+EDR specification compliant
48kbyte on-chip RAM allows full speed Bluetooth
data transfer, mixed voice and data, plus full seven
slave piconet operation
Extensive built-in self-test minimises production test
time
No external trimming is required in production
Antenna matching and filtering within IC
Logic for forward error correction, header error
control, access code correlation, demodulation,
CRC, encryption bitstream generation, whitening
and transmit pulse shaping
Transmitter
+6dBm RF transmit power with level control from
on-chip 6-bit DAC over a dynamic range >30dB
Transcoders for A-law, µ-law and linear voice from
host and A-law, µ-law and CVSD voice over air
Class 2 and Class 3 support without the need for an
external power amplifier or TX/RX switch
Physical Interfaces
Synchronous serial interface up to 4M baud for
system debugging
Receiver
Integrated channel filters
UART interface with programmable baud rate up to
3M baud with an optional bypass mode
Digital demodulator for improved sensitivity and
co-channel rejection
Full speed USB interface supports OHCI and UHCI
host interfaces. Compliant with USB v2.0
Real time digitised RSSI available on HCI interface
Fast AGC for enhanced dynamic range
Synchronous bi-directional serial programmable
audio interface
Synthesiser
Optional I2C™ compatible interface
Fully integrated synthesiser requires no external
VCO varactor diode, resonator or loop filter
Bluetooth Stack
Compatible with crystals between 8 and 32MHz (in
multiples of 250kHz) or an external clock
CSR's Bluetooth Protocol Stack runs on-chip in a variety
of configurations:
Accepts 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44,
19.68, 19.8 and 38.4MHz TCXO frequencies for
GSM and CDMA devices with sinusoidal or logic
level signals
Standard HCI (UART or USB)
Fully embedded to RFCOMM
Customer specific builds with embedded application
code
Auxiliary Features
Package Options
96-ball LFBGA 10 x 10 x 1.6mm 0.8mm pitch
Crystal oscillator with built-in digital trimming
Power management includes digital shutdown, and
wake up commands with an integrated low power
oscillator for ultra low Park/Sniff/Hold mode
Clock request output to control external clock
On-chip linear regulator, producing 1.8V output from
2.2V to 4.2V input
Power on reset cell detects low supply voltage
Arbitrary power supply sequencing permitted
8-bit ADC and DAC available to application
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Package Information
3 Package Information
3.1
BC419143B Pinout Diagram
Figure 3.1: BlueCore4-Flash Plug-n-Go 10 x 10mm LFBGA Package
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Package Information
3.2
BC419143B-ANN-E4 Device Terminal Functions
Radio
Ball
Pad Type
Description
RF_IN
D2
Analogue
Single ended receiver input
Bi-directional with
PIO[0]/RXEN
PIO[1]/TXEN
D3
C4
programmable strength
internal pull-up/down
Programmable input/output line
Programmable input/output line
Bi-directional with
programmable strength
internal pull-up/down
BAL_MATCH
RF_CONNECT
AUX_DAC
A1
B1
C2
Analogue
Analogue
Analogue
Tie to VSS_RADIO
50Ω RF matched I/O
Voltage DAC output
Synthesiser and
Oscillator
Ball
Pad Type
Description
XTAL_IN
L3
L4
Analogue
Analogue
For crystal or external clock input
Drive for crystal
XTAL_OUT
PCM Interface
Ball
Pad Type
Description
CMOS output, tristatable with
weak internal pull-down
PCM_OUT
G10
Synchronous data output
CMOS input, with weak
internal pull-down
PCM_IN
H11
G11
H10
Synchronous data input
Synchronous data sync
Synchronous data clock
Bi-directional with weak
internal pull-down
PCM_SYNC
PCM_CLK
Bi-directional with weak
internal pull-down
USB and UART
Ball
Pad Type
Description
CMOS output, tri-state with
weak internal pull-up
UART_TX
J10
UART data output active low
CMOS input with weak internal
pull-down
UART_RX
UART_RTS
UART_CTS
J11
L11
K11
UART data input active low (idle status high)
UART request to send active low
UART clear to send active low
CMOS output, tristatable with
weak internal pull-up
CMOS input with weak internal
pull-down
USB data plus with selectable internal 1.5kΩ
pull-up resistor
USB_DP
USB_DN
L9
L8
Bi-directional
Bi-directional
USB data minus
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Package Information
Test and Debug
Ball
Pad Type
Description
CMOS input with weak internal Reset if high. Input debounced so must be
pull-down high for >5ms to cause a reset
RESET
F9
CMOS input with weak internal Reset if low. Input debounced so must be low
pull-up for >5ms to cause a reset
RESETB
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
G9
CMOS input with weak internal Chip select for Serial Peripheral Interface,
C10
D10
D11
C11
pull-up
active low
CMOS input with weak internal
pull-down
Serial Peripheral Interface clock
CMOS input with weak internal
pull-down
Serial Peripheral Interface data input
Serial Peripheral Interface data output
CMOS output, tristatable with
weak internal pull-down
CMOS input with strong
internal pull-down
TEST_EN
E9
For test purposes only (leave unconnected)
Not available for BlueCore4-Flash Plug-n-Go
FLASH_EN
B10
No Connect
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Package Information
PIO Port
Ball
Pad Type
Description
Bi-directional with
PIO[2]
C3
programmable strength
internal pull-up/down
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Programmable input/output line
Bi-directional with
programmable strength
internal pull-up/down
PIO[3]
PIO[4]
PIO[5]
PIO[6]
PIO[7]
PIO[8]
PIO[9]
PIO[10]
PIO[11]
B2
H9
J8
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
K8
K9
B3
B4
A4
A5
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
Bi-directional with
programmable strength
internal pull-up/down
AIO[0]
AIO[1]
AIO[2]
K5
J6
Bi-directional
Bi-directional
Bi-directional
Programmable input/output line
Programmable input/output line
Programmable input/output line
K7
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Package Information
Power Supplies and
Control
Ball
L7
Pad Type
Description
VREG_IN
VREG_EN
Regulator input
Digital input
Linear regulator voltage input
Active high, regulator enable pin with internal
pull-up
J2
VDD_USB
VDD_PIO
L10
A3
VDD
VDD
Positive supply for UART/USB ports
Positive supply for PIO and AUX DAC(a)
Positive supply for all other digital
input/output ports(b)
VDD_PADS
VDD_DIG
E11
L6
VDD
Positive 1.8V supply output for VDD_MEM
and VDD_CORE
Regulator output
VDD
B11,
K6
Positive supply for internal memory and AIO
ports
VDD_MEM
VDD_CORE
VDD_RADIO
F11
E3
VDD
VDD
Positive supply for internal digital circuitry
Positive supply for RF circuitry
Positive supply for analogue circuitry and
1.8V regulated output
VDD_ANA
L5
VDD/Regulator output
VDD
VDD_BALUN
F1
Positive supply for balun
A2,
VSS_PADS
E10, VSS
K10
Ground connection for input/output
Ground connections for AIO and Extended
PIO ports
VSS_MEM
VSS_CORE
VSS_RADIO
D9, J9 VSS
F10
VSS
VSS
Ground connection for internal digital circuitry
Ground connections for RF circuitry
E2,F3,
G2
G3, H2
H3
Ground connections for VCO and
synthesiser
VSS_VCO
VSS_ANA
VSS
VSS
VSS
K4
Ground connection for analogue circuitry
Ground connection for balun
G1,J1,
K1
VSS_BALUN
(a)
Positive supply for PIO[3:0] and PIO[11:8]
(b)
Positive supply for SPI/PCM ports and PIO[7:4]
Unconnected Terminals Ball
A6, A7, A8, A9, A10, A11, B5, B6, B7,
Description
N/C
B8, B9, C1, C5, C6, C7, C8, C9, D1, E1, Leave unconnected
F2, H1, J3, J4, J5, J7, K2, K3, L1, L2
Advance Information
BC419143B-ds-001Pe
Page 13 of 97
© CSR plc 2006
Electrical Characteristics
4 Electrical Characteristics
Absolute Maximum Ratings
Rating
Min
Max
Storage Temperature
-40°C
+125°C
Supply Voltage: VDD_MEM, VDD_RADIO, VDD_ANA,
VDD_BAL and VDD_CORE
-0.4V
2.2V
Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB
Supply Voltage: VREG_IN
-0.4V
-0.4V
3.7V
5.6V
Other Terminal Voltages
VSS-0.4V
VDD+0.4V
Recommended Operating Conditions
Operating Condition
Min
Max
Operating Temperature Range
Guaranteed RF performance range (a)
-40°C
-25°C
+85°C
+85°C
Supply Voltage: VDD_MEM, VDD_RADIO, VDD_ANA
and VDD_CORE
1.7V
1.9V
Supply Voltage: VDD_PADS, VDD_PIO and VDD_USB
Supply Voltage: VREG_IN
1.7V
2.2V
3.6V
4.2V(b)
(a)
Typical figures are given for RF performance between -40°C and +85°C.
(b)
The device will operate without damage with VREG_IN as high as 5.6V, however the RF performance is not guaranteed
above 4.2V.
Advance Information
BC419143B-ds-001Pe
Page 14 of 97
© CSR plc 2006
Electrical Characteristics
Input/Output Terminal Characteristics (Supply)
Linear Regulator
Min
Typ
Max
Unit
Normal Operation
Output Voltage(a) (Iload = 70 mA)
Temperature Coefficient
1.70
1.78
1.85
+250
1
V
ppm/°C
mV rms
mV/A
µs
-250
-
-
Output Noise(b) (c)
-
Load Regulation (Iload < 100 mA)
Settling Time(b) (d)
-
-
-
50
-
50
Maximum Output Current
Minimum Load Current
140
5
-
-
mA
-
-
µA
Input Voltage
-
-
4.2(e)
350
50
V
Dropout Voltage (Iload = 70 mA)
Quiescent Current (excluding Ioad, Iload < 1mA)
Low Power Mode(f)
-
-
mV
25
35
µA
Quiescent Current (excluding Ioad, Iload < 100µA)
Disabled Mode(g)
4
7
10
µA
µA
Quiescent Current
1.5
2.5
3.5
(a)
For optimum performance, the VDD_ANA ball adjacent to VREG_IN should be used for regulator output,
Regulator output connected to 47nF pure and 4.7µF 2.2Ω ESR capacitors.
Frequency range is 100Hz to 100kHz.
(b)
(c)
(d)
(e)
1mA to 70mA pulsed load.
Operation up to 5.6V is permissible without damage and without the output voltage rising sufficiently to damage the rest
of BlueCore4-Flash Plug-n-Go, but output regulation and other specifications are no longer guaranteed at input voltages
in excess of 4.2V.
(f)
Low power mode is entered and exited automatically when the chip enters/leaves Deep Sleep mode.
Regulator is disabled when VREG_EN is pulled low. It is also disabled when VREG_IN is either open circuit or driven to
the same voltage as VDD_ANA.
(g)
Advance Information
BC419143B-ds-001Pe
Page 15 of 97
© CSR plc 2006
Electrical Characteristics
Input/Output Terminal Characteristics (Digital)
Digital Terminals
Min
Typ
Max
Unit
Input Voltage Levels
2.7V ≤ VDD ≤ 3.0V
VIL input logic level low
-0.4
-0.4
-
-
-
+0.8
+0.4
V
V
V
1.7V ≤ VDD ≤ 1.9V
VIH input logic level high
0.7VDD
VDD+0.4
Output Voltage Levels
V
OL output logic level low,
(lo = 4.0mA), 2.7V ≤ VDD ≤ 3.0V
OL output logic level low,
-
-
-
-
-
0.2
0.4
-
V
V
V
V
V
-
(lo = 4.0mA), 1.7V ≤ VDD ≤ 1.9V
VOH output logic level high,
(lo = -4.0mA), 2.7V ≤ VDD ≤ 3.0V
VOH output logic level high,
(lo = -4.0mA), 1.7V ≤ VDD ≤ 1.9V
Input and Tri-state Current with:
Strong pull-up
VDD-0.2
VDD-0.4
-
-100
+10
-5.0
+0.2
-1
-40
+40
-1.0
+1.0
0
-10
+100
-0.2
+5.0
+1
µA
µA
µA
µA
µA
pF
Strong pull-down
Weak pull-up
Weak pull-down
I/O pad leakage current
CI Input Capacitance
1.0
-
5.0
USB Terminals
Min
Typ
Max
Unit
VDD_USB for correct USB operation
Input Threshold
3.1
3.6
V
V
IL input logic level low
-
-
-
0.3VDD_USB
-
V
V
VIH input logic level high
Input Leakage Current
VSS_PADS < VIN < VDD_USB(a)
CI Input capacitance
0.7VDD_USB
-1
1
-
5
µA
2.5
10.0
pF
Output Voltage Levels to Correctly Terminated
USB Cable
VOL output logic level low
VOH output logic level high
0.0
2.8
-
-
0.2
V
V
VDD_USB
(a)
Internal USB pull-up disabled
Advance Information
BC419143B-ds-001Pe
Page 16 of 97
© CSR plc 2006
Electrical Characteristics
Power-on Reset
Min
1.40
1.50
0.05
Typ
1.50
1.60
0.10
Max
Unit
V
VDD_CORE falling threshold
VDD_CORE rising threshold
Hysteresis
1.60
1.70
0.15
V
V
Auxiliary ADC
Resolution
Min
Typ
Max
Unit
-
-
8
Bits
Input voltage range
(LSB size = VDD_ANA/255)
Accuracy
0
-
VDD_ANA
V
INL
-1
-
1
1
LSB
LSB
(Guaranteed monotonic)
Offset
DNL
0
-
-
-1
1
LSB
Gain Error
-0.8
-
0.8
-
%
Input Bandwidth
Conversion time
Sample rate(a)
-
-
-
100
2.5
-
kHz
-
µs
700
Samples/s
(a)
ADC is accessed through the VM function. The sample rate given is achieved as part of this function.
Auxiliary DAC
Min
-
Typ
Max
8
Unit
Bits
mV
Resolution
-
Average output step size(a)
Output Voltage
12.5
14.5
17.0
monotonic(a)
Voltage range (IO=0mA)
Current range
VSS_PADS
-
-
-
-
-
-
-
-
VDD_PIO
V
mA
V
-10.0
0.1
Minimum output voltage (IO=100µA)
Maximum output voltage (IO=10mA)
High Impedance leakage current
Offset
0.0
0.2
VDD_PIO-0.3
VDD_PIO
V
-1
-220
-2
1
120
2
µA
mV
LSB
µs
Integral non-linearity(a)
Settling time (50pF load)
-
10
(a)
Specified for an output voltage between 0.2V and VDD_PIO -0.2V. Output is high impedance when chip is in Deep Sleep
mode.
Advance Information
BC419143B-ds-001Pe
Page 17 of 97
© CSR plc 2006
Electrical Characteristics
Crystal Oscillator
Crystal frequency(a)
Digital trim range(b)
Trim step size(b)
Min
8.0
5.0
-
Typ
-
Max
Unit
MHz
pF
32.0
8.0
-
6.2
0.1
-
pF
Transconductance
Negative resistance(c)
External Clock
2.0
870
-
mS
Ω
1500
2400
Input frequency(d)
7.5
-
-
40.0
MHz
V pk-pk
ps rms
kΩ
Clock input level(e)
Allowable Jitter
0.2
VDD_ANA
-
-
-
-
15
-
XTAL_IN input impedance
XTAL_IN input capacitance
-
7
-
pF
(a)
Integer multiple of 250kHz
(b)
The difference between the internal capacitance at minimum and maximum settings of the internal digital trim.
XTAL frequency = 16MHz; XTAL C0 = 0.75pF; XTAL load capacitance = 8.5pF.
(c)
(d)
Clock input can be any frequency between 8MHz and 40MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of
7.68, 14.44, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz.
(e)
Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA.
A DC blocking capacitor is required between the signal and XTAL_IN.
Advance Information
BC419143B-ds-001Pe
Page 18 of 97
© CSR plc 2006
Electrical Characteristics
4.1
Power Consumption
Typical Average Current Consumption
VDD=1.8V
Mode
Temperature = +20°C
Output Power = +4dBm
Average
21
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
SCO connection HV3 (30ms interval Sniff Mode) (Slave)
SCO connection HV3 (30ms interval Sniff Mode) (Master)
SCO connection HV3 (No Sniff Mode) (Slave)
SCO connection HV1 (Slave)
21
28
42
SCO connection HV1 (Master)
42
ACL data transfer 115.2kbps UART no traffic (Master)
ACL data transfer 115.2kbps UART no traffic (Slave)
ACL data transfer 720kbps UART (Master or Slave)
ACL data transfer 720kbps USB (Master or Slave)
ACL connection, Sniff Mode 40ms interval, 38.4kbps UART
ACL connection, Sniff Mode 1.28s interval, 38.4kbps UART
Parked Slave, 1.28s beacon interval, 38.4kbps UART
Standby Mode (Connected to host, no RF activity)
Reset (RESET high or RESETB low)
5
22
45
45
3.2
0.45
0.55
47.0
15.0
µA
Typical Peak Current at +20°C
Device Activity/State
Current (mA)
Peak Current during cold boot (100ms sampling interval)
Peak TX Current Average across burst)
Peak RX Current
-
-
-
-
Average RX Current across burst
Conditions
VREG_IN, VDD_PIO, VDD_PADS
Host Interface
-
-
-
-
-
-
-
-
Baud Rate
Clock Source
Output Power
Receive Sensitivity
Device Mode
Packet Type
Advance Information
© CSR plc 2006
BC419143B-ds-001Pe
Page 19 of 97
Radio Characteristics - Basic Data Rate
5 Radio Characteristics - Basic Data Rate
5.1
Temperature +20°C
5.1.1 Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Bluetooth
Specification
Min
Typ
2.5
1.5
Max
Unit
dBm
dB
Maximum RF transmit power(a) (b)
-
-
-
-
-6 to +4(c)
RF power variation over temperature
range with compensation enabled(±)(d)
-
RF power variation over temperature
range with compensation disabled(±)(d)
-
2.5
-
-
dB
RF power control range
RF power range control resolution(e)
20dB bandwidth for modulated carrier
Adjacent channel transmit power
F = F0 ± 2MHz(f) (g)
-
-
-
35
0.5
780
-
-
-
≥16
-
dB
dB
≤1000
kHz
-
-
-
-40
-45
-50
-
-
-
≤-20
≤-40
≤-40
dBm
dBm
dBm
Adjacent channel transmit power
F = F0 ± 3MHz(f) (g)
Adjacent channel transmit power
F = F0 ± > 3MHz(f) (g)
∆f1avg Maximum Modulation
∆f2max Minimum Modulation
∆f1avg/∆f2avg
-
-
-
-
-
-
-
-
-
165
150
0.97
6
-
-
-
-
-
-
-
-
-
140<f1avg<175
115
kHz
kHz
≥0.80
±75
-
Initial carrier frequency tolerance
Drift Rate
kHz
7
≤20
kHz/50µs
kHz
Drift (single slot packet)
Drift (five slot packet)
8
≤25
9
≤40
kHz
2
nd Harmonic Content
rd Harmonic Content
TBD
TBD
≤-30
dBm
dBm
3
≤-30
(a)
The BlueCore4-Flash Plug-n-Go firmware maintains the transmit power within Bluetooth v2.0+EDR specification limits
Measurement using PSKEY_LC_MAX_TX_POWER setting corresponding to a PSKEY_LC_POWER_TABLE power
table entry = 63
(b)
(c)
(d)
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
These parameters are dependent on matching circuit used, and its behaviour over temperature, therefore these
parameters are not under CSR's direct control
(e)
(f)
Resolution guaranteed over the range -5dB to -25dB relative to maximum power for Tx Level > 20
Measured at F0 = 2441MHz
(g)
BlueCore4-Flash Plug-n-Go guaranteed to meet ACP performance in Bluetooth v2.0+EDR specification, three exceptions
allowed.
Advance Information
BC419143B-ds-001Pe
Page 20 of 97
© CSR plc 2006
Radio Characteristics - Basic Data Rate
Radio Characteristics
VDD = 1.8V
Frequency (GHz)
0.869 - 0.894(a)
0.869 - 0.894(b)
0.925 - 0.960(a)
1.570 - 1.580(c)
Temperature = +20°C
Min
Typ
TBD
TBD
TBD
TBD
Max
Cellular Band
GSM 850
CDMA 850
GSM 900
GPS
Unit
-
-
-
-
-
-
-
-
Emitted power in cellular
bands measured at
unbalanced port of the
balun. Output power =
TBDdBm
GSM 1800 /
DCS 1800
1.805 - 1.880(a)
-
TBD
-
dBm / Hz
1.930 - 1.990(d)
1.930 - 1.990(b)
1.930 - 1.990(a)
2.110 - 2.170(b)
2.110 - 2.170(e)
-
-
-
-
-
TBD
TBD
TBD
TBD
TBD
-
-
-
-
-
PCS 1900
GSM 1900
CDMA 1900
W-CDMA 2000
W-CDMA 2000
(a)
Integrated in 200kHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 1.2MHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 1MHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 30kHz bandwidth and then normalised to 1Hz bandwidth
Integrated in 5MHz bandwidth and then normalised to 1Hz bandwidth
(b)
(c)
(d)
(e)
Advance Information
BC419143B-ds-001Pe
Page 21 of 97
© CSR plc 2006
Radio Characteristics - Basic Data Rate
5.1.2 Receiver
Radio Characteristics
VDD = 1.8V
Min
Temperature = +20°C
Frequency
(GHz)
Bluetooth
Typ
Max
Unit
Specification
2.402
2.441
2.480
-
-
-
-
-85.0
-85.0
-87.0
0
-
-
-
-
Sensitivity at 0.1% BER
for all packet types
≤70
≥20
dBm
Maximum received signal at 0.1% BER
dBm
Frequency
(MHz)
Bluetooth
Specification
Min
Typ
Max
Unit
Continuous power
required to block
Bluetooth reception (for
input power of -67dBm
with 0.1% BER)
30-2000
-
-
0
0
-
-
-10
-27
2000-2400
dBm
measured at the
unbalanced port of the
balun.
2500-3000
-
0
-
-27
C/I co-channel
-
-
6
-
-
≤11
≤0
dB
dB
Adjacent channel selectivity C/I
F = F0 + 1MHz(a) (b)
-5
Adjacent channel selectivity C/I
F = F0 - 1MHz(a) (b)
-
-
-
-
-
-
-4
-
-
-
-
-
-
≤0
dB
dB
dB
dB
dB
dB
Adjacent channel selectivity C/I
F = F0 + 2MHz(a) (b)
-38
-23
-45
-44
-22
≤-30
≤-20
≤-40
≤-40
≤-9
Adjacent channel selectivity C/I
F = F0 - 2MHz(a) (b)
Adjacent channel selectivity C/I
F = F0 + 3MHz(a) (b)
Adjacent channel selectivity C/I
F = F0 -5MHz(a) (b)
Adjacent channel selectivity C/I
(a) (b)
F = FImage
Maximum level of intermodulation
interferers(c)
-
-
TBD
TBD
-
-
≤-39
dBm
Spurious output level(d)
-
dBm/Hz
(a)
Up to five exceptions are allowed in v2.0+EDR of the Bluetooth specification. BlueCore4-Flash Plug-n-Go is guaranteed
to meet the C/I performance as specified by the Bluetooth specification v2.0+EDR.
Measured at F = 2441MHz
(b)
(c)
Measured at f1 - f2 = 5MHz. Measurement is performed in accordance with Bluetooth RF test RCV/CA/05/c., i.e., wanted
signal at -64dBm.
(d)
Measured at unbalanced port of the balun. Integrated in 100kHz bandwidth and normalised to 1Hz. Actual figure is
typically below -150dBm/Hz except for peaks of -70dbm at 1600MHz, -60dBm inband at 2.4GHz and -70dBm at 3.2GHz.
Advance Information
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Page 22 of 97
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Radio Characteristics - Basic Data Rate
Radio Characteristics
VDD = 1.8V
Frequency (GHz)
0.824 - 0.849
0.824 - 0.849
0.880 - 0.915
Temperature = +20°C
Min
Typ
0
Max
Cellular Band
GSM 850
Unit
-
-
-
-
-
-
-10
-5
CDMA 850
GSM 900
Continuous power in
cellular bands required to
block Bluetooth reception
(for input power of -67dBm
with 0.1% BER) measured
at unbalanced port of the
balun.
GSM 1800 /
DCS 1800
1.710 - 1.785
1.850 - 1.910
-
-
0
0
-
-
dBm
GSM 1900 /
PCS 1900
1.850 - 1.910
1.920 - 1.980
0.824 - 0.849
0.824 - 0.849
0.880 - 0.915
-
-
-
-
-
-7
-10
-2
-
-
-
-
-
CDMA 1900
W-CDMA 2000
GSM 850
-12
-7
CDMA 850
GSM 900
Continuous power in
cellular bands required to
block Bluetooth reception
(for input power of -72dBm
with 0.1% BER) measured
at unbalanced port of the
balun.
GSM 1800 /
DCS 1800
1.710 - 1.785
1.850 - 1.910
-
-
0
0
-
-
dBm
GSM 1900 /
PCS 1900
1.850 - 1.910
1.920 - 1.980
-
-
-12
-14
-
-
CDMA 1900
W-CDMA 2000
Advance Information
BC419143B-ds-001Pe
Page 23 of 97
© CSR plc 2006
Radio Characteristics - Basic Data Rate
5.2
Temperature -40°C
5.2.1 Transmitter
Radio Characteristics
VDD = 1.8V
Min
Temperature = -40°C
Bluetooth
Typ
Max
Unit
Specification
Maximum RF transmit power(a)
RF power control range
RF power range control resolution
20dB bandwidth for modulated carrier
Adjacent channel transmit power
F = F0 ± 2MHz(c) (d)
-
-
-
-
3.5
35
-
-
-
-
-6 to +4(b)
dBm
dB
≥16
-
0.5
780
dB
≤1000
kHz
-
-
-40
-45
-
-
≤-20
≤-40
dBm
dBm
Adjacent channel transmit power
F = F0 ± 3MHz
∆f1avg Maximum Modulation
∆f2max Minimum Modulation
∆f2avg/∆f1avg
-
-
-
-
-
-
-
165
151
0.97
10
-
-
-
-
-
-
-
140<∆f1avg<175
kHz
kHz
115
≥0.80
±75
-
Initial carrier frequency tolerance
Drift Rate
kHz
7
≤20
kHz/50µs
kHz
Drift (single slot packet)
Drift (five slot packet)
8
≤25
12
≤40
kHz
(a)
BlueCore4-Flash Plug-n-Go firmware maintains the transmit power to be within the Bluetooth v2.0+EDR specification
limits
(b)
(c)
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
Measured at F0 = 2441MHz
(d)
Three exceptions are allowed in Bluetooth v2.0+EDR specification
5.2.2 Receiver
Radio Characteristics
VDD = 1.8V
Min
Temperature = -40°C
Frequency
(GHz)
Bluetooth
Typ
Max
Unit
Specification
2.402
2.441
2.480
-
-
-
-
-86
-86
-
-
-
-
Sensitivity at 0.1% BER
for all packet types
≤-70
dBm
dBm
-88
Maximum received signal at 0.1% BER
TBD
≥-20
Advance Information
BC419143B-ds-001Pe
Page 24 of 97
© CSR plc 2006
Radio Characteristics - Basic Data Rate
5.3
Temperature -25°C
5.3.1 Transmitter
Radio Characteristics
VDD = 1.8V
Min
Temperature = -25°C
Bluetooth
Typ
Max
Unit
Specification
Maximum RF transmit power(a)
RF power control range
-
-
-
-
3.0
35
-
-
-
-
-6 to +4(b)
dBm
dB
≥16
-
RF power range control resolution
20dB bandwidth for modulated carrier
Adjacent channel transmit power
F = F0± 2MHz(c) (d)
0.5
780
dB
≤1000
kHz
-
-
-40
-45
-
-
≤-20
≤-40
dBm
dBm
Adjacent channel transmit power
F = F0± 3MHz(c) (d)
∆f1avg Maximum Modulation
∆f2max Minimum Modulation
∆f2avg/∆f1avg
-
-
-
-
-
-
-
165
151
0.97
8
-
-
-
-
-
-
-
140<∆f1avg<175
kHz
kHz
115
≥0.80
±75
-
Initial carrier frequency tolerance
Drift Rate
kHz
7
≤20
kHz/50µs
kHz
Drift (single slot packet)
8
≤25
Drift (five slot packet)
12
≤40
kHz
(a)
BlueCore4-Flash Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits.
(b)
(c)
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
Measured at F0 = 2441MHz
(d)
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification.
5.3.2 Receiver
Radio Characteristics
VDD = 1.8V
Min
Temperature = -25°C
Frequency
(GHz)
Bluetooth
Typ
Max
Unit
Specification
2.402
2.441
2.480
-
-
-86
-86
-
-
-
-
Sensitivity at 0.1% BER
for all packet types
≤-70
dBm
dBm
-
-87
Maximum received signal at 0.1% BER
-
TBD
≥-20
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Radio Characteristics - Basic Data Rate
5.4
Temperature +85°C
5.4.1 Transmitter
Radio Characteristics
VDD = 1.8V
Min
Temperature = +85°C
Bluetooth
Typ
Max
Unit
Specification
Maximum RF transmit power(a)
RF power control range
-
-
-
-
0
-
-
-
-
-6 to +4(b)
dBm
dB
35
≥16
-
RF power range control resolution
20dB bandwidth for modulated carrier
Adjacent channel transmit power
F = F0± 2MHz(c) (d)
0.5
780
dB
≤1000
kHz
-
-
-40
-45
-
-
≤-20
≤-40
dBm
dBm
Adjacent channel transmit power
F = F0± 3MHz(c) (d)
∆f1avg Maximum Modulation
∆f2max Minimum Modulation
∆f2avg/∆f1avg
-
-
-
-
-
-
-
165
148
0.97
7
-
-
-
-
-
-
-
140<∆f1avg<175
kHz
kHz
115
≥0.80
±75
-
Initial carrier frequency tolerance
Drift Rate
kHz
7
≤20
kHz/50µs
kHz
Drift (single slot packet)
8
≤25
Drift (five slot packet)
9
≤40
kHz
(a)
BlueCore4-Flash Plug-n-Go firmware maintains the transmit power to be within the Bluetooth specification v2.0+EDR
limits
(b)
(c)
Class 2 RF transmit power range, Bluetooth specification v2.0+EDR
Measured at F0 = 2441MHz
(d)
Up to three exceptions are allowed in v2.0+EDR of the Bluetooth specification
5.4.2 Receiver
Radio Characteristics
VDD = 1.8V
Min
Temperature = +85°C
Frequency
(GHz)
Bluetooth
Typ
Max
Unit
Specification
2.402
2.441
2.480
-
-
-81
-81
-
-
-
-
Sensitivity at 0.1% BER
for all packet types
≤-70
dBm
dBm
-
-82
Maximum received signal at 0.1% BER
-20
TBD
≥-20
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Radio Characteristics - Enhanced Data Rate
6 Radio Characteristics - Enhanced Data Rate
6.1
Temperature +20°C
6.1.1 Transmitter
Radio Characteristics
VDD = 1.8V
Temperature = +20°C
Bluetooth
Min
Typ
Max
Unit
Specification
-6 to +4(b)
-4 to +1
≤10
Maximum RF transmit power(a)
Relative transmit power(c)
Carrier frequency stability(c)
-
-
-
-
-
-
6
-
-
-
-
-
-
dBm
dB
kHz
%
-1
3
RMS DEVM
99% DEVM
Peak DEVM
10
15
20
≤13(e)
Modulation Accuracy(c) (d)
≤20(e)
%
≤25(e)
%
(a)
BlueCore4-Flash Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
(b)
(c)
(d)
(e)
Measurement methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
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Radio Characteristics - Enhanced Data Rate
6.1.2 Receiver
Radio Characteristics
VDD = 1.8V
Modulation
Temperature = +20°C
Bluetooth
Specification
Min
Typ
Max
Unit
π/4 DQPSK
8DPSK
-
-
-
-
-
-
-86
-79
-6
-
-
-
-
-
-
≤-70
dBm
dBm
dBm
dBm
dB
Sensitivity at 0.01%
BER(a)
≤-70
π/4 DQPSK
8DPSK
≥-20
Maximum received
signal at 0.1% BER(a)
-7
≥-20
π/4 DQPSK
8DPSK
+11
+19
≤+13
C/I co-channel at 0.1%
BER(a)
≤+21
dB
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
-
-
-
-
-8
-2
-8
-2
-
-
-
-
≤0
≤+5
≤0
dB
dB
dB
dB
C/I F=F0 +1MHz(a) (b)
(c)
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
C/I F=F0 -1MHz (a) (b) (c)
≤+5
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
-
-
-
-
-
-
-
-
-
-
-35
-35
-23
-19
-43
-40
-43
-38
-17
-10
-
-
-
-
-
-
-
-
-
-
≤-30
≤-25
≤-20
≤-13
≤-40
≤-33
≤-40
≤-33
≤-7
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
C/I F=F0 +2MHz(a) (b) (c)
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
C/I F=F0 -2MHz(a) (b) (c)
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
C/I F≥F0 +3MHz(a) (b) (c)
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
C/I F≤F0 5MHz(a) (b) (c)
Adjacent channel
selectivity
π/4 DQPSK
8DPSK
(a) (b) (c)
C/I F=FImage
≤0
(a)
Measurements methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
(b)
Up to five exceptions are allowed in the Bluetooth v2.0 +EDR RF Test Specification.BlueCore4-Flash Plug-n-Go is
guaranteed to meet the C/I performance as specified by the Bluetooth v2.0 +EDR RF Test Specification
Measured at F0 = 2405MHz, 2441MHz, 2477MHz
(c)
Notes:
Results shown are referenced to the unbalanced port of the balun.
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Radio Characteristics - Enhanced Data Rate
6.2
Temperature -40°C
6.2.1 Transmitter
Radio Characteristics
VDD = 1.8V Temperature = -40°C
Bluetooth
Min
Typ
Max
Unit
Specification
-6 to +4(b)
-4 to +1
≤10
Maximum RF transmit power(a)
Relative transmit power(c)
Carrier frequency stability(c)
-
-
-
-
-
-
8
-
-
-
-
-
-
dBm
dB
kHz
%
-1
3
RMS DEVM
99% DEVM
Peak DEVM
10
15
20
≤13(e)
Modulation Accuracy(c) (d)
≤20(e)
%
≤25(e)
%
(a)
BlueCore4-Flash Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
(b)
(c)
(d)
(e)
Measurements methods are in accordance with the Bluetooth v2.0+EDR RF Test specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.2.2 Receiver
Radio Characteristics
VDD = 1.8V
Modulation
Temperature = -40°C
Bluetooth
Specification
Min
Typ
Max
Unit
π/4 DQPSK
8DPSK
-
-
-
-
-89
-82
-10
-10
-
-
-
-
≤-70
≤-70
≥-20
≥-20
dBm
dBm
dBm
dBm
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
8DPSK
Maximum received
signal at 0.1% BER(a)
(a)
Measurements methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
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Radio Characteristics - Enhanced Data Rate
6.3
Temperature -25°C
6.3.1 Transmitter
Radio Characteristics
VDD = 1.8V Temperature = -25°C
Bluetooth
Min
Typ
Max
Unit
Specification
-6 to +4(b)
-4 to +1
≤10
Maximum RF transmit power(a)
Relative transmit power(c)
Carrier frequency stability(c)
-
-
-
-
-
-
7
-
-
-
-
-
-
dBm
dB
kHz
%
-1
3
RMS DEVM
99% DEVM
Peak DEVM
10
15
20
≤13(e)
Modulation Accuracy(c) (d)
≤20(e)
%
≤25(e)
%
(a)
BlueCore4-Flash Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
(b)
(c)
(d)
(e)
Measurement methods are in accordance with the Bluetooth v2.0+EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.3.2 Receiver
Radio Characteristics
VDD = 1.8V
Modulation
Temperature =-25°C
Bluetooth
Specification
Min
Typ
Max
Unit
π/4 DQPSK
8DPSK
-
-
-
-
-87
-80
-10
-10
-
-
-
-
≤-70
≤-70
≥-20
≥20
dBm
dBm
dBm
dBm
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
8DPSK
Maximum received
signal at 0.1% BER(a)
(a)
Measurements methods are in accordance with the Bluetooth v2.0 +EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
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Radio Characteristics - Enhanced Data Rate
6.4
Temperature +85°C
6.4.1 Transmitter
Radio Characteristics
VDD = 1.8V Temperature = +85°C
Bluetooth
Specification
Min
Typ
Max
Unit
Maximum RF transmit power
(a)
-
1
-
-6 to +4(b)
dBm
Relative transmit power(c)
Carrier frequency stability(c)
-
-
-
-
-
-1
3
-
-
-
-
-
-4 to +1
≤10
dB
kHz
%
RMS DEVM
99% DEVM
Peak DEVM
10
15
20
≤13(e)
≤20(e)
≤25(e)
Modulation Accuracy(c) (d)
%
%
(a)
BlueCore4-Flash Plug-n-Go firmware keeps RF transmit power within the Bluetooth v2.0+EDR specification limits
Class 2 RF transmit power range, Bluetooth v2.0+EDR specification
(b)
(c)
(d)
(e)
Measurement methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Modulation accuracy utilises differential error vector magnitude (DEVM) with tracking of the carrier frequency drift.
The Bluetooth specification values are for 8DPSK modulation (values for the π/4 DQPSK modulation are less stringent)
Notes:
Results shown are referenced to the unbalanced port of the balun.
6.4.2 Receiver
Radio Characteristics
VDD = 1.8V
Modulation
Temperature = +85°C
Bluetooth
Specification
Min
Typ
Max
Unit
π/4 DQPSK
8DPSK
-
-
-
-
-84
-77
0
-
-
-
-
≤-70
≤-70
≥-20
≥-20
dBm
dBm
dBm
dBm
Sensitivity at 0.01%
BER(a)
π/4 DQPSK
8DPSK
Maximum received
signal at 0.1% BER(a)
-3
(a)
Measurements methods are in accordance with the Bluetooth v2.0 + EDR RF Test Specification
Notes:
Results shown are referenced to the unbalanced port of the balun.
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Device Diagram
7 Device Diagram
VDD_USB
VDD_PIO
AIO[0]
AIO[1]
AIO[2]
RESETB
RESET
VSS_PADS
VDD_PADS
FLASH_EN
TEST_EN
VDD_MEM
VSS_MEM
VSS_CORE
VDD_CORE
VDD_DIG
VDD_ANA
VSS_ANA
VSS_VCO
VREG_EN
VREG_IN
VSS_RADIO
XTAL_OUT
XTAL_IN
VDD_RADIO
Figure 7.1: BlueCore4-Flash Plug-n-Go Device Diagram
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Description of Functional Blocks
8 Description of Functional Blocks
8.1
RF Receiver
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated onto the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the
radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division
Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift
Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence
of noise allows BlueCore4-Flash Plug-n-Go to exceed the Bluetooth requirements for co-channel and adjacent
channel rejection.
For EDR, an ADC is used to digitise the IF received signal.
8.1.1 Low Noise Amplifier
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1(1)
Bluetooth operation; differential mode is used for Class 2 operation.
8.1.2 Analogue to Digital Converter
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples
the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed
according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the
dynamic range of the receiver, improving performance in interference limited environments.
8.2
RF Transmitter
8.2.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
8.2.2 Power Amplifier
The internal Power Amplifier (PA) has a maximum output power of +6dBm. This allows BlueCore4-Flash Plug-n-Go
to be used in Class 2 and Class 3 radios without an external RF PA.
8.2.3 Auxiliary DAC
An 8-bit voltage Auxiliary DAC is provided for power control of an external PA for Class 1 operation or any other
customer specific application.
8.3
Balun and Filter
The Plug-n-Go device incorporates a balun and filter to provide a 50Ω unbalanced antenna port.
8.4
RF Synthesiser
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator
(VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in
sufficient time across the guaranteed temperature range to meet the Bluetooth v2.0 + EDR specification.
8.5
Clock Input and Generation
The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal
reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
8.6
Baseband and Logic
8.6.1 Memory Management Unit
The Memory Management Unit (MMU) provides a number of dynamically allocated ring buffers that hold the data that
is in transit between the host and the air. The dynamic allocation of memory ensures efficient use of the available
Random Access Memory (RAM) and is performed by a hardware MMU to minimise the overheads on the processor
during data/voice transfers.
(1)
Class 1 operation is not recommended for Plug-n-Go devices and therefore is not recommended for BlueCore4-Flash Plug-n-Go.
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Description of Functional Blocks
8.6.2 Burst Mode Controller
During radio transmission the Burst Mode Controller (BMC) constructs a packet from header information previously
loaded into memory-mapped registers by the software and payload data/voice taken from the appropriate ring buffer
in the RAM. During radio reception, the BMC stores the packet header in memory-mapped registers and the payload
data in the appropriate ring buffer in RAM. This architecture minimises the intervention required by the processor
during transmission and reception.
8.6.3 Physical Layer Hardware Engine DSP
Dedicated logic is used to perform the following:
Forward error correction
Header error control
Cyclic redundancy check
Encryption
Data whitening
Access code correlation
Audio transcoding
The following voice data translations and operations are performed by firmware:
A-law/µ-law/linear voice data (from host)
A-law/µ-law/Continuously Variable Slope Delta (CVSD) (over the air)
Voice interpolation for lost packets
Rate mismatches
The hardware suports all optional and mandatory features of Bluetooth v2.0 + EDR including AFH and eSCO.
8.6.4 System RAM
48Kbytes of on-chip RAM is provided to support the RISC MCU and is shared between the ring buffers used to hold
voice/data for each active connection and the general purpose memory required by the Bluetooth stack.
8.6.5 Flash Memory (8Mbit)
8Mbits of internal Flash is available on the BC419143B. The Flash memory is provided for system firmware and the
Kalimba DSP co-processor code implementation.
8.6.6 USB
This is a full speed Universal Serial Bus (USB) interface for communicating with other compatible digital devices.
BlueCore4-Flash Plug-n-Go acts as a USB peripheral, responding to requests from a master host controller such as
a PC.
8.6.7 Synchronous Serial Interface
This is a synchronous serial port interface (SPI) for interfacing with other digital devices. The SPI port can be used for
system debugging. It can also be used for programming the Flash memory.
8.6.8 UART
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial
devices.
8.7
Microcontroller
The microcontroller (MCU), interrupt controller and event timer run the Bluetooth software stack and control the radio
and host interfaces. A 16-bit reduced instruction set computer (RISC) microcontroller is used for low power
consumption and efficient use of memory.
8.7.1 Programmable I/O
BlueCore4-Flash Plug-n-Go has a total of 15 (12 digital and 3 analogue) programmable I/O terminals. These are
controlled by firmware running on the device.
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Description of Functional Blocks
8.7.2 802.11 Co-Existence Interface
Dedicated hardware is provided to implement a variety of co-existence schemes. Channel skipping AFH, priority
signalling, channel signalling and host passing of channel instructions are all supported. The features are configured
in firmware. The details of some methods are proprietary (e.g., Intel WCS). Contact CSR for details.
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CSR Bluetooth Software Stacks
9 CSR Bluetooth Software Stacks
BlueCore4-Flash Plug-n-Go is supplied with Bluetooth v2.0 + EDR compliant stack firmware, which runs on the
internal RISC microcontroller.
The BlueCore4-Flash Plug-n-Go software architecture allows Bluetooth processing and the application program to be
shared in different ways between the internal RISC microcontroller and an external host processor (if any). The upper
layers of the Bluetooth stack (above HCI) can be run either on-chip or on the host processor.
9.1
BlueCore HCI Stack
HCI
LM
LC
Baseband
MCU
48KB RAM
USB
Host
Host I/O
UART
Radio
PCM I/O
Figure 9.1: BlueCore HCI Stack
In the implementation shown in the internal processor runs the Bluetooth stack up to the Host Controller Interface
(HCI). The Host processor must provide all upper layers including the application.
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CSR Bluetooth Software Stacks
9.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality
Bluetooth v2.0 + EDR mandatory functionality:
Adaptive frequency hopping (AFH), including classifier
Faster connection - enhanced inquiry scan (immediate FHS response)
LMP improvements
Parameter ranges
Optional Bluetooth v2.0 + EDR functionality supported:
Adaptive Frequency Hopping (AFH) as Master and Automatic Channel Classification
Fast Connect - Interlaced Inquiry and Page Scan plus RSSI during Inquiry
Extended SCO (eSCO), eV3 +CRC, eV4, eV5
SCO handle
Synchronisation
The firmware was written against the Bluetooth v2.0 + EDR specification.
Bluetooth components:
Baseband (including LC)
LM
HCI
Standard USB v1.1 and UART HCI Transport Layers
All standard radio packet types
Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps(1)
Operation with up to seven active slaves(1)
Scatternet v2.5 operation
Maximum number of simultaneous active ACL connections: 7(2)
Maximum number of simultaneous active SCO connections: 3(2)
Operation with up to three SCO links, routed to one or more slaves
All standard SCO voice coding, plus transparent SCO
Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan
All standard pairing, authentication, link key and encryption operations
Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold
Dynamic control of peers' transmit power via LMP
Master/Slave switch
Broadcast
Channel quality driven data rate
All standard Bluetooth test modes
The firmware's supported Bluetooth features are detailed in the standard Protocol Implementation Conformance
Statement (PICS) documents, available from www.csr.com.
(1)
This is the maximum allowed by Bluetooth v2.0 + EDR specification.
(2)
BlueCore4-Flash Plug-n-Go supports all combinations of active ACL and SCO channels for both master and slave operation, as specified
by the Bluetooth v2.0 + EDR specification.
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CSR Bluetooth Software Stacks
9.1.2 Key Features of the HCI Stack: Extra Functionality
The firmware extends the standard Bluetooth functionality with the following features:
Supports BlueCore Serial Protocol (BCSP), a proprietary, reliable alternative to the standard Bluetooth UART
Host Transport
Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,
called BlueCore Command (BCCMD), provides:
Access to the chip's general-purpose PIO port
The negotiated effective encryption key length on established Bluetooth links
Access to the firmware's random number generator
Controls to set the default and maximum transmit powers; these can help minimise interference
between overlapping, fixed-location piconets
Dynamic UART configuration
Radio transmitter enable/disable. A simple command connects to a dedicated hardware switch that
determines whether the radio can transmit.
The firmware can read the voltage on a pair of the chip's external pins. This is normally used to build a battery
monitor, using either VM or host code
A block of BCCMD commands provides access to the chip's Persistent Store configuration database (PS).
The database sets the device's Bluetooth address, Class of Device, radio (transmit class) configuration, SCO
routing, LM, USB and DFU constants, etc.
A UART break condition can be used in three ways:
1. Presenting a UART break condition to the chip can force the chip to perform a hardware reboot
2. Presenting a break condition at boot time can hold the chip in a low power state, preventing normal
initialisation while the condition exists
3. With BCSP, the firmware can be configured to send a break to the host before sending data. (This
is normally used to wake the host from a Deep Sleep state.)
The DFU standard has been extended with public/private key authentication, allowing manufacturers to
control the firmware that can be loaded onto their Bluetooth modules
A modified version of the DFU protocol allows firmware upgrade via the chip's UART
A block of radio test or BIST commands allows direct control of the chip's radio. This aids the development
of modules' radio designs, and can be used to support Bluetooth qualification.
Virtual Machine (VM). The firmware provides the VM environment in which to run application-specific code.
Although the VM is mainly used with BlueLab and RFCOMM builds (alternative firmware builds providing
L2CAP, SDP and RFCOMM), the VM can be used with this build to perform simple tasks such as flashing
LEDs via the chip's PIO port.
Hardware low power modes: Shallow Sleep and Deep Sleep. The chip drops into modes that significantly
reduce power consumption when the software goes idle.
SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed
over the chip's single PCM port (at the same time as routing any remaining SCO channels over HCI).
Note:
Always refer to the Firmware Release Note for the specific functionality of a particular build.
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CSR Bluetooth Software Stacks
9.2
BlueCore RFCOMM Stack
RFCOMM
SDP
L2CAP
HCI
LM
LC
Baseband
MCU
48KB RAM
USB
Host
Host I/O
UART
Radio
PCM I/O
Figure 9.2: BlueCore RFCOMM Stack
In the version of the firmware, shown in Figure 9.2 the upper layers of the Bluetooth stack up to RFCOMM are run
on-chip. This reduces host-side software and hardware requirements at the expense of some of the power and
flexibility of the HCI only stack.
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CSR Bluetooth Software Stacks
9.2.1 Key Features of the RFCOMM Stack
Interfaces to Host:
RFCOMM, an RS-232 serial cable emulation protocol
SDP, a service database look-up protocol
Connectivity:
Maximum number of active slaves: three
Maximum number of simultaneous active ACL connections: three
Maximum number of simultaneous active SCO connections: three
Data Rate: up to 350kbps(1)
Security:
Full support for all Bluetooth security features up to and including strong (128-bit) encryption.
Power Saving:
Full support for all Bluetooth power saving modes (Park, Sniff and Hold).
Data Integrity:
CQDDR increases the effective data rate in noisy environments.
RSSI used to minimise interference to other radio devices using the ISM band.
(1)
The data rate is with respect to BlueCore4-Flash Plug-n-Go with basic data rate packets.
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CSR Bluetooth Software Stacks
9.3
BlueCore Virtual Machine Stack
VM Application Software
RFCOMM
SDP
L2CAP
HCI
LM
LC
Baseband
MCU
48KB RAM
USB
Host (Optional)
Host I/O
UART
Radio
PCM I/O
Figure 9.3: Virtual Machine
In Figure 9.3, this version of the stack firmware shown requires no host processor (but it can use a host processor for
debugging, etc.). All software layers, including application software, run on the internal RISC processor in a protected
user software execution environment known as a Virtual Machine (VM).
The user may write custom application code to run on the BlueCore VM using BlueLab SDK supplied with the BlueLab
Multimedia and Casira development kits, available separately from CSR. This code will then execute alongside the
main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software routines,
thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is
changed.
Using the VM and the BlueLab SDK the user is able to develop applications such as a cordless handsfree kit or other
profiles without the requirement of a host controller. BlueLab is supplied with example code including a full
implementation of the handsfree profile.
Note:
Sample applications to control PIO lines can also be written with BlueLab SDK and the VM for the HCI stack.
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CSR Bluetooth Software Stacks
9.4
BlueCore HID Stack
VM Application Software
HID
SDP
L2CAP
HCI
LM
LC
Baseband
MCU
48KB RAM
Sensing
Hardware
(Optical Sensor
etc.)
PIO/UART
HID I/O
Radio
Figure 9.4: HID Stack
This version of the stack firmware requires no host processor. All software layers, including application software, run
on the internal RISC microcontroller in a protected user software execution environment known as a virtual machine
(VM).
The user may write custom application code to run on the BlueCore VM using BlueLab Professional SDK supplied with
the BlueLab Professional and Casira development kits, available separately from CSR. This code will then execute
alongside the main BlueCore firmware. The user is able to make calls to the BlueCore firmware for various operations.
The execution environment is structured so the user application does not adversely affect the main software routines,
thus ensuring that the Bluetooth stack software component does not need re-qualification when the application is
changed.
Using the VM and the BlueLab Professional SDK the user is able to develop Bluetooth HID devices such as an optical
mouse or keyboard. The user is able to customise features such as power management and connect/reconnect
behaviour.
The HID I/O component in the HID stack controls low latency data acquisition from external sensor hardware. With
this component running in native code, it does not incur the overhead of the VM code interpreter. Supported external
sensors include five mouse buttons, the Agilent ADNS-2030 optical sensor, quadrature scroll wheel, direct coupling
to a keyboard matrix and a UART interface to custom hardware.
A reference schematic for implementing a three button, optical mouse with scroll wheel is available from CSR.
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CSR Bluetooth Software Stacks
9.5
Host-Side Software
BlueCore4-Flash Plug-n-Go can be ordered with companion host-side software:
BlueCore3-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth
host-side stack together with IC hardware described in this document.
BlueCore3-Mobile includes software for a full host-side stack designed for modern ARM chip-based mobile
handsets together with IC hardware described in this document.
9.6
Device Firmware Upgrade
BlueCore4-Flash Plug-n-Go is supplied with boot loader software, which implements a Device Firmware Upgrade
(DFU) capability. This allows new firmware to be uploaded to the Flash memory through BlueCore4-Flash Plug-n-Go
UART or USB ports.
9.7
BCHS Software
BlueCore Embedded Host Software is designed to enable CSR customers to implement Bluetooth functionality into
embedded products quickly, cheaply and with low risk.
BCHS is developed to work with CSR's family of BlueCore ICs. BCHS is intended for embedded products that have a
host processor for running BCHS and the Bluetooth application, e.g., a mobile phone or a PDA. BCHS together with
the BlueCore IC with embedded Bluetooth core stack (L2CAP, RFCOMM and SDP) is a complete Bluetooth system
solution from RF to profiles.
BCHS includes most of the Bluetooth intelligence and gives the user a simple API. This makes it possible to develop
a Bluetooth product without in-depth Bluetooth knowledge.
The BlueCore Embedded Host Software contains three elements:
Example Drivers (BCSP and proxies)
Bluetooth Profile Managers
Example Applications
The profiles are qualified which makes the qualification of the final product very easy. BCHS is delivered with source
code (ANSI C). BCHS also comes with example applications in ANSI C, which makes the process of writing the
application easier.
9.8
Additional Software for Other Embedded Applications
When the upper layers of the Bluetooth protocol stack are run as firmware on BlueCore4-Flash Plug-n-Go, a UART
software driver is supplied that presents the L2CAP, RFCOMM and Service Discovery Protocol (SDP) APIs to higher
Bluetooth stack layers running on the host. The code is provided as C source or object code.
9.9
CSR Development Systems
CSR’s BlueLab Multimedia and Casira development kits are available to allow the evaluation of the BlueCore4-Flash
Plug-n-Go hardware and software, and as toolkits for developing on-chip and host software.
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Enhanced Data Rate
10 Enhanced Data Rate
EDR has been introduced to provide 2x and 3x(1) data rates with minimal disruption to higher layers of the Bluetooth
stack. BlueCore4-Flash Plug-n-Go supports both of the new data rates and is compliant with the Bluetooth v2.0+EDR
specification.
10.1
Enhanced Data Rate Baseband
At the baseband level EDR utilises both the same 1.6kHz slot rate and the 1MHz symbol rate as defined for the basic
data rate. Where EDR differs is that each symbol in the payload portion of a packet represents 2 or 3-bits. This is
achieved using two new distinct modulation schemes. These are summarised in Table 10.1 and in Figure 10.1. Link
Establishment and management are unchanged and still use GFSK for both the header and payload portions of these
packets.
Data Rate Scheme
Basic Data Rate
EDR
Bits Per Symbol
Modulation
GFSK
1
2
3
π/4 DQPSK
8DPSK (optional)
EDR
Table 10.1: Data Rate Schemes
Figure 10.1: Basic Rate and Enhanced Data Rate Packet Structure
10.2
Enhanced Data Rate π/4 DQPSK
The 2x data rate for EDR utilises a π/4-DQPSK. Each symbol represents two bits of information. Figure 10.2 shows
the constellation. It is described as having two planes, each having four points. Although it would appear that there are
eight possible phase states, the encoding ensures that the trajectory of the modulation between symbols is restricted
to the four states in the other plane.
For a given starting point, each phase change between symbols is restricted to +3π/4, +π/4, -π/4 or -3π/4 radians
(+135°, +45°, -135° or -45°). For example, the arrows shown in Figure 10.2 represents trajectory to the four possible
states in the other plane.Table 10.2 shows the phase shift encoding of symbols.
There are two primary advantages of utilising π/4-DQPSK modulation:
The scheme avoids the crossing of the origin (a +π or -π phase shift) and therefore minimises amplitude
variations in the envelope of the transmitted signal. This in turn allows the RF power amplifiers of the
transmitter to be operated closer to their compression point without introducing spectral distortions.
Consequently, the DC to RF efficiency is maximised.
The differential encoding also allows for the demodulation without the knowledge of an absolute value for the
phase of the RF carrier.
(1)
The inclusion of 3x data rates is optional.
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Enhanced Data Rate
01
00
11
10
Figure 10.2: π/4 DQPSK Constellation Pattern
Bit Pattern
Phase Shift
00
01
11
10
π/4
3π/4
-3π/4
-π/4
Table 10.2: 2-Bits Determine Phase Shift Between Consecutive Symbols
10.3
Enhanced Data Rate 8DPSK
The 3x data rate modulation uses eight phase differential phase shift keying (8DPSK). Each symbol in the payload
portion of the packet represents three baseband bits. Although it would appear that the 8DPSK is similar to π/4
DQPSK, the differential phase shifts between symbols are now permissible between any of the eight possible phase
states. This reduces the separation between adjacent symbols on the constellation to π/4 (45°) and thereby reduces
the noise and interference immunity of the modulation scheme. Nevertheless, since each symbol now represents 3
baseband bits, the actual throughput of the data is 3x when compared with the basic rate packet.
Figure 10.3 illustrates the 8DPSK constellation and Table 10.3 defines the phase encoding.
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Enhanced Data Rate
011
010
001
110
000
111
100
101
Figure 10.3: 8DPSK Constellation Pattern
Bit Pattern
Phase Shift
000
001
011
010
110
111
101
100
0
π/4
π/2
3π/4
π
-3π/4
-π/2
-π/4
Table 10.3: 3-Bits Determine Phase Shift Between Consecutive Symbols
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Device Terminal Descriptions
11 Device Terminal Descriptions
11.1
RF Ports
The BlueCore4-Flash Plug-n-Go RF_IN terminal can be configured as either a single-ended or differential input. The
operational mode is determined by setting the PS Key PSKEY_TXRX_PIO_CONTROL (0x20).
11.1.1 RF Plug-n-Go
The package used on the BlueCore4-Flash Plug-n-Go device is an RF Plug-n-Go package, where the terminal
RF_CONNECT forms an unbalanced ouput with a nominal 50Ω impedance. This terminal can be directly connected
to an antenna requiring no impedance matching network as Figure 11.1 indicates.
BlueCore
RF_CONNECT
R1
50Ω
Figure 11.1: Circuit for RF_CONNECT
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Device Terminal Descriptions
11.1.2 Single-Ended Input (RF_IN)
This is the single-ended RF input from the antenna. The input presents a complex impedance that requires a matching
network between the terminal and the antenna. Starting from the substrate (chip) side, the input can be modelled as
a lossy capacitor with the bond wire to the ball grid represented as a series inductance.
The terminal is DC blocked. The DC level must not exceed (VSS_RADIO -0.3V to VDD_RADIO + 0.3V).
BlueCore
L1
1.5nH
RF_IN
R1
6.8Ω
C1
0.68pF
Figure 11.2: Circuit RF_IN
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Device Terminal Descriptions
11.2
External Reference Clock Input (XTAL_IN)
The BlueCore4-Flash Plug-n-Go RF local oscillator and internal digital clocks are derived from the reference clock at
the BlueCore4-Flash Plug-n-Go XTAL_IN input. This reference may be either an external clock or from a crystal
connected between XTAL_IN and XTAL_OUT. The crystal mode is described in section 11.3.
11.2.1 External Mode
BlueCore4-Flash Plug-n-Go can be configured to accept an external reference clock from another device (such as
TCXO) at XTAL_IN by connecting XTAL_OUT to ground. The external clock can be either a digital level square wave
or sinusoidal, and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks
of the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor
(approximately 33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity, as the high
slew rate clock edges have lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 11.1:
Min
7.5MHz
20:80
Typ
Max
Frequency(a)
16MHz
40MHz
Duty cycle
50:50
80:20
Edge Jitter (At Zero Crossing)
Signal Level
-
-
-
15ps rms
VDD_ANA(b) (c)
400mV pk-pk
Table 11.1: External Clock Specifications
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
VDD_ANA is 1.8V nominal
If the external clock is driven through a DC blocking capacitor, then maximum allowable amplitude is reduced from
VDD_ANA to 800mV pk-pk.
(a)
(b)
(c)
11.2.2 XTAL_IN Impedance in External Mode
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from Deep Sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
11.2.3 Clock Timing Accuracy
As Figure 11.3 indicates, the 250ppm timing accuracy on the external clock is required 7ms after the assertion of the
system clock request line. This is to guarantee that the firmware can maintain timing accuracy in accordance with the
Bluetooth v2.0 + EDR specification. Radio activity may occur after 11ms, therefore, at this point the timing accuracy
of the external clock source must be within 20ppm.
Figure 11.3: TCXO Clock Accuracy
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Device Terminal Descriptions
11.2.4 Clock Start-Up Delay
BlueCore4-Flash Plug-n-Go hardware incorporates an automatic delay after the assertion of the system clock request
signal before running firmware. By default, the delay is 5 low-power oscillator (LPO) cycles. At a nominal LPO
frequency of 1 kHz, this equates to 5 ms. This is suitable for most applications using an external clock source.
However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period.
Under these conditions, BlueCore4-Flash Plug-n-Go provides a function that alters the system clock request signal to
the period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is in units of LPO cycles from 1 to 31. Setting the
key to zero gives a delay of 5 cycles, the default value.
The nominal frequency of the internal LPO is 1 kHz, however, the value varies somewhat between chips, so care
should be taken to pick a suitable value. If an external slow clock at 32 kHz is supplied, this is divided by 32 before use.
This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still keeping
the current consumption of BlueCore4-Flash Plug-n-Go as low as possible. BlueCore4-Flash Plug-n-Go consumes
about 2mA of current for the duration of PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.
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Device Terminal Descriptions
11.2.5 Input Frequencies and PS Key Settings
BlueCore4-Flash Plug-n-Go should be configured to operate with the chosen reference frequency. This is
accomplished by setting the PS Key PSKEY_ANA_FREQ (0x1fe) for all frequencies with an integer multiple of
250kHz. The input frequency default setting in BlueCore4-Flash Plug-n-Go is 26MHz.
The following CDMA/3G TCXO frequencies are also catered for: 7.68, 14.4, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68, 19.8
and 38.4MHz.
PSKEY_ANA_FREQ (0x1fe)
Reference Crystal Frequency (MHz)
(Units of 1kHz)
7.68
14.40
7680
14400
15360
16200
16800
19200
19440
19680
19800
38400
-
15.36
16.20
16.80
19.20
19.44
19.68
19.80
38.40
n x 250kHz
+26.00 Default
26000
Table 11.2: PS Key Values for CDMA/3G Phone TCXO Frequencies
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Device Terminal Descriptions
11.3
Crystal Oscillator (XTAL_IN, XTAL_OUT)
This section describes the crystal mode. See section 11.2 for the description of the external reference clock mode.
11.3.1 XTAL Mode
BlueCore4-Flash Plug-n-Go contains a crystal driver circuit. This operates with an external crystal and capacitors to
form a Pierce oscillator.
gm
-
Cint
Ctrim
Ctrim
Ct2
Ct1
Figure 11.4: Crystal Driver Circuit
Figure 11.5 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant
frequency. It forms a resonant circuit with its load capacitors.
Figure 11.5: Crystal Equivalent Circuit
The resonant frequency may be trimmed with the crystal load capacitance. BlueCore4-Flash Plug-n-Go contains
variable internal capacitors to provide a fine trim.
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Device Terminal Descriptions
Min
Typ
Max
Frequency
8MHz
26MHz
32MHz
Initial Tolerance
Pullability
-
-
±25ppm
±20ppm/pF
-
-
Table 11.3: Crystal Specification
The BlueCore4-Flash Plug-n-Go driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a
current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.
11.3.2 Load Capacitance
For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is
defined for the crystal. This is the total capacitance across the crystal viewed from its terminals. BlueCore4-Flash
Plug-n-Go provides some of this load with the capacitors Ctrim and Cint. The remainder should be from the external
capacitors labelled Ct1 and Ct2. Ct1 should be three times the value of Ct2 for best noise performance. This maximises
the signal swing, hence, slew rate at XTAL_IN (to which all on-chip clocks are referred). Crystal load capacitance, Cl
is calculated with Equation 11.1:
Ctrim
2
C
t1•Ct2
CI = Cint
+
+
Ct1 + Ct2
Equation 11.1: Load Capacitance
Where:
Ctrim = 3.4pF nominal (mid-range setting)
Cint = 1.5pF
Note:
Cint does not include the crystal internal self capacitance; it is the driver self capacitance.
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Device Terminal Descriptions
11.3.3 Frequency Trim
BlueCore4-Flash Plug-n-Go enables frequency adjustments to be made. This feature is typically used to remove initial
tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load
capacitance with on-chip trim capacitors, Ctrim. The value of Ctrim is set by a 6-bit word in the PS Key
PSKEY_ANA_FTRIM (0x1f6). Its value is calculated thus:
Ctrim = 110fF×PSKEY_ ANA_ FTRIM
Equation 11.2: Trim Capacitance
There are two Ctrim capacitors, which are both connected to ground. When viewed from the crystal terminals, they
appear in series so each least significant bit (LSB) increment of frequency trim presents a load across the crystal of
55fF.
The frequency trim is described by Equation 11.3.
∆
FX
(
FX
)
= pullabiliyt ×55×10−3
(
ppm/LSB
)
Equation 11.3: Frequency Trim
Where Fx is the crystal frequency and pullability is a crystal parameter with units of ppm/pF. Total trim range is 63
times the value above.
If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 11.4.
∂
∂
(
FX
)
Cm
CI C0
Equation 11.4: Pullability
FX
=
•
2
C
( )
2
(
+
)
Where:
C0 = Crystal self capacitance (shunt capacitance)
Cm = Crystal motional capacitance (series branch capacitance in crystal model). See Figure 11.5.
Note:
It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to
pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with ageing
and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is required.
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Device Terminal Descriptions
11.3.4 Transconductance Driver Model
The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one
terminal generates a voltage at the other. The transconductance amplifier in BlueCore4-Flash Plug-n-Go uses the
voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the
transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product
should be greater than three. The transconductance required for oscillation is defined by the relationship shown in
Equation 11.5:
2
(
3 2πFx
)
2 Rm ((C0 + Cint Ct1 + Ct2 + Ctrim
Ct1 + Ctrim Ct2 + Ctrim ))
+
gm
>
(
Ct1 + Ctrim )(Ct2 + Ctrim
)
Equation 11.5: Transconductance Required for Oscillation
BlueCore4-Flash Plug-n-Go guarantees a transconductance value of at least 2mA/V at maximum drive level.
Notes:
More drive strength is required for higher frequency crystals, higher loss crystals (larger Rm) or higher capacitance
loading.
Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is
determined by the crystal driver transconductance, by setting the PS Key PSKEY_XTAL_LVL (0x241).
11.3.5 Negative Resistance Model
An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The
driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the
negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the
BlueCore4-Flash Plug-n-Go crystal driver circuit is based on a transimpedance amplifier, an equivalent negative
resistance may be calculated for it with the following formula in Equation 11.6:
(
Ct1
+
Ctrim) (Ct2
+
Ctrim
)
Rneg
>
2
2
+
trim
gm
(
2
π
FX) ((C0
+
Cint )(Ct1
+
Ct2
+
2C
)
+
(
C
)(Ct2
Ctrim))
+
Ct1
trim
Equation 11.6: Equivalent Negative Resistance
This formula shows the negative resistance of the BlueCore4-Flash Plug-n-Go driver as a function of its drive strength.
The value of the driver negative resistance may be easily measured by placing an additional resistance in series with
the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the
oscillator.
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Device Terminal Descriptions
11.3.6 Crystal PS Key Settings
See tables in section 11.2.5.
11.3.7 Crystal Oscillator Characteristics
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
1000.0
100.0
10.0
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
10.5
11.5
12.5
Load Capacitance (pF)
8 MHz
20 MHz
32 MHz
12 MHz
24 MHz
16 MHz
28 MHz
Figure 11.6: Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency
Note:
Graph shows results for BlueCore4-Flash Plug-n-Go crystal driver at maximum drive level.
Conditions:
Ctrim = 3.4pF centre value
Crystal Co = 2pF
Transconductance setting = 2mA/V
Loop gain = 3
Ct1/Ct2 = 3
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Device Terminal Descriptions
Figure 11.7: Crystal Driver Transconductance vs. Driver Level Register Setting
Note:
Drive level is set by PS Key PSKEY_XTAL_LVL (0x241).
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Device Terminal Descriptions
Figure 11.8: Crystal Driver Negative Resistance as a Function of Drive Level Setting
Crystal parameters:
Crystal frequency 16MHz (refer to your software build release note for supported frequencies ).
Crystal C0 = 0.75pF
Circuit parameters:
Ctrim = 8pF, maximum value
Ct1,Ct2 = 5pF (3.9pF plus 1.1 pF stray)
(Crystal total load capacitance 8.5pF)
Note:
This is for a specific crystal and load capacitance.
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Device Terminal Descriptions
11.4
UART Interface
This is a standard Universal Asynchronous Receiver Transmitter (UART) interface for communicating with other serial
devices.
BlueCore4-Flash Plug-n-Go UART interface provides a simple mechanism for communicating with other serial devices
using the RS232 protocol.(1)
BlueCore
UART_TX
UART_RX
UART_RTS
UART_CTS
Figure 11.9: Universal Asynchronous Receiver
Four signals are used to implement the UART function, as shown in Figure 11.9. When BlueCore4-Flash Plug-n-Go
is connected to another digital device, UART_RX and UART_TX transfer data between the two devices. The
remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware flow control where
both are active low indicators. All UART connections are implemented using CMOS technology and have signalling
levels of 0V and VDD_USB.
UART configuration parameters, such as baud rate and packet format, are set using BlueCore4-Flash Plug-n-Go
software.
Note:
In order to communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port
adapter card is required for the PC.
Parameter
Possible Values
1200 baud (≤2%Error)
9600 baud (≤1%Error)
3M baud (≤1%Error)
RTS/CTS or None
None, Odd or Even
1 or 2
Minimum
Maximum
Baud Rate
Flow Control
Parity
Number of Stop Bits
Bits per Channel
8
Table 11.4: Possible UART Settings
The UART interface is capable of resetting BlueCore4-Flash Plug-n-Go upon reception of a break signal. A break is
identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 11.10. If tBRK is longer than
the value, defined by the PS Key PSKEY_HOST_IO_UART_RESET_TIMEOUT, (0x1a4), a reset will occur. This
feature allows a host to initialise the system to a known state. Also, BlueCore4-Flash Plug-n-Go can emit a break
character that may be used to wake the host.
(1)
Uses RS232 protocol, but voltage levels are 0V to VDD_USB (requires external RS232 transceiver chip).
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Device Terminal Descriptions
Figure 11.10: Break Signal
Note:
The DFU boot loader must be loaded into the Flash device before the UART or USB interfaces can be used. This
initial flash programming can be done via the SPI.
Table 11.5 shows a list of commonly used baud rates and their associated values for the PS Key
PSKEY_UART_BAUD_RATE (0x204). There is no requirement to use these standard values. Any baud rate within
the supported range can be set in the PS Key according to the formula in Equation 11.7.
PSKEY_UART_BAUD_RATE
BaudRate =
0.004096
Equation 11.7: Baud Rate
Persistent Store Value
Baud Rate
Error
Hex
Dec
5
1200
2400
0x0005
0x000a
0x0014
0x0027
0x004f
0x009d
0x00ec
0x013b
0x01d8
0x03b0
0x075f
0x0ebf
0x161e
0x1d7e
0x2c3d
1.73%
1.73%
1.73%
-0.82%
0.45%
-0.18%
0.03%
0.14%
0.03%
0.03%
-0.02%
0.00%
-0.01%
0.00%
0.00%
10
4800
20
9600
39
19200
38400
57600
76800
115200
230400
460800
921600
1382400
1843200
2764800
79
157
236
315
472
944
1887
3775
5662
7550
11325
Table 11.5: Standard Baud Rates
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11.4.1 UART Bypass
BlueCore
Another Device
Host Processor
RESET
UART_TX
UART_RTS
UART_CTS
UART_RX
PIO4
PIO5
PIO6
PIO7
RXD
CTS
RTS
TXD
TX
RTS
CTS
RX
UART
Test Interface
Figure 11.11: UART Bypass Architecture
11.4.2 UART Configuration While RESET is Active
The UART interface for BlueCore4-Flash Plug-n-Go while the chip is being held in reset is tri-state. This will allow the
user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices connected
to this bus must tri-state when BlueCore4-Flash Plug-n-Go reset is de-asserted and the firmware begins to run.
11.4.3 UART Bypass Mode
Alternatively, for devices that do not tri-state the UART bus, the UART bypass mode on BlueCore4-Flash Plug-n-Go
can be used. The default state of BlueCore4-Flash Plug-n-Go after reset is de-asserted; this is for the host UART bus
to be connected to the BlueCore4-Flash Plug-n-Go UART, thereby allowing communication to BlueCore4-Flash
Plug-n-Go via the UART. All UART bypass mode connections are implemented using CMOS technology and have
signalling levels of 0V and VDD_PADS.(1)
In order to apply the UART bypass mode, a BCCMD command will be issued to BlueCore4-Flash Plug-n-Go. Upon
this issue, it will switch the bypass to PIO[7:4] as Figure 11.11 indicates. Once the bypass mode has been invoked,
BlueCore4-Flash Plug-n-Go will enter the Deep Sleep state indefinitely.
In order to re-establish communication with BlueCore4-Flash Plug-n-Go, the chip must be reset so that the default
configuration takes effect.
It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is
invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.
11.4.4 Current Consumption in UART Bypass Mode
The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby
mode.
(1)
The range of the signalling level for the standard UART described in section 11.4 and the UART bypass may differ between CSR BlueCore
devices, as the power supply configurations are chip dependent. For BlueCore4-Flash Plug-n-Go, the standard UART is supplied by
VDD_USB, so has signalling levels of 0V and VDD_USB. Whereas in the UART bypass mode, the signals appear on PIO[4:7] which are
supplied by VDD_PADS, therefore the signalling levels are 0V and VDD_PADS.
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11.5
USB Interface
This is a full speed (12Mbits/s) Universal Serial Bus (USB) interface for communicating with other compatible digital
devices. BlueCore4-Flash Plug-n-Go acts as a USB peripheral, responding to requests from a master host controller
such as a PC.
The USB interface is capable of driving a USB cable directly. No external USB transceiver is required. The device
operates as a USB peripheral, responding to requests from a master host controller such as a PC. Both the OHCI and
the UHCI standards are supported. The set of USB endpoints implemented can behave as specified in the USB
section of the Bluetooth specification v2.0+EDR or alternatively can appear as a set of endpoints appropriate to USB
audio devices such as speakers.
As USB is a master/slave oriented system (in common with other USB peripherals), BlueCore4-Flash Plug-n-Go only
supports USB Slave operation.
11.5.1 USB Data Connections
The USB data lines emerge as pins USB_DP and USB_DN. These terminals are connected to the internal USB I/O
buffers of the BlueCore4-Flash Plug-n-Go, therefore, have a low output impedance. To match the connection to the
characteristic impedance of the USB cable, resistors must be placed in series with USB_DP/USB_DN and the cable.
11.5.2 USB Pull-Up Resistor
BlueCore4-Flash Plug-n-Go features an internal USB pull-up resistor. This pulls the USB_DP pin weakly high when
BlueCore4-Flash Plug-n-Go is ready to enumerate. It signals to the PC that it is a full speed (12Mbit/s) USB device.
The USB internal pull-up is implemented as a current source, and is compliant with section 7.1.5 of the USB
specification v1.2. The internal pull-up pulls USB_DP high to at least 2.8V when loaded with a 15kΩ ±5% pull-down
resistor (in the hub/host) when VDD_PADS=3.1V. This presents a Thevenin resistance to the host of at least 900Ω.
Alternatively, an external 1.5kΩ pull-up resistor can be placed between a PIO line and D+ on the USB cable. The
firmware must be alerted to which mode is used by setting PS Key PSKEY_USB_PIO_PULLUP appropriately. The
default setting uses the internal pull-up resistor.
11.5.3 USB Power Supply
The USB specification dictates that the minimum output high voltage for USB data lines is 2.8V. To safely meet the
USB specification, the voltage on the VDD_USB supply terminals must be an absolute minimum of 3.1V. CSR
recommends 3.3V for optimal USB signal quality.
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11.5.4 Self-Powered Mode
In self-powered mode, the circuit is powered from its own power supply and not from the VBUS (5V) line of the USB
cable. It draws only a small leakage current (below 0.5mA) from VBUS on the USB cable. This is the easier mode for
which to design, as the design is not limited by the power that can be drawn from the USB hub or root port. However,
it requires that VBUS be connected to BlueCore4-Flash Plug-n-Go via a resistor network (Rvb1 and Rvb2), so
BlueCore4-Flash Plug-n-Go can detect when VBUS is powered up. BlueCore4-Flash Plug-n-Go will not pull USB_DP
high when VBUS is off.
Self-powered USB designs (powered from a battery or PSU) must ensure that a PIO line is allocated for USB pull-up
purposes. A 1.5KΩ 5% pull-up resistor between USB_DP and the selected PIO line should be fitted to the design.
Failure to fit this resistor may result in the design failing to be USB compliant in self-powered mode. The internal pull-up
in BlueCore is only suitable for bus-powered USB devices, e.g., dongles.
BlueCore
PIO
1.5KΩ
5%
Rs
USB_DP
USB_DN
USB_ON
D+
Rs
D-
Rvb1
VBUS
Rvb2
GND
Figure 11.12: USB Connections for Self-Powered Mode
The terminal marked USB_ON can be any free PIO pin. The PIO pin selected must be registered by setting
PSKEY_USB_PIO_VBUS to the corresponding pin number.
Note:
USB_ON is shared with BlueCore4-Flash Plug-n-Go PIO terminals.
Identifier
Rs
Value
Function
27Ω nominal
22kΩ 5%
47kΩ 5%
Impedance matching to USB cable
VBUS ON sense divider
VBUS ON sense divider
Rvb1
Rvb2
Table 11.6: USB Interface Component Values
11.5.5 Bus-Powered Mode
In bus-powered mode, the application circuit draws its current from the 5V VBUS supply on the USB cable.
BlueCore4-Flash Plug-n-Go negotiates with the PC during the USB enumeration stage about how much current it is
allowed to consume.
For Class 2 Bluetooth applications, CSR recommends that the regulator used to derive 3.3V from VBUS is rated at
100mA average current and should be able to handle peaks of 120mA without foldback or limiting. In bus-powered
mode, BlueCore4-Flash Plug-n-Go requests 100mA during enumeration.
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For Class 1 Bluetooth applications, the USB power descriptor should be altered to reflect the amount of power
required. This is accomplished by setting the PS Key PSKEY_USB_MAX_POWER (0x2c6). This is higher than for a
Class 2 application due to the extra current drawn by the Transmit RF PA.
When selecting a regulator, be aware that VBUS may go as low as 4.4V. The inrush current (when charging reservoir
and supply decoupling capacitors) is limited by the USB specification. See USB Specification v1.1, section 7.2.4.1.
Some applications may require soft start circuitry to limit inrush current if more than 10µF is present between VBUS
and GND.
The 5V VBUS line emerging from a PC is often electrically noisy. As well as regulation down to 3.3V and 1.8V,
applications should include careful filtering of the 5V line to attenuate noise that is above the voltage regulator
bandwidth. Excessive noise on the 1.8V supply to the analogue supply pins of BlueCore4-Flash Plug-n-Go will result
in reduced receive sensitivity and a distorted RF transmit signal.
BlueCore
Rs
USB_DP
D+
Rs
D-
USB_DN
USB_ON
Rvb1
VBUS
GND
Voltage
Regulator
Figure 11.13: USB Connections for Bus-Powered Mode
11.5.6 Suspend Current
All USB devices must permit the USB controller to place them in a USB suspend mode. While in USB Suspend,
bus-powered devices must not draw more than 0.5mA from USB VBUS (self-powered devices may draw more than
0.5mA from their own supply). This current draw requirement prevents operation of the radio by bus-powered devices
during USB Suspend.
The voltage regulator circuit itself should draw only a small quiescent current (typically less than 100µA) to ensure
adherence to the suspend current requirement of the USB specification. This is not normally a problem with modern
regulators. Ensure that external LEDs and/or amplifiers can be turned off by BlueCore4-Flash Plug-n-Go. The entire
circuit must be able to enter the suspend mode. Refer to separate CSR documentation for more details on USB
Suspend.
11.5.7 Detach and Wake_Up Signalling
BlueCore4-Flash Plug-n-Go can provide out-of-band signalling to a host controller by using the control lines called
USB_DETACH and USB_WAKE_UP. These are outside the USB specification (no wires exist for them inside the USB
cable), but can be useful when embedding BlueCore4-Flash Plug-n-Go into a circuit where no external USB is visible
to the user. Both control lines are shared with PIO pins and can be assigned to any PIO pin by setting the PS Keys
PSKEY_USB_PIO_DETACH and PSKEY_USB_PIO_WAKEUP to the selected PIO number.
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USB_DETACH is an input which, when asserted high, causes BlueCore4-Flash Plug-n-Go to put USB_DN and
USB_DP in a high impedance state and turns off the pull-up resistor on DP. This detaches the device from the bus
and is logically equivalent to unplugging the device. When USB_DETACH is taken low, BlueCore4-Flash Plug-n-Go
will connect back to USB and await enumeration by the USB host.
USB_WAKE_UP is an active high output (used only when USB_DETACH is active) to wake up the host and allow USB
communication to recommence. It replaces the function of the software USB WAKE_UP message (which runs over
the USB cable) and cannot be sent while BlueCore4-Flash Plug-n-Go is effectively disconnected from the bus.
Figure 11.14: USB_DETACH and USB_WAKE_UP Signal
11.5.8 USB Driver
A USB Bluetooth device driver is required to provide a software interface between BlueCore4-Flash Plug-n-Go and
Bluetooth software running on the host computer. Suitable drivers are available from http://www.csrsupport.com.
11.5.9 USB 1.1 Compliance
BlueCore4-Flash Plug-n-Go is qualified to the USB Specification v1.1, details of which are available from
www.usb.org. The specification contains valuable information on aspects such as PCB track impedance, supply inrush
current and product labelling.
Although BlueCore4-Flash Plug-n-Go meets the USB specification, CSR cannot guarantee that an application circuit
designed around the chip is USB compliant. The choice of application circuit, component choice and PCB layout all
affect USB signal quality and electrical characteristics. The information in this document is intended as a guide and
should be read in association with the USB specification, with particular attention being given to Chapter 7.
Independent USB qualification must be sought before an application is deemed USB compliant and can bear the USB
logo. Such qualification can be obtained from a USB plugfest or from an independent USB test house.
Terminals USB_DP and USB_DN adhere to the USB specification v2.0 (Chapter 7) electrical requirements.
11.5.10 USB 2.0 Compatibility
BlueCore4-Flash Plug-n-Go is compatible with USB v2.0 host controllers; under these circumstances the two ends
agree the mutually acceptable rate of 12Mbits/s according to the USB v2.0 specification.
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11.6
Serial Peripheral Interface
BlueCore4-Flash Plug-n-Go uses 16-bit data and 16-bit address serial peripheral interface, where transactions may
occur when the internal processor is running or is stopped. This section details the considerations required when
interfacing to BlueCore4-Flash Plug-n-Go via the four dedicated serial peripheral interface terminals. Data may be
written or read one word at a time or the auto increment feature may be used to access blocks.
11.6.1 Instruction Cycle
The BlueCore4-Flash Plug-n-Go is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO.
shows the instruction cycle for an SPI transaction.
1
2
3
4
5
Reset the SPI interface
Write the command word
Write the address
Hold SPI_CSB high for two SPI_CLK cycles
Take SPI_CSB low and clock in the 8 bit command
Clock in the 16-bit address word
Write or read data words
Termination
Clock in or out 16-bit data word(s)
Take SPI_CSB high
Table 11.7: Instruction Cycle for an SPI Transaction
With the exception of reset, SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the
BlueCore4-Flash Plug-n-Go on the rising edge of the clock line SPI_CLK. When reading, BlueCore4-Flash Plug-n-Go
will reply to the master on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides
the clock on SPI_CLK. The transaction is teminated by taking SPI_CSB high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore4-Flash Plug-n-Go
offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept
low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or
read.
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11.6.2 Writing to the Device
To write to BlueCore4-Flash Plug-n-Go, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-bit
address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the location set by the address
(A). Thereafter for each subsequent 16-bits clocked in, the address (A) is incremented and the data written to
consecutive locations until the transaction terminates when SPI_CSB is taken high.
Figure 11.15: SPI Write Operation
11.6.3 Reading from the Device
Reading from BlueCore4-Flash Plug-n-Go is similar to writing to it. An 8-bit read command (00000011) is sent first
(C[7:0]), followed by the address of the location to be read (A[15:0]). BlueCore4-Flash Plug-n-Go then outputs on
SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed location during bits D[15:0].
The check word is composed of {command, address [15:8]}. The check word may be used to confirm a read operation
to a memory location. This overcomes the problems encountered with typical serial peripheral interface slaves,
whereby it is impossible to determine whether the data returned by a read operation is valid data or the result of the
slave device not responding.
If SPI_CSB is kept low, data from consecutive locations is read out on SPI_MISO for each subsequent 16 clocks, until
the transaction terminates when SPI_CSB is taken high.
Figure 11.16: SPI Read Operation
11.6.4 Multi-Slave Operation
BlueCore4-Flash Plug-n-Go should not be connected in a multi-slave arrangement by simple parallel connection of
slave MISO lines. When BlueCore4-Flash Plug-n-Go is deselected (SPI_CSB = 1), the SPI_MISO line does not float.
Instead, BlueCore4-Flash Plug-n-Go outputs 0 if the processor is running or 1 if it is stopped.
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11.7
PCM CODEC Interface
Pulse Code Modulation (PCM) is a standard method used to digitise audio (particularly voice) for transmission over
digital communication channels. Through its PCM interface, BlueCore4-Flash Plug-n-Go has hardware support for
continual transmission and reception of PCM data, thus reducing processor overhead for wireless headset
applications. BlueCore4-Flash Plug-n-Go offers a bi-directional digital audio interface that routes directly into the
baseband layer of the on-chip firmware. It does not pass through the HCI protocol layer.
Hardware on BlueCore4-Flash Plug-n-Go allows the data to be sent to and received from a SCO connection. (1)
Up to three SCO connections can be supported by the PCM interface at any one time.
BlueCore4-Flash Plug-n-Go can operate as the PCM interface master generating an output clock of 128, 256 or
512kHz. When configured as PCM interface slave, it can operate with an input clock up to 2048kHz. BlueCore4-Flash
Plug-n-Go is compatible with a variety of clock formats, including Long Frame Sync, Short Frame Sync and GCI timing
environments.
It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats at 8ksamples/s and can receive and
transmit on any selection of three of the first four slots following PCM_SYNC. The PCM configuration options are
enabled by setting the PS Key PS KEY_PCM_CONFIG32 (0x1b3).
BlueCore4-Flash Plug-n-Go interfaces directly to PCM audio devices including the following:
Qualcomm MSM 3000 series and MSM 5000 series CDMA baseband devices
OKI MSM7705 four channel A-law and µ-law CODEC
Motorola MC145481 8-bit A-law and µ-law CODEC
Motorola MC145483 13-bit linear CODEC
STW 5093 and 5094 14-bit linear CODECs
BlueCore4-Flash Plug-n-Go is also compatible with the Motorola SSI interface
11.7.1 PCM Interface Master/Slave
When configured as the master of the PCM interface, BlueCore4-Flash Plug-n-Go generates PCM_CLK and
PCM_SYNC.
BlueCore
PCM_OUT
PCM_IN
PCM_CLK
128/256/512kHz
8kHz
PCM_SYNC
Figure 11.17: BlueCore4-Flash Plug-n-Go as PCM Interface Master
When configured as the Slave of the PCM interface, BlueCore4-Flash Plug-n-Go accepts PCM_CLK rates up to
2048kHz.
(1)
Subject to firmware support. Contact CSR for current status.
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BlueCore
PCM_OUT
PCM_IN
PCM_CLK
PCM_SYNC
Upto 2048kHz
8kHz
Figure 11.18: BlueCore4-Flash Plug-n-Go as PCM Interface Slave
11.7.2 Long Frame Sync
Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples. In
Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When BlueCore4-Flash
Plug-n-Go is configured as PCM master, generating PCM_SYNC and PCM_CLK, then PCM_SYNC is 8-bits long.
When BlueCore4-Flash Plug-n-Go is configured as PCM Slave, PCM_SYNC may be from two consecutive falling
edges of PCM_CLK to half the PCM_SYNC rate, i.e., 62.5µs long.
PCM_SYNC
PCM_CLK
PCM_OUT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
PCM_IN
8
Undefined
Undefined
Figure 11.19: Long Frame Sync (Shown with 8-bit Companded Sample)
BlueCore4-Flash Plug-n-Go samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising
edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position or on
the rising edge.
11.7.3 Short Frame Sync
In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always one
clock cycle long.
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PCM_SYNC
PCM_CLK
PCM_OUT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15
16
PCM_IN Undefined
10 11 12 13 14 15 16
Undefined
Figure 11.20: Short Frame Sync (Shown with 16-bit Sample)
As with Long Frame Sync, BlueCore4-Flash Plug-n-Go samples PCM_IN on the falling edge of PCM_CLK and
transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of
PCM_CLK in the LSB position or on the rising edge.
11.7.4 Multi-slot Operation
More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections
can be carried over any of the first four slots.
LONG_PCM_SYNC
Or
SHORT_PCM_SYNC
PCM_CLK
PCM_OUT
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
PCM_IN Do Not Care
8
8 Do Not Care
Figure 11.21: Multi-slot Operation with Two Slots and 8-bit Companded Samples
11.7.5 GCI Interface
BlueCore4-Flash Plug-n-Go is compatible with the General Circuit Interface (GCI), a standard synchronous 2B+D
ISDN timing interface. The two 64Kbps B channels can be accessed when this mode is configured.
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PCM_SYNC
PCM_CLK
PCM_OUT
PCM_IN
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
Do Not
Care
Do Not
Care
8
B1 Channel
B2 Channel
Figure 11.22: GCI Interface
The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz. With BlueCore4-Flash Plug-n-Go
in Slave mode, the frequency of PCM_CLK can be up to 4.096MHz.
11.7.6 Slots and Sample Formats
BlueCore4-Flash Plug-n-Go can receive and transmit on any selection of the first four slots following each sync pulse.
Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample
formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.
BlueCore4-Flash Plug-n-Go supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. The sample
rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each
slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation compatible with
some Motorola CODECs.
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Sign
Extension
PCM_OUT
PCM_OUT
PCM_OUT
PCM_OUT
1
2
3
3
3
3
4
5
6
7
8
9
10
11
12
8-Bit
Sample
13
14
15 16
A 16-bit slot with 8-bit companded sample and sign extension selected.
8-Bit
Sample
1
2
4
5
6
7
8
9
10
11
12
Zeros
Padding
A 16-bit slot with 8-bit companded sample and zeros padding selected.
13
14
15 16
Sign
Extension
1
2
4
5
6
7
8
9
10
11
12
13
14
15 16
13-Bit
Sample
A 16-bit slot with 13-bit linear sample and sign extension selected.
13-Bit
Sample
1
2
4
5
6
7
8
9
10
11
12
13
14
15 16
Audio
Gain
A 16-bit slot with 13-bit linear sample and audio gain selected.
Figure 11.23: 16-Bit Slot Length and Sample Formats
11.7.7 Additional Features
BlueCore4-Flash Plug-n-Go has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also
be forced to 0 while keeping PCM_CLK running which some CODECS use to control power down.
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11.7.8 PCM Timing Information
Symbol
Parameter
Min
Typ
128
256
Max
Unit
4MHz DDS
generation. Selection
of frequency is
programmable. See
Table 11.10.
-
-
kHz
512
48MHz DDS
generation. Selection
of frequency is
programmable. See
Table 11.11 and
PCM_CLK and
PCM_SYNC
fmclk
PCM_CLK frequency
2.9
-
-
kHz
Generation on page
76.
-
PCM_SYNC frequency
PCM_CLK high
-
8
-
kHz
ns
(a)
tmclkh
4MHz DDS generation
4MHz DDS generation
980
730
(a)
tmclkl
PCM_CLK low
-
ns
48MHz DDS
generation
-
PCM_CLK jitter
21
20
20
20
20
20
20
ns pk-pk
Delay time from PCM_CLK high to PCM_SYNC
high
tdmclksynch
tdmclkpout
tdmclklsyncl
tdmclkhsyncl
tdmclklpoutz
tdmclkhpoutz
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Delay time from PCM_CLK high to valid
PCM_OUT
Delay time from PCM_CLK low to PCM_SYNC
low (Long Frame Sync only)
Delay time from PCM_CLK high to PCM_SYNC
low
Delay time from PCM_CLK low to PCM_OUT
high impedance
Delay time from PCM_CLK high to PCM_OUT
high impedance
tsupinclkl
thpinclkl
Set-up time for PCM_IN valid to PCM_CLK low
Hold time for PCM_CLK low to PCM_IN invalid
30
10
-
-
-
-
ns
ns
Table 11.8: PCM Master Timing
Assumes normal system clock operation. Figures will vary during low power modes, when system clock speeds are
reduced.
(a)
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t dmclklsyncl
t dmclksynch
t dmclkhsyncl
PCM_SYNC
fmlk
tmclkh
tmclkl
PCM_CLK
t dmclklpoutz
t dmclkpout
tr ,t f
t dmclkhpoutz
PCM_OUT
PCM_IN
MSB (LSB)
LSB (MSB)
t supinclkl
thpinclkl
MSB (LSB)
LSB (MSB)
Figure 11.24: PCM Master Timing Long Frame Sync
t dmclksynch
t dmclkhsyncl
PCM_SYNC
fmlk
tmclkh
tmclkl
PCM_CLK
t dmclklpoutz
t dmclkpout
tr ,t f
t dmclkhpoutz
PCM_OUT
PCM_IN
MSB (LSB)
LSB (MSB)
t supinclkl
thpinclkl
MSB (LSB)
LSB (MSB)
Figure 11.25: PCM Master Timing Short Frame Sync
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Device Terminal Descriptions
Symbol
fsclk
Parameter
Min
64
Typ
Max
Unit
kHz
kHz
ns
PCM clock frequency (Slave mode: input)
PCM clock frequency (GCI mode)
PCM_CLK low time
-
-
-
-
-
-
2048
fsclk
128
200
200
30
4096
tsclkl
-
-
-
-
tsclkh
PCM_CLK high time
ns
thsclksynch
tsusclksynch
Hold time from PCM_CLK low to PCM_SYNC high
Set-up time for PCM_SYNC high to PCM_CLK low
ns
30
ns
Delay time from PCM_SYNC or PCM_CLK
whichever is later, to valid PCM_OUT data (Long
Frame Sync only)
tdpout
-
-
-
-
-
-
20
20
20
ns
ns
ns
tdsclkhpout
tdpoutz
Delay time from CLK high to PCM_OUT valid data
Delay time from PCM_SYNC or PCM_CLK low,
whichever is later, to PCM_OUT data line high
impedance
tsupinsclkl
thpinsclkl
Set-up time for PCM_IN valid to CLK low
30
30
-
-
-
-
ns
ns
Hold time for PCM_CLK low to PCM_IN invalid
Table 11.9: PCM Slave Timing
fsclk
tsclkh
ttsclkl
PCM_CLK
t hsclksynch
t susclksynch
PCM_SYNC
tdpoutz
tdpout
MSB (LSB)
t dsclkhpout
tr ,t f
tdpoutz
PCM_OUT
PCM_IN
LSB (MSB)
t supinsclkl
t hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 11.26: PCM Slave Timing Long Frame Sync
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Device Terminal Descriptions
fsclk
tsclkh
ttsclkl
PCM_CLK
t susclksynch
t hsclksynch
PCM_SYNC
tdpoutz
tdpoutz
t dsclkhpout
MSB (LSB)
tr ,t f
PCM_OUT
PCM_IN
LSB (MSB)
t supinsclkl
t hpinsclkl
MSB (LSB)
LSB (MSB)
Figure 11.27: PCM Slave Timing Short Frame Sync
PCM_CLK and PCM_SYNC Generation
BlueCore4-Flash Plug-n-Go has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is
generating these signals by Direct Digital Synthesis (DDS) from BlueCore4-Flash Plug-n-Go internal 4MHz clock
(which is used in BlueCore2-External). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to
8kHz. The second is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a
greater range of frequencies to be generated with low jitter but consumes more power). This second method is
selected by setting bit 48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long
frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by
LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.
The Equation 11.8 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
CNT_RATE
f =
× 24MHz
CNT_LIMIT
Equation 11.8: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock
The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation 11.9:
PCM_CLK
f =
SYNC_LIMIT×8
Equation 11.9: PCM_SYNC Frequency Relative to PCM_CLK
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.
11.7.9 PCM Configuration
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 11.10 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 11.11. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e.,
first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz
PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT.
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Device Terminal Descriptions
Name
Bit Position Description
-
0
Set to 0
0 = master mode with internal generation of PCM_CLK and
PCM_SYNC.
SLAVE_MODE_EN
1
1 = slave mode requiring externally generated PCM_CLK
and PCM_SYNC.
0 = long frame sync (rising edge indicates start of frame).
1 = short frame sync (falling edge indicates start of frame).
Set to 0.
SHORT_SYNC_EN
-
2
3
0 = padding of 8 or 13-bit voice sample into a 16-bit slot by
inserting extra LSBs. When padding is selected with 13-bit
voice sample, the 3 padding bits are the audio gain setting;
with 8-bit sample the 8 padding bits are zeroes.
SIGN_EXTEND_EN
4
1 = sign-extension.
0 = MSB first of transmit and receive voice samples.
1 = LSB first of transmit and receive voice samples.
0 = drive PCM_OUT continuously.
LSB_FIRST_EN
5
6
1 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in the last bit of an active slot, assuming the next
slot is not active.
TX_TRISTATE_EN
0 = tri-state PCM_OUT immediately after falling edge of
PCM_CLK in last bit of an active slot, assuming the next slot
is also not active.
TX_TRISTATE_RISING_EDGE_EN
SYNC_SUPPRESS_EN
7
8
1 = tri-state PCM_OUT after rising edge of PCM_CLK.
0 = enable PCM_SYNC output when master.
1 = suppress PCM_SYNC whilst keeping PCM_CLK running.
Some CODECS utilise this to enter a low power state.
GCI_MODE_EN
MUTE_EN
9
1 = enable GCI mode
10
1 = force PCM_OUT to 0
0 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 4 MHz clock.
48M_PCM_CLK_GEN_EN
LONG_LENGTH_SYNC_EN
11
12
1 = set PCM_CLK and PCM_SYNC generation via DDS from
internal 48 MHz clock.
0 = set PCM_SYNC length to 8 PCM_CLK cycles.
1 = set length to 16 PCM_CLK cycles.
Only applies for long frame sync and with
48M_PCM_CLK_GEN_EN set to 1.
-
[20:16]
[22:21]
[26:23]
Set to 0b00000
Selects 128 (0b01), 256 (0b00), 512 (0b10) kHz PCM_CLK
frequency when master and 48M_PCM_CLK_GEN_EN (bit
11) is low.
MASTER_CLK_RATE
ACTIVE_SLOT
Default is 0001. Ignored by firmware.
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Device Terminal Descriptions
Name
Bit Position Description
Selects between 13 (0b00), 16 (0b01), 8 (0b10) bit sample
with 16 cycle slot duration or 8 (0b11) bit sample with 8 cycle
slot duration.
SAMPLE_FORMAT
[28:27]
Table 11.10: PSKEY_PCM_CONFIG32 Description
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Device Terminal Descriptions
Name
Bit Position Description
CNT_LIMIT
CNT_RATE
SYNC_LIMIT
[12:0]
[23:16]
[31:24]
Sets PCM_CLK counter limit
Sets PCM_CLK count rate
Sets PCM_SYNC division relative to PCM_CLK
Table 11.11: PSKEY_PCM_LOW_JITTER_CONFIG Description
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Device Terminal Descriptions
11.8
I/O Parallel Ports
Fifteen lines of programmable bi-directional input/outputs (I/O) are provided. PIO[11:8] and PIO[3:0] are powered from
VDD_PIO. PIO[7:4] are powered from VDD_PADS. AIO [2:0] are powered from VDD_MEM.
PIO lines can be configured through software to have either weak or strong pull-ups or pull-downs. All PIO lines are
configured as inputs with weak pull-downs at reset.
PIO[0] and PIO[1] are normally dedicated to RXEN and TXEN respectively, but they are available for general use.
Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or
PIO[2] can be configured as a request line for an external clock source. This is useful when the clock to
BlueCore4-Flash Plug-n-Go is provided from a system application specific integrated circuit (ASIC). Using
PSKEY_CLOCK_REQUEST_ENABLE (0x246), this terminal can be configured to be low when BlueCore4-Flash
Plug-n-Go is in Deep Sleep and high when a clock is required. The clock must be supplied within 4ms of the rising
edge of PIO[6] or PIO[2] to avoid losing timing accuracy in certain Bluetooth operating modes.
BlueCore4-Flash Plug-n-Go has three general purpose analogue interface pins, AIO[0], AIO[1] and AIO[2] also known
as the extended PIO lines. These are used to access internal circuitry and control signals. One pin is allocated to
decoupling for the on-chip band gap reference voltage; the other two may be configured to provide additional
functionality.
Auxiliary functions available via these pins include an 8-bit ADC and an 8-bit DAC. Typically the ADC is used for battery
voltage measurement. Signals selectable at these pins include the band gap reference voltage and a variety of clock
signals: 48, 24, 16, 8MHz and the XTAL clock frequency. When used with analogue signals, the voltage range is
constrained by the analogue supply voltage (1.8V). When configured to drive out digital level signals (e.g., clocks), the
output voltage level is determined by VDD_MEM (1.8V).
11.8.1 PIO Defaults
CSR cannot guarantee that these terminal functions remain the same. Refer to the software release note for the
implementation of these PIO lines, as they are firmware build-specific.
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Device Terminal Descriptions
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Device Terminal Descriptions
11.9
TCXO Enable OR Function
An OR function exists for clock enable signals from a host controller and BlueCore4-Flash Plug-n-Go where either
device can turn on the clock without having to wake up the other device. PIO[3] can be used as the host clock enables
input and PIO[2] can be used as the OR output with the TCXO enable signal from BlueCore4-Flash Plug-n-Go.
VDD
GSM System
TCXO
CLK IN
Enable
CLK REQ OUT
BlueCore System
CLK REQ IN/
PIO[3]
CLK REQ OUT/
CLK IN
PIO[2]
Figure 11.28: Example TCXO Enable OR Function
On reset and up to the time the PIO has been configured, PIO[2] will be tri-state. Therefore, the developer must ensure
that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that the
TCXO is oscillating at start up.
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Device Terminal Descriptions
11.10 RESET and RESETB
BlueCore4-Flash Plug-n-Go may be reset from several sources:
RESET or RESETB pins
Power on reset
A UART break character
Via a software configured watchdog timer
The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A reset
will be performed between 1.5ms and 4.0ms following RESET being active. It is recommended that RESET be applied
for a period greater than 5ms. The RESETB pin is the active low version of RESET and is OR'd on-chip with the active
high RESET, with either causing the reset function.
The power on reset occurs when the VDD_CORE supply falls below typically 1.5V and is released when VDD_CORE
rises above typically 1.6V.
At reset the digital I/O pins are set to inputs for bi-directional pins and outputs are tri-state. The PIOs have weak
pull-downs.
Following a reset, BlueCore4-Flash Plug-n-Go assumes the maximum XTAL_IN frequency, which ensures that the
internal clocks run at a safe (low) frequency until BlueCore4-Flash Plug-n-Go is configured for the actual XTAL_IN
frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore4-Flash Plug-n-Go free runs, again at a safe
frequency.
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Device Terminal Descriptions
11.10.1 Pin States on Reset
Table 11.12 shows the pin states of BlueCore4-Flash Plug-n-Go on reset.
Pin Name
PIO[11:0]
PCM_OUT
PCM_IN
State: BlueCore4-Flash Plug-n-Go
Input with weak pull-down
Tri-state with weak pull-down
Input with weak pull-down
Input with weak pull-down
Input with weak pull-down
Output tri-state with weak pull-up
Input with weak pull-down
Output tri-state with weak pull-up
Input with weak pull-down
Input with weak pull-down
Input with weak pull-down
Input with weak pull-up
PCM_SYNC
PCM_CLK
UART_TX
UART_RX
UART_RTS
UART_CTS
USB_DP
USB_DN
SPI_CSB
SPI_CLK
SPI_MOSI
SPI_MISO
AIO[2:0]
Input with weak pull-down
Input with weak pull-down
Output tri-state with weak pull-down
Output, driving low
RESET
Input with weak pull-down
Input with weak pull-up
RESETB
TEST_EN
AUX_DAC
RF_IN
Input with strong pull-down
High impedance
High impedance
XTAL_IN
High impedance, 250k to XTAL_OUT
High impedance, 250k to XTAL_IN
XTAL_OUT
Table 11.12: Pin States of BlueCore4-Flash Plug-n-Go on Reset
11.10.2 Status after Reset
The chip status after a reset is as follows:
Warm Reset: Baud rate and RAM data remain available
Cold Reset(1) : Baud rate and RAM data not available
(1)
A Cold Reset is either Power cycle, system reset (firmware fault code) or Reset signal. See section 11.10.
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Device Terminal Descriptions
11.11 Power Supply
11.11.1 Voltage Regulator (Plug-n-Go)
An on-chip linear voltage regulator can be used to power the 1.8V dependent supplies. It is advised that a smoothing
circuit using a 2.2µF low ESR capacitor and 2.2Ω resistor be placed on the output VDD_ANA.
In the Plug-n-Go package, an internal 2.2Ω resistor is provided between the regulator output VDD_ANA and
VDD_DIG.
The regulator is switched into a low power mode when the device is sent into Deep Sleep mode. When the on-chip
regulator is not required VDD_ANA is a 1.8V input and VREG_IN must be either open circuit or tied to VDD_ANA.
11.11.2 Sequencing
It is recommended that VDD_CORE, VDD_RADIO and VDD_ANA be powered at the same time. The order of
powering supplies for VDD_CORE, VDD_PIO, VDD_PADS and VDD_USB is not important. However, if VDD_CORE
is not present, all inputs have a weak pull-down irrespective of the reset state.
11.11.3 Sensitivity to Disturbances
CSR recommends if supplying BlueCore4-Flash Plug-n-Go from an external voltage source that VDD_ANA and
VDD_RADIO should have less than 10mV rms noise levels between 0 to 10MHz. In addition, avoid single tone
frequencies. CSR recommends a simple RC filter for VDD_CORE, as this reduces transients put back onto the power
supply rails.
The remaining supplies VDD_PIO, VDD_PADS and VDD_USB can be connected together with the VREG_IN to the
3.3V supply and simply decoupled.
The transient response of the regulator is also important. At the start of a packet, power consumption will jump to high
levels. See the average current consumption section. The regulator should have a response time of 20µs or less; it is
essential that the power rail recovers quickly.
11.11.4 VREG_EN Pin
The regulator enable pin, VREG_EN, can be used to enable and disable the BlueCore4-Flash Plug-n-Go device if the
on-chip regulator is being used. The pin is active high and has an internal weak pull-up to enable the regulator if
VREG_EN is not connected.
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Product Reliability Tests
12 Product Reliability Tests
Die
Test Conditions
Human Body Model
±200mA
Specification
JEDEC
Sample Size
ESD
36
Latch-up
Early Life
Hot Life Test
JEDEC
6
125°C
48 – 168 hours
1000 hours
240
125°C
320 (240 FITs)
Package
Test Conditions
(125°C 24 hours)
30°C/60%RH
-65°C to +150°C
121°C at 100% RH
130°C/85% RH
-55/125°C
Specification
Sample Size
Moisture Sensitivity Precon
JEDEC Level 3
192 hours five re-flow
simulation cycles
308
Temperature Cycling
AutoClave (Steam)
HAST
500 cycles
96 hours
77
77
77
77
77
96 hours
Thermal Shock
100 cycles
1000 hours
High Temperature Storage
150°C
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Product Reliability Tests for BlueCore4-Flash Plug-n-Go Automotive
13 Product Reliability Tests for BlueCore4-Flash Plug-n-Go
Automotive
13.1
AEC-Q100
The reliability tests in this section follow the tests outlined in the AEC-Q100 and were performed on BlueCore4-Flash
Plug-n-Go in VFBGA 10 x 10mm 96 I/O (lead-free solder balls). Samples are electrically tested at ambient
temperature.
This package qualification will (where moisture sensitivity preconditioning is required) use IPC/Jedec MSL3, i.e., the
finished product is allowed a maximum exposure to a ≤30°C/60%RH environment for 168 hours before mounting.
As part of CSR's automotive test program, customers will have access to the initial device reliability test report. They
will also have access to a quarterly reliability test report update for automotive parts.
Die
Test Conditions
Human Body Model
125°C VDDmax
Specification
JEDEC
Sample Size
24
ESD
Early Life
Hot Life Test
48 hours
2400
125°C VDDmax
1000 hours
90, 77, 77
Package
Test Conditions
Specification
Sample Size
Moisture
(125°C 24 hours)
Sensitivity
192 hours five reflow
simulation cycles
783
Precon
30°C/60%RH
JEDEC Level 3
Temperature Cycling
Autoclave (Steam)
Temperature Humidity Bias
Thermal Shock
High Temperature Storage
-65/150°C
121°C/100%RH
85°C/85%RH Vddmax
-55/125°C
500 cycles
96 hours
231 from Precon
231 from Precon
231 from Precon
77 from Precon
77
1000 hours
100 cycles
1000 hours
150°C
Other
Test Conditions
Sample Size
Bond Shear
Acid decapsulation of finished product
Acid decapsulation of finished product
Two reflow cycles
30 bonds
60 wires from Precon and
temperature cycling
Wire Pull
Solder Ball Shear
150 balls
Visual Inspection and
Dimensions
N/A
30 devices
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Application Schematic
14 Application Schematic
E N H S _ F L A
R E S E T
F 9
0
B 1
U O T A L X _ T
L 4
N I _ L A X T
N E _ S T T E
L 3
E 9
N I _ G E V R
L 7
S B U _
O
S D A
V D D
D V D _ P I
D V D _ P
L 1 0
A 3
E 1
N C
1
E S T B R E
A P D S S S V _
A P D S S S V _
A P D S S S V _
G 9
0
K 1
E 1 0
A 2
J 9
D 9
F 1
M
M E S _ V S
M
M E S _ V S
C O R E V S S _
0
C _ O D R E V D
D V D _ M E
D V D _ M E
D _ D V I D G
1 F 1
M
M
K 6
B 1
L 6
A
O
O
O
A _ N V S S
V _ C V S S
V _ C V S S
V _ C V S S
A R D I O S S V _
A R D I O S S V _
A R D I O S S V _
1
K 4
H 3
H 2
G 3
G 2
F 3
E 2
A 1
K 1
J 1
G 1
A _ N D A D V
L 5
H
T C M A B A L _
N U L B _ A V S S
N U L B _ A V S S
N U L B _ A V S S
D _ R V A D D I O
V D D _ B A L
E 3
F 1
N U
Figure 14.1: Application Circuit for Radio Characteristics Specification
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Package Dimensions
15 Package Dimensions
15.1
10 x 10 LFBGA 96-Ball 1.6mm Package
Top View
Bottom View
1
2
3
4
5
6
7
8
10 11
11 10
8
7
6
5
4
3
2
1
PX
X
Y
F
PY
A
B
C
D
E
F
G
H
J
A
B
C
D
E
F
4
E1 SE
E
G
H
J
K
L
K
e
L
G
SD
Øb 1
D
J
D1
H
0.1
Z
3
A3
A
A2
A1
Scale = 1mm
0.08
Z
SEATING PLANE
Z
2
1
2
3
4
5
Figure 15.1: BlueCore4-Flash Plug-n-Go 96-Ball LFBGA 1.6mm Package Dimensions
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RoHS Statement with a List of Banned Materials
16 RoHS Statement with a List of Banned Materials
16.1
RoHS Statement
BlueCore4-Flash Plug-n-Go where explicitly stated in this Data Sheet meets the requirements of Directive 2002/95/EC
of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS).
16.1.1 List of Banned Materials
The following banned substances are not present in BlueCore4-Flash Plug-n-Go which is compliant with RoHS:
Cadmium
Lead
Mercury
Hexavalent chromium
PBB (Polybrominated Bi-Phenyl)
PBDE (Polybrominated Diphenyl Ether)
In addition, BlueCore4-Flash Plug-n-Go is free from the following substances:
PVC (Poly Vinyl Chloride)
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Ordering Information
17 Ordering Information
17.1
BlueCore4-Flash Plug-n-Go
Package
Size
Interface Version
Order Number
Type
Shipment Method
96-Ball LFBGA
(Pb free)
UART and USB
10 x 10 x 1.6mm
Tape and reel
BC419143B-ANN-E4 (a)
(a)
Until BlueCore4-Flash Plug-n-Go reaches Production status order number is BC419143BES-ANN-E4.
Minimum Order Quantity
2kpcs taped and reeled
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Contact Information
18 Contact Information
CSR UK
CSR Denmark
Novi Science Park
Niels Jernes Vej 10
9220 Aalborg East
Denmark
CSR Japan
Churchill House
CSR KK
9F Kojimachi KS Square 5-3-3,
Kojimachi,
Cambridge Business Park
Cowley Road
Cambridge, CB4 0WZ
United Kingdom
Chiyoda-ku,
Tel: +45 72 200 380
Fax: +45 96 354 599
e-mail: sales@csr.com
Tokyo 102-0083
Tel: +44 (0) 1223 692 000
Fax: +44 (0) 1223 692 001
e-mail: sales@csr.com
Japan
Tel: +81-3-5276-2911
Fax: +81-3-5276-2915
e-mail: sales@csr.com
CSR Korea
2nd Floor, Hyo-Bong Building,
1364-1, Seocho-dong,
Seocho-gu,
CSR Taiwan
6th Floor, No. 407,
Rui Guang Road,
NeiHu,
CSR U.S.
2425 N. Central Expressway
Suite 1000
Richardson
Seoul 137-863,
Taipei 114,
Texas 75080
Korea
Taiwan, R.O.C.
USA
Tel: +82 2 3473 2372-5
Fax : +82 2 3473 2205
e-mail: sales@csr.com
Tel: +886 2 7721 5588
Fax: +886 2 7721 5589
e-mail: sales@csr.com
Tel: +1 (972) 238 2300
Fax: +1 (972) 231 1440
e-mail: sales@csr.com
To contact a CSR representative, go to www.csr.com/contacts.htm
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Document References
19 Document References
Document:
Reference
Specification of the Bluetooth system
Bluetooth Core Specification v2.0 + EDR
Bluetooth Test Document v2.0+EDR
Universal Serial Bus Specification
Selection of Flash Memory for Use with BlueCore
Selection of I2C EEPROMS for Use with BlueCore
v1.1, 22 February 2001 and v1.2, 05 November 2003
v2.0+EDR, 8 November 2004
v2.0.e.0, 5 November 2004
v1.1, 23 September 1998
CSR document bcore-an-001P
CSR document bcore-an-008P
16mm, 24mm, 32mm, 44mm and 56mm Embossed
Carrier Taping of Surface Mount Components for
Automatic Handling
IA-481-2
EIA-541
EIA-583
Packaging Material Standards for ESD Sensitive Items
Packaging Material Standards for Electrostatic Discharge
(ESD) Sensitive Items
IPC / JEDEC
J-STD-033
Standard for Handling, Packing, Shipping and Use of
Moisture / Reflow Sensitive Surface Mount Devices
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Terms and Definitions
20 Terms and Definitions
8DPSK
π/4 DQPSK
BlueCore®
Bluetooth™
ACL
8 phase Differential Phase Shift Keying
pi/4 rotated Differential Quaternary Phase Shift Keying
Group term for CSR’s range of Bluetooth chips
Set of technologies providing audio and data transfer over short-range radio connections
Asynchronous Connection-Less. Bluetooth data packet
Analogue to Digital Converter
Adaptive Frequency Hopping
Automatic Gain Control
ADC
AFH
AGC
A-law
ALU
Audio encoding standard
Arithmetic Logic Unit
API
Application Programming Interface
Application Specific Integrated Circuit
BlueCore™ Serial Protocol
Bit Error Rate. Used to measure the quality of a link
Built-In Self-Test
ASIC
BCSP
BER
BIST
BMC
Burst Mode Controller
CDMA
CMOS
CODEC
CQDDR
CRC
Code Division Multiple Access
Complementary Metal Oxide Semiconductor
Coder Decoder
Channel Quality Driven Data Rate
Cyclic Redundancy Check
CSB
Chip Select (Active Low)
CSR
Cambridge Silicon Radio
CTS
Clear to Send
CVSD
DAC
Continuous Variable Slope Delta Modulation
Digital to Analogue Converter
Decibels relative to 1mW
dBm
DDS
Direct Digital Synthesis
DC
Direct Current
DFU
Device Firmware Upgrade
DNL
Differential Linearity Error
DSP
Digital Signal Processor
EDR
Enhanced Data Rate
eSCO
ESR
Extended SCO
Equivalent Series Resistance
Finite Impulse Response
FIR
FSK
Frequency Shift Keying
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Terms and Definitions
GCI
General Circuit Interface
GFSK
GSM
HCI
Gaussian Frequency Shift Keying
Global System for Mobile communications
Host Controller Interface
I2C™
IF
Inter-Integrated Circuit
Intermediate Frequency
IIR
Infinite Impulse Response
Integral Linearity Error
INL
IQ Modulation
ISDN
ISM
In-Phase and Quadrature Modulation
Integrated Services Digital Network
Industrial, Scientific and Medical
DSP core for CSR’s range of chips
KiloSamples Per Second
Kalimba
ksps
L2CAP
LC
Logical Link Control and Adaptation Protocol (protocol layer)
Link Controller
LCD
Liquid Crystal Display
LFBGA
LMP
Low profile Fine Ball Grid Array
Link Manager Protocol
LNA
Low Noise Amplifier
LPF
Low Pass Filter
LSB
Least-Significant Bit
MCU
µ-law
MIPS
MMU
MISO
NOB
OHCI
PA
MicroController Unit
Audio Encoding Standard
Million Instructions Per Second
Memory Management Unit
Master In Serial Out
Number Of Bits
Open Host Controller Interface
Power Amplifier
PCM
PDA
Pulse Code Modulation. Refers to digital voice data
Personal Digital Assistant
Storage of BlueCore’s configuration values in non-volatile memory
Parallel Input Output
Persistent Store
PIO
PICS
pk-pk
PLL
Profile Implementation Confirmation Statement
Peak to Peak
Phase Lock Loop
ppm
parts per million
PS Key
RAM
REB
Persistent Store Key
Random Access Memory
Read enable (Active Low)
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Terms and Definitions
REF
Reference. Represents dimension for reference use only.
Radio Frequency
RF
RFCOMM
RISC
rms
Protocol layer providing serial port emulation over L2CAP
Reduced Instruction Set Computer
root mean squared
RSSI
RTS
Receive Signal Strength Indication
Ready To Send
RX
Receive or Receiver
SCO
SDK
Synchronous Connection-Oriented. Voice oriented Bluetooth packet
Software Development Kit
SDP
Service Discovery Protocol
SIG
Special Interest Group
SINAD
SNR
SPDIF
SPI
SIgnal to Noise ratio And Distortion
Signal to Noise Ratio
Sony and Philips Interface Specification
Serial Peripheral Interface
SSI
Synchronous Serial Interface
TBD
To Be Defined
TCXO
TX
Temperature Controlled crystal Oscillator
Transmit or Transmitter
UART
UHCI
USB
Universal Asynchronous Receiver Transmitter
Upper Host Control Interface
Universal Serial Bus or Upper Side Band (depending on context)
Voltage Controlled Oscillator
VCO
VFBGA
VM
Very Fine Ball Grid Array
Virtual Machine
W-CDMA
WEB
Wideband Code Division Multiple Access
Write Enable (Active Low)
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Document History
21 Document History
Date
Revision
Reason for Change
FEB 05
a
Original publication of this document. (CSR reference: BC419143B-ds-001Pa)
Amended System Architecture and Device Diagrams. Added Balun and Filter
block description. Minor amends. (CSR reference: BC419143B-ds-001Pb)
MAR 05
APR 05
b
c
Amended maximum baud rate to 3M baud and added additional data rates.
Electrical Characteristics and Radio Characteristics - Basic Data Rate updated
to reflect a radio performance temperature range of -40°C to +85°C.
Updated Auxilliary DAC in Description of Functional Blocks
Amendment to note (a) concerning specified output voltage in the Auxilliary DAC
table (Input/Output Terminal Characteristics) in Electrical Characteristics.
JUL 05
d
Amendment to note (g) concerning VREG_EN and VREG_IN in Linear
Regulator table in Electrical Characteristics.
Power Consumption moved from Radio Characteristics to Electrical
Characteristics section.
Changed title of Record of Changes to Document History; changed title of
Acronyms and Abbreviations to Terms and Definitions.
Updated references to VDD_MEM. See Electrical Characteristics, and
Sensitivity to Disturbances in Device Terminal Descriptions.
APR 06
e
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Product Data Sheet
BC419143B-DS-001Pe
April 2006
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