BB [ETC]
ST10F168 ERRATA SHEET REVISION BB ; ST10F168勘误表修订BB\n
| 型号： | BB |
| 厂家： | 
ETC |
| 描述： | ST10F168 ERRATA SHEET REVISION BB
|
| 文件： | 总2页 (文件大小：20K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ST10F168
16-Bit MCU With 256K Byte Flash and 8K Byte RAM Memories
ERRATA SHEET - REVISION BB
1 - DESCRIPTION
No problem will occur if the NMI pin is low (if
PWRDCFG = 0) or if all P2 pins used to exit from
power-down mode are at inactive level (if PWRD-
CFG = 1): the chip will normally enter powerdown
mode.
This Errata Sheet describes the functional and
electrical problems known.
The revision number BB can be found in the sec-
ond line printed on the ST10F168 package. It
looks like: XBB-XXXXXXX where "BB" identifies
the revision number.
Workaround:
Ensure that no instruction which writes to external
memory or an XPeripheral preceeds the PWRDN
instruction, otherwise insert e.g. a NOP instruction
in front of PWRDN. When a multiplexed bus with
memory tristate waitstate is used, the PWRDN
instruction should be executed from internal RAM
or XRAM.
2 - FUNCTIONAL PROBLEMS
The following malfunctions are known in this
device:
2.1 - ST_PWRDN.1 - Execution of PWRDN
Instruction
Summary of Remaining Functional Problems
Known on the ST10F168-BB
When instruction PWRDN is executed while pin
NMI is at a high level (if PWRDCFG bit is clear in
SYSCON register) or while at least one P2 pin
used to exit from power-down mode (if PWRD-
CFG bit is set in SYSCON register) is at the active
level, power down mode should not be entered,
and the PWRDN instruction should be ignored.
Name
Short Description
ST_PWRDN.1
Powerdown mode not ignored
3 - DEVIATIONS FROM DC/AC PRELIMINARY
SPECIFICATION
However, under the conditions described below,
the PWRDN instruction may not be ignored, and
no further instructions are fetched from external
memory, i.e. the CPU is in a quasi-idle state. This
problem will only occur in the following situations:
DC parameters
After characterization, the DC parameter of ALE
active current has been changed: I
from 500µA to 600µA.
change
ALEH
Note on on-chip oscillator
a) the instructions following the PWRDN instruc-
tion are located in an external memory, and a
multiplexed bus configuration with memory
tristate waitstate (bit MT-TCx=0) is used.
The XTAL2 output is not designed to provide a
valid signal when XTAL1 is supplied by an
external clock signal. It may happen, if the
external clock signal is not perfectly symetrical
b) the instruction preceeding the PWRDN instruc-
tion writes to external memory or an XPeripheral
(XRAM, CAN), and the instructions following the
PWRDN instruction are located in external mem-
ory. In this case, the problem will occur for any bus
configuration.
and centered on V / 2, that XTAL2 signal is not
DD
equal to XTAL1. This is due to the design of the
oscillator, which has a auto-adaptation gain
control dedicated to external crystal.
If an external clock signal is directly provided on
XTAL1 pin, then leave XTAL2 pin disconnected to
achieve the lowest consumption of the on-chip
oscillator.
Note The on-chip peripherals are still working
correctly, in particular the Watchdog Timer,
if not disabled, will reset the device upon
an overflow. Interrupts and PEC transfers,
however, can not be processed. In case
NMI is asserted low while the device is in
this quasi-idle state, power-down mode is
entered.
4 - ERRATA SHEET VERSION INFORMATION
This document was released on the 23rd of
May 2000. It reflects the current silicon status of
the ST10F168BB revision and is only valid for this.
May 2000
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This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST10F168
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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© 2000 STMicroelectronics - All Rights Reserved
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