AT29BV040A-25CI [ETC]
EEPROM|FLASH|512KX8|CMOS|BGA|32PIN|PLASTIC ;
| 型号： | AT29BV040A-25CI |
| 厂家： | 
ETC |
| 描述： | EEPROM|FLASH|512KX8|CMOS|BGA|32PIN|PLASTIC 内存集成电路 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总15页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Single Supply Voltage, Range 2.7V to 3.6V
• Single Supply for Read and Write
• Software Protected Programming
• Fast Read Access Time – 200 ns
• Low Power Dissipation
– 15 mA Active Current
– 40 µA CMOS Standby Current
• Sector Program Operation
– Single Cycle Reprogram (Erase and Program)
– 2048 Sectors (256 Bytes/Sector)
4-megabit
(512K x 8)
Single 2.7-volt
Battery-Voltage™
Flash Memory
– Internal Address and Data Latches for 256 Bytes
• Two 16K Bytes Boot Blocks with Lockout
• Fast Sector Program Cycle Time – 20 ms Max.
• Internal Program Control and Timer
• DATA Polling for End of Program Detection
• Minimum Endurance 10,000 Cycles
• CMOS and TTL Compatible Inputs and Outputs
• Commercial and Industrial Temperature Ranges
Description
The AT29BV040A is a 3-volt-only in-system Flash Programmable and Erasable Read
Only Memory (PEROM). Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS EEPROM technology,
the device offers access times to 200 ns, and a low 54 mW power dissipation. When
the device is deselected, the CMOS standby current is less than 40 µA. The device
AT29BV040A
Pin Configurations
Pin Name
A0 - A18
CE
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
CBGA
Top View
OE
WE
1
2
3
4
I/O0 - I/O7
NC
A
B
C
D
E
F
A7 A18 A14 A13
A6 A16 A17 A8
A5 A15 WE A9
A4 A12 VCC A11
A3 I/O0 I/O3 I/O7
A2 I/O1 I/O4 CE
A1 I/O2 I/O5 A10
A0 GND I/O6 OE
TSOP Top View
Type 1
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
A8
3
A13
A14
A17
WE
VCC
A18
A16
A15
A12
A7
4
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
5
6
7
8
9
G
H
10
11
12
13
14
15
16
A6
A1
A5
A2
Rev. 0383F–FLASH–05/02
A4
A3
endurance is such that any sector can be written to in excess of 10,000 times. The pro-
gramming algorithm is compatible with other devices in Atmel’s 2.7-volt-only Flash
memories.
To allow for simple in-system reprogrammability, the AT29BV040A does not require
high input voltages for programming. The device can be operated with a single 2.7V to
3.6V supply. Reading data out of the device is similar to reading from an EPROM.
Reprogramming the AT29BV040A is performed on a sector basis; 256 bytes of data are
loaded into the device and then simultaneously programmed.
During a reprogram cycle, the address locations and 256 bytes of data are captured at
microprocessor speed and internally latched, freeing the address and data bus for other
operations. Following the initiation of a program cycle, the device will automatically
erase the sector and then program the latched data using an internal control timer. The
end of a program cycle can be detected by DATA polling of I/O7. Once the end of a pro-
gram cycle has been detected, a new access for a read or program can begin.
Block Diagram
Device Operation
READ: The AT29BV040A is accessed like an EPROM. When CE and OE are low and
WE is high, the data stored at the memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high impedance state whenever CE
or OE is high. This dual-line control gives designers flexibility in preventing bus
contention.
SOFTWARE DATA PROTECTION PROGRAMMING: The AT29BV040 has 2048 indi-
vidual sectors, each 256 bytes. Using the software data protection feature, byte loads
are used to enter the 256 bytes of a sector to be programmed. The AT29BV040A can
only be programmed or reprogrammed using the software data protection feature. The
device is programmed on a sector basis. If a byte of data within the sector is to be
changed, data for the entire 256-byte sector must be loaded into the device. The
AT29BV040A automatically does a sector erase prior to loading the data into the sector.
An erase command is not required.
Software data protection protects the device from inadvertent programming. A series of
three program commands to specific addresses with specific data must be presented to
the device before programming may occur. The same three program commands must
begin each program operation. All software program commands must obey the sector
program timing specifications. Power transitions will not reset the software data protec-
tion feature, however the software feature will guard against inadvertent program cycles
during power transitions.
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AT29BV040A
0383F–FLASH–05/02
AT29BV040A
Any attempt to write to the device without the 3-byte command sequence will start the
internal write timers. No data will be written to the device; however, for the duration of
tWC, a read operation will effectively be a polling operation.
After the software data protection’s 3-byte command code is given, a byte load is per-
formed by applying a low pulse on the WE or CE input with CE or WE low (respectively)
and OE high. The address is latched on the falling edge of CE or WE, whichever occurs
last. The data is latched by the first rising edge of CE or WE.
The 256 bytes of data must be loaded into each sector. Any byte that is not loaded dur-
ing the programming of its sector will be indeterminate. Once the bytes of a sector are
loaded into the device, they are simultaneously programmed during the internal pro-
gramming period. After the first data byte has been loaded into the device, successive
bytes are entered in the same manner. Each new byte to be programmed must have its
high-to-low transition on WE (or CE) within 150 µs of the low-to-high transition of WE (or
CE) of the preceding byte. If a high-to-low transition is not detected within 150 µs of the
last low-to-high transition, the load period will end and the internal programming period
will start. A8 to A18 specify the sector address. The sector address must be valid during
each high-to-low transition of WE (or CE). A0 to A7 specify the byte address within the
sector. The bytes may be loaded in any order; sequential loading is not required.
HARDWARE DATA PROTECTION: Hardware features protect against inadvertent
programs to the AT29BV040A in the following ways: (a) VCC sense – if VCC is below
1.8V (typical), the program function is inhibited; (b) VCC power on delay – once VCC has
reached the VCC sense level, the device will automatically time out 10 ms (typical)
before programming; (c) Program inhibit – holding any one of OE low, CE high or WE
high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a program cycle.
INPUT LEVELS: While operating with a 2.7V to 3.6V power supply, the address inputs
and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely
affecting the operation of the device. The I/O lines can only be driven from 0 to VCC
0.6V.
+
PRODUCT IDENTIFICATION: The product identification mode identifies the device
and manufacturer as Atmel. It may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct
programming algorithm for the Atmel product. In addition, users may wish to use the
software product identification mode to identify the part (i.e. using the device code), and
have the system software use the appropriate sector size for program operations. In this
manner, the user can have a common board design for 256K to 4-megabit densities
and, with each density’s sector size in a memory map, have the system software apply
the appropriate sector size.
For details, see Operating Modes (for hardware operation) or Software Product Identifi-
cation. The manufacturer and device code is the same for both modes.
DATA POLLING: The AT29BV040A features DATA polling to indicate the end of a
program cycle. During a program cycle an attempted read of the last byte loaded will
result in the complement of the loaded data on I/O7. Once the program cycle has been
completed, true data is valid on all outputs and the next cycle may begin. DATA polling
may begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT29BV040A provides another method
for determining the end of a program or erase cycle. During a program or erase opera-
tion, successive attempts to read data from the device will result in I/O6 toggling
between one and zero. Once the program cycle has completed, I/O6 will stop toggling
3
0383F–FLASH–05/02
and valid data will be read. Examining the toggle bit may begin at any time during a pro-
gram cycle.
OPTIONAL CHIP ERASE MODES: The entire device may be erased by using a
6-byte software code. Please see Software Chip Erase application note for details.
BOOT BLOCK PROGRAMMING LOCKOUT: The AT29BV040A has two designated
memory blocks that have a programming lockout feature. This feature prevents pro-
gramming of data in the designated block once the feature has been enabled. Each of
these blocks consists of 16K bytes; the programming lockout feature can be set inde-
pendently for either block. While the lockout feature does not have to be activated, it can
be activated for either or both blocks.
These two 16K memory sections are referred to as boot blocks. Secure code which will
bring up a system can be contained in a boot block. The AT29BV040A blocks are
located in the first 16K bytes of memory and the last 16K bytes of memory. The boot
block programming lockout feature can therefore support systems that boot from the
lower addresses of memory or the higher addresses. Once the programming lockout
feature has been activated, the data in that block can no longer be erased or pro-
grammed; data in other memory locations can still be changed through the regular
programming methods. To activate the lockout feature, a series of seven program com-
mands to specific addresses with specific data must be performed. Please see Boot
Block Lockout Feature Enable Algorithm.
If the boot block lockout feature has been activated on either block, the chip erase func-
tion will be disabled.
BOOT BLOCK LOCKOUT DETECTION: A software method is available to determine
whether programming of either boot block section is locked out. See Software Product
Identification Entry and Exit sections. When the device is in the software product identifi-
cation mode, a read from location 00002H will show if programming the lower address
boot block is locked out while reading location 7FFF2H will do so for the upper boot
block. If the data is FE, the corresponding block can be programmed; if the data is FF,
the program lockout feature has been activated and the corresponding block cannot be
programmed. The software product identification exit mode should be used to return to
standard operation.
Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
Voltage on A9 (including NC Pins)
with Respect to Ground ...................................-0.6V to +13.5V
4
AT29BV040A
0383F–FLASH–05/02
AT29BV040A
DC and AC Operating Range
AT29BV040A-20
0°C - 70°C
AT29BV040A-25
0°C - 70°C
Operating
Temperature (Case)
Com.
Ind.
-40°C - 85°C
2.7V to 3.6V
-40°C - 85°C
2.7V to 3.6V
V
CC Power Supply(1)
Note:
1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an oper-
ational mode is started.
Operating Modes
Mode
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X(1)
X
WE
VIH
VIL
X
Ai
Ai
Ai
X
I/O
Read
DOUT
DIN
Program(2)
Standby/Write Inhibit
Program Inhibit
Program Inhibit
Output Disable
Product Identification
Hardware
High Z
VIH
X
X
VIL
VIH
X
X
High Z
VIL
VIL
VIH
A1 - A18 = VIL, A9 = VH(3), A0 = VIL
A1 - A18 = VIL, A9 = VH(3), A0 = VIH
A0 = VIL, A1 - A18 = VIL
Manufacturer Code(4)
Device Code(4)
Software(5)
Manufacturer Code(4)
Device Code(4)
A0 = VIH, A1 - A18 = VIL
Notes: 1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V 0.5V.
4. Manufacturer Code is 1F. The Device Code is C4.
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
Min
Max
1
Units
µA
µA
µA
µA
mA
mA
V
ILI
Input Load Current
Output Leakage Current
VCC Standby Current CMOS
VIN = 0V to VCC
VI/O = 0V to VCC
CE = VCC - 0.3V to VCC
ILO
1
ISB1
Com.
Ind.
40
50
1
ISB2
ICC
VCC Standby Current TTL
VCC Active Current
Input Low Voltage
CE = 2.0V to VCC
f = 5 MHz; IOUT = 0 mA; VCC = 3.6V
15
0.6
VIL
VIH
VOL
VOH
Input High Voltage
Output Low Voltage
Output High Voltage
2.0
2.4
V
IOL = 1.6 mA; VCC = 3.0V
IOH = -100 µA; VCC = 3.0V
0.45
V
V
5
0383F–FLASH–05/02
AC Read Characteristics
AT29BV040A-20
AT29BV040A-25
Symbol
Parameter
Min
Max
200
200
80
Min
Max
250
250
120
60
Units
ns
tACC
Address to Output Delay
CE to Output Delay
OE to Output Delay
CE or OE to Output Float
(1)
tCE
ns
(6)
tOE
0
0
0
0
0
0
ns
(7)(8)
tDF
50
ns
tOH
Output Hold from OE, CE or Address,
whichever occurred first
ns
AC Read Waveforms
Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC
6. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC
.
.
7. tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
8. This parameter is characterized and is not 100% tested.
6
AT29BV040A
0383F–FLASH–05/02
AT29BV040A
Input Test Waveforms and Measurement Level
tR, tF < 5 ns
Output Test Load
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Symbol
Typ
Max
6
Units
pF
Conditions
VIN = 0V
CIN
4
COUT
8
12
pF
VOUT = 0V
Note:
1. These parameters are characterized and not 100% tested.
7
0383F–FLASH–05/02
AC Byte Load Characteristics
Symbol
tAS, tOES
tAH
Parameter
Min
10
Max
Units
ns
Address, OE Set-up Time
Address Hold Time
100
0
ns
tCS
Chip Select Set-up Time
Chip Select Hold Time
Write Pulse Width (WE or CE)
Data Set-up Time
ns
tCH
0
ns
tWP
200
100
10
ns
tDS
ns
tDH, tOEH
tWPH
Data, OE Hold Time
Write Pulse Width High
ns
200
ns
AC Byte Load Waveforms(1)(2)
WE Controlled
CE Controlled
8
AT29BV040A
0383F–FLASH–05/02
AT29BV040A
Program Cycle Characteristics
Symbol
Parameter
Min
Max
Units
ms
ns
tWC
Write Cycle Time
Address Set-up Time
Address Hold Time
Data Set-up Time
Data Hold Time
20
tAS
10
100
100
10
tAH
ns
tDS
ns
tDH
ns
tWP
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
200
ns
tBLC
tWPH
150
µs
200
ns
Software Protected Program Waveform
Notes: 1. OE must be high when WE and CE are both low.
2. A8 through A18 must specify the sector address during each high to low transition of WE (or CE) after the software code has
been entered.
3. All bytes that are not loaded within the sector being programmed will be indeterminate.
Programming Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
TO
ADDRESS 5555
WRITES ENABLED
ENTER DATA
LOAD DATA
TO
SECTOR (256 BYTES)(3) PROTECT STATE(2)
Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex).
2. Data Protect state will be re-activated at end of program cycle.
3. 256 bytes of data MUST BE loaded.
9
0383F–FLASH–05/02
Data Polling Characteristics(1)(2)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
OE Hold Time
10
ns
OE to Output Delay(2)
Write Recovery Time
ns
tWR
0
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
Toggle Bit Characteristics(1)
Symbol
Parameter
Min
10
Typ
Max
Units
ns
tDH
Data Hold Time
tOEH
tOE
tOEHP
tWR
OE Hold Time
10
ns
OE to Output Delay(2)
OE High Pulse
ns
150
0
ns
Write Recovery Time
ns
Notes: 1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(4)
Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit.
3. Beginning and ending state of I/O6 will vary.
4. Any address location may be used but the address should not vary.
10
AT29BV040A
0383F–FLASH–05/02
AT29BV040A
Software Product Identification Entry(1)
Boot Block Lockout
Feature Enable Algorithm(1)
LOAD DATA AA
TO
LOAD DATA AA
ADDRESS 5555
TO
ADDRESS 5555
LOAD DATA 55
TO
LOAD DATA 55
TO
ADDRESS 2AAA
ADDRESS 2AAA
LOAD DATA 90
TO
LOAD DATA 80
TO
ADDRESS 5555
ADDRESS 5555
PAUSE 20 mS
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)
LOAD DATA AA
TO
ADDRESS 5555
Software Product Identification Exit(1)
LOAD DATA 55
TO
LOAD DATA AA
ADDRESS 2AAA
TO
ADDRESS 5555
LOAD DATA 40
TO
LOAD DATA 55
TO
ADDRESS 5555
ADDRESS 2AAA
LOAD DATA 00
TO
ADDRESS 00000H(2)
LOAD DATA FF
TO
LOAD DATA F0
TO
ADDRESS 7FFFFH(3)
ADDRESS 5555
PAUSE 20 mS
PAUSE 20 mS
PAUSE 20 mS
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
Notes: 1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Lockout feature set on lower address boot block.
3. Lockout feature set on higher address boot block.
2. A1 - A18 = VIL.
Manufacturer Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if
powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code is 1F. The Device Code is C4.
11
0383F–FLASH–05/02
Ordering Information
I
Active
15
CC (mA)
tACC
(ns)
Standby
Ordering Code
Package
Operation Range
200
0.04
0.05
0.04
0.05
AT29BV040A-20CC
AT29BV040A-20TC
32C1
32T
Commercial
(0° to 70°C)
15
15
15
AT29BV040A-20CI
AT29BV040A-20TI
32C1
32T
Industrial
(-40° to 85°C)
250
AT29BV040A-25CC
AT29BV040A-25TC
32C1
32T
Commercial
(0° to 70°C)
AT29BV040A-25CI
AT29BV040A-25TI
32C1
32T
Industrial
(-40° to 85°C)
Package Type
32C1
32T
32-ball, Plastic Chip-scale Ball Grid Array Package (CBGA)
32-lead, Thin Small Outline Package (TSOP)
12
AT29BV040A
0383F–FLASH–05/02
AT29BV040A
Packaging Information
32C1 – CBGA
E
A1 Ball ID
D
A1
Top View
A
1.30 REF
E1
Side View
A1 Ball Corner
e
2.20 REF
A
COMMON DIMENSIONS
(Unit of Measure = mm)
B
C
D
E
F
MIN
MAX
NOM
5.00
NOTE
SYMBOL
D1
E
4.90
5.10
E1
D
2.4 TYP
10.00
5.6 TYP
–
G
H
9.90
10.10
D1
A
e
–
1.20
–
4
3
2
1
A1
e
0.25
–
Øb
0.80 BSC
0.40 TYP
Bottom View
b
2/13/02
DRAWING NO. REV.
32C1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32C1, 32-ball (4 x 8 Array), 0.80 mm Pitch, 5.0 x 10.0 x 1.20 mm
Plastic Chip-scale Ball Grid Array Package (CBGA)
A
R
13
0383F–FLASH–05/02
32T – TSOP
PIN 1
0º ~ 8º
c
Pin 1 Identifier
D1
D
L
b
L1
e
A2
E
GAGE PLANE
A
SEATING PLANE
COMMON DIMENSIONS
(Unit of Measure = mm)
A1
MIN
–
MAX
1.20
0.15
1.05
20.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
19.80
18.30
7.90
0.50
–
1.00
Notes:
1. This package conforms to JEDEC reference MO-142, Variation BD.
2. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side.
3. Lead coplanarity is 0.10 mm maximum.
20.00
18.40
8.00
D1
E
18.50 Note 2
8.10
0.70
Note 2
L
0.60
L1
b
0.25 BASIC
0.22
0.17
0.10
0.27
0.21
c
–
e
0.50 BASIC
10/18/01
DRAWING NO. REV.
32T
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline
Package, Type I (TSOP)
B
R
14
AT29BV040A
0383F–FLASH–05/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Microcontrollers
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San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
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FAX (33) 2-40-18-19-60
Asia
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TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
ASIC/ASSP/Smart Cards
Zone Industrielle
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Japan
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
FAX 1(719) 540-1759
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
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相关型号：
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Flash, 512KX8, 350ns, PBGA32, 5 X 10 MM, 1.20 MM HEIGHT, 0.80 MM PITCH, PLASTIC, CSBGA-32
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AT29BV040A-35CI
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