AT25HP512CI-10CI-2.7 [ETC]
EEPROM ; EEPROM\n
| 型号： | AT25HP512CI-10CI-2.7 |
| 厂家： | 
ETC |
| 描述： | EEPROM
|
| 文件： | 总21页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• 128-byte Page Mode Only for Write Operations
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• 10 MHz (5V), 5MHz (2.7V) and 2 MHz (1.8V) Clock Rate
• Block Write Protection
• Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for
both Hardware and Software Data Protection
• High Reliability
– Endurance: 100K Write Cycles
– Data Retention: >40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 16-lead JEDEC SOIC and 8-lead Leadless Array Package
SPI Serial
EEPROMs
256K (32,768 x 8)
512K (65,536 x 8)
Description
The AT25HP256/512 provides 262,144/524,288 bits of serial electrically erasable pro-
grammable read only memory (EEPROM) organized as 32,768/65,536 words of 8-bits
each. The device is optimized for use in many industrial and commercial applications
where high-speed, low-power, and low-voltage operation are essential. The
AT25HP256/512 is available in a space saving 8-lead PDIP (AT25HP256/512), 8-lead
EIAJ SOIC (AT25HP256), 16-lead JEDEC SOIC (AT25HP512) and 8-lead Leadless
AT25HP256
AT25HP512
(continued)
Pin Configurations
Pin Name
Function
CS
Chip Select
16-lead SOIC
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
CS
SO
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
HOLD
NC
SO
NC
GND
VCC
WP
NC
NC
NC
NC
Power Supply
Write Protect
NC
NC
WP
GND
SCK
SI
HOLD
Suspends Serial Input
8-lead Leadless Array
8-lead SOIC
8-lead PDIP
VCC
HOLD
SCK
SI
8
7
6
5
1
2
3
4
CS
1
2
8
7
VCC
CS
SO
1
8
7
VCC
CS
SO
2
HOLD
SCK
SI
SO
HOLD
SCK
SI
WP
GND
3
4
6
5
3
6
5
WP
WP
GND
4
GND
Bottom View
Rev. 1113G–SEEPR–08/02
Array (AT25HP256/512) packages. In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.
The AT25HP256/512 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All programming cycles are completely self-timed, and no
separate ERASE cycle is required before WRITE.
BLOCK WRITE protection is enabled by programming the status register with top ¼, top ½ or entire array of write protec-
tion. Separate program enable and program disable instructions are provided for additional data protection. Hardware data
protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin may
be used to suspend any serial communication without resetting the serial sequence.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other condi-
tions beyond those indicated in the operational sec-
tions of this specification is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground .....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
32,768/65,536x8
2
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max
8
Units
pF
Conditions
VOUT = 0V
VIN = 0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
AC = 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
T
Symbol
VCC1
VCC2
VCC3
ICC1
ICC2
ISB1
Parameter
Test Condition
Min
1.8
2.7
4.5
Typ
Max
3.6
Units
V
Supply Voltage
Supply Voltage
5.5
V
Supply Voltage
5.5
V
Supply Current
Supply Current
Standby Current
Standby Current
Standby Current
Input Leakage
VCC = 5.0V at 5 MHz, SO = Open Read
VCC = 5.0V at 5 MHz, SO = Open Write
VCC = 1.8V, CS = VCC
6.0
4.0
0.1
0.2
2.0
10.0
7.0
mA
mA
µA
µA
µA
µA
µA
V
2.0
ISB2
VCC = 2.7V, CS = VCC
2.0
ISB3
VCC = 5.0V, CS = VCC
5.0
IIL
VIN = 0V to VCC
-3.0
-3.0
3.0
IOL
Output Leakage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
VIN = 0V to VCC, TAC = 0°C to 70°C
3.0
(1)
VIL
-0.6
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
VCC x 0.7
V
VOL1
VOH1
VOL2
VOH2
IOL = 3.0 mA
4.5V ≤ VCC ≤ 5.5V
V
IOH = -1.6 mA
VCC - 0.8
VCC - 0.2
V
IOL = 0.15 mA
1.8V ≤ VCC ≤ 3.6V
0.2
V
IOH = -100 µA
V
Note:
1. VIL and VIH max are reference only and are not tested.
3
1113G–SEEPR–08/02
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
10
5
2
fSCK
SCK Clock Frequency
MHz
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2
tRI
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
CS High Time
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
2
2
2
tFI
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
40
80
200
tWH
tWL
tCS
tCSS
tCSH
tSU
tH
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
40
80
200
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250
CS Setup Time
CS Hold Time
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
50
100
250
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
12
20
50
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
10
20
50
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
25
50
100
tHD
tCD
tV
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
25
50
100
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
40
80
200
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
tHO
Output Hold Time
4
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = As Specified,
CL = 1 TTL Gate and 30 pF (unless otherwise noted).
Symbol
Parameter
Voltage
Min
Max
Units
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
0
0
0
100
200
300
tLZ
Hold to Output Low Z
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
200
300
tHZ
Hold to Output High Z
Output Disable Time
Write Cycle Time
ns
ns
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
100
100
250
tDIS
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
10
10
10
tWC
ms
4.5 - 5.5
2.7 - 5.5
1.8 - 5.5
Endurance(1)
5.0V, 25°C, Page Mode
100K
Write Cycles
Note:
1. This parameter is characterized and is not 100% tested.
5
1113G–SEEPR–08/02
Serial Interface
Description
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25HP256/512
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25HP256/512 has separate pins designated for
data transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25HP256/512, and the serial output pin (SO) will remain in a high impedance state
until the falling edge of CS is detected again. This will reinitialize the serial
communication.
CHIP SELECT: The AT25HP256/512 is selected when the CS pin is low. When the
device is not selected, data will not be accepted via the SI pin, and the serial output pin
(SO) will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the
AT25HP256/512. When the device is selected and a serial sequence is underway,
HOLD can be used to pause the serial communication with the master device without
resetting the serial sequence. To pause, the HOLD pin must be brought low while the
SCK pin is low. To resume serial communication, the HOLD pin is brought high while the
SCK pin is low (SCK may still toggle during HOLD). Inputs to the SI pin will be ignored
while the SO pin is in the high impedance state.
WRITE PROTECT: The write protect pin (WP) will allow normal read/write operations
when held high. When the WP pin is brought low and WPEN bit is “1”, all write opera-
tions to the status register are inhibited. WP going low while CS is still low will interrupt a
write to the status register. If the internal write cycle has already been initiated, WP
going low will have no effect on any write operation to the status register. The WP pin
function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25HP256/512 in a system with the WP pin tied to ground and still
be able to write to the status register. All WP pin functions are enabled when the WPEN
bit is set to “1”.
6
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
SPI Serial Interface
Functional Description
AT25HP256/512
7
1113G–SEEPR–08/02
The AT25HP256/512 is designed to interface directly with the synchronous serial
peripheral interface (SPI) of the 6800 type series of microcontrollers.
The AT25HP256/512 utilizes an 8-bit instruction register. The list of instructions and
their operation codes are contained in Table 1. All instructions, addresses, and data are
transferred with the MSB first and start with a high-to-low CS transition.
Table 1. Instruction Set for the AT25HP256/512
Instruction Name
WREN
Instruction Format
0000 X110
Operation
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Memory Array
Write Data to Memory Array
WRDI
0000 X100
RDSR
0000 X101
WRSR
0000 X001
READ
0000 X011
WRITE
0000 X010
WRITE ENABLE (WREN): The device will power up in the write disable state when VCC
is applied. All programming instructions must therefore be preceded by a Write Enable
instruction.
WRITE DISABLE (WRDI): To protect the device against inadvertent writes, the Write
Disable instruction disables all programming modes. The WRDI instruction is indepen-
dent of the status of the WP pin.
READ STATUS REGISTER (RDSR): The Read Status Register instruction provides
access to the status register. The READY/BUSY and Write Enable status of the device
can be determined by the RDSR instruction. Similarly, the Block Write Protection bits
indicate the extent of protection employed. These bits are set by using the WRSR
instruction.
Table 2. Status Register Format
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WPEN
X
X
X
BP1
BP0
WEN
RDY
8
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
Table 3. Read Status Register Bit Definition
Bit
Definition
Bit 0 = 0 (RDY) indicates the device is READY. Bit 0 = 1 indicates the write
cycle is in progress.
Bit 0 (RDY)
Bit 1= 0 indicates the device is not WRITE ENABLED. Bit 1 = 1 indicates the
device is WRITE ENABLED.
Bit 1 (WEN)
Bit 2 (BP0)
Bit 3 (BP1)
See Table 4.
See Table 4.
Bits 4-6 are 0s when device is not in an internal write cycle.
Bit 7 (WPEN) See Table 5.
Bits 0-7 are 1s during an internal write cycle.
WRITE STATUS REGISTER (WRSR): The WRSR instruction allows the user to select
one of four levels of protection. The AT25HP256/512 is divided into four array seg-
ments. Top quarter (1/4), top half (1/2), or all of the memory segments can be protected.
Any of the data within any selected segment will therefore be READ only. The block
write protection levels and corresponding status register control bits are shown in Table
4.
The three bits, BP0, BP1, and WPEN are nonvolatile cells that have the same properties
and functions as the regular memory cells (e.g. WREN, tWC, RDSR).
Table 4. Block Write Protect Bits
Status Register Bits
BP1 BP0
Array Addresses Protected
AT25HP256/512
Level
0
0
0
1
1
0
1
0
1
None
1(1/4)
2(1/2)
3(All)
6000 - 7FFF/C000 - FFFF
4000 - 7FFF/8000 - FFFF
0000 - 7FFF/0000 - FFFF
The WRSR instruction also allows the user to enable or disable the write protect (WP)
pin through the use of the Write Protect Enable (WPEN) bit. Hardware write protection is
enabled when the WP pin is low and the WPEN bit is “1”. Hardware write protection is
disabled when either the WP pin is high or the WPEN bit is “0.” When the device is hard-
ware write protected, writes to the Status Register, including the Block Protect bits and
the WPEN bit, and the block-protected sections in the memory array are disabled.
Writes are only allowed to sections of the memory which are not block-protected.
NOTE: When the WPEN bit is hardware write protected, it cannot be changed back to
“0”, as long as the WP pin is held low.
Table 5. WPEN Operation
WPEN
WP
X
WEN
ProtectedBlocks
Protected
UnprotectedBlocks
Protected
Status Register
Protected
0
0
1
0
1
0
X
Protected
Writable
Writable
Low
Protected
Protected
Protected
9
1113G–SEEPR–08/02
Table 5. WPEN Operation
WPEN
WP
WEN
ProtectedBlocks
Protected
UnprotectedBlocks
Writable
Status Register
Protected
1
X
X
Low
High
High
1
0
1
Protected
Protected
Protected
Protected
Writable
Writable
READ SEQUENCE (READ): Reading the AT25HP256/512 via the SO (Serial Output)
pin requires the following sequence. After the CS line is pulled low to select a device,
the READ op-code is transmitted via the SI line followed by the byte address to be read
(Refer to Table 6). Upon completion, any data on the SI line will be ignored. The data
(D7-D0) at the specified address is then shifted out onto the SO line. If only one byte is
to be read, the CS line should be driven high after the data comes out. The READ
sequence can be continued since the byte address is automatically incremented and
data will continue to be shifted out. When the highest address is reached, the address
counter will roll over to the lowest address allowing the entire memory to be read in one
continuous READ cycle.
WRITE SEQUENCE (WRITE): In order to program the AT25HP256/512, two separate
instructions must be executed. First, the device must be write enabled via the Write
Enable (WREN) Instruction. Then a Write (WRITE) Instruction may be executed. Also,
the address of the memory location(s) to be programmed must be outside the protected
address field location selected by the Block Write Protection Level. During an internal
write cycle, all commands will be ignored except the RDSR instruction.
A Write Instruction requires the following sequence. After the CS line is pulled low to
select the device, the WRITE op-code is transmitted via the SI line followed by the byte
address and the data (D7-D0) to be programmed (Refer to Table 6). Programming will
start after the CS pin is brought high. (The LOW to High transition of the CS pin must
occur during the SCK low time immediately after clocking in the D0 (LSB) data bit.
The READY/BUSY status of the device can be determined by initiating a READ STA-
TUS REGISTER (RDSR) Instruction. If Bit 0 = 1, the WRITE cycle is still in progress. If
Bit 0 = 0, the WRITE cycle has ended. Only the READ STATUS REGISTER instruction
is enabled during the WRITE programming cycle.
The AT25HP256/512 is capable of a 128-byte PAGE WRITE operation. After each byte
of data is received, the seven low order address bits are internally incremented by one;
the high order bits of the address will remain constant. If more than 128-bytes of data
are transmitted, the address counter will roll over and the previously written data will be
overwritten. The AT25HP256/512 is automatically returned to the write disable state at
the completion of a WRITE cycle.
NOTE: If the device is not Write enabled (WREN), the device will ignore the Write
instruction and will return to the standby state, when CS is brought high. A new CS fall-
ing edge is required to re-initiate the serial communication.
Table 6. Address Key
Address
AN
AT25HP256/512
A14 - A0 / A15 - A0
A15 / none
Don’t Care Bits
NOTE: 128-byte PAGE WRITE operation only. Content of the page in the array will not
be guaranteed if less than 128 bytes of data is received (byte write is not supported).
10
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
Timing Diagrams (for SPI Mode 0 (0,0))
Synchronous Data Timing
t
CS
V
V
IH
CS
IL
t
t
CSH
CSS
V
IH
t
WL
t
WH
SKC
SI
V
IL
t
SU
t
H
V
V
IH
VALID IN
IL
t
V
t
t
HO
DIS
V
OH
HI-Z
HI- Z
SO
V
OL
WREN Timing
CS
SCK
SI
SO
WRDI Timing
CS
SCK
SI
WRDI OP-CODE
HI-Z
SO
11
1113G–SEEPR–08/02
RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
SI
INSTRUCTION
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
WRSR Timing
READ Timing
12
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
WRITE Timing (AT25HP256)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
SI
BYTE ADDRESS
...
1ST BYTE DATA IN
13
INSTRUCTION
1
0
15
14
7
6
5
3
2
2
4
0
3
1
HIGH IMPEDANCE
SO
PAGE WRITE Timing (AT25HP512)
CS
0
1
2
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 10431044 1045 1046 1047
SCK
SI
BYTE ADDRESS 1st BYTE DATA IN
128th BYTE DATA IN
INSTRUCTION
13
12
1
0
15
14
7
6
5
3
2
2
4
0
3
1
HIGH IMPEDANCE
SO
HOLD Timing
CS
tCD
tCD
SCK
HOLD
SO
tHD
tHD
tHZ
tLZ
13
1113G–SEEPR–08/02
AT25HP256 Ordering Information
tWC (max)
ICC (max)
ISB (max)
fMAX
(ms)
(µA)
(µA)
(kHz)
Ordering Code
Package
Operation Range
10
10
4000
3000
2.0
2.0
5000
AT25HP256-10CI-2.7
AT25HP256-10PI-2.7
AT25HP256W-10SI-2.7
8CN3
8P3
Industrial
(-40°C to 85°C)
8S2
2000
AT25HP256-10CI-1.8
AT25HP256-10PI-1.8
AT25HP256W-10SI-1.8
8CN3
8P3
Industrial
(-40°C to 85°C)
8S2
Package Type
8CN3
8P3
8-lead, 0.230" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
8-lead, 0.200" Wide, Plastic Small Outline Package (EIAJ)
Options
8S2
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
14
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
AT25HP512 Ordering Information
Ordering Code
Package
Operation Range
AT25HP512-10CI-2.7
AT25HP512CI-10CI-2.7
AT25HP512-10PI-2.7
AT25HP512W2-10SI-2.7
8CN3
8CN1
8P3
Industrial
(-40°C to 85°C)
16S2
AT25HP512-10CI-1.8
AT25HP512CI-10CI-1.8
AT25HP512-10PI-1.8
AT25HP512W2-10SI-1.8
8CN3
8CN1
8P3
Industrial
(-40°C to 85°C)
16S2
Note:
For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
Package Type
8-lead, 0.230" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Leadless Array Package (LAP)
8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)
16-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
Options
8CN3
8CN1
8P3
16S2
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
15
1113G–SEEPR–08/02
Packaging Information
8CN3 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.36
5.89
4.83
MAX
1.14
0.38
0.46
6.09
5.03
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.41
1
4
D
5.99
E
4.93
e1
L
e
1.27 BSC
0.56 REF
0.67
e1
L
Bottom View
0.62
0.92
0.72
1.02
1
1
L1
0.97
Note: 1. Metal Pad Dimensions.
11/14/01
DRAWING NO.
REV.
A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN3, 8-lead, (6 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
8CN3
R
16
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
8CN1 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
7
2
3
MIN
0.94
0.30
0.36
7.90
4.90
MAX
1.14
0.38
0.46
8.10
5.10
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.41
1
4
D
8.00
E
5.00
e1
L
e
1.27 BSC
0.60 REF
0.67
e1
L
Bottom View
0.62
0.92
0.72
1.02
1
1
L1
0.97
Note: 1. Metal Pad Dimensions.
11/13/01
DRAWING NO.
REV.
A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,
8CN1
R
Leadless Array Package (LAP)
17
1113G–SEEPR–08/02
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
18
AT25HP256/512
1113G–SEEPR–08/02
AT25HP256/512
8S2 – EIAJ SOIC
1
H
N
Top View
e
b
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
1.78
0.05
0.35
0.18
5.13
5.13
7.62
0.51
MAX
2.03
0.33
0.51
0.25
5.38
5.41
8.38
0.89
NOM
NOTE
SYMBOL
A
A1
b
A1
5
5
C
D
E
H
L
L
E
2, 3
4
End View
e
1.27 BSC
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/-0.005 mm.
5/2/02
TITLE
DRAWING NO.
REV.
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
2325 Orchard Parkway
San Jose, CA 95131
8S2
B
R
19
1113G–SEEPR–08/02
16S2 – JEDEC SOIC
C
1
E
H
N
A1
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
e
b
MIN
MAX
NOM
NOTE
SYMBOL
A
A
A1
b
0.0926
0.0040
0.0130
0.0091
0.3977
0.2914
0.3940
0.0160
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
0.4190
0.050
D
5
C
D
E
H
L
Side View
2
3
4
e
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AA for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "B", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
(0.024") per side.
1/9/02
TITLE
DRAWING NO.
REV.
A
2325 Orchard Parkway
San Jose, CA 95131
16S2, 16-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
16S2
R
20
AT25HP256/512
1113G–SEEPR–08/02
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© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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1113G–SEEPR–08/02
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