AT24C04A-10TI-2.7 [ETC]
I2C Serial EEPROM ; I2C串行EEPROM\n
| 型号： | AT24C04A-10TI-2.7 |
| 厂家： | 
ETC |
| 描述： | I2C Serial EEPROM
|
| 文件： | 总20页 (文件大小：249K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Write Protect Pin for Hardware Data Protection
– Utilizes Different Array Protection Compared to the AT24C02/04/08/16
• Low-voltage and Standard-voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
• Internally Organized 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K)
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate for AT24C02A, 04A and 08A
• 100 kHz (1.8V) and 400 kHz (2.5V, 2.7V and 5V) Clock Rate for AT24C16A
• 8-byte Page (2K), 16-byte Page (4K, 8K, 16K) Write Modes
• Partial Page Writes are Allowed
2-wire Serial
EEPROM
2K (256 x 8)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: One Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead JEDEC SOIC, 8-pin PDIP, and 8-lead TSSOP Packages
4K (512 x 8)
8K (1024 x 8)
16K (2048 x 8)
Description
The AT24C02A/04A/08A/16A provides 2048/4096/8192/16384 bits of serial electri-
cally erasable and programmable read only memory (EEPROM) organized as
256/512/1024/2048 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low power and low voltage operation are
essential. The AT24C02A/04A/08A/16A is available in space saving 8-pin PDIP, 8-lead
JEDEC SOIC, and 8-lead TSSOP (AT24C02A/04A) packages and is accessed via a
2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
AT24C02A
AT24C04A
AT24C08A
AT24C16A
Pin Configurations
8-pin PDIP
Pin Name
A0 - A2
SDA
Function
A0
A1
1
2
3
4
8
7
6
5
VCC
WP
Address Inputs
Serial Data
A2
SCL
SDA
GND
SCL
Serial Clock Input
Write Protect
No-connect
WP
8-lead SOIC
NC
A0
A1
A2
1
2
3
4
8
7
6
5
VCC
WP
SCL
SDA
GND
8-lead TSSOP
A0
1
2
3
4
8
7
6
5
VCC
A1
A2
WP
SCL
SDA
GND
Rev. 0976D–12/01
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Block Diagram
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device
address inputs that must be hard wired for the AT24C02A. As many as eight 2K devices
may be addressed on a single bus system (device addressing is discussed in detail
under the Device Addressing section).
The AT24C04A uses the A2 and A1 inputs for hard wire addressing and a total of four
4K devices may be addressed on a single bus system. The A0 pin is a no-connect.
2
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
The AT24C08A only uses the A2 input for hardwire addressing and a total of two 8K
devices may be addressed on a single bus system. The A0 and A1 pins are no-
connects.
The AT24C16A does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no-connects.
WRITE PROTECT (WP): The AT24C02A/04A/08A/16A have a Write Protect pin that
provides hardware data protection. The Write Protect pin allows normal read/write oper-
ations when connected to ground (GND). When the Write Protect pin is connected to
VCC, the write protection feature is enabled and operates as shown in the following
table.
Part of the Array Protected
WP Pin
Status
At VCC
At GND
24C02A
24C04A
24C08A
24C16A
Upper Half
(1K) Array
Upper Half
(2K) Array
Full (8K)
Array
Full (16K)
Array
Normal Read/Write Operations
Memory Organization AT24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each,
the 2K requires an 8-bit data word address for random word addressing.
AT24C04A, 4K SERIAL EEPROM: The 4K is internally organized with 32 pages of 16
bytes each. Random word addressing requires a 9-bit data word address.
AT24C08A, 8K SERIAL EEPROM: The 8K is internally organized with 64 pages of 16
bytes each. Random word addressing requires a 10-bit data word address.
AT24C16A, 16K SERIAL EEPROM: The 16K is internally organized with 128 pages of
16 bytes each. Random word addressing requires an 11-bit data word address.
Pin Capacitance
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol
CI/O
Test Condition
Max
8
Units
pF
Conditions
VI/O = 0V
VIN = 0V
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL)
CIN
6
pF
Note:
1. This parameter is characterized and is not 100% tested.
3
0976D–12/01
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol
VCC1
VCC2
VCC3
VCC4
ICC
Parameter
Test Condition
Min
1.8
2.5
2.7
4.5
Typ
Max
5.5
5.5
5.5
5.5
1.0
3.0
Units
V
Supply Voltage
Supply Voltage
Supply Voltage
Supply Voltage
V
V
V
Supply Current VCC = 5.0V READ at 100 kHz
Supply Current VCC = 5.0V WRITE at 100 kHz
0.4
2.0
mA
mA
ICC
Standby Current VCC
1.8V
=
=
=
=
ISB1
ISB2
ISB3
ISB4
VIN = VCC or VSS
IN = VCC or VSS
0.6
1.4
1.6
8.0
3.0
4.0
µA
µA
µA
µA
Standby Current VCC
2.5V
V
Standby Current VCC
2.7V
VIN = VCC or VSS
VIN = VCC or VSS
4.0
Standby Current VCC
5.0V
18.0
ILI
Input Leakage Current
Output Leakage Current
Input Low Level (1)
VIN = VCC or VSS
VOUT = VCC or VSS
0.10
0.05
3.0
µA
µA
V
ILO
VIL
VIH
3.0
-0.6
VCC x 0.3
VCC + 0.5
Input High Level (1)
VCC x 0.7
V
Output Low Level VCC
3.0V
=
=
VOL2
VOL1
IOL = 2.1 mA
0.4
0.2
V
V
Output Low Level VCC
1.8V
I
OL = 0.15 mA
Note:
1. VIL min and VIH max are reference only and are not tested.
4
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and
100 pF (unless otherwise noted).
AT24C02A/
04A/08A/16A
AT2402A/04A/
08A
2.5V, 2.7V
AT24C02A/
04A/08A/16A
5.0V
AT24C16A
2.5V
1.8V
Symbol
fSCL
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
kHz
µs
Clock Frequency, SCL
Clock Pulse Width Low
Clock Pulse Width High
Noise Suppression Time(1)
Clock Low to Data Out Valid
100
100
400
400
tLOW
tHIGH
tI
4.7
4.0
4.7
4.0
1.3
0.6
1.2
0.6
µs
100
4.5
100
4.5
100
0.9
50
ns
tAA
0.1
4.7
0.1
4.7
0.2
1.3
0.1
1.2
0.9
µs
Time the bus must be free before
a new transmission can start(2)
tBUF
µs
tHD.STA
tSU.STA
tHD.DAT
tSU.DAT
tR
Start Hold Time
4.0
4.7
0
4.0
4.7
0
0.6
0.6
0
0.6
0.6
0
µs
µs
µs
ns
µs
ns
µs
ns
ms
Start Set-up Time
Data In Hold Time
Data In Set-up Time
Inputs Rise Time(2)
Inputs Fall Time(2)
Stop Set-up Time
Data Out Hold Time
Write Cycle Time
200
200
100
100
1.0
1.0
0.3
0.3
tF
300
300
300
300
tSU.STO
tDH
4.7
4.7
0.6
0.6
50
100
100
100
tWR
10
10
10
10
Write
Cycles
Endurance(2) 5.0V, 25°C, Page Mode
1M
1M
1M
1M
Notes: 1. This parameter is characterized and is not 100% tested (TA = 25°C).
2. This parameter is characterized and is not 100% tested.
5
0976D–12/01
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8 bit words. The EEPROM sends a zero to acknowledge that it has
received each word. This happens during the ninth clock cycle.
STANDBY MODE: The AT24C02A/04A/08A/16A features a low power standby mode
which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the
completion of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA
high in each cycle while SCL is high and then (c) create a start condition as SDA is high.
6
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)
Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)
SCL
SDA
8th BIT
WORD n
ACK
(1)
tWR
STOP
START
CONDITION
CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the interval
clear/write cycle.
7
0976D–12/01
Data Validity
Start and Stop Definition
Output Acknowledge
8
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
Device Addressing
The 2K, 4K and 8K EEPROM devices all require an 8 bit device address word following
a start condition to enable the chip for a read or write operation (refer to Figure 1).
The device address word consists of a mandatory one, zero sequence for the first four
most significant bits as shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3
bits must compare to their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a
memory page address bit. The two device address bits must compare to their corre-
sponding hard-wired input pins. The A0 pin is no-connect.
The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for
memory page addressing. The A2 bit must compare to its corresponding hard-wired
input pin. The A1 and A0 pins are no-connect.
The 16K EEPROM does not use the device address pins, which limits the number of
devices on a single bus to one. The A0, A1 and A2 pins are no-connects.
The eighth bit of the device address is the read/write operation select bit. A read opera-
tion is initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is
not made, the chip will return to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8 bit data word address following the
device address word and acknowledgement. Upon receipt of this address, the EEPROM
will again respond with a zero and then clock in the first 8 bit data word. Following
receipt of the 8 bit data word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write sequence with a stop condi-
tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to the
nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will
not respond until the write is complete (refer to Figure 2).
PAGE WRITE: The 2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and
16K devices are capable of 16-byte page writes.
A page write is initiated the same as a byte write, but the microcontroller does not send
a stop condition after the first data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcontroller can transmit up to seven
(2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a zero
after each data word received. The microcontroller must terminate the page write
sequence with a stop condition (refer to Figure 3).
The data word address lower three (2K) or four (4K, 8K, 16K) bits are internally incre-
mented following the receipt of each data word. The higher data word address bits are
not incremented, retaining the memory page row location. When the word address,
internally generated, reaches the page boundary, the following byte is placed at the
beginning of the same page. If more than eight (2K) or sixteen (4K, 8K, 16K) data words
are transmitted to the EEPROM, the data word address will “roll over” and previous data
will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
ing a start condition followed by the device address word. The read/write bit is
representative of the operation desired. Only if the internal write cycle has completed
will the EEPROM respond with a zero allowing the read or write sequence to continue.
9
0976D–12/01
Read Operations
Read operations are initiated the same way as write operations with the exception that
the read/write select bit in the device address word is set to one. There are three read
operations: current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the
last address accessed during the last read or write operation, incremented by one. This
address stays valid between operations as long as the chip power is maintained. The
address “roll over” during read is from the last byte of the last memory page to the first
byte of the first page. The address “roll over” during write is from the last byte of the cur-
rent page to the first byte of the same page.
Once the device address with the read/write select bit set to one is clocked in and
acknowledged by the EEPROM, the current address data word is serially clocked out.
The microcontroller does not respond with an input zero but does generate a following
stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the
data word address. Once the device address word and data word address are clocked
in and acknowledged by the EEPROM, the microcontroller must generate another start
condition. The microcontroller now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM acknowledges the device
address and serially clocks out the data word. The microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or
a random address read. After the microcontroller receives a data word, it responds with
an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to
increment the data word address and serially clock out sequential data words. When the
memory address limit is reached, the data word address will “roll over” and the sequen-
tial read will continue. The sequential read operation is terminated when the
microcontroller does not respond with a zero but does generate a following stop condi-
tion (refer to Figure 6).
Figure 1. Device Address
A
A
A
A
A
P
A
R/W
LSB
2K
4K
1
0
0
0
0
1
1
1
1
0
0
0
0
0
2
2
2
1
MSB
R/W
R/W
R/W
1
1
1
P0
P0
1
1
8K
16K
P2 P1 P0
10
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
Figure 2. Byte Write
S
T
A
R
T
W
R
I
S
T
T
E
O
DEVICE
ADDRESS
P
WORD ADDRESS
DATA
SDA LINE
M
S
B
L R A
M
S
B
L
S
B
A
A
C
K
/
S
B
C
K
C
K
W
Figure 3. Page Write
S
T
W
R
I
S
T
A
R
T
E
O
P
DEVICE
ADDRESS
T
WORD ADDRESS (n)
DATA (n)
DATA (n + 1)
DATA (n + x)
SDA LINE
M
S
B
L R A
A
C
K
A
C
K
A
C
K
A
C
K
/
S
C
B W K
Figure 4. Current Address Read
S
T
A
R
T
R
E
A
D
S
T
O
P
DEVICE
ADDRESS
SDA LINE
M
S
B
L R A
DATA
N
O
/
S
B
C
K
W
A
C
K
11
0976D–12/01
Figure 5. Random Read
S
T
A
R
T
W
R
I
S
T
A
R
T
R
E
A
D
S
T
DEVICE
ADDRESS
T
E
O
P
DEVICE
ADDRESS
WORD
ADDRESS n
SDA LINE
M
S
B
L R A
L A
S C
B K
A
C
K
DATA n
N
O
M
M
S
B
L
S
B
/
S
B
C
K
S
B
W
A
C
K
DUMMY WRITE
Figure 6. Sequential Read
12
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
AT24C02A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
Ordering Code
Package
Operation Range
10
1500
4
100
AT24C02A-10PI-2.7
AT24C02AN-10SI-2.7
AT24C02A-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
10
800
3
100
AT24C02A-10PI-1.8
AT24C02AN-10SI-1.8
AT24C02A-10TI-1.8
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
8S1
8T
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
13
0976D–12/01
AT24C04A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
Ordering Code
Package
Operation Range
10
1500
4
100
AT24C04A-10PI-2.7
AT24C04AN-10SI-2.7
AT24C04A-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
10
800
3
100
AT24C04A-10PI-1.8
AT24C04AN-10SI-1.8
AT24C04A-10TI-1.8
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
8S1
8T
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
14
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
AT24C08A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
Ordering Code
Package
Operation Range
10
1500
4
100
100
AT24C08A-10PI-2.7
AT24C08AN-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
10
800
3
AT24C08A-10PI-1.8
AT24C08AN-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8S1
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
15
0976D–12/01
AT24C16A Ordering Information
tWR (max)
(ms)
ICC (max)
(µA)
ISB (max)
(µA)
fMAX
(kHz)
Ordering Code
Package
Operation Range
10
1500
4
400
100
AT24C16A-10PI-2.7
AT24C16AN-10SI-2.7
8P3
8S1
Industrial
(-40°C to 85°C)
10
800
3
AT24C16A-10PI-1.8
AT24C16AN-10SI-1.8
8P3
8S1
Industrial
(-40°C to 85°C)
Package Type
8P3
8-pin, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
Options
8S1
-2.7
-1.8
Low Voltage (2.7V to 5.5V)
Low Voltage (1.8V to 5.5V)
16
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
Packaging Information
8P3 – PDIP
D
PIN
1
E1
A
B1
SEATING PLANE
A1
L
B
e
B2
(4 PLACES)
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
MAX
NOM
NOTE
SYMBOL
eC
A
–
–
4.318
eB
A1
D
0.381
9.144
7.620
6.096
0.406
1.397
0.762
3.175
0.203
–
–
–
–
–
–
–
–
–
–
–
–
–
9.652 Note 2
8.255
E
E1
B
6.604 Note 2
0.508
B1
B2
L
1.651
Notes:
1. This package conforms to JEDEC reference MS-001 BA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
1.143
3.429
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
09/28/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
8P3
B
R
17
0976D–12/01
8S1 – JEDEC SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
18
AT24C02A/04A/08A/16A
0976D–12/01
AT24C02A/04A/08A/16A
8T– TSSOP
Top View
3
2
1
E
E1
N
Side View
A2
A
b
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
MAX
NOM
3.00
NOTE
SYMBOL
e
D
2.90
3.10
2, 5
E
6.40 BSC
4.40
D
E1
A
4.30
–
4.50
1.20
1.05
0.30
3, 5
4
–
A2
b
0.80
0.19
1.00
End View
–
e
0.65 BSC
0.60
L
0.45
0.75
L
L1
1.00 REF
L1
Notes:
1. These drawings are for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side.
3. Dimension "E1" does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.
4. Dimension "b" does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the "b" dimension at maximum
material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension "D" and "E1" to be determined at Datum Plane H.
10/26/01
DRAWING NO.
TITLE
REV.
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
8T, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
8T
A
R
19
0976D–12/01
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Printed on recycled paper.
0976D–12/01/0M
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