AT17LV020A-10JC [ETC]
Configuration EEPROM ; 配置EEPROM\n
| 型号： | AT17LV020A-10JC |
| 厂家： | 
ETC |
| 描述： | Configuration EEPROM
|
| 文件： | 总13页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial EEPROM Family for Configuring Altera FLEX® Devices
• Simple Interface to SRAM FPGAs
• EE Programmable 2M-bit Serial Memories Designed to Store Configuration Programs
for Field Programmable Gate Arrays (FPGAs)
• Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in the Space-efficient Surface-mount PLCC Package
• In-System Programmable Via 2-wire Bus
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V 5% LV and 5V 5% C Versions
• System-friendly READY Pin
FPGA
Configuration
EEPROM
Memory
2-Mbit
Description
The AT17C020A and AT17LV020A (high-density AT17A Series) FPGA Configuration
EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration mem-
ory for programming Altera FLEX® devices. The AT17A Series is packaged in the
popular 20-lead PLCC. The AT17A Series family uses a simple serial-access proce-
dure to configure one or more FPGA devices. The AT17A Series organization
supplies enough memory to configure one or multiple smaller FPGAs. Using a feature
of the AT17A Series, the user can select the polarity of the reset function by program-
ming internal EEPROM bytes. The AT17A parts generate their own internal clock and
can be used as a system “master” for loading the FPGA devices.
Altera Pinout
AT17C020A
AT17LV020A
The Atmel devices also support a system-friendly READY pin. The READY pin is used
to simplify system power-up considerations.
The AT17A Series Configurators can be programmed with industry-standard program-
mers, or Atmel’s ATDH2200E Programming Kit.
Pin Configurations
PLCC
DCLK
NC
4
5
6
7
8
18 SER_EN
17 NC
NC
16 NC
NC
15 READY
14 NC
OE
Rev. 1270A–05/00
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Block Diagram
SER_EN
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
OSC
CONTROL
ROW
ADDRESS
COUNTER
EEPROM
CELL
MATRIX
ROW
DECODER
OSC
BIT
COUNTER
COLUMN
DECODER
POWER ON
RESET
TC
DCLK READY
OE
nCS
nCASC (A2)
DATA
driven Low again, the address counter is reset and
the DATA output pin is tri-stated, regardless of the state
of the nCS.
Device Configuration
The control signals for the configuration EEPROM-nCS,
OE, and DCLK-interface directly with the FPGA device
control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configura-
tion EEPROM without requiring an external intelligent
controller.
When the Configurator has driven out all of its data and
nCASC is driven Low, the device tri-states the DATA pin to
avoid contention with other Configurators. Upon power-up,
the address counter is automatically reset.
The READY pin is available as an open-collector indicator
of the device’s reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete.
The configuration EEPROM’s OE and nCS pins control the
tri-state buffer on the DATA output pin and enable the
address counter and the oscillator. When OE is driven Low,
the configuration EEPROM resets its address counter and
tri-states its DATA pin. The nCS pin also controls the out-
put of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the
DATA output pin is tri-stated. When nCS is driven Low, the
counter and the DATA output pin are enabled. When OE is
This document discusses the EPF10K device interface.
For more details or information on other Altera applications,
please reference the “AT17A Series Conversions from
Altera FPGA Serial Configuration Memories” application
note.
AT17C/LV020A
2
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AT17C/LV020A
first AT17A Series device finishes sending configuration
data, it drives its nCASC pin Low, which drives the nCS pin
of the second AT17A Series device Low. This activates the
second AT17A Series device to send configuration data to
the FPGA device.
FPGA Device Configuration
FPGA devices can be configured with an AT17A Series
EEPROM as shown in Figure 1. The AT17A Series device
stores configuration data in its EEPROM array and clocks
the data out serially with its internal oscillator. The OE,
nCS, and DCLK pins supply the control signals for the
address counter and the output tri-state buffer. The AT17A
Series device sends a serial bitstream of configuration data
to its DATA pin, which is connected to the DATA0 input pin
on the FPGA device.
The first AT17A Series device clocks all subsequent
AT17A Series devices until configuration is complete. Once
all configuration data is transferred and nCS on the first
AT17A Series device is driven High by CONF_DONE on
the FPGA devices, the first AT17A Series device clocks 16
additional cycles to initialize the FPGA device before going
into zero-power (idle) state. If nCS on the first AT17A
Series device is driven High before all configuration data is
transferred – or if the nCS is not driven High after all config-
uration data is transferred – nSTATUS is driven Low,
indicating a configuration error.
When configuration data for an FPGA device exceeds the
capacity of a single AT17A Series device, multiple AT17A
Series devices can be serially linked together (Figure 2).
When multiple AT17A Series devices are required, the
nCASC and nCS pins provide handshaking between the
cascaded EEPROMs.
The READY pin is available as an open-collector indicator
of the device’s reset status; it is driven Low while the device
is in its power-on reset cycle and released (tri-stated) when
the cycle is complete. It can be used to hold the FPGA
device in reset while it is completing its power-on reset but
it cannot be used to effectively delay configuration (i.e., the
output is released well before the system VCC has
stabilized).
The position of an AT17A Series device in a chain deter-
mines its operation. The first AT17A Series device in a
Configurator chain is powered up or reset with nCS Low
and is configured for the FPGA device’s protocol. This
AT17A Series device supplies all clock pulses to one or
more FPGA devices and to any downstream AT17A Series
Configurator during configuration. The first AT17A Series
Configurator also provides the first stream of data to the
FPGA devices during multi-device configuration. Once the
Figure 1. Configuration with a Single AT17A Series Configurator
VCC
VCC
VCC
AT17C512A/010A/020A
AT17LV512A/010A/020A
EPF10K
DCLK
DCLK
nCONFIG
DATA
nCS
DATA0
CONF_DONE
nSTATUS
nCE
OE
MSEL0
MSEL1
READY
GND
Notes: 1. 1.0 kΩ resistors used unless otherwise specified.
2. Applicable to EPF6K.
3. Use of the READY pin is optional.
4. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
5. Reset polarity of EEPROM must be set active Low (OE active High).
3
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Figure 2. Configuration with Multiple AT17A Series Configurators
VCC
VCC
VCC
AT17C512A/010A/020A
AT17LV512A/010A/020A
DEVICE 1
AT17C512A/010A/020A
AT17LV512A/010A/020A
DEVICE 2
EPF10K
DCLK
DATA
DCLK
DCLK
nCONFIG
DATA
nCS
DATA0
nCS
OE
nCASC
READY
nCE
CONF_DONE
nSTATUS
OE
MSEL0
MSEL1
READY
GND
Notes: 1. 1.0 kΩ resistors used unless otherwise specified.
2. Use of the READY pin is optional.
3. Introducing a RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
4. Reset polarity of EEPROM must be set active Low (OE active High).
inside the chip. See the “Programming Specification for
AT17A Series Reset Polarity
Atmel’s Configuration EEPROMs” application note for fur-
The AT17A Series Configurator allows the user to program
ther information. The AT17 A-series parts are read/write at
the polarity of the OE pin as either RESET/OE or
5V nominal. The AT17LV A-series parts are read/write at
RESET/OE. For more details, please reference the “Pro-
3.3V nominal.
gramming Specification for Atmel’s FPGA Configuration
EEPROMs” application note.
Standby Mode
The AT17A Series Configurator enters a low-power
Programming Mode
standby mode whenever nCS is asserted High. In this
The programming mode is entered by bringing SER_EN
mode, the configuration consumes less than 0.5 mA of cur-
Low. In this mode the chip can be programmed by the
rent at 5V. The output remains in a high-impedance state
2-wire serial interface. The programming is done at VCC
regardless of the state of the OE input.
supply only. Programming super voltages are generated
AT17C/LV020A
4
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AT17C/LV020A
Pin Configurations
20
PLCC
Pin
Name
DATA
DCLK
I/O Description
2
I/O Three-state data output for configuration. Open-collector bi-directional pin for programming.
4
I/O Clock output or clock input. Rising edges on DCLK increment the internal address counter and present the
next bit of data to the DATA pin. The counter is incremented only if the OE input is held High, the nCS input
is held Low, and all configuration data has not been transferred to the target device (otherwise, as the
master device, the DCLK pin drives Low).
8
9
OE
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level resets the
address counter. A High logic level (with nCS Low) enables DATA and permits the address counter to
count. In the mode, if this pin is Low (reset), the internal oscillator becomes inactive and DCLK drives Low.
The logic polarity of this input is programmable and must be programmed active High (RESET active Low)
by the user during programming for Altera applications.
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the address counter
and enables DATA to drive out. If the AT17A Series is reset with nCS Low, the device initializes as the first
(and master) device in a daisy-chain. If the AT17A Series is reset with nCS High, the device initializes as a
subsequent AT17A Series device in the chain.
10
12
GND
Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND pins.
nCASC
O
Cascade select output (active Low). This output goes Low when the address counter has reached its
maximum value. In a daisy-chain of AT17A Series devices, the nCASC pin of one device is usually
connected to the nCS input pin of the next device in the chain, which permits DCLK from the master
Configurator to clock data from a subsequent AT17A Series device in the chain.
A2
I
O
I
Device selection input, A2. This is used to enable (or select) the device during programming, (i.e., when
SER_EN is Low; please refer to the “Programming Specification” application note for more details).
15
18
20
READY
SER_EN
VCC
Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated) when
power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used).
Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low, enables the
2-wire serial programming mode.
+3.3V/+5V power supply pin
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional
operation of the device at these or any other condi-
tions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum
Ratings conditions for extended periods of time
may affect device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF) ................................ 2000V
5
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Operating Conditions
AT17C020A
Min/Max
AT17LV020A
Min/Max
Symbol Description
Units
Supply voltage relative to GND
-0°C to +70°C
Commercial
Industrial
Military
4.75/5.25
4.5/5.5
3.15/3.45
3.15/3.45
3.15/3.45
V
Supply voltage relative to GND
-40°C to +85°C
VCC
V
V
Supply voltage relative to GND
-55°C to +125°C
4.5/5.5
AT17C/LV020A
6
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AT17C/LV020A
DC Characteristics
VCC = 5V 5% Commercial / 5V 10% Ind./Mil.
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Units
V
High-level input voltage
VIL
Low-level input voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = -4 mA)
Low-level output voltage (IOL = +4 mA)
Supply current, active mode (at FMAX)
Input or output leakage current (VIN = VCC or GND)
3.86
V
Commercial
0.32
0.37
V
3.76
V
Industrial
V
3.7
V
Military
0.4
10
V
mA
µA
mA
mA
-20
Commercial
20
0.5
0.75
ICCS
Supply current, standby mode AT17C020A
Industrial/Military
DC Characteristics
VCC = 3.3V 5%
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
Units
V
High-level input voltage
VIL
Low-level input voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level output voltage (IOH = -2.5 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = -2 mA)
Low-level output voltage (IOL = +3 mA)
High-level output voltage (IOH = -2 mA)
Low-level output voltage (IOL = +2.5 mA)
Supply current, active mode (at FMAX)
Input or output leakage current (VIN = VCC or GND)
2.4
V
Commercial
0.4
0.4
V
2.4
V
Industrial
V
2.4
V
Military
0.4
5
V
mA
µA
µA
µA
-20
Commercial
20
200
200
ICCS
Supply current, standby mode
Industrial/Military
7
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AC Characteristics
nCS
TSCE
THCE
TSCE
OE
DCLK
DATA
TLOE
TLC
THC
TOE
TCAC
TOH
TDF
TCE
TOH
AC Characteristics When Cascading
OE
nCS
DCLK
TCDF
LAST BIT
FIRST BIT
DATA
TOCK
TOCE
TOOE
nCASL
TOCE
AT17C/LV020A
8
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AT17C/LV020A
.
AC Characteristics for AT17C020A
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
35
Units
ns
(2)
TOE
OE to Data Delay
30
45
50
(2)
TCE
nCS to Data Delay
45
ns
(2)
TCAC
DCLK to Data Delay
55
ns
TOH
Data Hold From nCS, OE, or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0
0
ns
(3)
TDF
50
50
ns
TLC
20
20
20
20
20
25
ns
THC
TSCE
ns
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
THCE
0
0
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
MAX Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
12.5
30
20
12.5
30
ns
MHz
ns
250
250
250
250
THC
DCLK High Time Master Mode
30
30
ns
AC Characteristics for AT17C020A When Cascading
VCC = 5V 5% Commercial / VCC = 5V 10% Ind./Mil.
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
50
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
OE to nCASC Delay
MAX Input Clock Frequency
(2)
TOCK
35
40
ns
(2)
TOCE
35
35
ns
(2)
TOOE
30
30
ns
FMAX
12.5
12.5
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
9
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.
AC Characteristics for AT17LV020A
VCC = 3.3V 5% Commercial / VCC = 3.3V 5% Ind./Mil.
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
55
Units
ns
(2)
TOE
OE to Data Delay
50
55
60
(2)
TCE
nCS to Data Delay
60
ns
(2)
TCAC
DCLK to Data Delay
65
ns
TOH
Data Hold From nCS, OE, or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0
0
ns
(3)
TDF
50
50
ns
TLC
25
25
35
25
25
40
ns
THC
TSCE
ns
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
THCE
0
0
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
MAX Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
12
30
30
20
7.5
30
30
ns
MHz
ns
300
300
300
300
THC
DCLK High Time Master Mode
ns
AC Characteristics for AT17LV020A When Cascading
VCC = 3.3V 5% Commercial / VCC = 3.3V 5% Ind./Mil.
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
50
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
(2)
TOCK
50
55
ns
(2)
TOCE
35
40
ns
(2)
TOOE
OE to nCASC Delay
35
35
ns
FMAX
MAX Input Clock Frequency Slave Mode
12
7.5
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AT17C/LV020A
10
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AT17C/LV020A
Ordering Information - 5V Devices
Memory
Size
Ordering Code
Package
Operation Range
2M(1)
AT17C020A-10JC
20J
Commercial
(0°C to 70°C)
AT17C020A-10JI
20J
Industrial
(-40°C to 85°C)
Ordering Information - 3.3V Devices
Memory
Size
Ordering Code
Package
Operation Range
2M(1)
AT17LV020A-10JC
20J
Commercial
(0°C to 70°C)
AT17LV020A-10JI
20J
Industrial
(-40°C to 85°C)
Note:
1. Use 2M density parts to replace Altera EPC2.
Package Type
20J
20-lead, Plastic J-leaded Chip Carrier (PLCC)
11
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Packaging Information
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
AT17C/LV020A
12
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© Atmel Corporation 2000.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
ranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for
any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without
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®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.
Printed on recycled paper.
1270A–05/00/xM
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相关型号：
AT17LV040-10AI
Configuration Memory, 4MX1, Serial, CMOS, PQFP44, 1 MM HEIGHT, PLASTIC, MS-026ACB, TQFP-44
ATMEL
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