AT17C010A-10QI [ETC]
SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC ; 串行EEPROM | CMOS | TQFP | 32引脚|塑料\n
| 型号： | AT17C010A-10QI |
| 厂家： | 
ETC |
| 描述： | SERIAL EEPROM|CMOS|TQFP|32PIN|PLASTIC
|
| 文件： | 总15页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Serial EEPROM Family for Configuring Altera FLEX® Devices
• Simple Interface to SRAM FPGAs
• EE Programmable 512-Kbit and 1-Mbit Serial Memories Designed to Store
Configuration Programs for Field Programmable Gate Arrays (FPGAs)
• Cascadable Read Back to Support Additional Configurations or Future
Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in the Space-efficient Surface-mount PLCC and PDIP Packages for the
512-Kbit device and PLCC, PDIP and TQFP Packages for the 1-Mbit Device
• In-System Programmable via 2-wire Bus
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V 10% LV and 5V 5% C Versions
• System-friendly READY Pin
FPGA
Configuration
EEPROM
Memory
512-kilobit and
1-megabit
Description
The AT17C512A/010A and AT17LV512A/010A (high-density AT17A Series) FPGA
Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective con-
figuration memory for programming Altera FLEX® devices. The AT17C512A/LV512A
devices are packaged in the popular 8-lead PDIP and the 20-lead PLCC; the
AT17C010A/LV010A are packaged in the popular 8-lead PDIP, the 20-lead PLCC and
the 32-lead TQFP. The AT17A Series family uses a simple serial-access procedure to
configure one or more FPGA devices. The AT17A Series organization supplies
enough memory to configure one or multiple smaller FPGAs. Using a feature of the
AT17A Series, the user can select the polarity of the reset function by programming
four EEPROM bytes. The AT17A parts generate their own internal clock by default and
can be used as a system “master” for loading the FPGA devices. The internal clock
can be disabled by the industrial programmer to allow the AT17A parts to be used as
system “slave”, so that the external devices will provide the clock for loading the FPGA
devices.
Altera Pinout
AT17C512A
AT17LV512A
AT17C010A
AT17LV010A
The Atmel devices also support a system-friendly READY pin for the 20-lead PLCC
package and a write protect mechanism for all packages. The READY pin is used to
simplify system power-up considerations. The WP1 pin is used to protect part of the
Configurator memory during in-system programming.
The AT17A Series Configurator can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP cable.
Rev. 0974E–08/01
Pin Configuration
20-lead PLCC
8-lead PDIP
DATA
DCLK
OE
1
2
3
4
8
7
6
5
VCC
SER_EN
(A2) nCASC
GND
DCLK
WP1
NC
4
5
6
7
8
18 SER_EN
nCS
17 NC
16 NC
NC
15 READY
14 NC
OE
32-lead TQFP(1)
24 NC
NC
1
23 SER_EN
22 NC
DCLK
NC
2
3
4
5
6
7
8
21 NC
WP1
NC
20 READY
19 NC
NC
18 NC
OE
17 NC
NC
Note:
1. The 32-lead TQFP package is not available for
AT17C512A/LV512A devices.
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AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
Block Diagram
SER_EN
WP1
PROGRAMMING
DATA SHIFT
REGISTER
PROGRAMMING
MODE LOGIC
OSC
CONTROL
ROW
ADDRESS
COUNTER
EEPROM
CELL
MATRIX
ROW
DECODER
OSC
BIT
COUNTER
COLUMN
DECODER
POWER ON
RESET
TC
DCLK READY
(Optional)
OE
nCS
nCASC (A2)
DATA
Device Configuration The control signals for the configuration EEPROM (nCS, OE and DCLK) interface
directly with the FPGA device control signals. All FPGA devices can control the entire
configuration process and retrieve data from the configuration EEPROM without requir-
ing an external intelligent controller.
The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA
output pin and enable the address counter and the oscillator. When OE is driven Low,
the configuration EEPROM resets its address counter and tri-states its DATA pin. The
nCS pin also controls the output of the AT17A Series Configurator. If nCS is held High
after the OE reset pulse, the counter is disabled and the DATA output pin is tri-stated.
When nCS is driven Low, the counter and the DATA output pin are enabled. When OE
is driven Low again, the address counter is reset and the DATA output pin is tri-stated,
regardless of the state of the nCS.
When the Configurator has driven out all of its data and nCASC is driven Low, the
device tri-states the DATA pin to avoid contention with other Configurators. Upon
power-up, the address counter is automatically reset.
3
0974E–08/01
The READY pin is available as an open-collector indicator of the device’s reset status; it
is driven Low while the device is in its power-on reset cycle and released (tri-stated)
when the cycle is complete.
This document discusses the EPF10K device interface. For more details or information
on other Altera applications, please reference the “AT17A Series Conversions from
Altera FPGA Serial Configuration Memories” application note.
FPGA Device
Configuration
FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The
AT17A Series device stores configuration data in its EEPROM array and clocks the data
out serially with its internal oscillator. The OE, nCS and DCLK pins supply the control
signals for the address counter and the output tri-state buffer. The AT17A Series device
sends a serial bitstream of configuration data to its DATA pin, which is connected to the
DATA0 input pin on the FPGA device.
When configuration data for an FPGA device exceeds the capacity of a single AT17A
Series device, multiple AT17A Series devices can be serially linked together
(see Figure 2). When multiple AT17A Series devices are required, the nCASC and nCS
pins provide handshaking between the cascaded EEPROMs.
The position of an AT17A Series device in a chain determines its operation. The first
AT17A Series device in a Configurator chain is powered up or reset with nCS Low and
is configured for the FPGA device’s protocol. This AT17A Series device supplies all
clock pulses to one or more FPGA devices and to any downstream AT17A Series Con-
figurator during configuration. The first AT17A Series Configurator also provides the first
stream of data to the FPGA devices during multi-device configuration. Once the first
AT17A Series device finishes sending configuration data, it drives its nCASC pin Low,
which drives the nCS pin of the second AT17A Series device Low. This activates the
second AT17A Series device to send configuration data to the FPGA device.
The first AT17A Series device clocks all subsequent AT17A Series devices until config-
uration is complete. Once all configuration data is transferred and nCS on the first
AT17A Series device is driven High by CONF_DONE on the FPGA devices, the first
AT17A Series device clocks 16 additional cycles to initialize the FPGA device before
going into zero-power (idle) state. If nCS on the first AT17A Series device is driven High
before all configuration data is transferred–or if the nCS is not driven High after all con-
figuration data is transferred– nSTATUS is driven Low, indicating a configuration error.
The READY pin is available as an open-collector indicator of the device’s reset status; it
is driven Low while the device is in its power-on reset cycle and released (tri-stated)
when the cycle is complete. It can be used to hold the FPGA device in reset while it is
completing its power-on reset but it cannot be used to effectively delay configuration
(i.e., the output is released well before the system VCC has stabilized).
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AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
Figure 1. Configuration with a Single AT17A Series Configurator(1)(2)(3)
VCC
VCC
VCC
1 k
1 k
VCC
1 k
AT17C512A/010A/020A
AT17LV512A/010A/020A
EPF6K/EPF10K
DCLK
DCLK
nCONFIG
SER_EN
0.1
F
DATA
nCS
DATA0
CONF_DONE
nSTATUS
nCE
OE
MSEL0
MSEL1
READY
GND
Notes: 1. The use of the READY pin is optional for the 20-lead PLCC and the 32-lead TQFP packages. The 8-lead PDIP package
does not have a READY pin.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High)
5
0974E–08/01
Figure 2. Configuration with Multiple AT17A Series Configurators(1)(2)(3)
VCC
VCC
1 k
1 k
AT17C512A/010A/020A
AT17LV512A/010A/020A AT17LV512A/010A/020A
DEVICE 1 DEVICE 2
AT17C512A/010A/020A
VCC
1 k
EPF10K
DCLK DCLK
DCLK
nCONFIG
SER_EN
0.1
F
DATA
DATA
nCS
OE
DATA0
nCE CONF_DONE
nCS nCASC
OE
MSEL0
MSEL1
nSTATUS
READY
GND
Notes: 1. The use of the READY pin is optional for the 20-lead PLCC and the 32-lead TQFP packages. The 8-lead PDIP package
does not have a READY pin.
2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before
configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)
3. Reset polarity of EEPROM must be set active Low (OE active High).
AT17A Series Reset
Polarity
The AT17A Series Configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. For more details, please reference the “Programming Speci-
fication for Atmel’s FPGA Configuration EEPROMs” application note.
Programming Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the 2-wire serial interface. The programming is done at VCC supply
only. Programming super voltages are generated inside the chip. See the “Programming
Specification for Atmel’s Configuration EEPROMs” application note for further informa-
tion. The AT17A Series parts are read/write at 5V nominal. The AT17LVA Series parts
are read/write at 3.3V nominal.
Standby Mode
The AT17A Series Configurator enters a low-power standby mode whenever nCS is
asserted High. In this mode, the configuration consumes less than 0.5 mA of current at
5V. The output remains in a high-impedance state regardless of the state of the OE
input.
6
AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
Pin Configurations
8
20
PLCC
Pin
32
TQFP
Pin
PDIP
Pin
Name
I/O Description
1
2
31
DATA
I/O Three-state data output for configuration. Open-collector bi-directional pin for
programming.
2
4
2
DCLK
I/O Clock output or clock input. Rising edges on DCLK increment the internal address
counter and present the next bit of data to the DATA pin. The counter is
incremented only if the OE input is held High, the nCS input is held Low, and all
configuration data has not been transferred to the target device (otherwise, as the
master device, the DCLK pin drives Low).
5
8
4
7
WP1
OE
I
WRITE PROTECT (1). Used to protect portions of memory during programming.
Disabled by default due to internal pull-down resistor. This input pin is not used
during FPGA loading operations. See programming specifications for details.
3
I
Output enable (active High) and reset (active Low) when SER_EN is High. A Low
logic level resets the address counter. A High logic level (with nCS Low) enables
DATA and permits the address counter to count. In the mode, if this pin is Low
(reset), the internal oscillator becomes inactive and DCLK drives Low. The logic
polarity of this input is programmable and must be programmed active High
(RESET active Low) by the user during programming for Altera applications.
4
5
9
10
12
nCS
I
Chip select input (active Low). A Low input (with OE High) allows DCLK to
increment the address counter and enables DATA to drive out. If the AT17A Series
is reset with nCS Low, the device initializes as the first (and master) device in a
daisy-chain. If the AT17A Series is reset with nCS High, the device initializes as a
subsequent AT17A Series device in the chain.
10
GND
Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and
GND pins.
nCASC
O
Cascade select output (active Low). This output goes Low when the address
counter has reached its maximum value. In a daisy-chain of AT17A Series devices,
the nCASC pin of one device is usually connected to the nCS input pin of the next
device in the chain, which permits DCLK from the master Configurator to clock data
from a subsequent AT17A Series device in the chain.
6
12
15
15
20
A2
I
O
I
Device selection input, A2. This is used to enable (or select) the device during
programming, (i.e., when SER_EN is Low; please refer to the “Programming
Specification” application note for more details).
READY(1)
Open collector reset state indicator. Driven Low during power-up reset, released
(tri-stated) when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if
used).
7
8
18
20
23
27
SER_EN
VCC
Serial enable must be held High during FPGA loading operations. Bringing
SER_EN Low, enables the 2-wire serial programming mode.
+3.3V/+5V power supply pin
Note:
1. READY is an optional pin. It is not available in the 8-lead PDIP package.
7
0974E–08/01
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. These are stress ratings only,
and functional operation of the device at these or
any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to
Absolute Maximum Ratings conditions for
extended periods of time may affect device
reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260°C
Operating Conditions
AT17CXXXA
AT17LVXXXA
Symbol Description
Min
Max
Min
Max
Units
Commercial
Industrial
Military
Supply voltage relative to GND
-0°C to +70°C
4.75
5.25
3.0
3.6
V
Supply voltage relative to GND
-40°C to +85°C
VCC
4.5
4.5
5.5
5.5
3.0
3.0
3.6
3.6
V
V
Supply voltage relative to GND
-55°C to +125°C
8
AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
DC Characteristics
VCC = 5V 5% Commercial/5V 10% Industrial/Military
Symbol
VIH
Description
Min
2.0
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
0.0
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
High-level Output Voltage (IOH = -4 mA)
Low-level Output Voltage (IOL = +4 mA)
Supply Current, Active Mode (at FMAX)
Input or Output Leakage Current (VIN = VCC or GND)
3.86
V
Commercial
Industrial
Military
0.32
0.37
V
3.76
3.7
V
V
V
0.4
10
V
mA
µA
mA
mA
-10
10
Commercial
0.5
0.5
ICCS
Supply Current, Standby Mode AT17C512A/010A
Industrial/Military
DC Characteristics
VCC = 3.3V 10%
Symbol
VIH
Description
Min
2.0
0.0
2.4
Max
VCC
0.8
Units
V
High-level Input Voltage
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +2.5 mA)
Supply Current, Active Mode (at FMAX)
Input or Output Leakage Current (VIN = VCC or GND)
V
Commercial
Industrial
Military
0.4
0.4
V
2.4
2.4
V
V
V
0.4
5
V
mA
µA
µA
µA
-10
10
Commercial
100
100
ICCS
Supply Current, Standby Mode
Industrial/Military
9
0974E–08/01
AC Characteristics
nCS
TSCE
THCE
TSCE
OE
THOE
TLC
THC
DCLK
TOE
TCAC
TOH
TDF
TCE
DATA
TOH
AC Characteristics When Cascading
OE
nCS
DCLK
T
CDF
LAST BIT
FIRST BIT
DATA
T
T
T
OOE
OCK
OCE
nCASL
T
OCE
10
AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
.
AC Characteristics for AT17C512A/010A
VCC = 5V 5% Commercial/VCC = 5V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
30
Min
Max
35
Units
ns
(2)
TOE
OE to Data Delay
(2)
TCE
nCS to Data Delay
45
45
ns
(2)
TCAC
DCLK to Data Delay
50
55
ns
TOH
Data Hold From nCS, OE, or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0
0
ns
(3)
TDF
50
50
ns
TLC
20
20
20
0
20
20
25
0
ns
THC
ns
TSCE
THCE
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
Maximum Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
15
30
30
20
15
30
30
ns
MHz
ns
250
250
250
250
THC
DCLK High Time Master Mode
ns
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured =200 mV from steady state active levels.
AC Characteristics for AT17C512A/010A When Cascading
VCC = 5V 5% Commercial/VCC = 5V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
OE to nCASC Delay
50
35
35
30
(2)
TOCK
40
ns
(2)
TOCE
35
ns
(2)
TOOE
30
ns
FMAX
Maximum Input Clock Frequency
12.5
12.5
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured =200 mV from steady state active levels.
11
0974E–08/01
.
AC Characteristics for AT17LV512A/010A
VCC = 3.3V 10% Commercial/VCC = 3.3V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
55
Units
ns
(2)
TOE
OE to Data Delay
50
55
60
(2)
TCE
nCS to Data Delay
60
ns
(2)
TCAC
DCLK to Data Delay
65
ns
TOH
Data Hold From nCS, OE, or DCLK
nCS or OE to Data Float Delay
DCLK Low Time Slave Mode
DCLK High Time Slave Mode
nCS Setup Time to DCLK (to guarantee proper counting)
0
0
ns
(3)
TDF
50
50
ns
TLC
25
25
35
0
25
25
40
0
ns
THC
ns
TSCE
THCE
ns
nCS Hold Time from DCLK (to guarantee proper
counting)
ns
TLOE
FMAX
TLC
OE Low Time (guarantees counter is reset)
Maximum Input Clock Frequency Slave Mode
DCLK Low Time Master Mode
20
15
30
30
1.2
20
10
30
30
1.2
ns
MHz
ns
300
300
2.4
300
300
2.4
THC
DCLK High Time Master Mode
ns
VRDY
Ready Pin Open Collector Voltage
V
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
AC Characteristics for AT17LV512A/010A When Cascading
VCC = 3.3V 10% Commercial/VCC = 3.3V 10% Industrial/Military
Commercial
Industrial/Military(1)
Symbol
Description
Min
Max
Min
Max
50
Units
ns
(3)
TCDF
DCLK to Data Float Delay
DCLK to nCASC Delay
nCS to nCASC Delay
50
50
35
35
(2)
TOCK
55
ns
(2)
TOCE
40
ns
(2)
TOOE
OE to nCASC Delay
35
ns
FMAX
Maximum Input Clock Frequency Slave Mode
12.5
10
MHz
Notes: 1. Preliminary specifications for military operating range only.
2. AC test load = 50 pF.
3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels.
12
AT17C/LV512A/010A
0974E–08/01
AT17C/LV512A/010A
Ordering Information – 5V Devices
Memory
Size
Ordering Code
Package
Operation Range
512-Kbit(1)
AT17C512A-10PC
AT17C512A-10JC
8P3
20J
Commercial
(0°C to 70°C)
AT17C512A-10PI
AT17C512A-10JI
8P3
20J
Industrial
(-40°C to 85°C)
1-Mbit(2)
AT17C010A-10PC
AT17C010A-10JC
AT17C010A-10QC
8P3
20J
32A
Commercial
(0°C to 70°C)
AT17C010A-10PI
AT17C010A-10JI
AT17C010A-10QI
8P3
20J
32A
Industrial
(-40°C to 85°C)
Notes: 1. Use 512-Kbit density parts to replace Altera EPC1441.
2. Use 1-Mbit density parts to replace Altera EPC1.
Ordering Information – 3.3V Devices
Memory
Size
Ordering Code
Package
Operation Range
512-Kbit(1)
AT17LV512A-10PC
AT17LV512A-10JC
8P3
20J
Commercial
(0°C to 70°C)
AT17LV512A-10PI
AT17LV512A-10JI
8P3
20J
Industrial
(-40°C to 85°C)
1-Mbit(2)
AT17LV010A-10PC
AT17LV010A-10JC
AT17LV010A-10QC
8P3
20J
32A
Commercial
(0°C to 70°C)
AT17LV010A-10PI
AT17LV010A-10JI
AT17LV010A-10QI
8P3
20J
32A
Industrial
(-40°C to 85°C)
Notes: 1. Use 512-Kbit density parts to replace Altera EPC1441.
2. Use 1-Mbit density parts to replace Altera EPC1.
Package Type
8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
8P3
20J
32A
13
0974E–08/01
Packaging Information
8P3, 8-lead, 0.300” Wide, Plastic Dual Inline
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
Package (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AA
32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Flat package (TQFP)
Dimensions in Millimeters and (Inches)
PIN 1 ID
9.00 (0.354) BSC
0.45 (0.018)
0.30 (0.012)
0.80 (0.031) BSC
9.00 (0.354) BSC
7.00 (0.276) BSC
1.20 (0.047) MAX
0˚
7˚
0.20 (0.008)
0.10 (0.004)
0.15 (0.006)
0.05 (0.002)
0.75 (0.030)
0.45 (0.018)
14
AT17C/LV512A/010A
0974E–08/01
Atmel Headquarters
Atmel Product Operations
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